[ { "path": ".github/pull_request_template.md", "content": "Please do not submit a Pull Request via github. Our project makes use\nof mailing lists for patch submission and review. For more details\nplease see\nhttps://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842172/Create+and+Submit+a+Patch\n" }, { "path": ".gitignore", "content": "*~\n" }, { "path": "RM/data/RM.mdd", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver RM\n OPTION supported_peripherals = (RM);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = RM;\n PARAMETER name = dev_type, default = fpga_region, type = string;\n DTGPARAM name = compatible, default = \"fpga-region\", type = stringlist;\n DTGPARAM name = \"#address-cells\", default = 1, type = int;\n DTGPARAM name = \"#size-cells\", default = 1, type = int;\n DTGPARAM name = ranges, type = boolean;\nEND driver\n" }, { "path": "RM/data/RM.tcl", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tset val [get_property FAMILY [get_hw_designs]]\n\tswitch -glob $val {\n\t\t\"zynq\" {\n\t\t\thsi::utils::add_new_property $drv_handle \"fpga-mgr\" string \"<&devcfg>\"\n\t\t}\n\t}\n}\n" }, { "path": "ai_engine/data/ai_engine.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver ai_engine\n\n OPTION supported_peripherals = (ai_engine);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = ai_engine;\n\nEND driver\n" }, { "path": "ai_engine/data/ai_engine.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nvariable aie_array_cols_start\nvariable aie_array_cols_num\nproc generate_aie_array_device_info {node drv_handle bus_node} {\n\tset aie_array_id 0\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,ai-engine-v2.0\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\n\t#set default values for S80 device\n\tset hw_gen \"AIE\"\n\tset aie_rows_start 1\n\tset aie_rows_num 8\n\tset mem_rows_start 0\n\tset mem_rows_num 0\n\tset shim_rows_start 0\n\tset shim_rows_num 1\n\tset ::aie_array_cols_start 0\n\tset ::aie_array_cols_num 50\n\n\t# override the above default values if AIE primitives are available in\n\t# xsa\n\tset CommandExists [ namespace which hsi::get_hw_primitives]\n\tif {$CommandExists != \"\"} {\n\t\tset aie_prop [hsi::get_hw_primitives aie]\n\t\tif {$aie_prop != \"\"} {\n\t\t\tputs \"INFO: Reading AIE hardware properties from XSA.\"\n\n\t\t\tset hw_gen [get_property HWGEN [hsi::get_hw_primitives aie]]\n\t\t\tset aie_rows [get_property AIETILEROWS [hsi::get_hw_primitives aie]]\n\t\t\tset mem_rows [get_property MEMTILEROW [hsi::get_hw_primitives aie]]\n\t\t\tset shim_rows [get_property SHIMROW [hsi::get_hw_primitives aie]]\n\t\t\tset ::aie_array_cols_num [get_property AIEARRAYCOLUMNS [hsi::get_hw_primitives aie]]\n\n\t\t\tset aie_rows_start [lindex [split $aie_rows \":\"] 0]\n\t\t\tset aie_rows_num [lindex [split $aie_rows \":\"] 1]\n\t\t\tset mem_rows_start [lindex [split $mem_rows \":\"] 0]\n\t\t\tif {$mem_rows_start==-1} {\n\t\t\t\tset mem_rows_start 0\n\t\t\t}\n\t\t\tset mem_rows_num [lindex [split $mem_rows \":\"] 1]\n\t\t\tset shim_rows_start [lindex [split $shim_rows \":\"] 0]\n\t\t\tset shim_rows_num [lindex [split $shim_rows \":\"] 1]\n\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle: AIE hardware properties are not available in XSA, using defaults.\"\n\t\t}\n\t} else {\n\t\tdtg_warning \"$drv_handle: AIE hardware properties are not available in XSA, using defaults.\"\n\t}\n\n\tif {$hw_gen==\"AIE\"} {\n\t\tappend aiegen \"/bits/ 8 <0x1>\"\n\t} elseif {$hw_gen==\"AIEML\"} {\n\t\tappend aiegen \"/bits/ 8 <0x2>\"\n\t}\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,aie-gen\" $aiegen noformating\n\tappend shimrows \"/bits/ 8 <${shim_rows_start} ${shim_rows_num}>\"\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,shim-rows\" $shimrows noformating\n\tappend corerows \"/bits/ 8 <${aie_rows_start} ${aie_rows_num}>\"\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,core-rows\" $corerows noformating\n\tappend memrows \"/bits/ 8 <$mem_rows_start $mem_rows_num>\"\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mem-rows\" $memrows noformating\n\n\tset name [get_property NAME [get_current_part $drv_handle]]\n\tset part_num [string range $name 0 7]\n\n\tif {$part_num == \"xcvp2502\"} {\n\t\t#s100\n\t\tset power_domain \"&versal_firmware 0x18225072\"\n\t} elseif {$part_num == \"xcvp2802\"} {\n\t\t#s200\n\t\tset power_domain \"&versal_firmware 0x18227072\"\n\t} else {\n\t\tset power_domain \"&versal_firmware 0x18224072\"\n\t}\n\n\thsi::utils::add_new_dts_param \"${node}\" \"power-domains\" $power_domain intlist\n\thsi::utils::add_new_dts_param \"${node}\" \"#address-cells\" \"2\" intlist\n\thsi::utils::add_new_dts_param \"${node}\" \"#size-cells\" \"2\" intlist\n\thsi::utils::add_new_dts_param \"${node}\" \"ranges\" \"\" boolean\n\n\tset ai_clk_node [add_or_get_dt_node -n \"aie_core_ref_clk_0\" -l \"aie_core_ref_clk_0\" -p ${bus_node}]\n\tset clk_freq [get_property CONFIG.AIE_CORE_REF_CTRL_FREQMHZ [get_cells -hier $drv_handle]]\n\tset clk_freq [expr ${clk_freq} * 1000000]\n\thsi::utils::add_new_dts_param \"${ai_clk_node}\" \"compatible\" \"fixed-clock\" stringlist\n\thsi::utils::add_new_dts_param \"${ai_clk_node}\" \"#clock-cells\" 0 int\n\thsi::utils::add_new_dts_param \"${ai_clk_node}\" \"clock-frequency\" $clk_freq int\n\n\tset clocks \"aie_core_ref_clk_0\"\n\tset_drv_prop $drv_handle clocks \"$clocks\" reference\n\thsi::utils::add_new_dts_param \"${node}\" \"clock-names\" \"aclk0\" stringlist\n\n\treturn ${node}\n}\n\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset RpRm [hsi::utils::get_rp_rm_for_drv $drv_handle]\n\t\tregsub -all { } $RpRm \"\" RpRm\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n\n\tgenerate_aie_array_device_info ${node} ${drv_handle} ${bus_node}\n\n\tset ip [get_cells -hier $drv_handle]\n\tset unit_addr [get_baseaddr ${ip} no_prefix]\n\tset aperture_id 0\n\tset aperture_node [add_or_get_dt_node -n \"aie_aperture\" -u \"${unit_addr}\" -l \"aie_aperture_${aperture_id}\" -p ${node}]\n\n\tset reg [get_property CONFIG.reg ${drv_handle}]\n\thsi::utils::add_new_dts_param \"${aperture_node}\" \"reg\" $reg noformat\n\n\n\tset name [get_property NAME [get_current_part $drv_handle]]\n\tset part_num [string range $name 0 7]\n\tset part_num_v70 [string range $name 0 4]\n\n\tif {$part_num == \"xcvp2502\"} {\n\t\t#s100\n\t\tset power_domain \"&versal_firmware 0x18225072\"\n\t\thsi::utils::add_new_dts_param \"${aperture_node}\" \"xlnx,device-name\" \"100\" int\n\t\tset aperture_nodeid 0x18801000\n\t} elseif {$part_num == \"xcvp2802\"} {\n\t\t#s200\n\t\tset power_domain \"&versal_firmware 0x18227072\"\n\t\thsi::utils::add_new_dts_param \"${aperture_node}\" \"xlnx,device-name\" \"200\" int\n\t\tset aperture_nodeid 0x18803000\n\t} elseif {$part_num_v70 == \"xcv70\"} {\n\t\t#v70\n\t\tset power_domain \"&versal_firmware 0x18224072\"\n\t\thsi::utils::add_new_dts_param \"${aperture_node}\" \"xlnx,device-name\" \"0\" int\n\t\tset aperture_nodeid 0x18800000\n\t} else {\n\t\t#NON SSIT devices\n\t\tset intr_names \"interrupt1\"\n\t\tlappend intr_names \"interrupt2\"\n\t\tlappend intr_names \"interrupt3\"\n\t\tset intr_num \"0x0 0x94 0x4>, <0x0 0x95 0x4>, <0x0 0x96 0x4\"\n\t\tset power_domain \"&versal_firmware 0x18224072\"\n\t\thsi::utils::add_new_dts_param \"${aperture_node}\" \"interrupt-names\" $intr_names stringlist\n\t\thsi::utils::add_new_dts_param \"${aperture_node}\" \"interrupts\" $intr_num intlist\n\t\thsi::utils::add_new_dts_param \"${aperture_node}\" \"interrupt-parent\" gic reference\n\t\thsi::utils::add_new_dts_param \"${aperture_node}\" \"xlnx,device-name\" \"0\" int\n\t\tset aperture_nodeid 0x18800000\n\t}\n\n\thsi::utils::add_new_dts_param \"${aperture_node}\" \"power-domains\" $power_domain intlist\n\thsi::utils::add_new_dts_param \"${aperture_node}\" \"#address-cells\" \"2\" intlist\n\thsi::utils::add_new_dts_param \"${aperture_node}\" \"#size-cells\" \"2\" intlist\n\n\thsi::utils::add_new_dts_param \"${aperture_node}\" \"xlnx,columns\" \"$::aie_array_cols_start $::aie_array_cols_num\" intlist\n\thsi::utils::add_new_dts_param \"${aperture_node}\" \"xlnx,node-id\" \"${aperture_nodeid}\" intlist\n\n}\n" }, { "path": "ams/data/ams.mdd", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver ams\n\n OPTION supported_peripherals = (psu_ams);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = ams;\n\nEND driver\n" }, { "path": "ams/data/ams.tcl", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n set mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n if {[string match -nocase $mainline_ker \"none\"]} {\n set ams_list \"ams_ps ams_pl\"\n set dts_file [get_property CONFIG.pcw_dts [get_os]]\n foreach ams_name ${ams_list} {\n set ams_node [add_or_get_dt_node -n \"&${ams_name}\" -d $dts_file]\n hsi::utils::add_new_dts_param \"${ams_node}\" \"status\" \"okay\" string\n }\n }\n}\n" }, { "path": "apmps/data/apmps.mdd", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver apmps\n OPTION supported_peripherals = (psu_apm psv_apm psx_apm);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = apmps;\nEND driver\n" }, { "path": "apmps/data/apmps.tcl", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n" }, { "path": "audio_embed/data/audio_embed.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver audio_embed\n\n OPTION supported_peripherals = (v_uhdsdi_audio);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = audio_embed;\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "audio_embed/data/audio_embed.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,v-uhdsdi-audio-2.0\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset connected_embed_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] \"SDI_EMBED_ANC_DS_IN\"]\n\tif {[llength $connected_embed_ip] != 0} {\n\t\tset connected_embed_ip_type [get_property IP_NAME $connected_embed_ip]\n\t\tif {[string match -nocase $connected_embed_ip_type \"v_smpte_uhdsdi_tx_ss\"]} {\n\t\t\tset sdi_av_port [add_or_get_dt_node -n \"port\" -l sdi_av_port -u 0 -p $node]\n\t\t\thsi::utils::add_new_dts_param \"$sdi_av_port\" \"reg\" 0 int\n\t\t\tset sdi_embed_node [add_or_get_dt_node -n \"endpoint\" -l sditx_audio_embed_src -p $sdi_av_port]\n\t\t\thsi::utils::add_new_dts_param \"$sdi_embed_node\" \"remote-endpoint\" sdi_audio_sink_port reference\n\t\t}\n\t} else {\n\t\tdtg_warning \"$drv_handle connected_ip is NULL for the pin SDI_EMBED_ANC_DS_IN\"\n\t}\n\tset connected_extract_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] \"SDI_EXTRACT_ANC_DS_IN\"]\n\tif {[llength $connected_extract_ip] != 0} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,sdi-rx-video\" $connected_extract_ip reference\n\t} else {\n\t\tdtg_warning \"$drv_handle connected_extract_ip is NULL for the pin SDI_EXTRACT_ANC_DS_IN\"\n\t}\n\tset connected_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] \"S_AXIS_DATA\"]\n\tif {[llength $connected_ip] != 0} {\n\t\tset index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $connected_ip]\n\t\tif {$index != -1 } {\n\t\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,snd-pcm\" $connected_ip reference\n\t\t}\n\t} else {\n\t\tdtg_warning \"$drv_handle connected ip is NULL for the pin S_AXIS_DATA\"\n\t}\n\tset connect_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] \"M_AXIS_DATA\"]\n\tif {[llength $connect_ip] != 0} {\n\t\tset index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $connect_ip]\n\t\tif {$index != -1 } {\n\t\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,snd-pcm\" $connect_ip reference\n\t\t}\n\t} else {\n\t\tdtg_warning \"$drv_handle connected ip is NULL for the pin M_AXIS_DATA\"\n\t}\n}\n" }, { "path": "audio_formatter/data/audio_formatter.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver audio_formatter\n\n OPTION supported_peripherals = (audio_formatter);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = audio_formatter;\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "audio_formatter/data/audio_formatter.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,audio-formatter-1.0\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset tx_connect_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] \"m_axis_mm2s\"]\n\tif {[llength $tx_connect_ip] != 0} {\n hsi::utils::add_new_dts_param \"$node\" \"xlnx,tx\" $tx_connect_ip reference\n\t} else {\n\t\tdtg_warning \"$drv_handle pin m_axis_mm2s is not connected... check your design\"\n\t}\n\tset rx_connect_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_s2mm\"]\n\tif {[llength $rx_connect_ip] != 0} {\n hsi::utils::add_new_dts_param \"$node\" \"xlnx,rx\" $rx_connect_ip reference\n\t} else {\n\t\tdtg_warning \"$drv_handle pin s_axis_s2mm is not connected... check your design\"\n\t}\n\n}\n" }, { "path": "audio_spdif/data/audio_spdif.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver audio_spdif\n\n OPTION supported_peripherals = (spdif);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = audio_spdif;\n\nEND driver\n" }, { "path": "audio_spdif/data/audio_spdif.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,spdif-2.0\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset spdif_mode [get_property CONFIG.SPDIF_Mode [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,spdif-mode\" $spdif_mode int\n\tset cstatus_reg [get_property CONFIG.CSTATUS_REG [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,chstatus-reg\" $cstatus_reg int\n\tset userdata_reg [get_property CONFIG.USERDATA_REG [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,userdata-reg\" $userdata_reg int\n\tset axi_buffer_size [get_property CONFIG.AXI_BUFFER_Size [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,fifo-depth\" $axi_buffer_size int\n\tset clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"aud_clk_i\"]\n\tif {[llength $clk_freq] != 0} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"clock-frequency\" $clk_freq int\n\t}\n}\n" }, { "path": "axi_can/data/axi_can.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_can\n\n OPTION supported_peripherals = (can canfd);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_can;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,axi-can-1.00.a\";\n\nEND driver\n" }, { "path": "axi_can/data/axi_can.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n # try to source the common tcl procs\n # assuming the order of return is based on repo priority\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n set node [gen_peripheral_nodes $drv_handle]\n set compatible [get_comp_str $drv_handle]\n set compatible [append compatible \" \" \"xlnx,axi-can-1.00.a\"]\n set_drv_prop $drv_handle compatible \"$compatible\" stringlist\n set ip_name [get_property IP_NAME [get_cells -hier $drv_handle]]\n set ecc [get_property CONFIG.ENABLE_ECC [get_cells -hier $drv_handle]]\n if { [llength $ecc] } {\n\thsi::utils::add_new_dts_param $node \"xlnx,has-ecc\" \"\" boolean\n\t}\n set version [string tolower [common::get_property VLNV $drv_handle]]\n if {[string match -nocase $ip_name \"canfd\"]} {\n if {[string compare -nocase \"xilinx.com:ip:canfd:1.0\" $version] == 0} {\n hsi::utils::add_new_property $drv_handle \"compatible\" stringlist \"xlnx,canfd-1.0\"\n } else {\n hsi::utils::add_new_property $drv_handle \"compatible\" stringlist \"xlnx,canfd-2.0\"\n }\n set_drv_conf_prop $drv_handle NUM_OF_TX_BUF tx-mailbox-count hexint\n set_drv_conf_prop $drv_handle NUM_OF_TX_BUF rx-fifo-depth hexint\n } else {\n set_drv_conf_prop $drv_handle c_can_tx_dpth tx-fifo-depth hexint\n set_drv_conf_prop $drv_handle c_can_rx_dpth rx-fifo-depth hexint\n }\n\n set proc_type [get_sw_proc_prop IP_NAME]\n switch $proc_type {\n \"microblaze\" {\n gen_dev_ccf_binding $drv_handle \"s_axi_aclk\"\n\t}\n }\n}\n" }, { "path": "axi_cdma/data/axi_cdma.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_cdma\n\n OPTION supported_peripherals = (axi_cdma);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_cdma;\n DTGPARAM name = dev_type, default = dma , type = string;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,axi-cdma-1.00.a\";\n DTGPARAM name = \"#dma-cells\", type = int, default = 1;\n\nEND driver\n" }, { "path": "axi_cdma/data/axi_cdma.tcl", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\n\tset_drv_conf_prop $drv_handle C_INCLUDE_SG xlnx,include-sg boolean\n\tset_drv_conf_prop $drv_handle C_NUM_FSTORES xlnx,num-fstores\n\tset_drv_conf_prop $drv_handle C_USE_FSYNC xlnx,flush-fsync\n\tset_drv_conf_prop $drv_handle C_ADDR_WIDTH xlnx,addrwidth\n\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n set compatible [get_comp_str $drv_handle]\n set compatible [append compatible \" \" \"xlnx,axi-cdma-1.00.a\"]\n set_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset dma_ip [get_cells -hier $drv_handle]\n\tset cdma_count [hsi::utils::get_os_parameter_value \"cdma_count\"]\n\tif { [llength $cdma_count] == 0 } {\n\t\tset cdma_count 0\n\t}\n\n\tset baseaddr [get_baseaddr $dma_ip no_prefix]\n\tset tx_chan [add_dma_channel $drv_handle $node \"axi-cdma\" $baseaddr \"MM2S\" $cdma_count ]\n\tincr cdma_count\n\thsi::utils::set_os_parameter_value \"cdma_count\" $cdma_count\n\tset mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n\tif {[string match -nocase $mainline_ker \"none\"]} {\n\t\tset proc_type [get_sw_proc_prop IP_NAME]\n\t\tswitch $proc_type {\n\t\t\t \"microblaze\" {\n\t\t\t\tgen_dev_ccf_binding $drv_handle \"s_axi_lite_aclk m_axi_aclk\"\n\t\t\t\tset_drv_prop_if_empty $drv_handle \"clock-names\" \"s_axi_lite_aclk m_axi_aclk\" stringlist\n\t\t\t}\n\t\t}\n\t} else {\n\t\tgenerate_clk_nodes $drv_handle\n\t}\n}\n\nproc add_dma_channel {drv_handle parent_node xdma addr mode devid} {\n\t#set ip [get_cells -hier $drv_handle]\n\tset modellow [string tolower $mode]\n\tset modeIndex [string index $mode 0]\n\t#set node_name [format \"dma-channel@%x\" $addr]\n\tset dma_channel [add_or_get_dt_node -n \"dma-channel\" -u $addr -p $parent_node]\n\n\thsi::utils::add_new_dts_param $dma_channel \"compatible\" [format \"xlnx,%s-channel\" $xdma] stringlist\n\thsi::utils::add_new_dts_param $dma_channel \"xlnx,device-id\" $devid hexint\n\tadd_cross_property_to_dtnode $drv_handle \"CONFIG.C_INCLUDE_DRE\" $dma_channel \"xlnx,include-dre\" boolean\n\tadd_cross_property_to_dtnode $drv_handle \"CONFIG.C_M_AXI_DATA_WIDTH\" $dma_channel \"xlnx,datawidth\"\n\tadd_cross_property_to_dtnode $drv_handle \"CONFIG.C_USE_DATAMOVER_LITE\" $dma_channel \"xlnx,lite-mode\" boolean\n\tadd_cross_property_to_dtnode $drv_handle \"CONFIG.C_M_AXI_MAX_BURST_LEN\" $dma_channel \"xlnx,max-burst-len\"\n\n\tset intr_info [get_intr_id $drv_handle \"cdma_introut\" ]\n\tif { [llength $intr_info] && ![string match -nocase $intr_info \"-1\"] } {\n\t\thsi::utils::add_new_dts_param $dma_channel \"interrupts\" $intr_info intlist\n\t} else {\n\t\tdtg_warning \"ERROR: ${drv_handle}: cdma_introut port is not connected\"\n\t}\n\treturn $dma_channel\n}\n\nproc generate_clk_nodes {drv_handle} {\n set proc_type [get_sw_proc_prop IP_NAME]\n switch $proc_type {\n \"ps7_cortexa9\" {\n set_drv_prop_if_empty $drv_handle \"clocks\" \"clkc 15>, <&clkc 15\" reference\n set_drv_prop_if_empty $drv_handle \"clock-names\" \"s_axi_lite_aclk m_axi_aclk\" stringlist\n } \"psu_cortexa53\" {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"s_axi_lite_aclk\"]\n if {![string equal $clk_freq \"\"]} {\n if {[lsearch $bus_clk_list $clk_freq] < 0} {\n set bus_clk_list [lappend bus_clk_list $clk_freq]\n }\n }\n set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]\n set dts_file [current_dt_tree]\n set bus_node [add_or_get_bus_node $drv_handle $dts_file]\n set misc_clk_node [add_or_get_dt_node -n \"misc_clk_${bus_clk_cnt}\" -l \"misc_clk_${bus_clk_cnt}\" \\\n -d ${dts_file} -p ${bus_node}]\n\t hsi::utils::add_new_dts_param \"${misc_clk_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t hsi::utils::add_new_dts_param \"${misc_clk_node}\" \"#clock-cells\" 0 int\n\t hsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-frequency\" $clk_freq int\n set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]\n set_drv_prop_if_empty $drv_handle \"clocks\" \"$clk_refs>, <&$clk_refs\" reference\n set_drv_prop_if_empty $drv_handle \"clock-names\" \"s_axi_lite_aclk m_axi_aclk\" stringlist\n } \"microblaze\" {\n gen_dev_ccf_binding $drv_handle \"s_axi_lite_aclk m_axi_aclk\"\n set_drv_prop_if_empty $drv_handle \"clock-names\" \"s_axi_lite_aclk m_axi_aclk\" stringlist\n }\n default {\n error \"Unknown arch\"\n }\n }\n}\n" }, { "path": "axi_clk_wiz/data/axi_clk_wiz.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_clk_wiz\n\n OPTION supported_peripherals = (clk_wiz clk_wizard);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_clk_wiz;\n #DTGPARAM name = dtg.ip_params, type = boolean;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,clocking-wizard\";\n DTGPARAM name = clock-output-names, type = stringlist, default = \"\";\n DTGPARAM name = \"#clock-cells\", type = int, default = 1;\nEND driver\n" }, { "path": "axi_clk_wiz/data/axi_clk_wiz.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,clocking-wizard\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset ip [get_cells -hier $drv_handle]\n\tgen_speedgrade $drv_handle\n\tset j 0\n\tset output_names \"\"\n\tfor {set i 1} {$i < 8} {incr i} {\n\t\tif {[get_property CONFIG.C_CLKOUT${i}_USED $ip] != 0} {\n\t\t\tset freq [get_property CONFIG.C_CLKOUT${i}_OUT_FREQ $ip]\n\t\t\tset pin_name [get_property CONFIG.C_CLK_OUT${i}_PORT $ip]\n\t\t\tset basefrq [string tolower [get_property CONFIG.C_BASEADDR $ip]]\n\t\t\tset pin_name \"$basefrq-$pin_name\"\n\t\t\tlappend output_names $pin_name\n\t\t\tincr j\n\t\t}\n\t}\n\tif {![string_is_empty $output_names]} {\n\t\tset_property CONFIG.clock-output-names $output_names $drv_handle\n\t\thsi::utils::add_new_property $drv_handle \"xlnx,nr-outputs\" int $j\n\t}\n\n\n\tgen_dev_ccf_binding $drv_handle \"clk_in1 s_axi_aclk\" \"clocks clock-names\"\n\tset sw_proc [get_sw_processor]\n\tset proc_ip [get_cells -hier $sw_proc]\n\tset proctype [get_property IP_NAME $proc_ip]\n\tif {[string match -nocase $proctype \"microblaze\"] } {\n\t\tgen_dev_ccf_binding $drv_handle \"clk_in1 s_axi_aclk\" \"clocks clock-names\"\n\t}\n}\n\nproc gen_speedgrade {drv_handle} {\n\tset speedgrade [get_property SPEEDGRADE [get_hw_designs]]\n\tset num [regexp -all -inline -- {[0-9]} $speedgrade]\n\tif {![string equal $num \"\"]} {\n\t\thsi::utils::add_new_property $drv_handle \"xlnx,speed-grade\" int $num\n\t}\n}\n" }, { "path": "axi_dma/data/axi_dma.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_dma\n\n OPTION supported_peripherals = (axi_dma);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_dma;\n DTGPARAM name = dev_type, default = dma , type = string;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,axi-dma-1.00.a\";\n DTGPARAM name = \"#dma-cells\", type = int, default = 1;\n\nEND driver\n" }, { "path": "axi_dma/data/axi_dma.tcl", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\nset connected_ip 0\n\nproc generate {drv_handle} {\n global connected_ip\n # try to source the common tcl procs\n # assuming the order of return is based on repo priority\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n\n set node [gen_peripheral_nodes $drv_handle]\n if {$node == 0} {\n return\n }\n set compatible [get_comp_str $drv_handle]\n set compatible [append compatible \" \" \"xlnx,axi-dma-1.00.a\"]\n set_drv_prop $drv_handle compatible \"$compatible\" stringlist\n set dma_ip [get_cells -hier $drv_handle]\n set dma_count [hsi::utils::get_os_parameter_value \"dma_count\"]\n if { [llength $dma_count] == 0 } {\n set dma_count 0\n }\n set axiethernetfound 0\n set connected_ip [hsi::utils::get_connected_stream_ip $dma_ip \"M_AXIS_MM2S\"]\n if { [llength $connected_ip] } {\n set connected_ip_type [get_property IP_NAME $connected_ip]\n if { [string match -nocase $connected_ip_type axi_ethernet ]\n || [string match -nocase $connected_ip_type axi_ethernet_buffer ] } {\n set axiethernetfound 1\n }\n } else {\n dtg_warning \"$drv_handle connected ip is NULL for the pin M_AXIS_MM2S\"\n }\n set is_xxv [get_connected_ip $drv_handle \"M_AXIS_MM2S\"]\n if { $axiethernetfound || $is_xxv == 1} {\n set compatstring \"xlnx,eth-dma\"\n set_property compatible \"$compatstring\" $drv_handle\n }\n set tx_chan 0\n set rx_chan 0\n if { $axiethernetfound != 1 && $is_xxv != 1} {\n set_drv_conf_prop $drv_handle C_INCLUDE_SG xlnx,include-sg boolean\n set_drv_conf_prop $drv_handle C_SG_INCLUDE_STSCNTRL_STRM xlnx,sg-include-stscntrl-strm boolean\n set_drv_conf_prop $drv_handle c_enable_multi_channel xlnx,multichannel-dma boolean\n set_drv_conf_prop $drv_handle c_addr_width xlnx,addrwidth\n set_drv_conf_prop $drv_handle c_sg_length_width xlnx,sg-length-width\n\n set baseaddr [get_baseaddr $dma_ip no_prefix]\n set tx_chan [hsi::utils::get_ip_param_value $dma_ip C_INCLUDE_MM2S]\n if { $tx_chan == 1 } {\n set connected_ip [hsi::utils::get_connected_stream_ip $dma_ip \"M_AXIS_MM2S\"]\n set tx_chan_node [add_dma_channel $drv_handle $node \"axi-dma\" $baseaddr \"MM2S\" $dma_count ]\n set intr_info [get_intr_id $drv_handle \"mm2s_introut\"]\n #set intc [hsi::utils::get_interrupt_parent $dma_ip \"mm2s_introut\"]\n if { [llength $intr_info] && ![string match -nocase $intr_info \"-1\"] } {\n\t\t hsi::utils::add_new_dts_param $tx_chan_node \"interrupts\" $intr_info intlist\n } else {\n\t\t dtg_warning \"ERROR: ${drv_handle}: mm2s_introut port is not connected\"\n }\n add_dma_coherent_prop $drv_handle \"M_AXI_MM2S\"\n }\n set rx_chan [hsi::utils::get_ip_param_value $dma_ip C_INCLUDE_S2MM]\n if { $rx_chan ==1 } {\n set connected_ip [hsi::utils::get_connected_stream_ip $dma_ip \"S_AXIS_S2MM\"]\n set rx_bassaddr [format %08x [expr 0x$baseaddr + 0x30]]\n set rx_chan_node [add_dma_channel $drv_handle $node \"axi-dma\" $rx_bassaddr \"S2MM\" $dma_count]\n set intr_info [get_intr_id $drv_handle \"s2mm_introut\"]\n #set intc [hsi::utils::get_interrupt_parent $dma_ip \"s2mm_introut\"]\n if { [llength $intr_info] && ![string match -nocase $intr_info \"-1\"] } {\n\t\t hsi::utils::add_new_dts_param $rx_chan_node \"interrupts\" $intr_info intlist\n } else {\n\t\t dtg_warning \"ERROR: ${drv_handle}: s2mm_introut port is not connected\"\n }\n add_dma_coherent_prop $drv_handle \"M_AXI_S2MM\"\n }\n } else {\n\tset proc_type [get_sw_proc_prop IP_NAME]\n\tif {[string match -nocase $proc_type \"ps7_cortexa9\"] || [string match -nocase $proc_type \"microblaze\"] } {\n\t\tset_drv_property $drv_handle axistream-connected \"$connected_ip\" reference\n\t\tset_drv_property $drv_handle axistream-control-connected \"$connected_ip\" reference\n\t}\n\tset ip_prop CONFIG.c_include_mm2s_dre\n\tadd_cross_property $drv_handle $ip_prop $drv_handle \"xlnx,include-dre\" boolean\n\tset addr_width [get_property CONFIG.c_addr_width $dma_ip]\n\tset inhex [format %x $addr_width]\n\tappend addrwidth \"/bits/ 8 <0x$inhex>\"\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,addrwidth\" $addrwidth noformating\n\tset num_queues [get_property CONFIG.c_num_mm2s_channels $dma_ip]\n\tset inhex [format %x $num_queues]\n\tappend numqueues \"/bits/ 16 <0x$inhex>\"\n\thsi::utils::add_new_dts_param $node \"xlnx,num-queues\" $numqueues noformating\n }\n incr dma_count\n hsi::utils::set_os_parameter_value \"dma_count\" $dma_count\n set mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n if {[string match -nocase $mainline_ker \"none\"]} {\n set proc_type [get_sw_proc_prop IP_NAME]\n if {[string match -nocase $proc_type \"microblaze\"]} {\n generate_clk_nodes $drv_handle $axiethernetfound $tx_chan $rx_chan\n }\n } else {\n generate_clk_nodes $drv_handle $axiethernetfound $tx_chan $rx_chan\n }\n}\n\nproc add_dma_channel {drv_handle parent_node xdma addr mode devid} {\n set modellow [string tolower $mode]\n set modeIndex [string index $mode 0]\n set dma_channel [add_or_get_dt_node -n \"dma-channel\" -u $addr -p $parent_node]\n hsi::utils::add_new_dts_param $dma_channel \"compatible\" [format \"xlnx,%s-%s-channel\" $xdma $modellow] stringlist\n hsi::utils::add_new_dts_param $dma_channel \"xlnx,device-id\" $devid hexint\n\n\n add_cross_property_to_dtnode $drv_handle [format \"CONFIG.C_INCLUDE_%s_DRE\" $mode] $dma_channel \"xlnx,include-dre\" boolean\n if {[string match -nocase $mode \"MM2S\"]} {\n set datawidth [get_property CONFIG.C_M_AXI_MM2S_DATA_WIDTH [get_cells -hier $drv_handle]]\n }\n if {[string match -nocase $mode \"S2MM\"]} {\n set datawidth [get_property CONFIG.C_S_AXIS_S2MM_TDATA_WIDTH [get_cells -hier $drv_handle]]\n }\n hsi::utils::add_new_dts_param $dma_channel \"xlnx,datawidth\" $datawidth hexint\n\n set num_channles [get_property CONFIG.c_num_mm2s_channels [get_cells -hier $drv_handle]]\n hsi::utils::add_new_dts_param $dma_channel \"dma-channels\" $num_channles hexint\n\n return $dma_channel\n}\n\nproc add_dma_coherent_prop {drv_handle intf} {\n set ip_name [::hsi::get_cells -hier -filter \"NAME==$drv_handle\"]\n set connectedip [hsi::utils::get_connected_stream_ip $drv_handle $intf]\n if {[llength $connectedip] == 0} {\n return\n }\n set intrconnect [get_property IP_NAME [get_cells -hier $connectedip]]\n set num_master [get_property CONFIG.NUM_MI $connectedip]\n set done 0\n # check whether dma connected to interconnect ip, loop until you get the\n # port name ACP or HP\n while {[string match -nocase $intrconnect \"axi_interconnect\"]} {\n # loop over number of master interfaces\n set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectedip] -filter {TYPE==MASTER}]\n if {[llength $master_intf] == 0} {\n break\n }\n foreach interface ${master_intf} {\n set intf_port [hsi::utils::get_connected_intf $connectedip $interface]\n set intrconnect [hsi::utils::get_connected_stream_ip $connectedip $interface]\n if {![string_is_empty $intf_port] && [string match -nocase $intf_port \"S_AXI_ACP\"]} {\n hsi::utils::add_new_property $drv_handle \"dma-coherent\" boolean \"\"\n # here dma connected to ACP port\n set done 1\n break;\n }\n if {$done} {\n break\n }\n }\n }\n}\n\nproc generate_clk_nodes {drv_handle axiethernetfound tx_chan rx_chan} {\n\tset proc_type [get_sw_proc_prop IP_NAME]\n\tset clocknames \"s_axi_lite_aclk\"\n\tswitch $proc_type {\n\t\t\"ps7_cortexa9\" {\n\t\t\tset clocks \"clkc 15\"\n\t\t\tif { $axiethernetfound != 1 } {\n\t\t\t\tappend clocknames \" \" \"m_axi_sg_aclk\"\n\t\t\t\tappend clocks \"\" \">, <&clkc 15\"\n\t\t\t}\n\t\t\tif { $tx_chan ==1 } {\n\t\t\t\tappend clocknames \" \" \"m_axi_mm2s_aclk\"\n\t\t\t\tappend clocks \"\" \">, <&clkc 15\"\n\t\t\t}\n\t\t\tif { $rx_chan ==1 } {\n\t\t\t\tappend clocknames \" \" \"m_axi_s2mm_aclk\"\n\t\t\t\tappend clocks \"\" \">, <&clkc 15\"\n\t\t\t}\n\t\t\tset_drv_prop_if_empty $drv_handle \"clocks\" $clocks reference\n\t\t\tset_drv_prop_if_empty $drv_handle \"clock-names\" $clocknames stringlist\n\t\t} \"psu_cortexa53\" {\n\t\t\tforeach i [get_sw_cores device_tree] {\n\t\t\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\t\t\tif {[file exists $common_tcl_file]} {\n\t\t\t\t\tsource $common_tcl_file\n\t\t\t\t\tbreak\n\t\t\t\t}\n\t\t\t}\n\t\t\tset clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"s_axi_lite_aclk\"]\n\t\t\tif {![string equal $clk_freq \"\"]} {\n\t\t\t\tif {[lsearch $bus_clk_list $clk_freq] < 0} {\n\t\t\t\t\tset bus_clk_list [lappend bus_clk_list $clk_freq]\n\t\t\t\t}\n\t\t\t}\n\t\t\tset bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]\n\t\t\tset dts_file [current_dt_tree]\n\t\t\tset bus_node [add_or_get_bus_node $drv_handle $dts_file]\n\t\t\tset misc_clk_node [add_or_get_dt_node -n \"misc_clk_${bus_clk_cnt}\" -l \"misc_clk_${bus_clk_cnt}\" \\\n\t\t\t\t-d ${dts_file} -p ${bus_node}]\n\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"#clock-cells\" 0 int\n\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-frequency\" $clk_freq int\n\t\t\tset clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]\n\t\t\tset clocks \"$clk_refs\"\n\t\t\tif { $axiethernetfound != 1 } {\n\t\t\t\tappend clocknames \" \" \"m_axi_sg_aclk\"\n\t\t\t\tappend clocks \"\" \">, <&$clk_refs\"\n\t\t\t}\n\t\t\tif { $tx_chan ==1 } {\n\t\t\t\tappend clocknames \" \" \"m_axi_mm2s_aclk\"\n\t\t\t\tappend clocks \"\" \">, <&$clk_refs\"\n\t\t\t}\n\t\t\tif { $rx_chan ==1 } {\n\t\t\t\tappend clocknames \" \" \"m_axi_s2mm_aclk\"\n\t\t\t\tappend clocks \"\" \">, <&$clk_refs\"\n\t\t\t}\n\t\t\tset_drv_prop_if_empty $drv_handle \"clocks\" \"$clocks\" reference\n\t\t\tset_drv_prop_if_empty $drv_handle \"clock-names\" \"$clocknames\" stringlist\n\t\t} \"microblaze\" {\n\t\t\tif { $axiethernetfound != 1 } {\n\t\t\t\tappend clocknames \" \" \"m_axi_sg_aclk\"\n\t\t\t}\n\t\t\tif { $tx_chan ==1 } {\n\t\t\t\tappend clocknames \" \" \"m_axi_mm2s_aclk\"\n\t\t\t}\n\t\t\tif { $rx_chan ==1 } {\n\t\t\t\tappend clocknames \" \" \"m_axi_s2mm_aclk\"\n\t\t\t}\n\t\t\tgen_dev_ccf_binding $drv_handle \"$clocknames\"\n\t\t\tset_drv_prop_if_empty $drv_handle \"clock-names\" \"$clocknames\" stringlist\n\t\t}\n\t\tdefault {\n\t\t\terror \"Unknown arch\"\n\t\t}\n\t}\n}\n\nproc get_connected_ip {drv_handle dma_pin} {\n global connected_ip\n # Check whether dma is connected to 10G/25G MAC\n # currently we are handling only data fifo\n set intf [::hsi::get_intf_pins -of_objects [get_cells -hier $drv_handle] $dma_pin]\n set valid_eth_list \"xxv_ethernet axi_ethernet axi_10g_ethernet usxgmii ethernet_1_10_25g\"\n if {[string_is_empty ${intf}]} {\n return 0\n }\n set connected_ip [::hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] $intf]\n\n if {[string_is_empty ${connected_ip}]} {\n\tdtg_warning \"$drv_handle connected ip is NULL for the pin $intf\"\n return 0\n }\n set iptype [get_property IP_NAME [get_cells -hier $connected_ip]]\n if {[string match -nocase $iptype \"axis_data_fifo\"] } {\n # here dma connected to data fifo\n set dma_pin \"M_AXIS\"\n get_connected_ip $connected_ip $dma_pin\n } elseif {[lsearch -nocase $valid_eth_list $iptype] >= 0 } {\n # dma connected to 10G/25G MAC, 1G or 10G\n return 1\n } elseif {[string match -nocase $iptype \"axis_add_tuser\"]|| [string match -nocase $iptype \"axis_duplicate_master_out\"]} {\n\t\tset dma_pin \"mas_0\"\n\t\tget_connected_ip $connected_ip $dma_pin\n } elseif {[string match -nocase $iptype \"axis_switch\"]} {\n\t\tset dma_pin \"M00_AXIS\"\n\t\tget_connected_ip $connected_ip $dma_pin\n } else {\n # dma connected via interconnects\n set dma_pin \"M_AXIS\"\n get_connected_ip $connected_ip $dma_pin\n }\n}\n" }, { "path": "axi_emc/data/axi_emc.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_emc\n\n OPTION supported_peripherals = (axi_emc);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_emc;\n OPTION supported_os_types = (DTS);\n DTGPARAM name = dtg.ip_params, type = boolean;\n DTGPARAM name = dev_type, default = flash , type = string;\n DTGPARAM name = compatible, type =stringlist, default = \"cfi-flash\";\n DTGPARAM name = bank-width, type = int;\n\nEND driver\n" }, { "path": "axi_emc/data/axi_emc.tcl", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\n\tset ip [get_cells -hier $drv_handle]\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"cfi-flash\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset count [hsi::utils::get_ip_param_value $ip \"C_NUM_BANKS_MEM\"]\n\tif { [llength $count] == 0 } {\n\t\tset count 1\n\t}\n\tfor {set x 0} { $x < $count} {incr x} {\n\t\tset datawidth [hsi::utils::get_ip_param_value $ip [format \"C_MEM%d_WIDTH\" $x]]\n\t\tset_property bank-width \"[expr ($datawidth/8)]\" $drv_handle\n\t}\n}\n" }, { "path": "axi_ethernet/data/axi_ethernet.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_ethernet\n\n OPTION supported_peripherals = (axi_ethernet axi_ethernet_buffer axi_10g_ethernet xxv_ethernet usxgmii ethernet_1_10_25g);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_ethernet;\n OPTION supported_os_types = (DTS);\n PARAMETER name = dev_type, default = ethernet, type = string;\n DTGPARAM name = dtg.ip_params, type = boolean;\n DTGPARAM name = dtg.alias , type = reference, default = ethernet;\n DTGPARAM name = axistream-connected , type = reference;\n DTGPARAM name = axistream-control-connected, type = reference;\n DTGPARAM name = clock-frequency, type = int, default = 100000000;\n DTGPARAM name = compatible, type =stringlist, default = \"xlnx,axi-ethernet-1.00.a\";\n DTGPARAM name = device_type, type = string, default = network;\n DTGPARAM name = xlnx,txcsum, type = hex, default = 0x0;\n DTGPARAM name = xlnx,rxcsum, type = hex, default = 0x0;\n DTGPARAM name = xlnx,rxmem, type = hex, default = 0x8000;\n DTGPARAM name = xlnx,phyaddr, type = hex, default = 0x0;\n DTGPARAM name = phy-mode, default = gmii\n\nEND driver\n\n\n" }, { "path": "axi_ethernet/data/axi_ethernet.tcl", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nset rxethmem 0\n\nproc generate {drv_handle} {\n global rxethmem\n set rxethmem 0\n global ddrv_handle\n set ddrv_handle $drv_handle\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n set remove_pl [get_property CONFIG.remove_pl [get_os]]\n if {[is_pl_ip $drv_handle] && $remove_pl} {\n return 0\n }\n\n set node [gen_peripheral_nodes $drv_handle]\n set hw_design [hsi::current_hw_design]\n set board_name \"\"\n if {[llength $hw_design]} {\n set board [split [get_property BOARD $hw_design] \":\"]\n set board_name [lindex $board 1]\n }\n update_eth_mac_addr $drv_handle\n set compatible [get_comp_str $drv_handle]\n set compatible [append compatible \" \" \"xlnx,axi-ethernet-1.00.a\"]\n set_drv_prop $drv_handle compatible \"$compatible\" stringlist\n set dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n set default_dts [set_drv_def_dts $drv_handle]\n\n #adding stream connectivity\n set eth_ip [get_cells -hier $drv_handle]\n # search for a valid bus interface name\n # This is required to work with Vivado 2015.1 due to IP PIN naming change\n set hasbuf [get_property CONFIG.processor_mode $eth_ip]\n set ip_name [get_property IP_NAME $eth_ip]\n set num_cores 1\n if {($ip_name == \"xxv_ethernet\") || ($ip_name == \"ethernet_1_10_25g\")} {\n set ip_mem_handles [hsi::utils::get_ip_mem_ranges [get_cells -hier $drv_handle]]\n set num 0\n set base [string tolower [get_property BASE_VALUE [lindex $ip_mem_handles $num]]]\n set high [string tolower [get_property HIGH_VALUE [lindex $ip_mem_handles $num]]]\n set reg [generate_reg_property $base $high]\n hsi::utils::add_new_dts_param \"${node}\" \"reg\" $reg inthexlist\n set num_cores [get_property CONFIG.NUM_OF_CORES [get_cells -hier $drv_handle]]\n }\n set new_label \"\"\n set clk_label \"\"\n set connected_ip \"\"\n set eth_node \"\"\n for {set core 0} {$core < $num_cores} {incr core} {\n if {(($ip_name == \"xxv_ethernet\") || ($ip_name == \"ethernet_1_10_25g\")) && ($core != 0)} {\n if {$dt_overlay} {\n set bus_node \"amba\"\n } else {\n set bus_node \"amba_pl\"\n }\n set dts_file [current_dt_tree]\n\t set ipmem_len [llength $ip_mem_handles]\n\t if {$ipmem_len > 1} {\n set base_addr [string tolower [get_property BASE_VALUE [lindex $ip_mem_handles $core]]]\n regsub -all {^0x} $base_addr {} base_addr\n append new_label $drv_handle \"_\" $core\n append clk_label $drv_handle \"_\" $core\n set eth_node [add_or_get_dt_node -n \"ethernet\" -l \"$new_label\" -u $base_addr -d $dts_file -p $bus_node]\n set base [string tolower [get_property BASE_VALUE [lindex $ip_mem_handles $core]]]\n set high [string tolower [get_property HIGH_VALUE [lindex $ip_mem_handles $core]]]\n set reg [generate_reg_property $base $high]\n hsi::utils::add_new_dts_param \"${eth_node}\" \"reg\" $reg inthexlist\n\t }\n }\n if {(($hasbuf == \"true\") || ($hasbuf == \"\")) && ($ip_name != \"axi_10g_ethernet\") && ($ip_name != \"ten_gig_eth_mac\") && ($ip_name != \"xxv_ethernet\") && ($ip_name != \"usxgmii\") && ($ip_name != \"ethernet_1_10_25g\")} {\n\n foreach n \"AXI_STR_RXD m_axis_rxd\" {\n set intf [get_intf_pins -of_objects $eth_ip ${n}]\n if {[string_is_empty ${intf}] != 1} {\n break\n }\n }\n if { [llength $intf] } {\n set intf_net [get_intf_nets -of_objects $intf ]\n if { [llength $intf_net] } {\n set target_intf [::hsi::utils::get_other_intf_pin $intf_net $intf]\n if { [llength $target_intf] } {\n set connected_ip [get_connectedip $intf]\n\t\tif {[llength $connected_ip]} {\n\t\t\tset_property axistream-connected \"$connected_ip\" $drv_handle\n\t\t\tset_property axistream-control-connected \"$connected_ip\" $drv_handle\n\t\t\tset ip_prop CONFIG.c_include_mm2s_dre\n\t\t\tadd_cross_property $connected_ip $ip_prop $drv_handle \"xlnx,include-dre\" boolean\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle connected ip is NULL for the interface $intf\"\n\t\t}\n set ip_prop CONFIG.Enable_1588\n add_cross_property $eth_ip $ip_prop $drv_handle \"xlnx,eth-hasptp\" boolean\n }\n }\n }\n foreach n \"AXI_STR_RXD m_axis_tx_ts\" {\n set intf [get_intf_pins -of_objects $eth_ip ${n}]\n if {[string_is_empty ${intf}] != 1} {\n break\n }\n }\n\n if {[string_is_empty ${intf}] != 1} {\n set tx_tsip [get_connectedip $intf]\n set_drv_prop $drv_handle axififo-connected \"$tx_tsip\" reference\n }\n } else {\n foreach n \"AXI_STR_RXD m_axis_rx\" {\n set intf [get_intf_pins -of_objects $eth_ip ${n}]\n if {[string_is_empty ${intf}] != 1} {\n break\n }\n }\n\n if {($ip_name == \"xxv_ethernet\") || ($ip_name == \"ethernet_1_10_25g\") || ($ip_name == \"usxgmii\")} {\n \tforeach n \"AXI_STR_RXD axis_rx_0\" {\n set intf [get_intf_pins -of_objects $eth_ip ${n}]\n if {[string_is_empty ${intf}] != 1} {\n break\n }\n }\n }\n\n if { [llength $intf] } {\n set connected_ip [get_connectedip $intf]\n }\n\n foreach n \"AXI_STR_RXD m_axis_tx_ts\" {\n set intf [get_intf_pins -of_objects $eth_ip ${n}]\n if {[string_is_empty ${intf}] != 1} {\n break\n }\n }\n\n if {[string_is_empty ${intf}] != 1} {\n set tx_tsip [get_connectedip $intf]\n\tif {[llength $tx_tsip]} {\n set_drv_prop $drv_handle axififo-connected \"$tx_tsip\" reference\n\t}\n } else {\n set port_pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $eth_ip] \"tx_ptp_tag_field_in_0\"]]\n\tif {[llength $port_pins]} {\n set periph [::hsi::get_cells -of_objects $port_pins]\n if {[llength $periph]} {\n if {[string match -nocase [get_property IP_NAME $periph] \"xlslice\"]} {\n set intf \"Din\"\n set in1_pin [::hsi::get_pins -of_objects $periph -filter \"NAME==$intf\"]\n set sink_pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $periph] $in1_pin]]\n\t\t if {[llength $sink_pins]} {\n set per [::hsi::get_cells -of_objects $sink_pins]\n if {[llength $per] && [string match -nocase [get_property IP_NAME $per] \"axis_clock_converter\"]} {\n set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $per] \"s_axis_tdata\"]]\n if {[llength $pins]} {\n set txfifo [get_cells -of_objects $pins]\n if {[llength $txfifo]} {\n set_drv_prop $drv_handle axififo-connected \"$txfifo\" reference\n }\n }\n }\n }\n }\n }\n }\n }\n set rxfifo_port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $eth_ip] \"rx_ptp_tstamp_out_0\"]]\n if {[llength $rxfifo_port_pins]} {\n set periph [::hsi::get_cells -of_objects $rxfifo_port_pins]\n if {[llength $periph]} {\n if {[string match -nocase [get_property IP_NAME $periph] \"xlconcat\"]} {\n set intf \"dout\"\n set in1_pin [::hsi::get_pins -of_objects $periph -filter \"NAME==$intf\"]\n set sink_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $periph] $in1_pin]]\n if {[llength $sink_pins]} {\n set per [::hsi::get_cells -of_objects $sink_pins]\n if {[llength $per] && [string match -nocase [get_property IP_NAME $per] \"axis_dwidth_converter\"]} {\n set con_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $per] \"M_AXIS\"]\n if {[llength $con_ip]} {\n if {[string match -nocase [get_property IP_NAME $con_ip] \"axis_clock_converter\"]} {\n set rxtsfifo_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $con_ip] \"M_AXIS\"]\n if {[llength $rxtsfifo_ip]} {\n set_drv_prop $drv_handle xlnx,rxtsfifo \"$rxtsfifo_ip\" reference\n }\n }\n }\n }\n }\n }\n }\n }\n if {![string_is_empty $connected_ip]} {\n set_property axistream-connected \"$connected_ip\" $drv_handle\n set_property axistream-control-connected \"$connected_ip\" $drv_handle\n set ip_prop CONFIG.c_include_mm2s_dre\n add_cross_property $connected_ip $ip_prop $drv_handle \"xlnx,include-dre\" boolean\n }\n set_property xlnx,rxmem \"$rxethmem\" $drv_handle\n if {(($ip_name == \"xxv_ethernet\") || ($ip_name == \"ethernet_1_10_25g\")) && ($core != 0)} {\n set intf [get_intf_pins -of_objects $eth_ip \"axis_rx_${core}\"]\n if {[llength $intf] && [llength $eth_node]} {\n set connected_ip [get_connectedip $intf]\n if {![string_is_empty $connected_ip]} {\n hsi::utils::add_new_dts_param $eth_node \"axistream-connected\" \"$connected_ip\" reference\n hsi::utils::add_new_dts_param $eth_node \"axistream-control-connected\" \"$connected_ip\" reference\n }\n hsi::utils::add_new_dts_param $eth_node \"xlnx,include-dre\" \"\" boolean\n hsi::utils::add_new_dts_param $eth_node \"xlnx,rxmem\" \"$rxethmem\" hex\n }\n }\n }\n\n if {$ip_name == \"axi_ethernet\"} {\n\tset txcsum [get_property CONFIG.TXCSUM $eth_ip]\n\tset txcsum [get_checksum $txcsum]\n\tset rxcsum [get_property CONFIG.RXCSUM $eth_ip]\n\tset rxcsum [get_checksum $rxcsum]\n\tset phytype [get_property CONFIG.PHY_TYPE $eth_ip]\n\tset phytype [get_phytype $phytype]\n\tset phyaddr [get_property CONFIG.PHYADDR $eth_ip]\n\tset phyaddr [::hsi::utils::convert_binary_to_decimal $phyaddr]\n\tset rxmem [get_property CONFIG.RXMEM $eth_ip]\n\tset rxmem [get_memrange $rxmem]\n\tset_property xlnx,txcsum \"$txcsum\" $drv_handle\n\tset_property xlnx,rxcsum \"$rxcsum\" $drv_handle\n\tset_property xlnx,phyaddr \"$phyaddr\" $drv_handle\n\tset_property xlnx,rxmem \"$rxmem\" $drv_handle\n }\n\n set is_nobuf 0\n if {$ip_name == \"axi_ethernet\"} {\n set avail_param [list_property [get_cells -hier $drv_handle]]\n if {[lsearch -nocase $avail_param \"CONFIG.speed_1_2p5\"] >= 0} {\n if {[get_property CONFIG.speed_1_2p5 [get_cells -hier $drv_handle]] == \"2p5G\"} {\n set is_nobuf 1\n set_property compatible \"xlnx,axi-2_5-gig-ethernet-1.0\" $drv_handle\n }\n }\n }\n\n if { $hasbuf == \"false\" && $is_nobuf == 0} {\n\t set ip_prop CONFIG.processor_mode\n\t add_cross_property $eth_ip $ip_prop $drv_handle \"xlnx,eth-hasnobuf\" boolean\n }\n\n #adding clock frequency\n set clk [get_pins -of_objects $eth_ip \"S_AXI_ACLK\"]\n if {[llength $clk] } {\n set freq [get_property CLK_FREQ $clk]\n set_property clock-frequency \"$freq\" $drv_handle\n if {$ip_name == \"xxv_ethernet\" && [llength $eth_node]} {\n hsi::utils::add_new_dts_param $eth_node \"clock-frequency\" \"$freq\" int\n }\n }\n\n # node must be created before child node\n set node [gen_peripheral_nodes $drv_handle]\n if {$ip_name == \"axi_ethernet\"} {\n\tset hier_params [gen_hierip_params $drv_handle]\n }\n set mdio_node [gen_mdio_node $drv_handle $node]\n\n\n set phytype [string tolower [get_property CONFIG.PHY_TYPE $eth_ip]]\n if {$phytype == \"rgmii\" && $board_name == \"kc705\"} {\n set phytype \"rgmii-rxid\"\n } elseif {$phytype == \"1000basex\"} {\n set phytype \"1000base-x\"\n }\n set_property phy-mode \"$phytype\" $drv_handle\n if {$phytype == \"sgmii\" || $phytype == \"1000base-x\"} {\n set_property phy-mode \"$phytype\" $drv_handle\n\t set phynode [pcspma_phy_node $eth_ip]\n\t set phya [lindex $phynode 0]\n\t if { $phya != \"-1\"} {\n\t\tset phy_name \"[lindex $phynode 1]\"\n\t set_drv_prop $drv_handle pcs-handle \"$drv_handle$phy_name\" reference\n\t\tgen_phy_node $mdio_node $phy_name $phya $drv_handle\n\t\tif {[llength $node]} {\n\t\t\thsi::utils::add_new_dts_param $node \"managed\" \"in-band-status\" string\n\t\t\thsi::utils::add_new_dts_param $node \"xlnx,switch-x-sgmii\" \"\" boolean\n\t\t}\n\t }\n }\n if {$ip_name == \"xxv_ethernet\" && $core != 0 && [llength $eth_node]} {\n append new_label \"_\" mdio\n set mdionode [add_or_get_dt_node -l \"$new_label\" -n mdio -p $eth_node]\n hsi::utils::add_new_dts_param \"${mdionode}\" \"#address-cells\" 1 int \"\"\n hsi::utils::add_new_dts_param \"${mdionode}\" \"#size-cells\" 0 int \"\"\n set new_label \"\"\n }\n if {$ip_name == \"axi_10g_ethernet\"} {\n set phytype [string tolower [get_property CONFIG.base_kr $eth_ip]]\n set_property phy-mode \"$phytype\" $drv_handle\n set compatible [get_comp_str $drv_handle]\n set compatible [append compatible \" \" \"xlnx,ten-gig-eth-mac\"]\n set_property compatible \"$compatible\" $drv_handle\n }\n if {$ip_name == \"xxv_ethernet\"} {\n set phytype [string tolower [get_property CONFIG.BASE_R_KR $eth_ip]]\n set linerate [get_property CONFIG.LINE_RATE $eth_ip]\n set_property phy-mode \"${linerate}g${phytype}\" $drv_handle\n set compatible [get_comp_str $drv_handle]\n set compatible [append compatible \" \" \"xlnx,xxv-ethernet-1.0\"]\n set_property compatible \"$compatible\" $drv_handle\n set_property \"managed\" \"in-band-status\" $drv_handle\n if { $core!= 0 && [llength $eth_node]} {\n hsi::utils::add_new_dts_param $eth_node \"compatible\" $compatible stringlist\n hsi::utils::add_new_dts_param $eth_node \"phy-mode\" \"${linerate}g${phytype}\" string\n hsi::utils::add_new_dts_param $eth_node \"managed\" \"in-band-status\" string\n }\n }\n if {$ip_name == \"usxgmii\"} {\n set compatible [get_comp_str $drv_handle]\n set compatible [append compatible \" \" \"xlnx,xxv-usxgmii-ethernet-1.0\"]\n set_property compatible $compatible $drv_handle\n # phy-mode is usxgmii in this case ip_name also same\n set_property phy-mode \"$ip_name\" $drv_handle\n hsi::utils::add_new_dts_param $node \"xlnx,usxgmii-rate\" 1000 int\n }\n set ips [get_cells -hier $drv_handle]\n foreach ip [get_drivers] {\n if {[string compare -nocase $ip $connected_ip] == 0} {\n set target_handle $ip\n }\n }\n set hsi_version [get_hsi_version]\n set ver [split $hsi_version \".\"]\n set version [lindex $ver 0]\n if {![string_is_empty $connected_ip]} {\n set connected_ipname [get_property IP_NAME $connected_ip]\n if {$connected_ipname == \"axi_mcdma\" || $connected_ipname == \"axi_dma\"} {\n set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n set num_queues [get_property CONFIG.c_num_mm2s_channels $connected_ip]\n set inhex [format %x $num_queues]\n set numqueues \"/bits/ 16 <0x$inhex>\"\n hsi::utils::add_new_dts_param $node \"xlnx,num-queues\" $numqueues noformating\n if {$version < 2018} {\n dtg_warning \"quotes to be removed or use 2018.1 version for $node param xlnx,num-queues\"\n }\n set id 1\n for {set i 2} {$i <= $num_queues} {incr i} {\n set i [format \"%x\" $i]\n append id \"\\\"\"\n append id \",\\\"\" $i\n set i [expr 0x$i]\n }\n set_drv_prop $drv_handle \"xlnx,channel-ids\" $id stringlist\n if {$ip_name == \"xxv_ethernet\" && $core!= 0 && [llength $eth_node]} {\n hsi::utils::add_new_dts_param $eth_node \"xlnx,num-queues\" $numqueues noformating\n hsi::utils::add_new_dts_param $eth_node \"xlnx,channel-ids\" $id stringlist\n }\n set intr_val [get_property CONFIG.interrupts $target_handle]\n set intr_parent [get_property CONFIG.interrupt-parent $target_handle]\n set int_names [get_property CONFIG.interrupt-names $target_handle]\n if { $hasbuf == \"true\" && $ip_name == \"axi_ethernet\"} {\n set intr_val1 [get_property CONFIG.interrupts $drv_handle]\n lappend intr_val1 $intr_val\n\t\tset intr_name [get_property CONFIG.interrupt-names $drv_handle]\n\t\tappend intr_names \" \" $intr_name \" \" $int_names\n\t\tif {![string match -nocase $proctype \"microblaze\"]} {\n\t\t set null \"\"\n\t set_property \"interrupt-names\" $null $drv_handle\n\t set_property \"interrupts\" $null $drv_handle\n\t\t}\n } else {\n\t\tset intr_names $int_names\n\t }\n if {![string_is_empty $intr_parent]} {\n if {(($ip_name == \"xxv_ethernet\") || ($ip_name == \"ethernet_1_10_25g\")) && ($core!= 0) && [llength $eth_node]} {\n hsi::utils::add_new_dts_param \"${eth_node}\" \"interrupts\" $intr_val int\n hsi::utils::add_new_dts_param \"${eth_node}\" \"interrupt-parent\" $intr_parent reference\n hsi::utils::add_new_dts_param \"${eth_node}\" \"interrupt-names\" $intr_names stringlist\n } else {\n\t\t\tif { $hasbuf == \"true\" && $ip_name == \"axi_ethernet\"} {\n\t\t\t\tregsub -all \"\\{||\\t\" $intr_val1 {} intr_val1\n\t\t\t\tregsub -all \"\\}||\\t\" $intr_val1 {} intr_val1\n\t\t\t\tif {![string match -nocase $proctype \"microblaze\"]} {\n\t\t\t\t set_property \"interrupts\" $intr_val1 $drv_handle\n\t\t\t\t set_property \"interrupt-names\" $intr_names $drv_handle\n\t\t\t\t}\n\t\t\t\thsi::utils::add_new_dts_param \"${node}\" \"interrupts\" $intr_val1 int\n\t\t\t} else {\n\t\t\t\thsi::utils::add_new_dts_param \"${node}\" \"interrupts\" $intr_val int\n\t\t\t}\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"interrupt-parent\" $intr_parent reference\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"interrupt-names\" $intr_names stringlist\n\t\t}\n }\n }\n if {$connected_ipname == \"axi_dma\" || $connected_ipname == \"axi_mcdma\"} {\n\t set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t if {![string match -nocase $proctype \"microblaze\"]} {\n set eth_clk_names [get_property CONFIG.clock-names $drv_handle]\n set eth_clks [get_property CONFIG.clocks $drv_handle]\n\t\tif {(($ip_name == \"xxv_ethernet\") || ($ip_name == \"ethernet_1_10_25g\")) && ($core == 0)} {\n\t\t\tset_property \"zclocks\" $eth_clks $drv_handle\n\t\t\tset_drv_prop $drv_handle \"zclock-names\" $eth_clk_names stringlist\n\t\t}\n\t\tif {(($ip_name == \"xxv_ethernet\") || ($ip_name == \"ethernet_1_10_25g\")) && ($core != 0)} {\n\t\t\tset eth_clks [get_property CONFIG.zclocks $drv_handle]\n\t\t\tset eth_clk_names [get_property CONFIG.zclock-names $drv_handle]\n\t\t}\n set eth_clkname_len [llength $eth_clk_names]\n set i 0\n set dclk \"\"\n while {$i < $eth_clkname_len} {\n set clkname [lindex $eth_clk_names $i]\n for {set corenum 0} {$corenum < $num_cores} {incr corenum} {\n if {[string match -nocase $clkname \"rx_core_clk_$corenum\"]} {\n set core_clk_$corenum \"rx_core_clk\"\n set index_$corenum $i\n }\n if {[string match -nocase $clkname \"s_axi_aclk_$corenum\"]} {\n set axi_aclk_$corenum \"s_axi_aclk\"\n set axi_index_$corenum $i\n }\n if {[string match -nocase $clkname \"dclk\"]} {\n set dclk \"dclk\"\n set dclk_index $i\n }\n }\n incr i\n }\n set eth_clk_len [expr {[llength [split $eth_clks \",\"]]}]\n set clk_list [split $eth_clks \",\"]\n set clk_names [get_property CONFIG.clock-names $target_handle]\n set clks [get_property CONFIG.clocks $target_handle]\n append names \"$eth_clk_names\" \"$clk_names\"\n set names \"\"\n append clk \"$eth_clks>,\" \"<&$clks\"\n set null \"\"\n set_property \"clock-names\" $null $drv_handle\n set_property \"clocks\" $null $drv_handle\n if {(($ip_name == \"xxv_ethernet\") || ($ip_name == \"ethernet_1_10_25g\")) && ($core== 0)} {\n\t\t if {[llength $dclk]} {\n lappend clknames \"$core_clk_0\" \"$dclk\" \"$axi_aclk_0\"\n\t\t } else {\n lappend clknames \"$core_clk_0\" \"$axi_aclk_0\"\n\t\t }\n append clknames1 \"$clknames\" \"$clk_names\"\n set index0 [lindex $clk_list $axi_index_0]\n regsub -all \"\\>||\\t\" $index0 {} index0\n\t\t set ini0 [lindex $clk_list $index_0]\n\t\t regsub -all \" \" $ini0 \"\" ini0\n\t\t regsub -all \"\\<&||\\t\" $ini0 {} ini0\n\t\t if {[llength $dclk]} {\n\t\t\tset dclk_ini [lindex $clk_list $dclk_index]\n\t\t\tset dclk_ini [string trim $dclk_ini]\n\t\t\tif {![string match -nocase \"<&*\" \"$dclk_ini\"]} {\n\t\t\t\tset dclk_ini \"<&$dclk_ini\"\n\t\t\t}\n\t\t\tappend clkvals \"$ini0, $dclk_ini, $index0>, <&$clks\"\n\t\t } else {\n\t\t\tappend clkvals \"$ini0, $index0>, <&$clks\"\n\t\t }\n set_property \"clocks\" $clkvals $drv_handle\n set_property \"clock-names\" $clknames1 $drv_handle\n set clknames1 \"\"\n }\n if {(($ip_name == \"xxv_ethernet\") || ($ip_name == \"ethernet_1_10_25g\")) && ($core == 1) && [llength $eth_node]} {\n\t\t if {[llength $dclk]} {\n lappend clknames1 \"$core_clk_1\" \"$dclk\" \"$axi_aclk_1\"\n\t\t } else {\n lappend clknames1 \"$core_clk_1\" \"$axi_aclk_1\"\n\t\t }\n append clk_names1 \"$clknames1\" \"$clk_names\"\n set index1 [lindex $clk_list $axi_index_1]\n regsub -all \"\\>||\\t\" $index1 {} index1\n set ini1 [lindex $clk_list $index_1]\n regsub -all \" \" $ini1 \"\" ini1\n regsub -all \"\\<&||\\t\" $ini1 {} ini1\n\t\t if {[llength $dclk]} {\n\t\t\tset dclk_ini1 [lindex $clk_list $dclk_index]\n\t\t\tset dclk_ini1 [string trim $dclk_ini1]\n\t\t\tif {![string match -nocase \"<&*\" \"$dclk_ini1\"]} {\n\t\t\t\tset dclk_ini1 \"<&$dclk_ini1\"\n\t\t\t}\n\t\t\tappend clkvals1 \"$ini1, $dclk_ini1, $index1>, <&$clks\"\n\t\t } else {\n\t\t\tappend clkvals1 \"$ini1, $index1>, <&$clks\"\n\t\t }\n hsi::utils::add_new_dts_param \"${eth_node}\" \"clocks\" $clkvals1 reference\n hsi::utils::add_new_dts_param \"${eth_node}\" \"clock-names\" $clk_names1 stringlist\n set clk_names1 \"\"\n set clkvals1 \"\"\n }\n if {(($ip_name == \"xxv_ethernet\") || ($ip_name == \"ethernet_1_10_25g\")) && ($core == 2) && [llength $eth_node]} {\n\t\t if {[llength $dclk]} {\n lappend clknames2 \"$core_clk_2\" \"$dclk\" \"$axi_aclk_2\"\n\t\t } else {\n lappend clknames2 \"$core_clk_2\" \"$axi_aclk_2\"\n\t\t }\n append clk_names2 \"$clknames2\" \"$clk_names\"\n set index2 [lindex $clk_list $axi_index_2]\n regsub -all \"\\>||\\t\" $index2 {} index2\n set ini2 [lindex $clk_list $index_2]\n regsub -all \" \" $ini2 \"\" ini2\n regsub -all \"\\<&||\\t\" $ini2 {} ini2\n\t\t if {[llength $dclk]} {\n\t\t\tset dclk_ini2 [lindex $clk_list $dclk_index]\n\t\t\tset dclk_ini2 [string trim $dclk_ini2]\n\t\t\tif {![string match -nocase \"<&*\" \"$dclk_ini2\"]} {\n\t\t\t\tset dclk_ini2 \"<&$dclk_ini2\"\n\t\t\t}\n\t\t\tappend clkvals2 \"$ini2, $dclk_ini2, $index2>, <&$clks\"\n\t\t } else {\n\t\t\tappend clkvals2 \"$ini2, $index2>, <&$clks\"\n\t\t }\n append clk_label2 $drv_handle \"_\" $core\n hsi::utils::add_new_dts_param \"${eth_node}\" \"clocks\" $clkvals2 reference\n hsi::utils::add_new_dts_param \"${eth_node}\" \"clock-names\" $clk_names2 stringlist\n set clk_names2 \"\"\n set clkvals2 \"\"\n }\n if {(($ip_name == \"xxv_ethernet\") || ($ip_name == \"ethernet_1_10_25g\")) && ($core == 3) && [llength $eth_node]} {\n\t\t if {[llength $dclk]} {\n lappend clknames3 \"$core_clk_3\" \"$dclk\" \"$axi_aclk_3\"\n\t\t } else {\n lappend clknames3 \"$core_clk_3\" \"$axi_aclk_3\"\n\t\t }\n append clk_names3 \"$clknames3\" \"$clk_names\"\n set index3 [lindex $clk_list $axi_index_3]\n regsub -all \"\\>||\\t\" $index3 {} index3\n set ini [lindex $clk_list $index_3]\n regsub -all \" \" $ini \"\" ini\n regsub -all \"\\<&||\\t\" $ini {} ini\n\t\t if {[llength $dclk]} {\n\t\t\tset dclk_ini3 [lindex $clk_list $dclk_index]\n\t\t\tset dclk_ini3 [string trim $dclk_ini3]\n\t\t\tif {![string match -nocase \"<&*\" \"$dclk_ini3\"]} {\n\t\t\t\tset dclk_ini3 \"<&$dclk_ini3\"\n\t\t\t}\n\t\t\tappend clkvals3 \"$ini, $dclk_ini3, $index3>, <&$clks\"\n\t\t } else {\n\t\t\tappend clkvals3 \"$ini, $index3>, <&$clks\"\n\t\t }\n append clk_label3 $drv_handle \"_\" $core\n hsi::utils::add_new_dts_param \"${eth_node}\" \"clocks\" $clkvals3 reference\n hsi::utils::add_new_dts_param \"${eth_node}\" \"clock-names\" $clk_names3 stringlist\n set clk_names3 \"\"\n set clkvals3 \"\"\n }\n\t }\n }\n }\n if {(($ip_name == \"xxv_ethernet\") || ($ip_name == \"ethernet_1_10_25g\")) && ($core!= 0) && [llength $eth_node]} {\n gen_drv_prop_eth_ip $drv_handle $eth_node\n }\n gen_dev_ccf_binding $drv_handle \"s_axi_aclk\"\n }\n set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n if {![string match -nocase $proctype \"microblaze\"]} {\n set null \"NULL\"\n set_property \"zclock-names\" $null $drv_handle\n set_property \"zclocks\" \"$null\" $drv_handle\n }\n}\n\nproc pcspma_phy_node {slave} {\n\tset phyaddr [get_property CONFIG.PHYADDR $slave]\n\tset phyaddr [::hsi::utils::convert_binary_to_decimal $phyaddr]\n\tset phymode \"phy$phyaddr\"\n\n\treturn \"$phyaddr $phymode\"\n}\n\nproc get_checksum {value} {\n if {[string compare -nocase $value \"None\"] == 0} {\n set value 0\n } elseif {[string compare -nocase $value \"Partial\"] == 0} {\n set value 1\n } else {\n set value 2\n }\n\n return $value\n}\n\nproc get_memrange {value} {\n\tset values [split $value \"k\"]\n\tlassign $values value1 value2\n\n\treturn [expr $value1 * 1024]\n}\n\nproc get_phytype {value} {\n if {[string compare -nocase $value \"MII\"] == 0} {\n set value 0\n } elseif {[string compare -nocase $value \"GMII\"] == 0} {\n set value 1\n } elseif {[string compare -nocase $value \"RGMII\"] == 0} {\n set value 3\n } elseif {[string compare -nocase $value \"SGMII\"] == 0} {\n set value 4\n } else {\n set value 5\n }\n\n return $value\n}\n\nproc gen_hierip_params {drv_handle} {\n\tset prop_name_list [deault_parameters $drv_handle]\n foreach prop_name ${prop_name_list} {\n ip2drv_prop $drv_handle $prop_name\n }\n}\n\nproc deault_parameters {ip_handle {dont_generate \"\"}} {\n set par_handles [get_ip_conf_prop_list $ip_handle \"CONFIG.*\"]\n set valid_prop_names {}\n foreach par $par_handles {\n regsub -all {CONFIG.} $par {} tmp_par\n # Ignore some parameters that are always handled specially\n switch -glob $tmp_par {\n $dont_generate - \\\n \"Component_Name\" - \\\n\t\t\t\"DIFFCLK_BOARD_INTERFACE\" - \\\n\t\t\t\"EDK_IPTYPE\" - \\\n\t\t\t\"ETHERNET_BOARD_INTERFACE\" - \\\n\t\t\t\"Include_IO\" - \\\n\t\t\t\"PHY_TYPE\" - \\\n\t\t\t\"RXCSUM\" - \\\n\t\t\t\"TXCSUM\" - \\\n\t\t\t\"TXMEM\" - \\\n\t\t\t\"RXMEM\" - \\\n\t\t\t\"PHYADDR\" - \\\n\t\t\t\"C_BASEADDR\" - \\\n\t\t\t\"C_HIGHADDR\" - \\\n\t\t\t\"processor_mode\" - \\\n\t\t\t\"ENABLE_AVB\" - \\\n\t\t\t\"ENABLE_LVDS\" - \\\n\t\t\t\"Enable_1588_1step\" - \\\n\t\t\t\"Enable_1588\" - \\\n\t\t\t\"speed_1_2p5\" - \\\n\t\t\t\"lvdsclkrate\" - \\\n\t\t\t\"gtrefclkrate\" - \\\n\t\t\t\"drpclkrate\" - \\\n\t\t\t\"Enable_Pfc\" - \\\n\t\t\t\"Frame_Filter\" - \\\n\t\t\t\"MCAST_EXTEND\" - \\\n\t\t\t\"MDIO_BOARD_INTERFACE\" - \\\n\t\t\t\"Number_of_Table_Entries\" - \\\n\t\t\t\"PHYRST_BOARD_INTERFACE\" - \\\n\t\t\t\"RXVLAN_STRP\" - \\\n\t\t\t\"RXVLAN_TAG\" - \\\n\t\t\t\"RXVLAN_TRAN\" - \\\n\t\t\t\"TXVLAN_STRP\" - \\\n\t\t\t\"TXVLAN_TAG\" - \\\n\t\t\t\"TXVLAN_TRAN\" - \\\n\t\t\t\"SIMULATION_MODE\" - \\\n\t\t\t\"Statistics_Counters\" - \\\n\t\t\t\"Statistics_Reset\" - \\\n\t\t\t\"Statistics_Width\" - \\\n\t\t\t\"SupportLevel\" - \\\n\t\t\t\"TIMER_CLK_PERIOD\" - \\\n\t\t\t\"Timer_Format\" - \\\n\t\t\t\"SupportLevel\" - \\\n\t\t\t\"TransceiverControl\" - \\\n\t\t\t\"USE_BOARD_FLOW\" - \\\n \"HW_VER\" { } \\\n default {\n lappend valid_prop_names $par\n }\n }\n }\n return $valid_prop_names\n}\n\nproc gen_phy_node args {\n set mdio_node [lindex $args 0]\n set phy_name [lindex $args 1]\n set phya [lindex $args 2]\n set drv [lindex $args 3]\n\n set phy_node [add_or_get_dt_node -l $drv$phy_name -n phy -u $phya -p $mdio_node]\n hsi::utils::add_new_dts_param \"${phy_node}\" \"reg\" $phya int\n hsi::utils::add_new_dts_param \"${phy_node}\" \"device_type\" \"ethernet-phy\" string\n\n return $phy_node\n}\n\nproc is_ethsupported_target {connected_ip} {\n set connected_ipname [get_property IP_NAME $connected_ip]\n if {$connected_ipname == \"axi_dma\" || $connected_ipname == \"axi_fifo_mm_s\" || $connected_ipname == \"axi_mcdma\"} {\n return \"true\"\n } else {\n return \"false\"\n }\n}\n\nproc get_targetip {ip} {\n global ddrv_handle\n if {[string_is_empty $ip] != 0} {\n return\n }\n set p2p_busifs_i [get_intf_pins -of_objects $ip -filter \"TYPE==INITIATOR || TYPE==MASTER\"]\n set target_periph \"\"\n foreach p2p_busif $p2p_busifs_i {\n set busif_name [string toupper [get_property NAME $p2p_busif]]\n set conn_busif_handle [::hsi::utils::get_connected_intf $ip $busif_name]\n if {[string_is_empty $conn_busif_handle] != 0} {\n continue\n }\n set target_periph [get_cells -of_objects $conn_busif_handle]\n set cell_name [get_cells -hier $target_periph]\n set target_name [get_property IP_NAME [get_cells -hier $target_periph]]\n if {$target_name == \"axis_data_fifo\" || $target_name == \"Ethernet_filter\"} {\n #set target_periph [get_cells -of_objects $conn_busif_handle]\n set master_slaves [get_intf_pins -of [get_cells -hier $cell_name]]\n if {[llength $master_slaves] == 0} {\n return\n }\n set master_intf \"\"\n foreach periph_intf $master_slaves {\n set prop [get_property TYPE $periph_intf]\n if {$prop == \"INITIATOR\"} {\n set master_intf $periph_intf\n }\n }\n if {[llength $master_intf] == 0} {\n return\n }\n set intf [get_intf_pins -of_objects $cell_name $master_intf]\n set intf_net [get_intf_nets -of_objects $intf]\n set intf_pins [::hsi::utils::get_other_intf_pin $intf_net $intf]\n foreach intf $intf_pins {\n set target_intf [get_intf_pins -of_objects $intf_net -filter \"TYPE==TARGET\" $intf]\n if {[llength $target_intf]} {\n set connected_ip [get_cells -of_objects $target_intf]\n if {[llength $connected_ip]} {\n set cell [get_cells -hier $connected_ip]\n set target_name [get_property IP_NAME [get_cells -hier $cell]]\n if {$target_name == \"axis_data_fifo\"} {\n return [get_targetip $connected_ip]\n }\n if {![string_is_empty $connected_ip] && [is_ethsupported_target $connected_ip] == \"true\"} {\n return $connected_ip\n }\n } else {\n dtg_warning \"$ddrv_handle connected ip is NULL for the target intf $target_intf\"\n }\n } else {\n dtg_warning \"$ddrv_handle target interface is NULL for the intf pin $intf\"\n }\n }\n }\n }\n return $target_periph\n}\n\nproc get_connectedip {intf} {\n global rxethmem\n if { [llength $intf]} {\n set connected_ip \"\"\n set intf_net [get_intf_nets -of_objects $intf ]\n if { [llength $intf_net] } {\n set target_intf [::hsi::utils::get_other_intf_pin $intf_net $intf]\n if { [llength $target_intf] } {\n set connected_ip [get_cells -of_objects $target_intf]\n if {[llength $connected_ip]} {\n set target_ipname [get_property IP_NAME $connected_ip]\n if {$target_ipname == \"ila\"} {\n return\n }\n if {$target_ipname == \"axis_data_fifo\"} {\n set fifo_width_bytes [get_property CONFIG.TDATA_NUM_BYTES $connected_ip]\n if {[string_is_empty $fifo_width_bytes]} {\n set fifo_width_bytes 1\n }\n set rxethmem [get_property CONFIG.FIFO_DEPTH $connected_ip]\n # FIFO can be other than 8 bits, and we need the rxmem in bytes\n set rxethmem [expr $rxethmem * $fifo_width_bytes]\n } else {\n\t # In 10G MAC case if the rx_stream interface is not connected to\n\t # a Stream-fifo set the rxethmem value to a default jumbo MTU size\n\t set rxethmem 9600\n\t }\n } else {\n dtg_warning \"$drv_handle connected_ip is NULL for the target_intf $target_intf\"\n }\n }\n\tif {[string_is_empty $connected_ip]} {\n\t\treturn \"\"\n\t}\n set target_ip [is_ethsupported_target $connected_ip]\n if { $target_ip == \"true\"} {\n return $connected_ip\n } else {\n set i 0\n set retries 5\n # When AXI Ethernet Configured in Non-Buf mode or In case of 10G MAC\n # The Ethernet MAC won't directly got connected to fifo or dma\n # We need to traverse through stream data fifo's and axi interconnects\n # Inorder to find the target IP(AXI DMA or AXI FIFO)\n while {$i < $retries} {\n set target_ip \"false\"\n set target_periph [get_targetip $connected_ip]\n if {[string_is_empty $target_periph] == 0} {\n set target_ip [is_ethsupported_target $target_periph]\n }\n if { $target_ip == \"true\"} {\n return $target_periph\n }\n set connected_ip $target_periph\n incr i\n }\n dtg_warning \"Couldn't find a valid target_ip Please cross check hw design\"\n }\n }\n }\n}\n\nproc gen_drv_prop_eth_ip {drv_handle ipname} {\n set prop_name_list [default_parameters $drv_handle]\n foreach prop_name ${prop_name_list} {\n ip2_prop $ipname $prop_name $drv_handle\n }\n}\n\nproc ip2_prop {ip_name ip_prop_name drv_handle} {\n set drv_prop_name $ip_prop_name\n regsub -all {CONFIG.C_} $drv_prop_name {xlnx,} drv_prop_name\n regsub -all {_} $drv_prop_name {-} drv_prop_name\n set drv_prop_name [string tolower $drv_prop_name]\n set value [get_property ${ip_prop_name} [get_cells -hier $drv_handle]]\n if {[llength $value]} {\n if {$value != \"-1\" && [llength $value] !=0} {\n set type \"hex\"\n if {[string equal -nocase $type \"boolean\"]} {\n if {[expr $value < 1]} {\n return 0\n }\n set value \"\"\n }\n if {[regexp \"(int|hex).*\" $type match]} {\n regsub -all {\"} $value \"\" value\n }\n hsi::utils::add_new_dts_param \"$ip_name\" \"$drv_prop_name\" $value $type\n return 0\n }\n }\n}\n" }, { "path": "axi_gpio/data/gpio.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver gpio\n\n OPTION supported_peripherals = (axi_gpio);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = gpio;\n PARAMETER name = dev_type, default = gpio, type = string;\n DTGPARAM name = dtg.ip_params, type = boolean;\n DTGPARAM name = gpio-controller, type = boolean;\n DTGPARAM name = compatible, default = \"xlnx,xps-gpio-1.00.a\", type = stringlist;\n DTGPARAM name = \"#gpio-cells\", default = 2, type = int;\n DTGPARAM name = dtg.device_type, default = gpio, type = string;\nEND driver\n" }, { "path": "axi_gpio/data/gpio.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,xps-gpio-1.00.a\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset intr_present [get_property CONFIG.C_INTERRUPT_PRESENT [get_cells -hier $drv_handle]]\n\tif {[string match $intr_present \"1\"]} {\n\t\tset node [gen_peripheral_nodes $drv_handle]\n\t\tif {$node != 0} {\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"#interrupt-cells\" 2 int \"\"\n\t\t}\n\t\thsi::utils::add_new_property $drv_handle \"interrupt-controller\" boolean \"\"\n\t}\n\tset proc_type [get_sw_proc_prop IP_NAME]\n\tswitch $proc_type {\n\t\t\"microblaze\" {\n\t\t\tgen_dev_ccf_binding $drv_handle \"s_axi_aclk\"\n\t\t\tset_drv_prop_if_empty $drv_handle \"clock-names\" \"s_axi_aclk\" stringlist\n\t\t}\n\t}\n\t#Workaround: There is no unique way to differentiate the gt_ctrl, so hardcoding the size\n\t#for the address 0xa4010000 to 0x40000\n\tset ips [get_cells -hier -filter {IP_NAME == \"mrmac\"}]\n\tif {[llength $ips]} {\n\t\tset mem_ranges [hsi::utils::get_ip_mem_ranges [get_cells -hier $drv_handle]]\n\t\tforeach mem_range $mem_ranges {\n\t\t\tset base_addr [string tolower [get_property BASE_VALUE $mem_range]]\n\t\t\tset high_addr [string tolower [get_property HIGH_VALUE $mem_range]]\n\t\t\tif {[string match -nocase $base_addr \"0xa4010000\"]} {\n\t\t\t\tset reg \"0x0 0xa4010000 0x0 0x40000\"\n\t\t\t\thsi::utils::add_new_dts_param \"${node}\" \"reg\" $reg inthexlist\n\t\t\t}\n\t\t}\n\t}\n}\n" }, { "path": "axi_iic/data/axi_iic.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_iic\n\n OPTION supported_peripherals = (axi_iic);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_iic;\n PARAMETER name = dev_type, default = i2c, type = string;\n DTGPARAM name = dtg.alias , type = reference, default = i2c;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,xps-iic-2.00.a\";\n DTGPARAM name = \"#address-cells\", default = 1, type = int;\n DTGPARAM name = \"#size-cells\", default = 0, type = int;\n\nEND driver\n" }, { "path": "axi_iic/data/axi_iic.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n set compatible [get_comp_str $drv_handle]\n set compatible [append compatible \" \" \"xlnx,xps-iic-2.00.a\"]\n set_drv_prop $drv_handle compatible \"$compatible\" stringlist\n set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n if {[string match -nocase $proctype \"microblaze\"] } {\n gen_dev_ccf_binding $drv_handle \"s_axi_aclk\"\n }\n}\n" }, { "path": "axi_mcdma/data/axi_mcdma.mdd", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_mcdma\n\n OPTION supported_peripherals = (axi_mcdma);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_mcdma;\n DTGPARAM name = dtg.ip_params, type = boolean;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,axi-mcdma-1.00.a\";\n DTGPARAM name = \"#dma-cells\", type = int, default = 1;\n\nEND driver\n" }, { "path": "axi_mcdma/data/axi_mcdma.tcl", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,axi-mcdma-1.00.a xlnx,eth-dma\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset mcdma_ip [get_cells -hier $drv_handle]\n\tset dma_count [hsi::utils::get_os_parameter_value \"dma_count\"]\n\tif { [llength $dma_count] == 0 } {\n\t\tset dma_count 0\n\t}\n\tset axiethernetfound 0\n\tset connected_ip [hsi::utils::get_connected_stream_ip $mcdma_ip \"M_AXIS_MM2S\"]\n\tif { [llength $connected_ip] } {\n\t\tset connected_ip_type [get_property IP_NAME $connected_ip]\n\t\tif { [string match -nocase $connected_ip_type axi_ethernet ] || [string match -nocase $connected_ip_type axi_ethernet_buffer ] } {\n\t\t\tset axiethernetfound 1\n\t\t}\n\t} else {\n\t\tdtg_warning \"$drv_handle connected ip is NULL for the pin M_AXIS_MM2S\"\n\t}\n\n\tset is_xxv [get_connected_ip $drv_handle \"M_AXIS_MM2S\"]\n\tset is_mrmac [is_mrmac_connected $drv_handle \"M_AXIS_MM2S\"]\n\t# if tsn ip exists in the design then it is through mcdma so changing the compatible string\n\tset tsn_inst_name [get_cells -filter {IP_NAME =~ \"*tsn*\"}]\n\tif { $axiethernetfound || $is_xxv == 1 || $is_mrmac == 1 || [llength $tsn_inst_name] } {\n\t\tset compatstring \"xlnx,eth-dma\"\n\t\tset_property compatible \"$compatstring\" $drv_handle\n\t}\n\tif { $axiethernetfound != 1 && $is_xxv != 1 && $is_mrmac != 1} {\n\t\tset ip_prop CONFIG.c_include_mm2s_dre\n\t\tadd_cross_property $drv_handle $ip_prop $drv_handle \"xlnx,include-dre\" boolean\n\t\tset_drv_conf_prop $drv_handle c_addr_width xlnx,addrwidth\n\t\tset baseaddr [get_baseaddr $mcdma_ip no_prefix]\n\t\tset tx_chan [hsi::utils::get_ip_param_value $mcdma_ip C_INCLUDE_MM2S]\n\t\tif { $tx_chan == 1 } {\n\t\t\tset tx_chan_node [add_dma_channel $drv_handle $node \"axi-dma\" $baseaddr \"MM2S\" $dma_count ]\n\t\t\tset num_mm2s_channles [get_property CONFIG.c_num_mm2s_channels [get_cells -hier $drv_handle]]\n\t\t\tset intr_info [get_interrupt_info $drv_handle \"MM2S\"]\n\t\t\tif { [llength $intr_info] && ![string match -nocase $intr_info \"-1\"] } {\n\t\t\t\thsi::utils::add_new_dts_param $tx_chan_node \"interrupts\" $intr_info intlist\n\t\t\t} else {\n\t\t\t\tdtg_warning \"ERROR: ${drv_handle}: mm2s_introut port is not connected\"\n\t\t\t}\n\t\t\tset intr_parent [get_property CONFIG.interrupt-parent $drv_handle]\n\t\t\tif {[llength $intr_parent]} {\n\t\t\t\thsi::utils::add_new_dts_param \"${tx_chan_node}\" \"interrupt-parent\" $intr_parent reference\n\t\t\t}\n\t\t\tadd_dma_coherent_prop $drv_handle \"M_AXI_MM2S\"\n\t\t}\n\t\tset rx_chan [hsi::utils::get_ip_param_value $mcdma_ip C_INCLUDE_S2MM]\n\t\tif { $rx_chan ==1 } {\n\t\t\tset rx_bassaddr [format %08x [expr 0x$baseaddr + 0x30]]\n\t\t\tset rx_chan_node [add_dma_channel $drv_handle $node \"axi-dma\" $rx_bassaddr \"S2MM\" $dma_count]\n\t\t\tset intr_info [get_interrupt_info $drv_handle \"S2MM\"]\n\t\t\tif { [llength $intr_info] && ![string match -nocase $intr_info \"-1\"] } {\n\t\t\t\thsi::utils::add_new_dts_param $rx_chan_node \"interrupts\" $intr_info intlist\n\t\t\t} else {\n\t\t\t\tdtg_warning \"ERROR: ${drv_handle}: s2mm_introut port is not connected\"\n\t\t\t}\n\t\t\tset intr_parent [get_property CONFIG.interrupt-parent $drv_handle]\n\t\t\tif {[llength $intr_parent]} {\n\t\t\t\thsi::utils::add_new_dts_param \"${rx_chan_node}\" \"interrupt-parent\" $intr_parent reference\n\t\t\t}\n\t\t\tadd_dma_coherent_prop $drv_handle \"M_AXI_S2MM\"\n\t\t}\n\t} else {\n\t\tset ip_prop CONFIG.c_include_mm2s_dre\n\t\tadd_cross_property $drv_handle $ip_prop $drv_handle \"xlnx,include-dre\" boolean\n\t\tset addr_width [get_property CONFIG.c_addr_width $mcdma_ip]\n\t\tset inhex [format %x $addr_width]\n\t\tappend addrwidth \"/bits/ 8 <0x$inhex>\"\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,addrwidth\" $addrwidth noformating\n\t}\n\tincr dma_count\n\thsi::utils::set_os_parameter_value \"dma_count\" $dma_count\n}\n\nproc get_interrupt_info {drv_handle chan_name} {\n\tif {[string match -nocase $chan_name \"MM2S\"]} {\n\t\tset num_channles [get_property CONFIG.c_num_mm2s_channels [get_cells -hier $drv_handle]]\n\t} else {\n\t\tset num_channles [get_property CONFIG.c_num_s2mm_channels [get_cells -hier $drv_handle]]\n\t}\n\tset intr_info \"\"\n\tfor {set i 1} {$i <= $num_channles} {incr i} {\n\t\tset intr_pin_name [format \"%s_%s_introut\" [string tolower $chan_name] ch$i]\n\t\tset intr1_info [get_intr_id $drv_handle $intr_pin_name]\n\t\tif {[string match -nocase $intr1_info \"-1\"]} {\n\t\t\tcontinue\n\t\t}\n\t\tlappend intr_info $intr1_info\n\t}\n\tif {[llength $intr_info]} {\n\t\tregsub -all \"\\{||\\t\" $intr_info {} intr_info\n\t\tregsub -all \"\\}||\\t\" $intr_info {} intr_info\n\t\treturn $intr_info\n\t}\n}\n\nproc get_connected_ip {drv_handle dma_pin} {\n\tglobal connected_ip\n\t# Check whether dma is connected to 10G/25G MAC\n\t# currently we are handling only data fifo\n\tset intf [::hsi::get_intf_pins -of_objects [get_cells -hier $drv_handle] $dma_pin]\n\tset valid_eth_list \"xxv_ethernet axi_ethernet axi_10g_ethernet usxgmii ethernet_1_10_25g\"\n\tif {[string_is_empty ${intf}]} {\n\t\treturn 0\n\t}\n\tset connected_ip [::hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] $intf]\n\n\tif {[string_is_empty ${connected_ip}]} {\n\t\tdtg_warning \"$drv_handle connected ip is NULL for the pin $intf\"\n\t\treturn 0\n\t}\n\tset iptype [get_property IP_NAME [get_cells -hier $connected_ip]]\n\tif {[string match -nocase $iptype \"axis_data_fifo\"] } {\n\t\t# here dma connected to data fifo\n\t\tset dma_pin \"M_AXIS\"\n\t\tget_connected_ip $connected_ip $dma_pin\n\t} elseif {[lsearch -nocase $valid_eth_list $iptype] >= 0 } {\n\t\t# dma connected to 10G/25G MAC, 1G or 10G\n\t\treturn 1\n\t} else {\n\t\t# dma connected via interconnects\n\t\tset dma_pin \"M_AXIS\"\n\t\tget_connected_ip $connected_ip $dma_pin\n\t}\n}\n\nproc is_mrmac_connected {drv_handle dma_pin} {\n\tset intf [::hsi::get_intf_pins -of_objects [get_cells -hier $drv_handle] $dma_pin]\n\tif {[llength $intf]} {\n\t\tset connected_ip [::hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] $intf]\n\t\tif {[llength $connected_ip]} {\n\t\t\tif {[string match -nocase [get_property IP_NAME $connected_ip] \"axis_data_fifo\"]} {\n\t\t\t\tset mux_ip [::hsi::utils::get_connected_stream_ip [get_cells -hier $connected_ip] \"M_AXIS\"]\n\t\t\t\tif {[llength $mux_ip]} {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $mux_ip] \"mrmac_10g_mux\"]} {\n\t\t\t\t\t\tset data_fifo_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mux_ip] \"tx_m_axis_tdata\"]]\n\t\t\t\t\t\tset data_fifo_per [::hsi::get_cells -of_objects $data_fifo_pin]\n\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $data_fifo_per] \"axis_data_fifo\"]} {\n\t\t\t\t\t\t\tset fifo_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $data_fifo_per] \"m_axis_tdata\"]]\n\t\t\t\t\t\t\tset mrmac_per [::hsi::get_cells -of_objects $fifo_pin]\n\t\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $mrmac_per] \"mrmac\"]} {\n\t\t\t\t\t\t\t\treturn 1\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc add_dma_channel {drv_handle parent_node xdma addr mode devid} {\n\n\tset modellow [string tolower $mode]\n\tset modeIndex [string index $mode 0]\n\tset dma_channel [add_or_get_dt_node -n \"dma-channel\" -u $addr -p $parent_node]\n\thsi::utils::add_new_dts_param $dma_channel \"compatible\" [format \"xlnx,%s-%s-channel\" $xdma $modellow] stringlist\n\thsi::utils::add_new_dts_param $dma_channel \"xlnx,device-id\" $devid hexint\n\n\tadd_cross_property_to_dtnode $drv_handle [format \"CONFIG.C_INCLUDE_%s_DRE\" $mode] $dma_channel \"xlnx,include-dre\" boolean\n\t# detection based on two property\n\tset datawidth_list \"[format \"CONFIG.C_%s_AXIS_%s_DATA_WIDTH\" $modeIndex $mode] [format \"CONFIG.C_%s_AXIS_%s_TDATA_WIDTH\" $modeIndex $mode]\"\n\tadd_cross_property_to_dtnode $drv_handle $datawidth_list $dma_channel \"xlnx,datawidth\"\n\tif {[string match -nocase $mode \"MM2S\"]} {\n\t\tset num_channles [get_property CONFIG.c_num_mm2s_channels [get_cells -hier $drv_handle]]\n\t} else {\n\t\tset num_channles [get_property CONFIG.c_num_s2mm_channels [get_cells -hier $drv_handle]]\n\t}\n\thsi::utils::add_new_dts_param $dma_channel \"dma-channels\" $num_channles hexint\n\treturn $dma_channel\n}\n\nproc add_dma_coherent_prop {drv_handle intf} {\n\n\tset ip_name [::hsi::get_cells -hier -filter \"NAME==$drv_handle\"]\n\tset connectedip [hsi::utils::get_connected_stream_ip $drv_handle $intf]\n\tif {[llength $connectedip] == 0} {\n\t\treturn\n\t}\n\tset intrconnect [get_property IP_NAME [get_cells -hier $connectedip]]\n\tset num_master [get_property CONFIG.NUM_MI $connectedip]\n\tset done 0\n\n\t# check whether dma connected to interconnect ip, loop until you get the\n\t# port name ACP or HP\n\twhile {[string match -nocase $intrconnect \"axi_interconnect\"]} {\n\t\t# loop over number of master interfaces\n\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectedip] -filter {TYPE==MASTER}]\n\t\tif {[llength $master_intf] == 0} {\n\t\t\tbreak\n\t\t}\n\t\tforeach interface ${master_intf} {\n\t\t\tset intf_port [hsi::utils::get_connected_intf $connectedip $interface]\n\t\t\tset intrconnect [hsi::utils::get_connected_stream_ip $connectedip $interface]\n\t\t\tif {![string_is_empty $intf_port] && [string match -nocase $intf_port \"S_AXI_ACP\"]} {\n\t\t\t\thsi::utils::add_new_property $drv_handle \"dma-coherent\" boolean \"\"\n\t\t\t\t# here dma connected to ACP port\n\t\t\t\tset done 1\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif {$done} {\n\t\t\t\tbreak\n\t\t\t}\n\t\t}\n\t}\n}\n" }, { "path": "axi_pcie/data/axi_pcie.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_pcie\n\n OPTION supported_peripherals = (axi_pcie axi_pcie3 qdma xdma pcie_dma_versal);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_pcie;\n PARAMETER name = dev_type, default = axi-pcie, type = string;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,axi-pcie-host-1.00.a\";\n DTGPARAM name = \"#address-cells\", default = 3, type = int;\n DTGPARAM name = \"#size-cells\", default = 2 , type = int;\n DTGPARAM name = \"#interrupt-cells\", default = 1 , type = int;\n DTGPARAM name = device_type, type = string, default = pci;\n\nEND driver\n\n" }, { "path": "axi_pcie/data/axi_pcie.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc set_pcie_ranges {drv_handle proctype} {\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"qdma\"] \\\n\t\t|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"xdma\"]} {\n\t\tset axibar_num [get_ip_property $drv_handle \"CONFIG.axibar_num\"]\n\t} else {\n\t\tset axibar_num [get_ip_property $drv_handle \"CONFIG.AXIBAR_NUM\"]\n\t}\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"pcie_dma_versal\"]} {\n\t\tset axibar_num [get_ip_property $drv_handle \"CONFIG.C_AXIBAR_NUM\"]\n\t}\n\tset range_type 0x02000000\n\t# 64-bit high address.\n\tset high_64bit 0x00000000\n\tset ranges \"\"\n\tfor {set x 0} {$x < $axibar_num} {incr x} {\n\t\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"qdma\"] \\\n\t\t\t|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"xdma\"] \\\n\t\t\t|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"axi_pcie3\"] \\\n\t\t\t|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"pcie_dma_versal\"] \\\n\t\t\t} {\n\t\t\tset axi_baseaddr [get_ip_property $drv_handle [format \"CONFIG.axibar_%d\" $x]]\n\t\t\tset pcie_baseaddr [get_ip_property $drv_handle [format \"CONFIG.axibar2pciebar_%d\" $x]]\n\t\t\tset axi_highaddr [get_ip_property $drv_handle [format \"CONFIG.axibar_highaddr_%d\" $x]]\n\t\t} else {\n\t\t\tset axi_baseaddr [get_ip_property $drv_handle [format \"CONFIG.C_AXIBAR_%d\" $x]]\n\t\t\tset pcie_baseaddr [get_ip_property $drv_handle [format \"CONFIG.C_AXIBAR2PCIEBAR_%d\" $x]]\n\t\t\tset axi_highaddr [get_ip_property $drv_handle [format \"CONFIG.C_AXIBAR_HIGHADDR_%d\" $x]]\n\t\t}\n\t\tset size [expr $axi_highaddr -$axi_baseaddr + 1]\n\t\t# Check the size of pci memory region is 4GB or not,if\n\t\t# yes then split the size to MSB and LSB.\n\t\tif {[regexp -nocase {([0-9a-f]{9})} \"$size\" match]} {\n\t\t set size [format 0x%016x [expr $axi_highaddr -$axi_baseaddr + 1]]\n set low_size [string range $size 0 9]\n set high_size \"0x[string range $size 10 17]\"\n set size \"$low_size $high_size\"\n } else {\n set size [format 0x%08x [expr $axi_highaddr - $axi_baseaddr + 1]]\n\t\t set size \"$high_64bit $size\"\n }\n\t\tif {[regexp -nocase {([0-9a-f]{9})} \"$axi_baseaddr\" match] || [regexp -nocase {([0-9a-f]{9})} \"$axi_highaddr\" match]} {\n\t\t\tset range_type 0x43000000\n\t\t}\n\n\t\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"qdma\"] \\\n\t\t\t|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"xdma\"] \\\n\t\t\t|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"pcie_dma_versal\"]} {\n\t\t\tif {[regexp -nocase {([0-9a-f]{9})} \"$pcie_baseaddr\" match]} {\n\t\t\t\tset temp $pcie_baseaddr\n\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\tset len [string length $temp]\n\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\tset high_base \"0x[string range $temp $rem $len]\"\n\t\t\t\tset low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\tset low_base [format 0x%08x $low_base]\n\t\t\t\tset pcie_baseaddr \"$low_base $high_base\"\n\t\t\t} else {\n\t\t\t\tset pcie_baseaddr \"$high_64bit $pcie_baseaddr\"\n\t\t\t}\n\t\t\tif {[regexp -nocase {([0-9a-f]{9})} \"$axi_baseaddr\" match]} {\n\t\t\t\tset temp $axi_baseaddr\n\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\tset len [string length $temp]\n\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\tset high_base \"0x[string range $temp $rem $len]\"\n\t\t\t\tset low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\tset low_base [format 0x%08x $low_base]\n\t\t\t\tset axi_baseaddr \"$low_base $high_base\"\n\t\t\t} else {\n\t\t\t\tif {[string match -nocase $proctype \"microblaze\"] } {\n\t\t\t\t\tset axi_baseaddr \"$axi_baseaddr\"\n\t\t\t\t} else {\n\t\t\t\t\tset axi_baseaddr \"0x0 $axi_baseaddr\"\n\t\t\t\t}\n\t\t\t}\n\t\t\tset value \"<$range_type $pcie_baseaddr $axi_baseaddr $size>\"\n\t\t} else {\n\t\t\tset value \"<$range_type $high_64bit $pcie_baseaddr $axi_baseaddr $size>\"\n\t\t}\n\t\tif {[string match \"\" $ranges]} {\n\t\t\tset ranges $value\n\t\t} else {\n\t\t\tappend ranges \", \" $value\n\t\t}\n\t}\n\tset_property CONFIG.ranges $ranges $drv_handle\n}\n\nproc get_reg_prop {highaddr baseaddr proctype} {\n\tset reg \"\"\n\tset size [format 0x%X [expr $highaddr -$baseaddr + 1]]\n\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$baseaddr\" match]} {\n\t\tset temp $baseaddr\n\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\tset len [string length $temp]\n\t\tset rem [expr {${len} - 8}]\n\t\tset high_base \"0x[string range $temp $rem $len]\"\n\t\tset low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\tset low_base [format 0x%08x $low_base]\n\t\tset reg \"$low_base $high_base 0x0 $size\"\n\t} else {\n\t\tif {[string match -nocase $proctype \"microblaze\"] } {\n\t\t\tset reg \"$baseaddr $size\"\n\t\t} else {\n\t\t\tset reg \"0x0 $baseaddr 0x0 $size\"\n\t\t}\n\t}\n\treturn $reg\n}\n\nproc set_pcie_reg {drv_handle proctype} {\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"xdma\"] \\\n\t\t|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"axi_pcie3\"] \\\n\t\t|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"pcie_dma_versal\"]} {\n\t\tset baseaddr [get_ip_property $drv_handle CONFIG.baseaddr]\n\t\tset highaddr [get_ip_property $drv_handle CONFIG.highaddr]\n\t\tset reg [get_reg_prop $highaddr $baseaddr $proctype]\n\t\tif {[llength $reg]} {\n\t\t\tset_property CONFIG.reg $reg $drv_handle\n\t\t}\n\t} elseif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"qdma\"]} {\n\t\tset mem_ranges [hsi::utils::get_ip_mem_ranges $drv_handle]\n\t\tset reg \"\"\n\t\tset reg_names \"\"\n\t\tforeach mem_range $mem_ranges {\n\t\t\tset baseaddr [string tolower [get_property BASE_VALUE $mem_range]]\n\t\t\tset highaddr [string tolower [get_property HIGH_VALUE $mem_range]]\n\t\t\tset slave_intf [string tolower [get_property SLAVE_INTERFACE $mem_range]]\n\t\t\tdtg_verbose \"slave_intf:$slave_intf\"\n\t\t\tset reg_prop \"\"\n\t\t\tif {[string match -nocase $slave_intf \"s_axi_lite\"]} {\n\t\t\t\tset reg_prop [get_reg_prop $highaddr $baseaddr $proctype]\n\t\t\t\tappend reg_names \" \" \"cfg\"\n\t\t\t} elseif {[string match -nocase $slave_intf \"s_axi_lite_csr\"]} {\n\t\t\t\tset reg_prop [get_reg_prop $highaddr $baseaddr $proctype]\n\t\t\t\tappend reg_names \" \" \"breg\"\n\t\t\t}\n\t\t\tif {[llength $reg_prop]} {\n\t\t\t\tif {![llength $reg]} {\n\t\t\t\t\tset reg \"$reg_prop\"\n\t\t\t\t} else {\n\t\t\t\t\tappend reg \">, <\" \"$reg_prop\"\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[llength $reg]} {\n\t\t\tset_property CONFIG.reg $reg $drv_handle\n\t\t}\n\t\tif {[llength $reg_names]} {\n\t\t\thsi::utils::add_new_property $drv_handle \"reg-names\" stringlist \"$reg_names\"\n\t\t}\n\t} else {\n\t\tset baseaddr [get_ip_property $drv_handle CONFIG.BASEADDR]\n\t\tset highaddr [get_ip_property $drv_handle CONFIG.HIGHADDR]\n\t\tset size [format 0x%X [expr $highaddr -$baseaddr + 1]]\n\t\tset_property CONFIG.reg \"$baseaddr $size\" $drv_handle\n\t}\n}\n\nproc axibar_num_workaround {drv_handle} {\n\t# this required to workaround 2014.2_web tag kernel\n\t# must have both xlnx,pciebar2axibar-0 and xlnx,pciebar2axibar-1 generated\n\tset axibar_num [get_ip_property $drv_handle \"CONFIG.AXIBAR_NUM\"]\n\tif {[expr $axibar_num <= 1]} {\n\t\tset axibar_num 2\n\t}\n\treturn $axibar_num\n}\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tset compatible [get_comp_str $drv_handle]\n\tif {![string match -nocase $proctype \"psv_cortexa72\"]} {\n\t\tset compatible [append compatible \" \" \"xlnx,axi-pcie-host-1.00.a\"]\n\t}\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"xdma\"]} {\n\t\thsi::utils::add_new_property $drv_handle \"compatible\" stringlist \"xlnx,xdma-host-3.00\"\n\t\tset msi_rx_pin_en [get_property CONFIG.msi_rx_pin_en [get_cells -hier $drv_handle]]\n\t\tif {[string match -nocase $msi_rx_pin_en \"true\"]} {\n\t\t\tset intr_names \"misc msi0 msi1\"\n\t\t\tset_drv_prop $drv_handle \"interrupt-names\" $intr_names stringlist\n\t\t}\n\t}\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"qdma\"]} {\n\t\thsi::utils::add_new_property $drv_handle \"compatible\" stringlist \"xlnx,qdma-host-3.00\"\n\t}\n\tset_pcie_reg $drv_handle $proctype\n\tset_pcie_ranges $drv_handle $proctype\n\tset_drv_prop $drv_handle interrupt-map-mask \"0 0 0 7\" intlist\n\tif {[string match -nocase $proctype \"microblaze\"] } {\n\t\tset_drv_prop $drv_handle bus-range \"0x0 0xff\" hexint\n\t}\n\t# Add Interrupt controller child node\n\tif {[string match -nocase $proctype \"psv_cortexa72\"]} {\n\t\tset psv_pcieintc_cnt [get_os_dev_count \"psv_pci_intc_cnt\"]\n\t\tset pcie_child_intc_node [add_or_get_dt_node -l \"psv_pcie_intc_${psv_pcieintc_cnt}\" -n interrupt-controller -p $node]\n\t\tset int_map \"0 0 0 1 &psv_pcie_intc_${psv_pcieintc_cnt} 1>, <0 0 0 2 &psv_pcie_intc_${psv_pcieintc_cnt} 2>, <0 0 0 3 &psv_pcie_intc_${psv_pcieintc_cnt} 3>,\\\n\t\t\t<0 0 0 4 &psv_pcie_intc_${psv_pcieintc_cnt} 4\"\n\t\t\tincr psv_pcieintc_cnt\n\t\t\thsi::utils::set_os_parameter_value \"psv_pci_intc_cnt\" $psv_pcieintc_cnt\n\t\t\tset intr_names \"misc msi0 msi1\"\n\t\t\tset_drv_prop $drv_handle \"interrupt-names\" $intr_names stringlist\n\t} else {\n\t\tset pcieintc_cnt [get_os_dev_count \"pci_intc_cnt\"]\n\t\tset pcie_child_intc_node [add_or_get_dt_node -l \"pcie_intc_${pcieintc_cnt}\" -n interrupt-controller -p $node]\n\t\tset int_map \"0 0 0 1 &pcie_intc_${pcieintc_cnt} 1>, <0 0 0 2 &pcie_intc_${pcieintc_cnt} 2>, <0 0 0 3 &pcie_intc_${pcieintc_cnt} 3>,\\\n\t\t\t<0 0 0 4 &pcie_intc_${pcieintc_cnt} 4\"\n\t\tincr pcieintc_cnt\n\t\thsi::utils::set_os_parameter_value \"pci_intc_cnt\" $pcieintc_cnt\n\t}\n\tset_drv_prop $drv_handle interrupt-map $int_map int\n\thsi::utils::add_new_dts_param \"${pcie_child_intc_node}\" \"interrupt-controller\" \"\" boolean\n\thsi::utils::add_new_dts_param \"${pcie_child_intc_node}\" \"#address-cells\" 0 int\n\thsi::utils::add_new_dts_param \"${pcie_child_intc_node}\" \"#interrupt-cells\" 1 int\n}\n" }, { "path": "axi_perf_mon/data/axi_perf_mon.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_perf_mon\n\n OPTION supported_peripherals = (axi_perf_mon);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_perf_mon;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,axi-perf-monitor\";\n\nEND driver\n" }, { "path": "axi_perf_mon/data/axi_perf_mon.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,axi-perf-monitor\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset check_list \"enable-profile enable-trace num-monitor-slots enable-event-count enable-event-log have-sampled-metric-cnt num-of-counters metric-count-width metrics-sample-count-width global-count-width metric-count-scale\"\n\tforeach p ${check_list} {\n\t\tset ip_conf [string toupper \"c_${p}\"]\n\t\tregsub -all {\\-} $ip_conf {_} ip_conf\n\t\tset_drv_conf_prop $drv_handle ${ip_conf} xlnx,${p} hexint\n\t}\n}\n" }, { "path": "axi_qspi/data/axi_qspi.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_qspi\n\n OPTION supported_peripherals = (axi_quad_spi);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_qspi;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,xps-spi-2.00.a\";\n DTGPARAM name = dtg.alias , default = spi;\n\nEND driver\n" }, { "path": "axi_qspi/data/axi_qspi.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,xps-spi-2.00.a\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset_drv_conf_prop $drv_handle \"C_NUM_SS_BITS\" \"xlnx,num-ss-bits\"\n\tset_drv_conf_prop $drv_handle \"C_NUM_SS_BITS\" \"num-cs\"\n\tset_drv_conf_prop $drv_handle \"C_NUM_TRANSFER_BITS\" \"bits-per-word\" int\n\tset_drv_conf_prop $drv_handle \"C_FIFO_DEPTH\" \"fifo-size\" int\n\tset_drv_conf_prop $drv_handle \"C_SPI_MODE\" \"xlnx,spi-mode\" int\n\tset_drv_conf_prop $drv_handle \"C_USE_STARTUP\" \"xlnx,startup-block\" boolean\n}\n" }, { "path": "axi_sysace/data/axi_sysace.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_sysace\n\n OPTION supported_peripherals = (axi_sysace);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_sysace;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,xps-sysace-1.00.a\";\n DTGPARAM name = port-number, type = int, default = 0;\n\nEND driver\n\n" }, { "path": "axi_sysace/data/axi_sysace.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n\n" }, { "path": "axi_tft/data/axi_tft.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_tft\n\n OPTION supported_peripherals = (axi_tft);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_tft;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,xps-tft-1.00.a\";\n\nEND driver\n\n" }, { "path": "axi_tft/data/axi_tft.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n\n" }, { "path": "axi_timebase_wdt/data/axi_timebase_wdt.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_timebase_wdt\n\n OPTION supported_peripherals = (axi_timebase_wdt);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_timebase_wdt;\n\n DTGPARAM name = dev_type, default = watchdog , type = string;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,xps-timebase-wdt-1.00.a\";\n\nEND driver\n" }, { "path": "axi_timebase_wdt/data/axi_timebase_wdt.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,xps-timebase-wdt-1.00.a\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\t# get bus clock frequency\n\tset clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"S_AXI_ACLK\"]\n\tif {![string equal $clk_freq \"\"]} {\n\t\tset_property CONFIG.clock-frequency $clk_freq $drv_handle\n\t}\n\tset_drv_conf_prop $drv_handle \"C_WDT_ENABLE_ONCE\" \"xlnx,wdt-enable-once\"\n\tset_drv_conf_prop $drv_handle \"C_WDT_INTERVAL\" \"xlnx,wdt-interval\"\n\n}\n\n" }, { "path": "axi_traffic_gen/data/axi_traffic_gen.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_traffic_gen\n\n OPTION supported_peripherals = (axi_traffic_gen);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_traffic_gen;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,axi-traffic-gen\";\n DTGPARAM name = \"xlnx,device-id\", type = int, default = 0;\n\nEND driver\n\n" }, { "path": "axi_traffic_gen/data/axi_traffic_gen.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,axi-traffic-gen\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\t# the interrupt related setting is only required for AXI4 protocol only\n\tset atg_mode [get_property \"CONFIG.C_ATG_MODE\" [get_cells -hier $drv_handle]]\n\tif { ![string match -nocase $atg_mode \"AXI4\"] } {\n\t\treturn 0\n\t}\n\tset proc_type [get_sw_proc_prop IP_NAME]\n\t# set up interrupt-names\n\tset intr_list \"irq_out err_out\"\n\tset interrupts \"\"\n\tset interrupt_names \"\"\n\tforeach irq ${intr_list} {\n\t\tset intr_info [get_intr_id $drv_handle $irq]\n\t\tif { [string match -nocase $intr_info \"-1\"] } {\n\t\t\tif {[string match -nocase $proc_type \"psv_cortexa72\"] || [string match -nocase $proc_type \"psx_cortexa78\"]} {\n\t\t\t\tcontinue\n\t\t\t} else {\n\t\t\t\terror \"ERROR: ${drv_handle}: $irq port is not connected\"\n\t\t\t}\n\t\t}\n\t\tif { [string match -nocase $interrupt_names \"\"] } {\n\t\t\tif {[string match -nocase $irq \"irq_out\"]} {\n\t\t\t\tset irq \"irq-out\"\n\t\t\t}\n\t\t\tif {[string match -nocase $irq \"err_out\"]} {\n\t\t\t\tset irq \"err-out\"\n\t\t\t}\n\t\t\tset interrupt_names \"$irq\"\n\t\t\tset interrupts \"$intr_info\"\n\t\t} else {\n\t\t\tif {[string match -nocase $irq \"irq_out\"]} {\n\t\t\t\tset irq \"irq-out\"\n\t\t\t}\n\t\t\tif {[string match -nocase $irq \"err_out\"]} {\n\t\t\t\tset irq \"err-out\"\n\t\t\t}\n\t\t\tappend interrupt_names \" \" \"$irq\"\n\t\t\tappend interrupts \" \" \"$intr_info\"\n\t\t}\n\t}\n\thsi::utils::add_new_property $drv_handle \"interrupts\" int $interrupts\n\thsi::utils::add_new_property $drv_handle \"interrupt-names\" stringlist $interrupt_names\n}\n" }, { "path": "axi_usb2_device/data/axi_usb2_device.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_usb2_device\n\n OPTION supported_peripherals = (axi_usb2_device);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_usb2_device;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,usb2-device-4.00.a\";\n\nEND driver\n\n" }, { "path": "axi_usb2_device/data/axi_usb2_device.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,usb2-device-4.00.a\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset ip [get_cells -hier $drv_handle]\n\tset include_dma [get_property CONFIG.C_INCLUDE_DMA $ip]\n\tif { $include_dma eq \"1\"} {\n\t\tset_drv_conf_prop $drv_handle C_INCLUDE_DMA xlnx,has-builtin-dma boolean\n\t}\n\n}\n" }, { "path": "axi_vcu/data/axi_vcu.mdd", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_vcu\n\n OPTION supported_peripherals = (vcu);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_vcu;\n\nEND driver\n" }, { "path": "axi_vcu/data/axi_vcu.tcl", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n # try to source the common tcl procs\n # assuming the order of return is based on repo priority\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n # Generate properties required for vcu node\n set node [gen_peripheral_nodes $drv_handle]\n if {$node == 0} {\n return\n }\n hsi::utils::add_new_dts_param \"${node}\" \"#address-cells\" 2 int\n hsi::utils::add_new_dts_param \"${node}\" \"#size-cells\" 2 int\n hsi::utils::add_new_dts_param \"${node}\" \"#clock-cells\" 1 int\n set vcu_ip [get_cells -hier $drv_handle]\n set baseaddr [get_baseaddr $vcu_ip no_prefix]\n set slcr_offset 0x40000\n set logicore_offset 0x41000\n set vcu_slcr_reg [format %08x [expr 0x$baseaddr + $slcr_offset]]\n set logicore_reg [format %08x [expr 0x$baseaddr + $logicore_offset]]\n set reg \"0x0 0x$vcu_slcr_reg 0x0 0x1000>, <0x0 0x$logicore_reg 0x0 0x1000\"\n set_drv_prop $drv_handle reg $reg int\n set intr_val [get_property CONFIG.interrupts $drv_handle]\n set intr_parent [get_property CONFIG.interrupt-parent $drv_handle]\n set clock-names \"pll_ref\"\n set clock-names [append clock-names \" aclk\"]\n hsi::utils::add_new_dts_param \"${node}\" \"clock-names\" ${clock-names} stringlist\n zynq_gen_pl_clk_binding $drv_handle\n set first_reg_name \"vcu_slcr\"\n set second_reg_name \" logicore\"\n set reg_name [append first_reg_name $second_reg_name]\n hsi::utils::add_new_dts_param \"${node}\" \"reg-names\" ${reg_name} stringlist\n hsi::utils::add_new_dts_param \"${node}\" \"ranges\" \"\" boolean\n set compatible [get_ipdetails $drv_handle \"compatible\"]\n set vcu_comp \" xlnx,vcu\"\n set compatible [append compatible $vcu_comp]\n set_drv_prop $drv_handle compatible \"$compatible\" stringlist\n hsi::utils::add_new_dts_param \"${node}\" \"compatible\" ${compatible} stringlist\n\n # Generate child encoder\n set ver [get_ipdetails $drv_handle \"ver\"]\n set encoder_enable [get_property CONFIG.ENABLE_ENCODER [get_cells -hier $drv_handle]]\n if {[string match -nocase $encoder_enable \"TRUE\"]} {\n set encoder_node [add_or_get_dt_node -l \"encoder\" -n \"al5e@$baseaddr\" -p $node]\n set encoder_comp \"al,al5e-${ver}\"\n set encoder_comp [append encoder_comp \" al,al5e\"]\n hsi::utils::add_new_dts_param \"${encoder_node}\" \"compatible\" $encoder_comp stringlist\n set encoder_reg \"0x0 0x$baseaddr 0x0 0x10000\"\n hsi::utils::add_new_dts_param \"${encoder_node}\" \"reg\" $encoder_reg int\n hsi::utils::add_new_dts_param \"${encoder_node}\" \"interrupts\" $intr_val int\n hsi::utils::add_new_dts_param \"${encoder_node}\" \"interrupt-parent\" $intr_parent reference\n }\n # Fenerate child decoder\n set decoder_enable [get_property CONFIG.ENABLE_DECODER [get_cells -hier $drv_handle]]\n if {[string match -nocase $decoder_enable \"TRUE\"]} {\n set decoder_offset 0x20000\n set decoder_reg [format %08x [expr 0x$baseaddr + $decoder_offset]]\n set decoder_node [add_or_get_dt_node -l \"decoder\" -n \"al5d@$decoder_reg\" -p $node]\n set decoder_comp \"al,al5d-${ver}\"\n set decoder_comp [append decoder_comp \" al,al5d\"]\n hsi::utils::add_new_dts_param \"${decoder_node}\" \"compatible\" $decoder_comp stringlist\n set decoder_reg \"0x0 0x$decoder_reg 0x0 0x10000\"\n hsi::utils::add_new_dts_param \"${decoder_node}\" \"reg\" $decoder_reg int\n hsi::utils::add_new_dts_param \"${decoder_node}\" \"interrupts\" $intr_val int\n hsi::utils::add_new_dts_param \"${decoder_node}\" \"interrupt-parent\" $intr_parent reference\n }\n set clknames \"pll_ref aclk vcu_core_enc vcu_mcu_enc vcu_core_dec vcu_mcu_dec\"\n overwrite_clknames $clknames $drv_handle\n set ip [get_cells -hier $drv_handle]\n set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] \"vcu_resetn\"]]\n\tforeach pin $pins {\n\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tif {[llength $sink_periph]} {\n\t\t\tset sink_ip [get_property IP_NAME $sink_periph]\n\t\t\tif {[string match -nocase $sink_ip \"xlslice\"]} {\n\t\t\t\tset gpio [get_property CONFIG.DIN_FROM $sink_periph]\n\t\t\t\tset pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph \"Din\"]]]\n\t\t\t\tforeach pin $pins {\n\t\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t\tif {[llength $periph]} {\n\t\t\t\t\t\tset ip [get_property IP_NAME $periph]\n\t\t\t\t\t\tset proc_type [get_sw_proc_prop IP_NAME]\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psv_cortexa72\"] } {\n\t\t\t\t\t\t\tif { $ip in { \"versal_cips\" \"ps_wizard\" }} {\n\t\t\t\t\t\t\t\t# As in versal there is only bank0 for MIOs\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 26]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio0 $gpio 0\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n\t\t\t\t\t\t\tif {[string match -nocase $ip \"zynq_ultra_ps_e\"]} {\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 78]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio $gpio 0\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $ip \"axi_gpio\"]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"$periph $gpio 0 1\" reference\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"periph for the pin:$pin is NULL $periph...check the design\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"peripheral for the pin:$pin is NULL $sink_periph...check the design\"\n\t\t}\n\t}\n}\n\nproc get_ipdetails {drv_handle arg} {\n set slave [get_cells -hier ${drv_handle}]\n set vlnv [split [get_property VLNV $slave] \":\"]\n set ver [lindex $vlnv 3]\n set name [lindex $vlnv 2]\n set ver [lindex $vlnv 3]\n set comp_prop \"xlnx,${name}-${ver}\"\n regsub -all {_} $comp_prop {-} comp_prop\n if {[string match -nocase $arg \"ver\"]} {\n return $ver\n } else {\n return $comp_prop\n }\n}\n" }, { "path": "axi_vdma/data/axi_vdma.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_vdma\n\n OPTION supported_peripherals = (axi_vdma);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_vdma;\n PARAMETER name = dev_type, default = dma, type = string;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,axi-vdma-1.00.a\";\n DTGPARAM name = \"#dma-cells\", type = int, default = 1;\n\nEND driver\n" }, { "path": "axi_vdma/data/axi_vdma.tcl", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,axi-vdma-1.00.a\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset dma_ip [get_cells -hier $drv_handle]\n\tset vdma_count [hsi::utils::get_os_parameter_value \"vdma_count\"]\n\tif { [llength $vdma_count] == 0 } {\n\t\tset vdma_count 0\n\t}\n\n\t# check for C_ENABLE_DEBUG parameters\n\t# C_ENABLE_DEBUG_INFO_15 - Enable S2MM Frame Count Interrupt bit\n\t# C_ENABLE_DEBUG_INFO_14 - Enable S2MM Delay Counter Interrupt bit\n\t# C_ENABLE_DEBUG_INFO_7 - Enable MM2S Frame Count Interrupt bit\n\t# C_ENABLE_DEBUG_INFO_6 - Enable MM2S Delay Counter Interrupt bit\n\tset dbg15 [hsi::utils::get_ip_param_value $dma_ip C_ENABLE_DEBUG_INFO_15]\n\tset dbg14 [hsi::utils::get_ip_param_value $dma_ip C_ENABLE_DEBUG_INFO_14]\n\tset dbg07 [hsi::utils::get_ip_param_value $dma_ip C_ENABLE_DEBUG_INFO_7]\n\tset dbg06 [hsi::utils::get_ip_param_value $dma_ip C_ENABLE_DEBUG_INFO_6]\n\n\tif { $dbg15 != 1 || $dbg14 != 1 || $dbg07 != 1 || $dbg06 != 1 } {\n\t\tputs \"ERROR: Failed to generate AXI VDMA node,\"\n\t\tputs \"ERROR: Essential VDMA Debug parameters for driver are not enabled in IP\"\n\t\treturn;\n\t}\n\n\tset_drv_conf_prop $drv_handle C_INCLUDE_SG xlnx,include-sg boolean\n\tset_drv_conf_prop $drv_handle c_num_fstores xlnx,num-fstores\n\tset_drv_conf_prop $drv_handle C_USE_FSYNC xlnx,flush-fsync\n\tset_drv_conf_prop $drv_handle c_addr_width xlnx,addrwidth\n\n\tset baseaddr [get_baseaddr $dma_ip no_prefix]\n\tset tx_chan [hsi::utils::get_ip_param_value $dma_ip C_INCLUDE_MM2S]\n\tif { $tx_chan == 1 } {\n\t\tset connected_ip [hsi::utils::get_connected_stream_ip $dma_ip \"M_AXIS_MM2S\"]\n\t\tset tx_chan_node [add_dma_channel $drv_handle $node \"axi-vdma\" $baseaddr \"MM2S\" $vdma_count ]\n\t\tset intr_info [get_intr_id $drv_handle \"mm2s_introut\"]\n\t\t#set intc [hsi::utils::get_interrupt_parent $dma_ip \"mm2s_introut\"]\n\t if { [llength $intr_info] && ![string match -nocase $intr_info \"-1\"] } {\n\t\t\thsi::utils::add_new_dts_param $tx_chan_node \"interrupts\" $intr_info intlist\n\t } else {\n\t\t\tdtg_warning \"ERROR: ${drv_handle}: mm2s_introut port is not connected\"\n\t\t}\n\t}\n\tset rx_chan [hsi::utils::get_ip_param_value $dma_ip C_INCLUDE_S2MM]\n\tif { $rx_chan ==1 } {\n\t\tset connected_ip [hsi::utils::get_connected_stream_ip $dma_ip \"S_AXIS_S2MM\"]\n\t\tset rx_bassaddr [format %08x [expr 0x$baseaddr + 0x30]]\n\t\tset rx_chan_node [add_dma_channel $drv_handle $node \"axi-vdma\" $rx_bassaddr \"S2MM\" $vdma_count]\n\t\tset intr_info [get_intr_id $drv_handle \"s2mm_introut\"]\n\t\t#set intc [hsi::utils::get_interrupt_parent $dma_ip \"s2mm_introut\"]\n\t if { [llength $intr_info] && ![string match -nocase $intr_info \"-1\"] } {\n\t\t\thsi::utils::add_new_dts_param $rx_chan_node \"interrupts\" $intr_info intlist\n\t } else {\n\t\t\tdtg_warning \"ERROR: ${drv_handle}: s2mm_introut port is not connected\"\n\t\t}\n\t}\n\tincr vdma_count\n\thsi::utils::set_os_parameter_value \"vdma_count\" $vdma_count\n\tset mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n\tif {[string match -nocase $mainline_ker \"none\"]} {\n\t\tset proc_type [get_sw_proc_prop IP_NAME]\n\t\tset clocknames \"s_axi_lite_aclk\"\n\t\tif { $tx_chan ==1 } {\n\t\t\tappend clocknames \" \" \"m_axi_mm2s_aclk\"\n\t\t\tappend clocknames \" \" \"m_axi_mm2s_aclk\"\n\t\t}\n\t\tif { $rx_chan ==1 } {\n\t\t\tappend clocknames \" \" \"m_axi_s2mm_aclk\"\n\t\t\tappend clocknames \" \" \"m_axi_s2mm_aclk\"\n\t\t}\n\t\tswitch $proc_type {\n\t\t\t\"microblaze\" {\n\t\t\t\tgen_dev_ccf_binding $drv_handle \"$clocknames\"\n\t\t\t\tset_drv_prop_if_empty $drv_handle \"clock-names\" \"$clocknames\" stringlist\n\t\t\t}\n\t\t}\n\t} else {\n\t\t\tgenerate_clk_nodes $drv_handle $tx_chan $rx_chan\n\t}\n}\n\nproc add_dma_channel {drv_handle parent_node xdma addr mode devid} {\n\tset ip [get_cells -hier $drv_handle]\n\tset modellow [string tolower $mode]\n\tset modeIndex [string index $mode 0]\n\tset dma_channel [add_or_get_dt_node -n \"dma-channel\" -u $addr -p $parent_node]\n\thsi::utils::add_new_dts_param $dma_channel \"compatible\" [format \"xlnx,%s-%s-channel\" $xdma $modellow] stringlist\n\thsi::utils::add_new_dts_param $dma_channel \"xlnx,device-id\" $devid hexint\n\tif {[string match -nocase $mode \"S2MM\"]} {\n\t\tset vert_flip [hsi::utils::get_ip_param_value $ip C_ENABLE_VERT_FLIP]\n\t\tif {$vert_flip == 1} {\n\t\t\thsi::utils::add_new_dts_param $dma_channel \"xlnx,enable-vert-flip\" \"\" boolean\n\t\t}\n\t}\n\tadd_cross_property_to_dtnode $drv_handle [format \"CONFIG.C_INCLUDE_%s_DRE\" $mode] $dma_channel \"xlnx,include-dre\" boolean\n\t# detection based on two property\n\tset datawidth_list \"[format \"CONFIG.C_%s_AXIS_%s_DATA_WIDTH\" $modeIndex $mode] [format \"CONFIG.C_%s_AXIS_%s_TDATA_WIDTH\" $modeIndex $mode]\"\n\tadd_cross_property_to_dtnode $drv_handle $datawidth_list $dma_channel \"xlnx,datawidth\"\n\tadd_cross_property_to_dtnode $drv_handle [format \"CONFIG.C_%s_GENLOCK_MODE\" $mode] $dma_channel \"xlnx,genlock-mode\" boolean\n\n\treturn $dma_channel\n}\n\nproc generate_clk_nodes {drv_handle tx_chan rx_chan} {\n set proc_type [get_sw_proc_prop IP_NAME]\n set clocknames \"s_axi_lite_aclk\"\n switch $proc_type {\n \"ps7_cortexa9\" {\n set clocks \"clkc 15\"\n if { $tx_chan ==1 } {\n append clocknames \" \" \"m_axi_mm2s_aclk\"\n append clocknames \" \" \"m_axi_mm2s_aclk\"\n append clocks \"\" \">, <&clkc 15\"\n append clocks \"\" \">, <&clkc 15\"\n }\n if { $rx_chan ==1 } {\n append clocknames \" \" \"m_axi_s2mm_aclk\"\n append clocknames \" \" \"m_axi_s2mm_aclk\"\n append clocks \"\" \">, <&clkc 15\"\n append clocks \"\" \">, <&clkc 15\"\n }\n set_drv_prop_if_empty $drv_handle \"clocks\" $clocks reference\n set_drv_prop_if_empty $drv_handle \"clock-names\" $clocknames stringlist\n } \"psu_cortexa53\" {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"s_axi_lite_aclk\"]\n if {![string equal $clk_freq \"\"]} {\n if {[lsearch $bus_clk_list $clk_freq] < 0} {\n set bus_clk_list [lappend bus_clk_list $clk_freq]\n }\n }\n set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]\n set dts_file [current_dt_tree]\n set bus_node [add_or_get_bus_node $drv_handle $dts_file]\n set misc_clk_node [add_or_get_dt_node -n \"misc_clk_${bus_clk_cnt}\" -l \"misc_clk_${bus_clk_cnt}\" \\\n -d ${dts_file} -p ${bus_node}]\n\t hsi::utils::add_new_dts_param \"${misc_clk_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t hsi::utils::add_new_dts_param \"${misc_clk_node}\" \"#clock-cells\" 0 int\n\t hsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-frequency\" $clk_freq int\n # create the node and assuming reg 0 is taken by cpu\n set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]\n set clocks \"$clk_refs\"\n if { $tx_chan ==1 } {\n append clocknames \" \" \"m_axi_mm2s_aclk\"\n append clocknames \" \" \"m_axi_mm2s_aclk\"\n append clocks \"\" \">, <&$clk_refs\"\n append clocks \"\" \">, <&$clk_refs\"\n }\n if { $rx_chan ==1 } {\n append clocknames \" \" \"m_axi_s2mm_aclk\"\n append clocknames \" \" \"m_axi_s2mm_aclk\"\n append clocks \"\" \">, <&$clk_refs\"\n append clocks \"\" \">, <&$clk_refs\"\n }\n set_drv_prop_if_empty $drv_handle \"clocks\" $clocks reference\n set_drv_prop_if_empty $drv_handle \"clock-names\" $clocknames stringlist\n } \"microblaze\" {\n if { $tx_chan ==1 } {\n append clocknames \" \" \"m_axi_mm2s_aclk\"\n append clocknames \" \" \"m_axi_mm2s_aclk\"\n }\n if { $rx_chan ==1 } {\n append clocknames \" \" \"m_axi_s2mm_aclk\"\n append clocknames \" \" \"m_axi_s2mm_aclk\"\n }\n gen_dev_ccf_binding $drv_handle \"$clocknames\"\n set_drv_prop_if_empty $drv_handle \"clock-names\" \"$clocknames\" stringlist\n }\n default {\n error \"Unknown arch\"\n }\n }\n}\n" }, { "path": "axi_vdu/data/axi_vdu.mdd", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_vdu\n\n OPTION supported_peripherals = (vdu);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_vdu;\n\nEND driver\n" }, { "path": "axi_vdu/data/axi_vdu.tcl", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc gen_reset_gpio {drv_handle node} {\n set ip [get_cells -hier $drv_handle]\n set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] \"vdu_resetn\"]]\n foreach pin $pins {\n set sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tif {[llength $sink_periph]} {\n\t\t\tset sink_ip [get_property IP_NAME $sink_periph]\n\t\t if {[string match -nocase $sink_ip \"axi_gpio\"]} {\n\t\t\t hsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"$sink_periph 0 1\" reference\n\t\t\t}\n\t\t\tif {[string match -nocase $sink_ip \"xlslice\"]} {\n\t\t\t\tset gpio [get_property CONFIG.DIN_FROM $sink_periph]\n\t\t\t\tset pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph \"Din\"]]]\n\t\t\t\tforeach pin $pins {\n\t\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t\tif {[llength $periph]} {\n\t\t\t\t\t\tset ip [get_property IP_NAME $periph]\n\t\t\t\t\t\tset proc_type [get_sw_proc_prop IP_NAME]\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psv_cortexa72\"] } {\n\t\t\t\t\t\t\tif { $ip in { \"versal_cips\" \"ps_wizard\" }} {\n\t\t\t\t\t\t\t\t# As in versal there is only bank0 for MIOs\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 26]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio0 $gpio 0\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n\t\t\t\t\t\t\tif {[string match -nocase $ip \"zynq_ultra_ps_e\"]} {\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 78]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio $gpio 0\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $ip \"axi_gpio\"]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"$periph $gpio 0 1\" reference\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"periph for the pin:$pin is NULL $periph...check the design\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"peripheral for the pin:$pin is NULL $sink_periph...check the design\"\n\t\t}\n\t}\n}\n\nproc get_intr_width {intr_parent} {\n set intr_width \"\"\n if { [string match -nocase $intr_parent \"gic\"] } {\n set intr_width \"3\"\n\t} else {\n set intr_width \"2\"\n\t}\n return $intr_width\n}\n\nproc generate {drv_handle} {\n # try to source the common tcl procs\n # assuming the order of return is based on repo priority\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n # Generate properties required for vdu node\n set node [gen_peripheral_nodes $drv_handle]\n if {$node == 0} {\n return\n }\n set drv_label [ps_node_mapping $drv_handle label]\n set default_dts [set_drv_def_dts $drv_handle]\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n set vdu_ip [get_cells -hier $drv_handle]\n set core_clk [get_property CONFIG.Actual_CORE_CLK [get_cells -hier $drv_handle]]\n if {[llength $core_clk]} {\n hsi::utils::add_new_dts_param \"${node}\" \"xlnx,core_clk\" ${core_clk} int\n }\n set mcu_clk [get_property CONFIG.Actual_MCU_CLK [get_cells -hier $drv_handle]]\n if {[llength $mcu_clk]} {\n hsi::utils::add_new_dts_param \"${node}\" \"xlnx,mcu_clk\" ${mcu_clk} int\n }\n set ref_clk [get_property CONFIG.REF_CLK [get_cells -hier $drv_handle]]\n if {[llength $ref_clk]} {\n hsi::utils::add_new_dts_param \"${node}\" \"xlnx,ref_clk\" ${ref_clk} int\n }\n gen_reset_gpio \"$drv_handle\" \"$node\"\n set intr_val \"\"\n set intr_parent \"\"\n set intr_names \"\"\n global drv_handlers_mapping\n if {[info exists drv_handlers_mapping] && [dict exists $drv_handlers_mapping $drv_handle]} {\n if {[dict exists $drv_handlers_mapping $drv_handle \"interrupts\"]} {\n set intr_val [dict get $drv_handlers_mapping $drv_handle \"interrupts\"]\n }\n if {[dict exists $drv_handlers_mapping $drv_handle \"interrupt-parent\"]} {\n set intr_parent [dict get $drv_handlers_mapping $drv_handle \"interrupt-parent\"]\n }\n if {[dict exists $drv_handlers_mapping $drv_handle \"interrupt-names\"]} {\n set intr_names [dict get $drv_handlers_mapping $drv_handle \"interrupt-names\"]\n }\n }\n set intrnames_List \"\"\n if {[llength $intr_names]} {\n set intrnames_List [regexp -inline -all -- {\\S+} $intr_names]\n }\n set baseaddr [get_baseaddr $vdu_ip no_prefix]\n set num_decoders [get_property CONFIG.NUM_DECODER_INSTANCES [get_cells -hier $drv_handle]]\n set al5d_baseoffset \"0x20000\"\n set al5d_baseaddr [format %08x [expr 0x$baseaddr + $al5d_baseoffset]]\n set al5d_offset \"0x100000\"\n set intr_width \"\"\n for {set inst 0} {$inst < $num_decoders} {incr inst} {\n set al5d_node [add_or_get_dt_node -n al5d@$al5d_baseaddr -d $default_dts -p $bus_node]\n hsi::utils::add_new_dts_param $al5d_node \"compatible\" \"al,al5d\" string\n hsi::utils::add_new_dts_param $al5d_node \"al,devicename\" \"allegroDecodeIP$inst\" string\n hsi::utils::add_new_dts_param $al5d_node \"xlnx,vdu\" \"$drv_label\" reference\n hsi::utils::add_new_dts_param $al5d_node \\\n \"/*To be filled by user depending on design else CMA region will be used */\" \"\" comment\n hsi::utils::add_new_dts_param $al5d_node \"/*memory-region = <&mem_reg_0> */\" \"\" comment\n\n\t\t# check if base address is 64bit and split it as MSB and LSB\n\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"0x$al5d_baseaddr\" match]} {\n\t\t set temp $al5d_baseaddr\n\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\tset len [string length $temp]\n\t\t\tset rem [expr {${len} - 8}]\n\t\t\tset high_base \"0x[string range $temp $rem $len]\"\n\t\t\tset low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\tset low_base [format 0x%08x $low_base]\n\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$al5d_offset\" match]} {\n\t\t\t set temp $al5d_offset\n\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\tset len [string length $temp]\n\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\tset high_size \"0x[string range $temp $rem $len]\"\n\t\t\t\tset low_size \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\tset low_size [format 0x%08x $low_size]\n\t\t\t\tset reg \"$low_base $high_base $low_size $high_size\"\n\t\t\t} else {\n\t\t\t\tset reg \"$low_base $high_base 0x0 $al5d_offset\"\n\t\t\t}\n\t\t} else {\n\t\t\tset reg \"0x0 0x$al5d_baseaddr 0x0 $al5d_offset\"\n\t\t}\n hsi::utils::add_new_dts_param $al5d_node \"reg\" \"$reg\" int\n if {[llength $intr_parent]} {\n set intr_width [get_intr_width $intr_parent]\n hsi::utils::add_new_dts_param $al5d_node \"interrupt-parent\" \"$intr_parent\" reference\n }\n\n if {[llength $intr_width] && [llength $intr_val]} {\n set intrs_List [regexp -inline -all -- {\\S+} $intr_val]\n set intrs_cnt [llength $intrs_List]\n set start \"[expr {${inst} * $intr_width}]\"\n set end \"[expr {$start + $intr_width - 1}]\"\n if { $intrs_cnt > $intr_width } {\n hsi::utils::add_new_dts_param $al5d_node \"interrupts\" \"[lrange $intrs_List $start $end]\" intlist\n } else {\n hsi::utils::add_new_dts_param $al5d_node \"interrupts\" \"$intrs_List\" intlist\n }\n }\n\n if {[llength $intrnames_List]} {\n set intrnames_cnt [llength $intrnames_List]\n if { $intrnames_cnt > 1 } {\n hsi::utils::add_new_dts_param $al5d_node \"interrupt-names\" \"[lindex $intrnames_List $inst]\" string\n } else {\n hsi::utils::add_new_dts_param $al5d_node \"interrupt-names\" \"[lindex $intrnames_List 0]\" string\n }\n }\n set al5d_baseaddr [format %08x [expr 0x$al5d_baseaddr + $al5d_offset]]\n }\n}\n" }, { "path": "axi_xadc/data/axi_xadc.mdd", "content": "#\n# (C) Copyright 2015-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axi_xadc\n\n OPTION supported_peripherals = (xadc_wiz);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axi_xadc;\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "axi_xadc/data/axi_xadc.tcl", "content": "#\n# (C) Copyright 2015-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tgen_xadc_driver_prop $drv_handle\n}\n\nproc gen_xadc_driver_prop {drv_handle} {\n\tgen_drv_prop_from_ip $drv_handle\n\tgen_dev_ccf_binding $drv_handle \"s_axi_aclk\"\n\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,axi-xadc-1.00.a\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset adc_ip [get_cells -hier $drv_handle]\n\tset has_dma [get_property CONFIG.C_HAS_EXTERNAL_MUX $adc_ip]\n\tif {$has_dma == 0} {\n\t\tset has_dma_str \"none\"\n\t} elseif {$has_dma == 1} {\n\t\tset has_dma_str \"single\"\n\t}\n\n\thsi::utils::add_new_property $drv_handle \"xlnx,external-mux\" string $has_dma_str\n\tif {$has_dma != 0} {\n\t\tset ext_mux_chan [get_property CONFIG.EXTERNAL_MUX_CHANNEL $adc_ip]\n\t\tif {[string match -nocase $ext_mux_chan \"VP_VN\"] } {\n\t\t\tset chan_nr 0\n\t\t} else {\n\t\t\tfor {set i 0} { $i < 16 } { incr i} {\n\t\t\t\tif {[string match -nocase $ext_mux_chan \"VAUXP${i}_VAUXN${i}\"]} {\n\t\t\t\t\tset chan_nr [expr $i + 1]\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\thsi::utils::add_new_property $drv_handle \"xlnx,external-mux-channel\" int $chan_nr\n\t}\n}\n" }, { "path": "axis_switch/data/axis_switch.mdd", "content": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver axis_switch\n\n OPTION supported_peripherals = (axis_switch);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = axis_switch;\n\nEND driver\n" }, { "path": "axis_switch/data/axis_switch.tcl", "content": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\t#set compatible [append compatible \" \" \"xlnx,axis-switch\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n set routing_mode [get_property CONFIG.ROUTING_MODE [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,routing-mode\" $routing_mode int\n\tset num_si [get_property CONFIG.NUM_SI [get_cells -hier $drv_handle]]\n hsi::utils::add_new_dts_param \"$node\" \"xlnx,num-si-slots\" $num_si int\n set num_mi [get_property CONFIG.NUM_MI [get_cells -hier $drv_handle]]\n hsi::utils::add_new_dts_param \"$node\" \"xlnx,num-mi-slots\" $num_mi int\n\n\tset ports_node [add_or_get_dt_node -n \"ports\" -l axis_switch_ports$drv_handle -p $node]\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n set port1_node [add_or_get_dt_node -n \"port\" -l axis_switch_port1$drv_handle -u 1 -p $ports_node]\n\thsi::utils::add_new_dts_param \"$port1_node\" \"reg\" 1 int\n\tset count 0\n\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $drv_handle] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\tset ip [get_cells -hier $drv_handle]\n foreach intf $master_intf {\n\t\tset connectip [get_connected_stream_ip [get_cells -hier $ip] $intf]\n\t\tif {[llength $connectip]} {\n\t\tset outipname [get_property IP_NAME $connectip]\n\t\tset valid_mmip_list \"mipi_csi2_rx_subsystem v_tpg v_smpte_uhdsdi_rx_ss v_smpte_uhdsdi_tx_ss v_demosaic v_gamma_lut v_proc_ss v_frmbuf_rd v_frmbuf_wr v_uhdsdi_audio i2s_receiver mipi_dsi_tx_subsystem v_mix v_multi_scaler v_scenechange\"\n\t\tif {[lsearch -nocase $valid_mmip_list $outipname] >= 0} {\n set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip]\n\t\t\tincr count\n\t\t}\n\t\tif {$count ==1} {\n\t\t\tif {[llength $connectip]} {\n\t\t\t\tset port_node [add_or_get_dt_node -n \"port\" -l axis_switch_port1$ip -u 1 -p $ports_node]\n\t\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 1 int\n set axis_node [add_or_get_dt_node -n \"endpoint\" -l axis_switch_out1$ip -p $port_node]\n gen_axis_switch_port1_endpoint $ip \"axis_switch_out1$ip\"\n hsi::utils::add_new_dts_param \"$axis_node\" \"remote-endpoint\" $connectip$ip reference\n gen_axis_switch_port1_remote_endpoint $ip $connectip$ip\n\t\t\t}\n\t\t}\n if {$count == 2} {\n if {[llength $connectip]} {\n set port_node [add_or_get_dt_node -n \"port\" -l axis_switch_port2$ip -u 2 -p $ports_node]\n hsi::utils::add_new_dts_param \"$port_node\" \"reg\" 2 int\n set axis_node [add_or_get_dt_node -n \"endpoint\" -l axis_switch_out2$ip -p $port_node]\n gen_axis_switch_port2_endpoint $ip \"axis_switch_out2$ip\"\n hsi::utils::add_new_dts_param \"$axis_node\" \"remote-endpoint\" $connectip$ip reference\n gen_axis_switch_port2_remote_endpoint $ip $connectip$ip\n\t\t\t}\n\t\t}\n\t\t}\n\t}\n}\n" }, { "path": "canfdps/data/canfdps.mdd", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver canfdps\n\n OPTION supported_peripherals = (psu_canfd psv_canfd psx_canfd);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = canfdps;\n\nEND driver\n" }, { "path": "canfdps/data/canfdps.tcl", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n" }, { "path": "canps/data/canps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver canps\n\n OPTION supported_peripherals = (ps7_can psu_can psv_can);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = canps;\n\nEND driver\n" }, { "path": "canps/data/canps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n" }, { "path": "cpu/data/cpu.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver cpu\n\n OPTION driver_state = ACTIVE;\n OPTION supported_peripherals = (microblaze);\n OPTION supported_os_types = (DTS);\n OPTION NAME = cpu;\n\n DTGPARAM name = dev_type, default = cpu , type = string;\n DTGPARAM name = device_type, default = cpu , type = string;\n DTGPARAM name = clock-frequency, type = int , default = 1000000 ;\n DTGPARAM name = clocks, type = int, default = &clk_cpu;\n DTGPARAM name = timebase-frequency, type = int , default = 1000000 ;\n DTGPARAM name = d-cache-baseaddr, type = hexint ;\n DTGPARAM name = d-cache-highaddr, type = hexint ;\n DTGPARAM name = d-cache-line-size, type = hexint ;\n DTGPARAM name = d-cache-size, type = hexint ;\n DTGPARAM name = i-cache-baseaddr, type = hexint ;\n DTGPARAM name = i-cache-highaddr, type = hexint ;\n DTGPARAM name = i-cache-line-size, type = hexint ;\n DTGPARAM name = i-cache-size, type = hexint ;\n DTGPARAM name = model, type = string;\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "cpu/data/cpu.tcl", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n\n set ip [get_cells -hier $drv_handle]\n set clk \"\"\n set clkhandle [get_pins -of_objects $ip \"CLK\"]\n if { [string compare -nocase $clkhandle \"\"] != 0 } {\n set clk [get_property CLK_FREQ $clkhandle]\n }\n if { [llength $ip] } {\n set_property CONFIG.clock-frequency \"$clk\" $drv_handle\n set_property CONFIG.timebase-frequency \"$clk\" $drv_handle\n }\n\n set icache_size [hsi::utils::get_ip_param_value $ip \"C_CACHE_BYTE_SIZE\"]\n set isize [check_64bit $icache_size]\n set icache_base [hsi::utils::get_ip_param_value $ip \"C_ICACHE_BASEADDR\"]\n set ibase [check_64bit $icache_base]\n set icache_high [hsi::utils::get_ip_param_value $ip \"C_ICACHE_HIGHADDR\"]\n set ihigh_base [check_64bit $icache_high]\n set dcache_size [hsi::utils::get_ip_param_value $ip \"C_DCACHE_BYTE_SIZE\"]\n set dsize [check_64bit $dcache_size]\n set dcache_base [hsi::utils::get_ip_param_value $ip \"C_DCACHE_BASEADDR\"]\n set dbase [check_64bit $dcache_base]\n set dcache_high [hsi::utils::get_ip_param_value $ip \"C_DCACHE_HIGHADDR\"]\n set dhigh_base [check_64bit $dcache_high]\n set icache_line_size [expr 4*[hsi::utils::get_ip_param_value $ip \"C_ICACHE_LINE_LEN\"]]\n set dcache_line_size [expr 4*[hsi::utils::get_ip_param_value $ip \"C_DCACHE_LINE_LEN\"]]\n\n\n if { [llength $icache_size] != 0 } {\n set_property CONFIG.i-cache-baseaddr \"$ibase\" $drv_handle\n set_property CONFIG.i-cache-highaddr \"$ihigh_base\" $drv_handle\n set_property CONFIG.i-cache-size \"$isize\" $drv_handle\n set_property CONFIG.i-cache-line-size \"$icache_line_size\" $drv_handle\n }\n if { [llength $dcache_size] != 0 } {\n set_property CONFIG.d-cache-baseaddr \"$dbase\" $drv_handle\n set_property CONFIG.d-cache-highaddr \"$dhigh_base\" $drv_handle\n set_property CONFIG.d-cache-size \"$dsize\" $drv_handle\n set_property CONFIG.d-cache-line-size \"$dcache_line_size\" $drv_handle\n }\n\n set model \"[get_property IP_NAME $ip],[hsi::utils::get_ip_version $ip]\"\n set_property CONFIG.model $model $drv_handle\n\n # create root node\n set master_root_node [gen_root_node $drv_handle]\n set nodes [gen_cpu_nodes $drv_handle]\n}\n\nproc check_64bit {base} {\n\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$base\" match]} {\n\t\tset temp $base\n\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\tset len [string length $temp]\n\t\tset rem [expr {${len} - 8}]\n\t\tset high_base \"0x[string range $temp $rem $len]\"\n\t\tset low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\tset low_base [format 0x%08x $low_base]\n\t\tif {$low_base == 0x0} {\n\t\t\tset reg \"$high_base\"\n\t\t} else {\n\t\t\tset reg \"$low_base $high_base\"\n\t\t}\n\t} else {\n\t\tset reg \"$base\"\n\t}\n\treturn $reg\n}\n" }, { "path": "cpu_cortexa53/data/cpu_cortexa53.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver cpu_cortexa53\n\n OPTION driver_state = ACTIVE;\n OPTION supported_peripherals = (psu_cortexa53);\n OPTION supported_os_types = (DTS);\n OPTION NAME = cpu_cortexa53;\n\nEND driver\n" }, { "path": "cpu_cortexa53/data/cpu_cortexa53.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tglobal dtsi_fname\n\tset mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n\tset valid_mainline_kernel_list \"v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4\"\n if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } {\n\t\tset dtsi_fname \"zynqmp/zynqmp.dtsi\"\n\t} else {\n\t\tset dtsi_fname \"zynqmp/zynqmp.dtsi\"\n\t}\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\n\t# create root node\n\tset master_root_node [gen_root_node $drv_handle]\n\tset nodes [gen_cpu_nodes $drv_handle]\n}\n" }, { "path": "cpu_cortexa72/data/cpu_cortexa72.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver cpu_cortexa72\n\n OPTION driver_state = ACTIVE;\n OPTION supported_peripherals = (psv_cortexa72);\n OPTION supported_os_types = (DTS);\n OPTION NAME = cpu_cortexa72;\n\nEND driver\n" }, { "path": "cpu_cortexa72/data/cpu_cortexa72.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tglobal dtsi_fname\n\tset dtsi_fname \"versal/versal.dtsi\"\n\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\n\t# create root node\n\tset master_root_node [gen_root_node $drv_handle]\n\tset nodes [gen_cpu_nodes $drv_handle]\n}\n" }, { "path": "cpu_cortexa78/data/cpu_cortexa78.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver cpu_cortexa78\n\n OPTION driver_state = ACTIVE;\n OPTION supported_peripherals = (psx_cortexa78);\n OPTION supported_os_types = (DTS);\n OPTION NAME = cpu_cortexa78;\n\nEND driver\n" }, { "path": "cpu_cortexa78/data/cpu_cortexa78.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tglobal dtsi_fname\n set board_dtsi_file \"\"\n\tset overrides [get_property CONFIG.periph_type_overrides [get_os]]\n\tforeach override $overrides {\n\t if {[lindex $override 0] == \"BOARD\"} {\n\t set board_dtsi_file [lindex $override 1]\n\t }\n\t}\n #TMP fix to support ipp fixed clocks\n if {[string match -nocase $board_dtsi_file \"versal-net-ipp-rev1.9\"]} {\n set dtsi_fname \"versal-net/versal-net-ipp-rev1.9.dtsi\"\n } else {\n\t set dtsi_fname \"versal-net/versal-net.dtsi\"\n }\n\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\n\t# create root node\n\tset master_root_node [gen_root_node $drv_handle]\n\tset nodes [gen_cpu_nodes $drv_handle]\n}\n" }, { "path": "cpu_cortexa9/data/cpu_cortexa9.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver cpu_cortexa9\n\n OPTION driver_state = ACTIVE;\n OPTION supported_peripherals = (ps7_cortexa9);\n OPTION supported_os_types = (DTS);\n OPTION NAME = cpu_cortexa9;\n\nEND driver\n" }, { "path": "cpu_cortexa9/data/cpu_cortexa9.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tglobal dtsi_fname\n\tset dtsi_fname \"zynq/zynq-7000.dtsi\"\n\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\n\t# create root node\n\tset master_root_node [gen_root_node $drv_handle]\n\tset nodes [gen_cpu_nodes $drv_handle]\n}\n" }, { "path": "dccps/data/dccps.mdd", "content": "# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver dccps\n\n OPTION supported_peripherals = (psu_coresight_0 psv_coresight psx_coresight);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = dccps;\n DTGPARAM name = device_type , type = string, default = serial;\n DTGPARAM name = dtg.alias, type = string, default = serial;\n DTGPARAM name = port-number, type = int, default = 0;\n\nEND driver\n" }, { "path": "dccps/data/dccps.tcl", "content": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset ip [get_cells -hier $drv_handle]\n\tset def_dts [get_property CONFIG.pcw_dts [get_os]]\n\tset dcc_node [add_or_get_dt_node -n \"&dcc\" -d $def_dts]\n\thsi::utils::add_new_dts_param \"${dcc_node}\" \"status\" \"okay\" string\n}\n" }, { "path": "ddrcps/data/ddrcps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver ddrcps\n\n OPTION supported_peripherals = (ps7_ddrc psu_ddrc psv_ddrc);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = ddrcps;\n\nEND driver\n" }, { "path": "ddrcps/data/ddrcps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n" }, { "path": "ddrps/data/ddrps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver ddrps\n\n OPTION supported_peripherals = (ps7_ddr psu_ddr psv_ddr);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = ddrps;\n\nEND driver\n" }, { "path": "ddrps/data/ddrps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\n# workaround for ps7 ddrc has none zero start address\nproc gen_ps7_ddr_reg_property {drv_handle} {\n proc_called_by\n set regprop [ hsi::utils::get_os_parameter_value \"regp\"]\n set psu_cortexa53 \"\"\n set slave [get_cells -hier ${drv_handle}]\n set ip_mem_handles [hsi::utils::get_ip_mem_ranges $slave]\n set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n if {[string match -nocase $proctype \"ps7_cortexa9\"]} {\n set value 0\n } else {\n set value [generate_secure_memory $drv_handle]\n }\n if { $value !=0} {\n hsi::utils::set_os_parameter_value \"regp\" $value\n set_drv_prop_if_empty $drv_handle reg $value intlist\n } else {\n set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n foreach mem_handle ${ip_mem_handles} {\n #set base [get_property BASE_VALUE $mem_handle]\n\t set base 0x0\n set high [get_property HIGH_VALUE $mem_handle]\n\t set mem_size [format 0x%x [expr {${high} - ${base} + 1}]]\n if {[string match -nocase $proctype \"psu_cortexa53\"]} {\n # Check if memory crossing 4GB map, then split 2GB below 32 bit limit\n # and remaining above 32 bit limit\n if { [expr {${mem_size} + ${base}}] >= [expr 0x100000000] } {\n set low_mem_size [expr {0x80000000 - ${base}}]\n set high_mem_size [expr {${mem_size} - ${low_mem_size}}]\n set low_mem_size [format \"0x%x\" ${low_mem_size}]\n set high_mem_size [get_high_mem_size $high_mem_size]\n set regval \"0x0 ${base} 0x0 $low_mem_size>, <0x8 0x00000000 $high_mem_size\"\n } else {\n set regval \"0x0 ${base} 0x0 ${mem_size}\"\n }\n } else {\n set regval \"$base $mem_size\"\n }\n if {[string_is_empty $regprop]} {\n\t\tset regprop $regval\n } else {\n # ensure no duplication\n if {![regexp \".*${regprop}.*\" \"$regval\" matched]} {\n set regprop \"$regval\"\n }\n }\n }\n hsi::utils::set_os_parameter_value \"regp\" $regprop\n set_drv_prop_if_empty $drv_handle reg $regprop intlist\n }\n}\n\nproc generate_secure_memory {drv_handle} {\n set regprop [ hsi::utils::get_os_parameter_value \"regp\"]\n set psu_cortexa53 \"\"\n set slave [get_cells -hier ${drv_handle}]\n set ip_mem_handles [hsi::utils::get_ip_mem_ranges $slave]\n set firstelement [lindex $ip_mem_handles 0]\n set index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] [get_cells $firstelement]]\n set avail_param [list_property [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]]\n set addr_64 \"0\"\n set size_64 \"0\"\n if {[lsearch -nocase $avail_param \"TRUSTZONE\"] >= 0} {\n foreach bank ${ip_mem_handles} {\n set state [get_property TRUSTZONE [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]]\n if {[string match -nocase $state \"NonSecure\"]} {\n set index [lsearch -start $index [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] [get_cells -hier $bank]]\n set base [get_property BASE_VALUE [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]]\n set high [get_property HIGH_VALUE [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]]\n set mem_size [format 0x%x [expr {${high} - ${base} + 1}]]\n if {[regexp -nocase {0x([0-9a-f]{9})} \"$base\" match]} {\n set addr_64 \"1\"\n set temp $base\n set temp [string trimleft [string trimleft $temp 0] x]\n set len [string length $temp]\n set rem [expr {${len} - 8}]\n set high_base \"0x[string range $temp $rem $len]\"\n set low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n set low_base [format 0x%08x $low_base]\n }\n if {[regexp -nocase {0x([0-9a-f]{9})} \"$mem_size\" match]} {\n set size_64 \"1\"\n set temp $mem_size\n set temp [string trimleft [string trimleft $temp 0] x]\n set len [string length $temp]\n set rem [expr {${len} - 8}]\n set high_size \"0x[string range $temp $rem $len]\"\n set low_size \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n set low_size [format 0x%08x $low_size]\n }\n if {[string match $regprop \"\"]} {\n if {[string match $addr_64 \"1\"] && [string match $size_64 \"1\"]} {\n set regprop \"$low_base $high_base $low_size $high_size\"\n } elseif {[string match $addr_64 \"1\"] && [string match $size_64 \"0\"]} {\n set regprop \"${low_base} ${high_base} 0x0 ${mem_size}\"\n } elseif {[string match $addr_64 \"0\"] && [string match $size_64 \"1\"]} {\n set regprop \"0x0 ${base} 0x0 ${mem_size}\"\n } else {\n set regprop \"0x0 ${base} 0x0 ${mem_size}\"\n }\n } else {\n if {[string match $addr_64 \"1\"] && [string match $size_64 \"1\"]} {\n append regprop \">, \" \"<$low_base $high_base $low_size $high_size\"\n } elseif {[string match $addr_64 \"1\"] && [string match $size_64 \"0\"]} {\n append regprop \">, \" \"<${low_base} ${high_base} 0x0 ${mem_size}\"\n } elseif {[string match $addr_64 \"0\"] && [string match $size_64 \"1\"]} {\n append regprop \">, \" \"<0x0 ${base} 0x0 ${mem_size}\"\n } else {\n append regprop \">, \" \"<0x0 ${base} 0x0 ${mem_size}\"\n }\n }\n }\n set addr_64 \"0\"\n set size_64 \"0\"\n set index [expr $index + 1]\n }\n return $regprop\n } else {\n return 0\n }\n}\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n gen_ps7_ddr_reg_property $drv_handle\n set value [get_property CONFIG.reg $drv_handle]\n if {![string match $value \"\"]} {\n add_memory_node $drv_handle\n }\n}\n\nproc get_high_mem_size {high_mem_size} {\n\tset size \"0x0 0x0\"\n\tset high_mem_size [format \"0x%x\" ${high_mem_size}]\n\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$high_mem_size\" match]} {\n\t\tset temp $high_mem_size\n\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\tset len [string length $temp]\n\t\tset rem [expr {${len} - 8}]\n\t\tset high_mem \"0x[string range $temp $rem $len]\"\n\t\tset low_mem \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\tset low_mem [format 0x%08x $low_mem]\n\t\tset size \"$low_mem $high_mem\"\n\t} else {\n\t\tset size \"0x0 $high_mem_size\"\n\t}\n\treturn $size\n}\n" }, { "path": "ddrpsv/data/ddrpsv.mdd", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver ddrpsv\n\n OPTION supported_peripherals = (axi_noc axi_noc2 noc_mc_ddr4 noc_mc_ddr5);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = ddrpsv;\n\nEND driver\n" }, { "path": "ddrpsv/data/ddrpsv.tcl", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset master_dts [get_property CONFIG.master_dts [get_os]]\n\tset cur_dts [current_dt_tree]\n\tset master_dts_obj [get_dt_trees ${master_dts}]\n\tset_cur_working_dts $master_dts\n\tset parent_node [add_or_get_dt_node -n / -d ${master_dts}]\n\n\tset sw_proc [hsi::get_sw_processor]\n\tset periph [get_cells -hier $drv_handle]\n\tset interface_block_names [get_property ADDRESS_BLOCK [get_mem_ranges -of_objects [get_cells -hier $sw_proc] $periph]]\n\n\tset Supported_channels { \\\n\t\t\"C*_DDR_LOW0*\" \"C*_DDR_LOW1*\" \"C*_DDR_LOW2*\" \"C*_DDR_LOW3*\" \"C*_DDR_CH0*\" \"C*_DDR_CH1*\" \"C*_DDR_CH2*\" \"C*_DDR_CH3*\" \\\n\t\t\"HBM0_*PC0*\" \"HBM0_*PC1*\" \"HBM1_*PC0*\" \"HBM1_*PC1*\" \"HBM2_*PC0*\" \"HBM2_*PC1*\" \"HBM3_*PC0*\" \"HBM3_*PC1*\" \"HBM4_*PC0*\" \\\n\t\t\"HBM4_*PC1*\" \"HBM5_*PC0*\" \"HBM5_*PC1*\" \"HBM6_*PC0*\" \"HBM6_*PC1*\" \"HBM7_*PC0*\" \"HBM7_*PC1*\" \"HBM8_*PC0*\" \"HBM8_*PC1*\" \\\n\t\t\"HBM9_*PC0*\" \"HBM9_*PC1*\" \"HBM10_*PC0*\" \"HBM10_*PC1*\" \"HBM11_*PC0*\" \"HBM11_*PC1*\" \"HBM12_*PC0*\" \"HBM12_*PC1*\" \"HBM13_*PC0*\" \\\n\t\t\"HBM13_*PC1*\" \"HBM14_*PC0*\" \"HBM14_*PC1*\" \"HBM15_*PC0*\" \"HBM15_*PC1*\" \\\n\t}\n\tset Configured_channels [dict create]\n\n\tset i 0\n\tforeach block_name $interface_block_names {\n\t\tforeach channel $Supported_channels {\n\t\t\tif {[string match $channel $block_name]} {\n\t\t\t\t# Remove C* for ddr case for unique dict key\n\t\t\t\tregsub -all {^C[0-9]_} $block_name {} trim_blockname\n\t\t\t\tset memlabel \"ddr\"\n\t\t\t\tif {[string match -nocase \"*HBM*\" $block_name]} {\n\t\t\t\t\tset memlabel \"hbm\"\n\t\t\t\t}\n\t\t\t\tset base_addr [common::get_property BASE_VALUE [lindex [get_mem_ranges -of_objects [get_cells -hier $sw_proc] $periph] $i]]\n\t\t\t\tif {[dict exists $Configured_channels $memlabel] && [dict exists $Configured_channels $memlabel $trim_blockname]} {\n\t\t\t\t\tset base_addrtmp [dict get $Configured_channels $memlabel $trim_blockname \"base_addr\"]\n\t\t\t\t\tif {[string compare $base_addrtmp $base_addr] < 0 } {\n\t\t\t\t\t\tset base_addr $base_addrtmp\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset high_addr [common::get_property HIGH_VALUE [lindex [get_mem_ranges -of_objects [get_cells -hier $sw_proc] $periph] $i]]\n\t\t\t\tdict set Configured_channels $memlabel $trim_blockname \"base_addr\" $base_addr\n\t\t\t\tdict set Configured_channels $memlabel $trim_blockname \"high_addr\" $high_addr\n\t\t\t}\n\t\t}\n\t\tincr i\n\t}\n\n\tforeach memlabel [dict keys $Configured_channels] {\n\t\tset Reg_values \"\"\n\t\tforeach chkey [dict keys [dict get $Configured_channels $memlabel]] {\n\t\t\tset base_addr [dict get $Configured_channels $memlabel $chkey \"base_addr\"]\n\t\t\tset high_addr [dict get $Configured_channels $memlabel $chkey \"high_addr\"]\n\t\t\tset Reg_values [lappend Reg_values [generate_reg_property $base_addr $high_addr]]\n\t\t}\n\t\tif {[llength $Reg_values]} {\n\t\t\tset Reg_values [join $Reg_values \">, <\"]\n\t\t\tgenerate_mem_node $Reg_values $parent_node $memlabel $drv_handle\n\t\t}\n\t}\n}\n\n\nproc generate_mem_node {reg_val parent_node mem_label drv_handle} {\n\tif {[llength $reg_val]} {\n\t\tset higheraddr [expr [lindex $reg_val 0] << 32]\n\t\tset loweraddr [lindex $reg_val 1]\n\t\tset baseaddr [format 0x%x [expr {${higheraddr} + ${loweraddr}}]]\n\t\tregsub -all {^0x} $baseaddr {} baseaddr\n\t\tset memory_node [add_or_get_dt_node -n memory -l \"memory$drv_handle\\_$mem_label\" -u $baseaddr -p $parent_node]\n\t\tif {[catch {set dev_type [get_property CONFIG.device_type $drv_handle]} msg]} {\n\t\t\tset dev_type memory\n\t\t}\n\t\tif {[string_is_empty $dev_type]} {set dev_type memory}\n\t\thsi::utils::add_new_dts_param \"${memory_node}\" \"device_type\" $dev_type string\n\t\thsi::utils::add_new_dts_param \"${memory_node}\" \"reg\" $reg_val inthexlist\n\t}\n}\n" }, { "path": "debug_bridge/data/debug_bridge.mdd", "content": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver debug_bridge\n\n OPTION supported_peripherals = (debug_bridge);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = debug_bridge;\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "debug_bridge/data/debug_bridge.tcl", "content": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"generic-uio\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n}\n" }, { "path": "demosaic/data/demosaic.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver demosaic\n\n OPTION supported_peripherals = (v_demosaic);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = demosaic;\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "demosaic/data/demosaic.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,v-demosaic\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset s_axi_ctrl_addr_width [get_property CONFIG.C_S_AXI_CTRL_ADDR_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,s-axi-ctrl-addr-width\" $s_axi_ctrl_addr_width int\n\tset s_axi_ctrl_data_width [get_property CONFIG.C_S_AXI_CTRL_DATA_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,s-axi-ctrl-data-width\" $s_axi_ctrl_data_width int\n\tset max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]]\n\tset max_rows [get_property CONFIG.MAX_ROWS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,max-height\" $max_rows int\n\tset max_cols [get_property CONFIG.MAX_COLS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,max-width\" $max_cols int\n\tset max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]]\n\n\tset ports_node [add_or_get_dt_node -n \"ports\" -l demosaic_ports$drv_handle -p $node]\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\tset port1_node [add_or_get_dt_node -n \"port\" -l demosaic_port1$drv_handle -u 1 -p $ports_node]\n\thsi::utils::add_new_dts_param \"$port1_node\" \"reg\" 1 int\n\n\tset outip [get_connected_stream_ip [get_cells -hier $drv_handle] \"m_axis_video\"]\n\tset outipname [get_property IP_NAME $outip]\n\tset valid_mmip_list \"mipi_csi2_rx_subsystem v_tpg v_hdmi_rx_ss v_smpte_uhdsdi_rx_ss v_smpte_uhdsdi_tx_ss v_demosaic v_gamma_lut v_proc_ss v_frmbuf_rd v_frmbuf_wr v_hdmi_tx_ss v_hdmi_txss1 v_uhdsdi_audio audio_formatter i2s_receiver i2s_transmitter mipi_dsi_tx_subsystem v_mix v_multi_scaler v_scenechange\"\n\tif {[lsearch -nocase $valid_mmip_list $outipname] >= 0} {\n\tforeach ip $outip {\n\t\tif {[llength $ip]} {\n\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip]\n\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\t\tset demonode [add_or_get_dt_node -n \"endpoint\" -l demo_out$drv_handle -p $port1_node]\n\t\t\t\tgen_endpoint $drv_handle \"demo_out$drv_handle\"\n\t\t\t\thsi::utils::add_new_dts_param \"$demonode\" \"remote-endpoint\" $ip$drv_handle reference\n\t\t\t\tgen_remoteendpoint $drv_handle \"$ip$drv_handle\"\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $ip] \"v_frmbuf_wr\"]} {\n\t\t\t\t\tgen_frmbuf_wr_node $ip $drv_handle\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $ip] \"system_ila\"]} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\tset connectip [get_connect_ip $ip $master_intf]\n\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\tset demonode [add_or_get_dt_node -n \"endpoint\" -l demo_out$drv_handle -p $port1_node]\n\t\t\t\t\tgen_endpoint $drv_handle \"demo_out$drv_handle\"\n\t\t\t\t\thsi::utils::add_new_dts_param \"$demonode\" \"remote-endpoint\" $connectip$drv_handle reference\n\t\t\t\t\tgen_remoteendpoint $drv_handle \"$connectip$drv_handle\"\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"v_frmbuf_wr\"]} {\n\t\t\t\t\t\tgen_frmbuf_wr_node $connectip $drv_handle\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle pin m_axis_video is not connected..check your design\"\n\t\t}\n\t}\n\t}\n\tgen_gpio_reset $drv_handle $node\n}\n\nproc gen_frmbuf_wr_node {outip drv_handle} {\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n set vcap [add_or_get_dt_node -n \"vcap_$drv_handle\" -p $bus_node]\n hsi::utils::add_new_dts_param $vcap \"compatible\" \"xlnx,video\" string\n hsi::utils::add_new_dts_param $vcap \"dmas\" \"$outip 0\" reference\n hsi::utils::add_new_dts_param $vcap \"dma-names\" \"port0\" string\n set vcap_ports_node [add_or_get_dt_node -n \"ports\" -l vcap_ports$drv_handle -p $vcap]\n hsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#address-cells\" 1 int\n hsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#size-cells\" 0 int\n set vcap_port_node [add_or_get_dt_node -n \"port\" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node]\n hsi::utils::add_new_dts_param \"$vcap_port_node\" \"reg\" 0 int\n hsi::utils::add_new_dts_param \"$vcap_port_node\" \"direction\" input string\n set vcap_in_node [add_or_get_dt_node -n \"endpoint\" -l $outip$drv_handle -p $vcap_port_node]\n gen_endpoint $drv_handle \"demo_out$drv_handle\"\n hsi::utils::add_new_dts_param \"$vcap_in_node\" \"remote-endpoint\" demo_out$drv_handle reference\n gen_remoteendpoint $drv_handle \"$outip$drv_handle\"\n}\n\nproc gen_gpio_reset {drv_handle node} {\n\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] \"ap_rst_n\"]]\n\tset proc_type [get_sw_proc_prop IP_NAME]\n\tforeach pin $pins {\n\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tif {[llength $sink_periph]} {\n\t\t\tset sink_ip [get_property IP_NAME $sink_periph]\n\t\t\tif {[string match -nocase $sink_ip \"xlslice\"]} {\n\t\t\t\tset gpio [get_property CONFIG.DIN_FROM $sink_periph]\n\t\t\t\tset pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph \"Din\"]]]\n\t\t\t\tforeach pin $pins {\n\t\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t\tif {[llength $periph]} {\n\t\t\t\t\t\tset ip [get_property IP_NAME $periph]\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psv_cortexa72\"] } {\n\t\t\t\t\t\t\tif { $ip in { \"versal_cips\" \"ps_wizard\" }} {\n\t\t\t\t\t\t\t\t# As versal has only bank0 for MIOs\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 26]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio0 $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n\t\t\t\t\t\t\tif {[string match -nocase $ip \"zynq_ultra_ps_e\"]} {\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 78]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $ip \"axi_gpio\"]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"$periph $gpio 0 1\" reference\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"$drv_handle: peripheral is NULL for the $pin $periph\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle: peripheral is NULL for the $pin $sink_periph\"\n\t\t}\n\t}\n}\n" }, { "path": "devcfg/data/devcfg.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver devcfg\n\n OPTION supported_peripherals = (ps7_dev_cfg);\n OPTION supported_os_types = (DTS)\n OPTION driver_state = ACTIVE;\n OPTION NAME = devcfg;\n\nEND driver\n" }, { "path": "devcfg/data/devcfg.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n" }, { "path": "device_tree/data/common_proc.tcl", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\n#\n# common procedures\n#\n\n# global variables\nglobal def_string zynq_soc_dt_tree bus_clk_list pl_ps_irq1 pl_ps_irq0 intrpin_width\nset pl_ps_irq1 0\nset pl_ps_irq0 0\nset intrpin_width 0\nset def_string \"__def_none\"\nset zynq_soc_dt_tree \"dummy.dtsi\"\nset bus_clk_list \"\"\nglobal or_id\nglobal or_cnt\nset or_id 0\nset or_cnt 0\nglobal set drv_handlers_mapping [dict create]\nglobal set end_mappings [dict create]\nglobal set remote_mappings [dict create]\nglobal set port1_end_mappings [dict create]\nglobal set port2_end_mappings [dict create]\nglobal set port3_end_mappings [dict create]\nglobal set port4_end_mappings [dict create]\nglobal set axis_port1_remo_mappings [dict create]\nglobal set axis_port2_remo_mappings [dict create]\nglobal set axis_port3_remo_mappings [dict create]\nglobal set axis_port4_remo_mappings [dict create]\nglobal set port1_broad_end_mappings [dict create]\nglobal set port2_broad_end_mappings [dict create]\nglobal set port3_broad_end_mappings [dict create]\nglobal set port4_broad_end_mappings [dict create]\nglobal set port5_broad_end_mappings [dict create]\nglobal set port6_broad_end_mappings [dict create]\nglobal set port7_broad_end_mappings [dict create]\nglobal set broad_port1_remo_mappings [dict create]\nglobal set broad_port2_remo_mappings [dict create]\nglobal set broad_port3_remo_mappings [dict create]\nglobal set broad_port4_remo_mappings [dict create]\nglobal set broad_port5_remo_mappings [dict create]\nglobal set broad_port6_remo_mappings [dict create]\nglobal set broad_port7_remo_mappings [dict create]\nglobal set axis_switch_in_end_mappings [dict create]\nglobal set axis_switch_port1_end_mappings [dict create]\nglobal set axis_switch_port2_end_mappings [dict create]\nglobal set axis_switch_port3_end_mappings [dict create]\nglobal set axis_switch_port4_end_mappings [dict create]\nglobal set axis_switch_in_remo_mappings [dict create]\nglobal set axis_switch_port1_remo_mappings [dict create]\nglobal set axis_switch_port2_remo_mappings [dict create]\nglobal set axis_switch_port3_remo_mappings [dict create]\nglobal set axis_switch_port4_remo_mappings [dict create]\n\n\nproc get_clock_frequency {ip_handle portname} {\n\tset clk \"\"\n\tset clkhandle [get_pins -of_objects $ip_handle $portname]\n\tif {[string compare -nocase $clkhandle \"\"] != 0} {\n\t\tset width [::hsi::utils::get_port_width $clkhandle]\n\t\tif {$width >= 2} {\n\t\t\tset clk [get_property CLK_FREQ $clkhandle ]\n\t\t\tregsub -all \":\" $clk { } clk\n\t\t\tset clklen [llength $clk]\n\t\t\tif {$clklen > 1} {\n\t\t\t\tset clk [lindex $clk 0]\n\t\t\t}\n\t\t} else {\n\t\t\tset clk [get_property CLK_FREQ $clkhandle ]\n\t\t}\n\t}\n\treturn $clk\n}\n\nproc set_drv_property args {\n\tset drv_handle [lindex $args 0]\n\tset conf_prop [lindex $args 1]\n\tset value [lindex $args 2]\n\tif {[llength $value] !=0} {\n\t\tif {$value != \"-1\" && [llength $value] !=0} {\n\t\t\tset type \"hexint\"\n\t\t\tif {[llength $args] >= 4} {\n\t\t\t\tset type [lindex $args 3]\n\t\t\t\tif {[string equal -nocase $type \"boolean\"]} {\n\t\t\t\t\tif {[expr $value < 1]} {\n\t\t\t\t\t\treturn 0\n\t\t\t\t\t}\n\t\t\t\t\tset value \"\"\n\t\t\t\t}\n\t\t\t}\n\t\t\t# remove CONFIG. as add_new_property does not work with CONFIG.\n\t\t\tregsub -all {^CONFIG.} $conf_prop {} conf_prop\n\t\t\thsi::utils::add_new_property $drv_handle $conf_prop $type $value\n\t\t}\n\t}\n}\n\n# set driver property based on IP property\nproc set_drv_conf_prop args {\n\tset drv_handle [lindex $args 0]\n\tset pram [lindex $args 1]\n\tset conf_prop [lindex $args 2]\n\tset ip [get_cells -hier $drv_handle]\n\tset value [get_property CONFIG.${pram} $ip]\n\tif {[llength $value] !=0} {\n\t\tregsub -all \"MIO( |)\" $value \"\" value\n\t\tif {$value != \"-1\" && [llength $value] !=0} {\n\t\t\tset type \"hexint\"\n\t\t\tif {[llength $args] >= 4} {\n\t\t\t\tset type [lindex $args 3]\n\t\t\t\tif {[string equal -nocase $type \"boolean\"]} {\n\t\t\t\t\tif {[expr $value < 1]} {\n\t\t\t\t\t\treturn 0\n\t\t\t\t\t}\n\t\t\t\t\tset value \"\"\n\t\t\t\t}\n\t\t\t}\n\t\t\tregsub -all {^CONFIG.} $conf_prop {} conf_prop\n\t\t\thsi::utils::add_new_property $drv_handle $conf_prop $type $value\n\t\t}\n\t}\n}\n\n# set driver property based on other IP's property\nproc add_cross_property args {\n\tset src_handle [lindex $args 0]\n\tset src_prams [lindex $args 1]\n\tset dest_handle [lindex $args 2]\n\tset dest_prop [lindex $args 3]\n\tset ip [get_cells -hier $src_handle]\n\tset ipname [get_property IP_NAME $ip]\n\n\tforeach conf_prop $src_prams {\n\t\tset value [get_property ${conf_prop} $ip]\n\t\tif {$conf_prop == \"CONFIG.processor_mode\"} {\n\t\t\tset value \"true\"\n\t\t}\n\t\tif {$ipname == \"axi_ethernet\"} {\n\t\t\tset value [is_property_set $value]\n\t\t}\n\t\tif {[llength $value]} {\n\t\t\tif {$value != \"-1\" && [llength $value] !=0} {\n\t\t\t\tset type \"hexint\"\n\t\t\t\tif {[llength $args] >= 5} {\n\t\t\t\t\tset type [lindex $args 4]\n\t\t\t\t}\n\t\t\t\tif {[string equal -nocase $type \"boolean\"]} {\n\t\t\t\t\tif {[expr $value < 1]} {\n\t\t\t\t\t\treturn 0\n\t\t\t\t\t}\n\t\t\t\t\tset value \"\"\n\t\t\t\t}\n\t\t\t\tif {[regexp \"(int|hex).*\" $type match]} {\n\t\t\t\t\tregsub -all {\"} $value \"\" value\n\t\t\t\t}\n\t\t\t\tset ipname [get_property IP_NAME [get_cells -hier $ip]]\n\t\t\t\tif {[string match -nocase $ipname \"axi_mcdma\"] && [string match -nocase $dest_prop \"xlnx,include-sg\"] } {\n\t\t\t\t\tset type \"boolean\"\n\t\t\t\t\tset value \"\"\n\t\t\t\t}\n\t\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$value\" match]} {\n\t\t\t\t\tset temp $value\n\t\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\t\tset len [string length $temp]\n\t\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\t\tset high_base \"0x[string range $temp $rem $len]\"\n\t\t\t\t\tset low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\t\tset low_base [format 0x%08x $low_base]\n\t\t\t\t\tset value \"$low_base $high_base\"\n\t\t\t\t}\n\t\t\t\thsi::utils::add_new_property $dest_handle $dest_prop $type $value\n\t\t\t\treturn 0\n\t\t\t}\n\t\t}\n\t}\n}\n\n# TODO: merge to add_cross_property by detecting if dest_node is dt node or driver\nproc add_cross_property_to_dtnode args {\n\tset src_handle [lindex $args 0]\n\tset src_prams [lindex $args 1]\n\tset dest_node [lindex $args 2]\n\tset dest_prop [lindex $args 3]\n\tset ip [get_cells -hier $src_handle]\n\tforeach conf_prop $src_prams {\n\t\tset value [get_property ${conf_prop} $ip]\n\t\tif {[llength $value]} {\n\t\t\tif {$value != \"-1\" && [llength $value] !=0} {\n\t\t\t\tset type \"hexint\"\n\t\t\t\tif {[llength $args] >= 5} {\n\t\t\t\t\tset type [lindex $args 4]\n\t\t\t\t}\n\t\t\t\tif {[string equal -nocase $type \"boolean\"]} {\n\t\t\t\t\tif {[expr $value < 1]} {\n\t\t\t\t\t\treturn 0\n\t\t\t\t\t}\n\t\t\t\t\tset value \"\"\n\t\t\t\t}\n\t\t\t\tif {[regexp \"(int|hex).*\" $type match]} {\n\t\t\t\t\tregsub -all {\"} $value \"\" value\n\t\t\t\t}\n\t\t\t\thsi::utils::add_new_dts_param $dest_node $dest_prop $value $type\n\t\t\t\treturn 0\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc get_ip_property {drv_handle parameter} {\n\tset ip [get_cells -hier $drv_handle]\n\treturn [get_property ${parameter} $ip]\n}\n\nproc is_it_in_pl {ip} {\n\t# FIXME: This is a workaround to check if IP that's in PL however,\n\t# this is not entirely correct, it is a hack and only works for\n\t# IP_NAME that does not matches ps7_*\n\t# better detection is required\n\n\t# handles interrupt that coming from get_drivers only\n\tif {[llength [get_drivers $ip]] < 1} {\n\t\treturn -1\n\t}\n\tset ip_type [get_property IP_NAME $ip]\n\tif {![regexp \"ps*\" \"$ip_type\" match]} {\n\t\treturn 1\n\t}\n\treturn -1\n}\n\nproc get_intr_id {drv_handle intr_port_name} {\n\tset slave [get_cells -hier $drv_handle]\n\tset intr_info \"\"\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tforeach pin ${intr_port_name} {\n\t\tset intc [::hsi::utils::get_interrupt_parent $drv_handle $pin]\n\t\tif {[string_is_empty $intc] == 1} {continue}\n\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\tif {[llength $intc] > 1} {\n\t\t\t\tforeach intr_cntr $intc {\n\t\t\t\t\tif { [::hsi::utils::is_ip_interrupting_current_proc $intr_cntr] } {\n\t\t\t\t\t\tset intc $intr_cntr\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] \"psu_cortexa53\"] && [string match -nocase $intc \"axi_intc\"] } {\n\t\t\t\tset intc [::hsi::utils::get_interrupt_parent $drv_handle $pin]\n\t\t\t}\n\t\t\tif {[string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] \"psv_cortexa72\"] && [string match -nocase $intc \"axi_intc\"] } {\n\t\t\t\tset intc [::hsi::utils::get_interrupt_parent $drv_handle $pin]\n\t\t\t}\n\t\t\tif {[string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] \"psx_cortexa78\"] && [string match -nocase $intc \"axi_intc\"] } {\n\t\t\t\tset intc [::hsi::utils::get_interrupt_parent $drv_handle $pin]\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\tset intr_id [get_psu_interrupt_id $drv_handle $pin]\n\t\t} else {\n\t\t\tset intr_id [::hsi::utils::get_interrupt_id $drv_handle $pin]\n\t\t}\n\t\tif {[string match -nocase $intr_id \"-1\"]} {continue}\n\t\tset intr_type [get_intr_type $intc $slave $pin]\n\t\tif {[string match -nocase $intr_type \"-1\"]} {\n\t\t\tcontinue\n\t\t}\n\n\t\tset cur_intr_info \"\"\n\t\tif { [string match -nocase $proctype \"ps7_cortexa9\"] } {\n\t\t\tif {[string match \"[get_property IP_NAME $intc]\" \"ps7_scugic\"] } {\n\t\t\t\tif {$intr_id > 32} {\n\t\t\t\t\tset intr_id [expr $intr_id - 32]\n\t\t\t\t}\n\t\t\t\tset cur_intr_info \"0 $intr_id $intr_type\"\n\t\t\t} elseif {[string match \"[get_property IP_NAME $intc]\" \"axi_intc\"] } {\n\t\t\t\tset cur_intr_info \"$intr_id $intr_type\"\n\t\t\t}\n\t\t} elseif {[string match -nocase $intc \"psu_acpu_gic\"] \\\n\t\t\t|| [string match -nocase [get_property IP_NAME $intc] \"psv_acpu_gic\"] \\\n\t\t\t|| [string match -nocase [get_property IP_NAME $intc] \"psx_acpu_gic\"]} {\n\t\t set cur_intr_info \"0 $intr_id $intr_type\"\n\t\t} else {\n\t\t\tset cur_intr_info \"$intr_id $intr_type\"\n\t\t}\n\n\t\tif {[string_is_empty $intr_info]} {\n\t\t\tset intr_info \"$cur_intr_info\"\n\t\t} else {\n\t\t\tappend intr_info \" \" $cur_intr_info\n\t\t}\n\t}\n\n\tif {[string_is_empty $intr_info]} {\n\t\tset intr_info -1\n\t}\n\n\treturn $intr_info\n}\n\nproc dtg_debug msg {\n\treturn\n\tputs \"# [lindex [info level -1] 0] #>> $msg\"\n}\n\nproc dtg_verbose msg {\n\tset verbose [get_property CONFIG.dt_verbose [get_os]]\n\tif {$verbose} {\n\t\tputs \"VERBOSE: $msg\"\n\t}\n}\n\nproc dtg_warning msg {\n\tputs \"WARNING: $msg\"\n}\n\nproc proc_called_by {} {\n\treturn\n\tputs \"# [lindex [info level -1] 0] #>> called by [lindex [info level -2] 0]\"\n}\n\nproc Pop {varname {nth 0}} {\n\tupvar $varname args\n\tset r [lindex $args $nth]\n\tset args [lreplace $args $nth $nth]\n\treturn $r\n}\n\nproc string_is_empty {input} {\n\tif {[string compare -nocase $input \"\"] != 0} {\n\t\treturn 0\n\t}\n\treturn 1\n}\n\nproc gen_dt_node_search_pattern args {\n\tproc_called_by\n\t# generates device tree node search pattern and return it\n\n\tglobal def_string\n\tforeach var {node_name node_label node_unit_addr} {\n\t\tset ${var} ${def_string}\n\t}\n\twhile {[string match -* [lindex $args 0]]} {\n\t\tswitch -glob -- [lindex $args 0] {\n\t\t\t-n* {set node_name [Pop args 1]}\n\t\t\t-l* {set node_label [Pop args 1]}\n\t\t\t-u* {set node_unit_addr [Pop args 1]}\n\t\t\t-- {Pop args ; break}\n\t\t\tdefault {\n\t\t\t\terror \"gen_dt_node_search_pattern bad option - [lindex $args 0]\"\n\t\t\t}\n\t\t}\n\t\tPop args\n\t}\n\tset pattern \"\"\n\t# TODO: is these search patterns correct\n\t# TODO: check if pattern in the list or not\n\tif {![string equal -nocase ${node_label} ${def_string}] && \\\n\t\t![string equal -nocase ${node_name} ${def_string}] && \\\n\t\t![string equal -nocase ${node_unit_addr} ${def_string}]} {\n\t\tlappend pattern \"^${node_label}:${node_name}@${node_unit_addr}$\"\n\t\tlappend pattern \"^${node_name}@${node_unit_addr}$\"\n\t}\n\n\tif {![string equal -nocase ${node_label} ${def_string}] && \\\n\t\t![string equal -nocase ${node_name} ${def_string}]} {\n\t\tlappend pattern \"^${node_label}:${node_name}\"\n\t}\n\n\tif {![string equal -nocase ${node_name} ${def_string}] && \\\n\t\t![string equal -nocase ${node_unit_addr} ${def_string}]} {\n\t\tlappend pattern \"^${node_name}@${node_unit_addr}$\"\n\t}\n\n\tif {![string equal -nocase ${node_label} ${def_string}]} {\n\t\tlappend pattern \"^&${node_label}$\"\n\t\tlappend pattern \"^${node_label}:\"\n\t}\n\n\treturn $pattern\n}\n\nproc set_cur_working_dts {{dts_file \"\"}} {\n\t# set current working device tree\n\t# return the tree object\n\tproc_called_by\n\tif {[string_is_empty ${dts_file}] == 1} {\n\t\treturn [current_dt_tree]\n\t}\n\tset dt_idx [lsearch [get_dt_trees] ${dts_file}]\n\tif {$dt_idx >= 0} {\n\t\tset dt_tree_obj [current_dt_tree [lindex [get_dt_trees] $dt_idx]]\n\t} else {\n\t\tset dt_tree_obj [create_dt_tree -dts_file $dts_file]\n\t}\n\treturn $dt_tree_obj\n}\n\nproc get_baseaddr {slave_ip {no_prefix \"\"}} {\n\t# only returns the first addr\n\tset ip_mem_handle [lindex [hsi::utils::get_ip_mem_ranges [get_cells -hier $slave_ip]] 0]\n\tif { [string_is_empty $ip_mem_handle] } {\n\t\treturn -1\n\t}\n\tset addr [string tolower [get_property BASE_VALUE $ip_mem_handle]]\n\tif {![string_is_empty $no_prefix]} {\n\t\tregsub -all {^0x} $addr {} addr\n\t}\n\treturn $addr\n}\n\nproc get_highaddr {slave_ip {no_prefix \"\"}} {\n\tset ip_mem_handle [lindex [hsi::utils::get_ip_mem_ranges [get_cells -hier $slave_ip]] 0]\n\tset addr [string tolower [get_property HIGH_VALUE $ip_mem_handle]]\n\tif {![string_is_empty $no_prefix]} {\n\t\tregsub -all {^0x} $addr {} addr\n\t}\n\treturn $addr\n}\n\nproc get_all_tree_nodes {dts_file} {\n\t# Workaround for -hier not working with -of_objects\n\t# get all the nodes presented in a dt_tree and return node list\n\tproc_called_by\n\tset cur_dts [current_dt_tree]\n\tcurrent_dt_tree $dts_file\n\tset all_nodes [get_dt_nodes -hier]\n\tcurrent_dt_tree $cur_dts\n\treturn $all_nodes\n}\n\nproc check_node_in_dts {node_name dts_file_list} {\n\t# check if the node is in the device-tree file\n\t# return 1 if found\n\t# return 0 if not found\n\tproc_called_by\n\tforeach tmp_dts_file ${dts_file_list} {\n\t\tset dts_nodes [get_all_tree_nodes $tmp_dts_file]\n\t\t# TODO: better detection here\n\t\tforeach pattern ${node_name} {\n\t\t\tforeach node ${dts_nodes} {\n\t\t\t\tif {[regexp $pattern $node match]} {\n\t\t\t\t\tdtg_debug \"Node $node ($pattern) found in $tmp_dts_file\"\n\t\t\t\t\treturn 1\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\treturn 0\n}\n\nproc get_node_object {lu_node {dts_files \"\"} {error_out \"yes\"}} {\n\t# get the node object based on the args\n\t# returns the dt node object\n\tproc_called_by\n\tif [string_is_empty $dts_files] {\n\t\tset dts_files [get_dt_trees]\n\t}\n\tset cur_dts [current_dt_tree]\n\tforeach dts_file ${dts_files} {\n\t\tset dts_nodes [get_all_tree_nodes $dts_file]\n\t\tforeach node ${dts_nodes} {\n\t\t\tif {[regexp $lu_node $node match]} {\n\t\t\t\tset node_data [split $node \":\"]\n\t\t\t\tset node_label [lindex $node_data 0]\n\t\t\t\tset lu_node_data [split $lu_node \":\"]\n\t\t\t\tset lu_node_label [lindex $lu_node_data 0]\n\t\t\t\tif {![string match -nocase \"$node_label\" \"$lu_node_label\"]} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\t# workaround for -hier not working with -of_objects\n\t\t\t\tcurrent_dt_tree $dts_file\n\t\t\t\tset node_obj [get_dt_nodes -hier $node]\n\t\t\t\tcurrent_dt_tree $cur_dts\n\t\t\t\treturn $node_obj\n\t\t\t}\n\t\t}\n\t}\n\tif {[string_is_empty $error_out]} {\n\t\treturn \"\"\n\t} else {\n\t\terror \"Failed to find $lu_node node !!!\"\n\t}\n}\n\nproc update_dt_parent args {\n\t# update device tree node's parent\n\t# return the node name\n\tproc_called_by\n\tglobal def_string\n\tset node [lindex $args 0]\n\tset new_parent [lindex $args 1]\n\tif {[llength $args] >= 3} {\n\t\tset dts_file [lindex $args 2]\n\t} else {\n\t\tset dts_file [current_dt_tree]\n\t}\n\tset node [get_node_object $node $dts_file]\n\t# Skip if node is a reference node (start with &) or amba\n\tif {[regexp \"^&.*\" \"$node\" match] || [regexp \"amba_apu\" \"$node\" match] || [regexp \"amba\" \"$node\" match]} {\n\t\treturn $node\n\t}\n\n\tif {[string_is_empty $new_parent] || \\\n\t\t[string equal ${def_string} \"$new_parent\"]} {\n\t\treturn $node\n\t}\n\n\t# Currently the PARENT node must within the same dt tree\n\tif {![check_node_in_dts $new_parent $dts_file]} {\n\t\terror \"Node '$node' is not in $dts_file tree\"\n\t}\n\n\tset cur_parent [get_property PARENT $node]\n\t# set new parent if required\n\tif {![string equal -nocase ${cur_parent} ${new_parent}] && [string_is_empty ${new_parent}] == 0} {\n\t\tdtg_debug \"Update parent to $new_parent\"\n\t\tset_property PARENT \"${new_parent}\" $node\n\t}\n\treturn $node\n}\n\nproc get_all_dt_labels {{dts_files \"\"}} {\n\t# get all dt node labels\n\tset cur_dts [current_dt_tree]\n\tset labels \"\"\n\tif [string_is_empty $dts_files] {\n\t\tset dts_files [get_dt_trees]\n\t}\n\tforeach dts_file ${dts_files} {\n\t\tset dts_nodes [get_all_tree_nodes $dts_file]\n\t\tforeach node ${dts_nodes} {\n\t\t\tset node_label [get_property \"NODE_LABEL\" $node]\n\t\t\tif {[string_is_empty $node_label]} {\n\t\t\t\tcontinue\n\t\t\t}\n\t\t\tlappend labels $node_label\n\t\t}\n\t}\n\tcurrent_dt_tree $cur_dts\n\treturn $labels\n}\n\nproc list_remove_element {cur_list elements} {\n\tforeach e ${elements} {\n\t\tset rm_idx [lsearch $cur_list $e]\n\t\tset cur_list [lreplace $cur_list $rm_idx $rm_idx]\n\t}\n\treturn $cur_list\n}\n\nproc update_overlay_custom_dts_include {include_file overlay_custom_dts} {\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tset overlay_custom_dts_obj [get_dt_trees ${overlay_custom_dts}]\n\tif {[string_is_empty $overlay_custom_dts_obj] == 1} {\n\t\tset overlay_custom_dts_obj [set_cur_working_dts ${overlay_custom_dts}]\n\t}\n\tif {[string equal ${include_file} ${overlay_custom_dts_obj}]} {\n\t\treturn 0\n\t}\n\tset cur_inc_list [get_property INCLUDE_FILES $overlay_custom_dts_obj]\n\tset tmp_list [split $cur_inc_list \",\"]\n\tif { [lsearch $tmp_list $include_file] < 0} {\n\t\tif {[string_is_empty $cur_inc_list]} {\n\t\t\tset cur_inc_list $include_file\n\t\t} else {\n\t\t\tappend cur_inc_list \",\" $include_file\n\t\t}\n\t\tset_property INCLUDE_FILES ${cur_inc_list} $overlay_custom_dts_obj\n\t}\n}\n\nproc update_system_dts_include {include_file} {\n\t# where should we get master_dts data\n\tset master_dts [get_property CONFIG.master_dts [get_os]]\n\tset cur_dts [current_dt_tree]\n\tset master_dts_obj [get_dt_trees ${master_dts}]\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tset overrides [get_property CONFIG.periph_type_overrides [get_os]]\n\tset dtsi_file \" \"\n\tforeach override $overrides {\n\t\tif {[lindex $override 0] == \"BOARD\"} {\n\t\t\tset dtsi_file [lindex $override 1]\n\t\t}\n\t}\n\n\tif {[string_is_empty $master_dts_obj] == 1} {\n\t\tset master_dts_obj [set_cur_working_dts ${master_dts}]\n\t}\n\tif {[string equal ${include_file} ${master_dts_obj}]} {\n\t\treturn 0\n\t}\n\tset cur_inc_list [get_property INCLUDE_FILES $master_dts_obj]\n\tset tmp_list [split $cur_inc_list \",\"]\n\tif { [lsearch $tmp_list $include_file] < 0} {\n\t\tif {[string_is_empty $cur_inc_list]} {\n\t\t\tset cur_inc_list $include_file\n\t\t} else {\n\t\t\tif {[string match -nocase $proctype \"microblaze\"]} {\n\t\t\t\tappend cur_inc_list \",\" $include_file\n\t\t\t\tset field [split $cur_inc_list \",\"]\n\t\t\t\tif {[regexp $dtsi_file $include_file match]} {\n\t\t\t\t} else {\n\t\t\t\t\tset cur_inc_list [lsort -decreasing $field]\n\t\t\t\t\tset cur_inc_list [join $cur_inc_list \",\"]\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\t# -decreasing order doens not works for versal when boardfile specified as versal-vc-p-a2197-00-...\n\t\t\t\t# Make sure the board file always after versal-net.dtsi or versal-net-clk-ccf.dtsi if exists\n\t\t\t\tset pclk_index -1\n\t\t\t\tforeach pfile {\"versal-clk.dtsi\" \"versal-net-clk-ccf.dtsi\"} {\n\t\t\t\t\tset tmp_pclk_index [lsearch -exact [split $cur_inc_list \",\"] \"$pfile\"]\n\t\t\t\t\tif {$tmp_pclk_index >= 0} {\n\t\t\t\t\t\tset pclk_index $tmp_pclk_index\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {[regexp $dtsi_file $include_file match] && $pclk_index >= 0} {\n\t\t\t\t\tset field [split $cur_inc_list \",\"]\n\t\t\t\t\tset cur_inc_list [linsert $field [expr $pclk_index + 1] $include_file]\n\t\t\t\t\tset cur_inc_list [join $cur_inc_list \",\"]\n\t\t\t\t} else {\n\t\t\t\t\tappend cur_inc_list \",\" $include_file\n\t\t\t\t\tset field [split $cur_inc_list \",\"]\n\t\t\t\t\tset cur_inc_list [lsort -decreasing $field]\n\t\t\t\t\tset cur_inc_list [join $cur_inc_list \",\"]\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tset_property INCLUDE_FILES ${cur_inc_list} $master_dts_obj\n\t}\n\n\t# set dts version\n\tset dts_ver [get_property DTS_VERSION $master_dts_obj]\n\tif {[string_is_empty $dts_ver]} {\n\t\tset_property DTS_VERSION \"/dts-v1/\" $master_dts_obj\n\t}\n\n\tset_cur_working_dts $cur_dts\n}\n\nproc get_rp_rm_for_drv {drv_handle} {\n\tset pr_regions [hsi::get_cells -hier -filter BD_TYPE==BLOCK_CONTAINER]\n\tset rmName \"\"\n\tforeach pr_region $pr_regions {\n\t\tset is_dfx [get_property CONFIG.ENABLE_DFX [hsi::get_cells -hier $pr_region]]\n\t\tif {[llength $is_dfx] && $is_dfx == 0} {\n\t\t\treturn \"\"\n\t\t}\n\t\tset rmName [get_property RECONFIG_MODULE_NAME [hsi::get_cells -hier $pr_region]]\n\t\tset inst [hsi::current_hw_instance [hsi::get_cells -hier $pr_region]]\n\t\tset drv [hsi::get_cells $drv_handle]\n\t\t::hsi::current_hw_instance\n\t\tif {[llength $drv] != 0} {\n\t\t\tappend rpName \"$inst\" \"_\" \"$rmName\"\n\t\t\treturn $rpName\n\n\t\t}\n\t}\n}\n\nproc get_rm_names {pr} {\n set pr_regions [hsi::get_cells -hier -filter BD_TYPE==BLOCK_CONTAINER]\n set rm_names {}\n foreach pr_region $pr_regions {\n\t\tif {[regexp $pr $pr_region match]} {\n\t\t\tset rm_name [get_property RECONFIG_MODULE_NAME [hsi::get_cells -hier $pr_region]]\n\t\t}\n }\n return $rm_name\n}\n\nproc set_drv_def_dts {drv_handle} {\n\t# optional dts control by adding the following line in mdd file\n\t# PARAMETER name = def_dts, default = ps.dtsi, type = string;\n\tset default_dts [get_property CONFIG.def_dts $drv_handle]\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tset partial_image [get_property CONFIG.partial_image [get_os]]\n\tif {[is_pl_ip $drv_handle] && $remove_pl} {\n\t\treturn\n\t}\n\tglobal bus_clk_list\n\tif {[string_is_empty $default_dts]} {\n\t\tif {[is_pl_ip $drv_handle]} {\n\t\t\tset RpRm [get_rp_rm_for_drv $drv_handle]\n\t\t\tregsub -all { } $RpRm \"\" RpRm\n\t\t\tif {[llength $RpRm]} {\n\t\t\t\tset default_dts \"pl-partial-$RpRm.dtsi\"\n\t\t\t} else {\n\t\t\t\tset default_dts \"pl.dtsi\"\n\t\t\t}\n\t\t} else {\n\t\t\t# PS IP, read pcw_dts property\n\t\t\tset default_dts [get_property CONFIG.pcw_dts [get_os]]\n\t\t}\n\t}\n\tset default_dts [set_cur_working_dts $default_dts]\n\tif {$dt_overlay } {\n\t\tset RpRm [get_rp_rm_for_drv $drv_handle]\n\t\tif {[llength $RpRm]} {\n\t\t\tif {$partial_image} {\n\t\t\t\tregsub -all { } $RpRm \"\" RpRm\n\t\t\t\tset partial_imag imag\n\t\t\t\tappend RpRm1 $RpRm $partial_imag\n\t\t\t\tset defaultdts1 \"pl-partial-$RpRm1.dtsi\"\n\t\t\t\tset defdt [create_dt_tree -dts_file $defaultdts1]\n\t\t\t\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\t\t\tset_property DTS_VERSION \"/dts-v1/;\\n/plugin/\" $defdt\n\t\t\t\tif {[string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\t\t\tset targets \"fpga\"\n\t\t\t\t} else {\n\t\t\t\t\tset targets \"fpga_full\"\n\t\t\t\t}\n\t\t\t\tset fpga_node [add_or_get_dt_node -n \"&$targets\" -d ${defdt}]\n\t\t\t\tset child_node1 \"$fpga_node\"\n\t\t\t\tset pr_regions [hsi::get_cells -hier -filter BD_TYPE==BLOCK_CONTAINER]\n\t\t\t\tif {[llength $pr_regions]} {\n\t\t\t\t\tset pr_len [llength $pr_regions]\n\t\t\t\t\tfor {set pr 0} {$pr < $pr_len} {incr pr} {\n\t\t\t\t\t\tset pr1 [lindex $pr_regions $pr]\n\t\t\t\t\t\tif {[regexp $pr1 $RpRm match]} {\n\t\t\t\t\t\t\tset targets \"fpga_PR$pr\"\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $fpga_node target \"$targets\" reference\n\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\t\t\thsi::utils::add_new_dts_param \"${child_node1}\" \"#address-cells\" 2 int\n\t\t\t\thsi::utils::add_new_dts_param \"${child_node1}\" \"#size-cells\" 2 int\n\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\t\t\tset hw_name [::hsi::get_hw_files -filter \"TYPE == partial_bit\"]\n\t\t\t\t} else {\n\t\t\t\t\tset hw_name [::hsi::get_hw_files -filter \"TYPE == partial_pdi\"]\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node1}\" \"firmware-name\" \"$hw_name.bin\" string\n\t\t\t\t} else {\n\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node1}\" \"firmware-name\" \"$hw_name.pdi\" string\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase $default_dts \"pl-partial-$RpRm.dtsi\"]} {\n\t\t\t\t\tset_property DTS_VERSION \"/dts-v1/;\\n/plugin/\" $default_dts\n\t\t\t\t\tset child_node \" \"\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif {![llength $RpRm] && [is_pl_ip $drv_handle]} {\n\t\t\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\t\tset default_dt \"pl.dtsi\"\n\t\t\tset defaultdts [set_cur_working_dts $default_dt]\n\t\t\tset master_dts [get_dt_trees ${defaultdts}]\n\t\t\tset_property DTS_VERSION \"/dts-v1/;\\n/plugin/\" $master_dts\n\t\t\tif {[string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\t\tset targets \"fpga\"\n\t\t\t} else {\n\t\t\t\tset targets \"fpga_full\"\n\t\t\t}\n\t\t\tset fpga_node [add_or_get_dt_node -n \"&$targets\" -d ${defaultdts}]\n\t\t\tset child_node $fpga_node\n\t\t\tset pr_regions [hsi::get_cells -hier -filter BD_TYPE==BLOCK_CONTAINER]\n\t\t\tset classic_soc [get_property CONFIG.classic_soc [get_os]]\n\t\t\tif {[llength $pr_regions]} {\n\t\t\t\tset pr_len [llength $pr_regions]\n\t\t\t\tfor {set pr 0} {$pr < $pr_len} {incr pr} {\n\t\t\t\t\tset pr_node [add_or_get_dt_node -l \"fpga_PR$pr\" -n \"fpga-PR$pr\" -p $child_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${pr_node}\" \"compatible\" \"fpga-region\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${pr_node}\" \"#address-cells\" 2 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${pr_node}\" \"#size-cells\" 2 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${pr_node}\" \"ranges\" \"\" boolean\n\t\t\t\t}\n\t\t\t}\n\t\t\tset hw_name [get_property CONFIG.firmware_name [get_os]]\n\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"ps7_cortexa9\"]} {\n\t\t\t\tif {![llength $hw_name]} {\n\t\t\t\t\tset hw_name [::hsi::get_hw_files -filter \"TYPE == bit\"]\n\t\t\t\t}\n\t\t\t\thsi::utils::add_new_dts_param \"${child_node}\" \"firmware-name\" \"$hw_name.bin\" string\n\t\t\t}\n\t\t\tset UID [get_property HW_DESIGN_ID [hsi::current_hw_design]]\n\t\t\tset PID [get_property HW_PARENT_ID [hsi::current_hw_design]]\n\t\t\tif {[string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\t\tif {![llength $pr_regions]} {\n\t\t\t\t\t#fpga node required to add non-reg nodes for versal{-net}\n\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node}\" \"#address-cells\" 2 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node}\" \"#size-cells\" 2 int\n\t\t\t\t}\n\t\t\t\tif {![llength $hw_name]} {\n\t\t\t\t\tset hw_name [::hsi::get_hw_files -filter \"TYPE == pdi\"]\n\t\t\t\t}\n\t\t\t\t#external-fpga-config is required only in dfx case\n\t\t\t\tif {!$classic_soc && [llength $pr_regions]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node}\" \"external-fpga-config\" \"\" boolean\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[llength $UID]} {\n\t\t\t\thsi::utils::add_new_dts_param \"${child_node}\" \"uid\" $UID int\n\t\t\t}\n\t\t\tif {[llength $PID]} {\n\t\t\t\thsi::utils::add_new_dts_param \"${child_node}\" \"pid\" $PID int\n\t\t\t}\n\t\t}\n\t}\n\n\tif {[is_pl_ip $drv_handle] && $dt_overlay} {\n\t\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\tif {[string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\tset targets \"fpga\"\n\t\t} else {\n\t\t\tset targets \"fpga_full\"\n\t\t}\n\t\t#fpga node for new soc boot flow.\n\t\tset new_soc_hw_name [::hsi::get_hw_files -filter \"TYPE == pl_pdi\"]\n\t\tif {[llength $new_soc_hw_name]} {\n\t\t\tset fpga_node [add_or_get_dt_node -n \"&$targets\" -d ${default_dts}]\n\t\t\tset child_node \"$fpga_node\"\n\t\t\t#if configured firmware name exists\n\t\t\tset hw_name [get_property CONFIG.firmware_name [get_os]]\n\t\t\tif {![llength $hw_name]} {\n\t\t\t\tset hw_name $new_soc_hw_name\n\t\t\t}\n\t\t\thsi::utils::add_new_dts_param \"${child_node}\" \"#address-cells\" 2 int\n\t\t\thsi::utils::add_new_dts_param \"${child_node}\" \"#size-cells\" 2 int\n\t\t\tif {[regexp \".*.pdi\" $hw_name matched]} {\n\t\t\t\thsi::utils::add_new_dts_param \"${child_node}\" \"firmware-name\" \"$hw_name\" string\n\t\t\t} else {\n\t\t\t\thsi::utils::add_new_dts_param \"${child_node}\" \"firmware-name\" \"$hw_name.pdi\" string\n\t\t\t}\n\t\t}\n\t\tset RpRm [get_rp_rm_for_drv $drv_handle]\n\t\tregsub -all { } $RpRm \"\" RpRm\n\t\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\tif {[llength $RpRm]} {\n\t\t\tif {$partial_image} {\n puts \"frag0 ret\"\n\t\t\t} else {\n\t\t\t\tset default_dts \"pl-partial-$RpRm.dtsi\"\n\t\t\t\tset master_dts_obj [get_dt_trees ${default_dts}]\n\t\t\t\tset_property DTS_VERSION \"/dts-v1/;\\n/plugin/\" $master_dts_obj\n\t\t\t\tset fpga_node [add_or_get_dt_node -n \"&$targets\" -d ${default_dts}]\n\t\t\t\tset child_node2 \"$fpga_node\"\n\t\t\t\tset classic_soc [get_property CONFIG.classic_soc [get_os]]\n\t\t\t\tif {$classic_soc} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node2}\" \"#address-cells\" 2 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node2}\" \"#size-cells\" 2 int\n\t\t\t\t}\n\t\t\t\tset pr_regions [hsi::get_cells -hier -filter BD_TYPE==BLOCK_CONTAINER]\n\t\t\t\tif {[llength $pr_regions]} {\n\t\t\t\t\tset pr_len [llength $pr_regions]\n\t\t\t\t\tfor {set pr 0} {$pr < $pr_len} {incr pr} {\n\t\t\t\t\t\tset pr1 [lindex $pr_regions $pr]\n\t\t\t\t\t\tif {[regexp $pr1 $RpRm match]} {\n\t\t\t\t\t\t\tset targets \"fpga_PR$pr\"\n\t\t\t\t\t\t\tif {$classic_soc} {\n\t\t\t\t\t\t\t\tset targets \"fpga\"\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {[llength $pr_regions]} {\n\t\t\t\t\tset pr_len [llength $pr_regions]\n\t\t\t\t\tfor {set pr 0} {$pr < $pr_len} {incr pr} {\n\t\t\t\t\t\tset pr0 [lindex $pr_regions $pr]\n\t\t\t\t\t\tif {[regexp $pr0 $RpRm match]} {\n\t\t\t\t\t\t\tset targets \"fpga_PR$pr\"\n\t\t\t\t\t\t\tif {$classic_soc} {\n\t\t\t\t\t\t\t\tset targets \"fpga\"\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tset fpga_node [add_or_get_dt_node -n \"&$targets\" -d ${default_dts}]\n\t\t\t\t\t\t\tset child_node2 \"$fpga_node\"\n\t\t\t\t\t\t\tset intf_pins [::hsi::get_intf_pins -of_objects $pr0]\n\t\t\t\t\t\t\tforeach intf $intf_pins {\n\t\t\t\t\t\t\t\tset connectip [get_connected_stream_ip [get_cells -hier $pr0] $intf]\n\t\t\t\t\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\t\t\t\t\tif { [get_property IP_NAME $connectip] in { \"dfx_decoupler\" \"dfx_axi_shutdown_manager\" } } {\n\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param $child_node2 \"fpga-bridges\" \"$connectip\" reference\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {!$classic_soc} {\n\t\t\t\t\thsi::utils::add_new_dts_param $child_node2 \"partial-fpga-config\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset hw_name [get_property CONFIG.firmware_name [get_os]]\n\t\t\t\tset rprmpartial $hw_name\n\t\t\t\tif {![llength $hw_name]} {\n\t\t\t\t\tif {[llength $pr_regions]} {\n\t\t\t\t\t\tset pr_len [llength $pr_regions]\n\t\t\t\t\t\tfor {set pr 0} {$pr < $pr_len} {incr pr} {\n\t\t\t\t\t\t\tset pr0 [lindex $pr_regions $pr]\n\t\t\t\t\t\t\tif {[regexp $pr0 $RpRm match]} {\n\t\t\t\t\t\t\t\tset RmName_prop [get_rm_names $pr0]\n\t\t\t\t\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\t\t\t\t\t\t\tappend pdi_name ${RmName_prop} \"_\" \"BIT_FILE\"\n\t\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\t\tappend pdi_name ${RmName_prop} \"_\" \"PDI_FILE\"\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\tset rprmpartial [file tail [get_property $pdi_name [hsi::current_hw_design]]]\n\t\t\t\t\t\t\t\tif {[llength $rprmpartial]} {\n\t\t\t\t\t\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node2}\" \"firmware-name\" \"$rprmpartial.bin\" string\n\t\t\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\t\t\tif {[regexp \".*.pdi\" $rprmpartial matched]} {\n\t\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node2}\" \"firmware-name\" \"$rprmpartial\" string\n\t\t\t\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node2}\" \"firmware-name\" \"$rprmpartial.pdi\" string\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\tappend uid_prop ${RmName_prop} \"_\" \"HW_DESIGN_ID\"\n\t\t\t\t\t\t\t\tset UID [get_property $uid_prop [hsi::current_hw_design]]\n\t\t\t\t\t\t\t\tappend pid_prop ${RmName_prop} \"_\" \"HW_PARENT_ID\"\n\t\t\t\t\t\t\t\tset PID [get_property $pid_prop [hsi::current_hw_design]]\n\t\t\t\t\t\t\t\tif {[llength $UID]} {\n\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node2}\" \"uid\" $UID int\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\tif {[llength $PID]} {\n\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node2}\" \"pid\" $PID int\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tset RpRm1 [get_rp_rm_for_drv $drv_handle]\n\t\t\t\t\tregsub -all { } $RpRm1 \"_\" RpRm\n\t\t\t\t\tif {[llength $RpRm]} {\n\t\t\t\t\t\tset bitfiles_len [llength $hw_name]\n\t\t\t\t\t\tfor {set i 0} {$i < $bitfiles_len} {incr i} {\n\t\t\t\t\t\t\tset rprm_bit_file_name [lindex $hw_name $i]\n\t\t\t\t\t\t\tif {[regexp [lindex $RpRm1 1] $rprm_bit_file_name match]} {\n\t\t\t\t\t\t\t\tset rprmpartial [lindex $hw_name $i]\n\t\t\t\t\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node2}\" \"firmware-name\" \"$rprmpartial.bin\" string\n\t\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\t\tif {[regexp \".*.pdi\" $rprmpartial matched]} {\n\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node2}\" \"firmware-name\" \"$rprmpartial\" string\n\t\t\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node2}\" \"firmware-name\" \"$rprmpartial.pdi\" string\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {[llength $hw_name]} {\n\t\t\t\t\tputs \"rprmpartial:$hw_name\"\n\t\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node2}\" \"firmware-name\" \"$hw_name.bin\" string\n\t\t\t\t\t} else {\n\t\t\t\t\t\tif {[regexp \".*.pdi\" $hw_name matched]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node2}\" \"firmware-name\" \"$hw_name\" string\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node2}\" \"firmware-name\" \"$hw_name.pdi\" string\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tset child_node $fpga_node\n\t\t\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\t\tif {[string match -nocase $proctype \"psv_cortexa72\"]} {\n\t\t\t\tset targets \"fpga\"\n\t\t\t}\n\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\t\tset targets \"fpga_full\"\n\t\t\t}\n\t\t\tset pr_regions [hsi::get_cells -hier -filter BD_TYPE==BLOCK_CONTAINER]\n\t\t\tif {[llength $pr_regions]} {\n\t\t\t\tset pr_len [llength $pr_regions]\n\t\t\t\tfor {set pr 0} {$pr < $pr_len} {incr pr} {\n\t\t\t\t\tset pr_node [add_or_get_dt_node -l \"fpga_PR$pr\" -n \"fpga-PR$pr\" -p $child_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${pr_node}\" \"compatible\" \"fpga-region\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${pr_node}\" \"#address-cells\" 2 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${pr_node}\" \"#size-cells\" 2 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${pr_node}\" \"ranges\" \"\" boolean\n\t\t\t\t}\n\t\t\t}\n }\n\t\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\tset zynq_periph [get_cells -hier -filter {IP_NAME == zynq_ultra_ps_e}]\n\t\t\tset avail_param [list_property [get_cells -hier $zynq_periph]]\n\t\t\tif {![llength $RpRm]} {\n\t\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__USE__FABRIC__RST\"] >= 0} {\n\t\t\t\t\tset val [get_property CONFIG.PSU__USE__FABRIC__RST [get_cells -hier $zynq_periph]]\n\t\t\t\t\tif {$val == 1} {\n\t\t\t\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_NUM_FABRIC_RESETS\"] >= 0} {\n\t\t\t\t\t\t\tset val [get_property CONFIG.C_NUM_FABRIC_RESETS [get_cells -hier $zynq_periph]]\n\t\t\t\t\t\t\tswitch $val {\n\t\t\t\t\t\t\t\t\"1\" {\n\t\t\t\t\t\t\t\t\tset resets \"zynqmp_reset 116\"\n\t\t\t\t\t\t\t\t} \"2\" {\n\t\t\t\t\t\t\t\t\tset resets \"zynqmp_reset 116>,<&zynqmp_reset 117\"\n\t\t\t\t\t\t\t\t} \"3\" {\n\t\t\t\t\t\t\t\t\tset resets \"zynqmp_reset 116>, <&zynqmp_reset 117>, <&zynqmp_reset 118\"\n\t\t\t\t\t\t\t\t} \"4\" {\n\t\t\t\t\t\t\t\t\tset resets \"zynqmp_reset 116>, <&zynqmp_reset 117>, <&zynqmp_reset 118>, <&zynqmp_reset 119\"\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tif {$val != 0} {\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${child_node}\" \"resets\" \"$resets\" reference\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tset overlay_custom_dts [get_property CONFIG.overlay_custom_dts [get_os]]\n\t\tif {[llength $overlay_custom_dts] && ![llength $RpRm]} {\n\t\t\tupdate_overlay_custom_dts_include $default_dts $overlay_custom_dts\n\t\t\tset dts_file pl-custom.dtsi\n\t\t\tset root_node [add_or_get_dt_node -n / -d ${dts_file}]\n\t\t\tupdate_overlay_custom_dts_include $dts_file $overlay_custom_dts\n\t\t}\n\t\tset partial_overlay_custom_dts [get_property CONFIG.partial_overlay_custom_dts [get_os]]\n\t\tif {[llength $partial_overlay_custom_dts] && [llength $RpRm]} {\n\t\t\tappend partial_overlay_dts $partial_overlay_custom_dts \"-\" $RpRm \".dts\"\n\t\t\tupdate_overlay_custom_dts_include $default_dts $partial_overlay_dts\n\t\t\tset dts_file pl-partial-custom-$RpRm.dtsi\n\t\t\tset root_node [add_or_get_dt_node -n / -d ${dts_file}]\n\t\t\tupdate_overlay_custom_dts_include $dts_file $partial_overlay_dts\n\t\t}\n\t} else {\n\t\tupdate_system_dts_include $default_dts\n\t}\n\n\treturn $default_dts\n}\n\nproc dt_node_def_checking {node_label node_name node_ua node_obj} {\n\t# check if the node_object has matching label, name and unit_address properties\n\tglobal def_string\n\tif {[string equal -nocase $node_label $def_string]} {\n\t\tset node_label \"\"\n\t}\n\tif {[string equal -nocase $node_ua $def_string]} {\n\t\tset node_ua \"\"\n\t}\n\tif {[string match -nocase \"data_source\" $node_label]} {\n\t\treturn 1\n\t}\n\t# ignore reference node as it does not have label and unit_addr\n\tif {![regexp \"^&.*\" \"$node_obj\" match]} {\n\t\tset old_label [get_property \"NODE_LABEL\" $node_obj]\n\t\tset old_name [get_property \"NODE_NAME\" $node_obj]\n\t\tset old_ua [get_property \"UNIT_ADDRESS\" $node_obj]\n\t\tset config_prop [list_property -regexp $node_obj \"CONFIG.*\"]\n\t\tif {[string_is_empty $old_ua]} {\n\t\t\treturn 1\n\t\t}\n\t\tif {![string equal -nocase -length [string length $node_label] $node_label $old_label] || \\\n\t\t\t![string equal -nocase $node_ua $old_ua] || \\\n\t\t\t![string equal -nocase -length [string length $node_name] $node_name $old_name]} {\n\t\t\tif {[string compare -nocase $config_prop \"\"]} {\n\t\t\t\tdtg_debug \"dt_node_def_checking($node_obj): label: ${node_label} - ${old_label}, name: ${node_name} - ${old_name}, unit addr: ${node_ua} - ${old_ua}\"\n\t\t\t\treturn 0\n\t\t\t}\n\t\t}\n\t}\n\treturn 1\n}\n\nproc add_or_get_dt_node args {\n\t# Creates the dt node or the parent node if required\n\t# return dt node\n\tproc_called_by\n\tglobal def_string\n\tforeach var {node_name node_label node_unit_addr parent_obj dts_file} {\n\t\tset ${var} ${def_string}\n\t}\n\tset auto_ref 1\n\tset auto_ref_parent 0\n\tset force_create 0\n\twhile {[string match -* [lindex $args 0]]} {\n\t\tswitch -glob -- [lindex $args 0] {\n\t\t\t-force {set force_create 1}\n\t\t\t-disable_auto_ref {set auto_ref 0}\n\t\t\t-auto_ref_parent {set auto_ref_parent 1}\n\t\t\t-n* {set node_name [Pop args 1]}\n\t\t\t-l* {set node_label [Pop args 1]}\n\t\t\t-u* {set node_unit_addr [Pop args 1]}\n\t\t\t-p* {set parent_obj [Pop args 1]}\n\t\t\t-d* {set dts_file [Pop args 1]}\n\t\t\t-- {Pop args ; break}\n\t\t\tdefault {\n\t\t\t\terror \"add_or_get_dt_node bad option - [lindex $args 0]\"\n\t\t\t}\n\t\t}\n\t\tPop args\n\t}\n\n\t# if no dts_file provided\n\tif {[string equal -nocase ${dts_file} ${def_string}]} {\n\t\tset dts_file [current_dt_tree]\n\t}\n\n\t# node_name sanity checking\n\tif {[string equal -nocase ${node_name} ${def_string}]} {\n\t\terror \"Node name must be provided...\"\n\t}\n\n\t# Generate unique label name to prevent issue caused by static dtsi\n\t# better way of handling this issue is required\n\tset label_list [get_all_dt_labels]\n\t# TODO: This only handle label duplication once. if multiple IP has\n\t# the same label, it will not work. Better handling required.\n\tif {[lsearch $label_list $node_label] >= 0} {\n\t\tset tmp_node [get_node_object ${node_label}]\n\t\t# rename if the node default properties differs\n\t\tif {[dt_node_def_checking $node_label $node_name $node_unit_addr $tmp_node] == 0} {\n\t\t\tdtg_warning \"label '$node_label' found in existing tree\"\n\t\t}\n\t}\n\n\tset search_pattern [gen_dt_node_search_pattern -n ${node_name} -l ${node_label} -u ${node_unit_addr}]\n\n\tdtg_debug \"\"\n\tdtg_debug \"node_name: ${node_name}\"\n\tdtg_debug \"node_label: ${node_label}\"\n\tdtg_debug \"node_unit_addr: ${node_unit_addr}\"\n\tdtg_debug \"search_pattern: ${search_pattern}\"\n\tdtg_debug \"parent_obj: ${parent_obj}\"\n\tdtg_debug \"dts_file: ${dts_file}\"\n\n\t# save the current working dt_tree first\n\tset cur_working_dts [current_dt_tree]\n\t# tree switch the target tree\n\tset_cur_working_dts ${dts_file}\n\tset parent_dts_file ${dts_file}\n\n\t# Set correct parent object\n\t# Check if the parent object in other dt_trees or not. If yes, update\n\t# parent node with reference node (&parent_obj).\n\t# Check if parent is / and see if it in the target dts file\n\t# if not /, then check if parent is created (FIXME: is right???)\n\tset tmp_dts_list [list_remove_element [get_dt_trees] ${dts_file}]\n\tset node_in_dts [check_node_in_dts ${parent_obj} ${tmp_dts_list}]\n\tif {${node_in_dts} == 1 && \\\n\t\t ![string equal ${parent_obj} \"/\" ]} {\n\t\tset parent_obj [get_node_object ${parent_obj} ${tmp_dts_list}]\n\t\tset parent_label [get_property \"NODE_LABEL\" $parent_obj]\n\t\tif {[string_is_empty $parent_label]} {\n\t\t\tset parent_label [get_property \"NODE_NAME\" $parent_obj]\n\t\t}\n\t\tif {[string_is_empty $parent_label]} {\n\t\t\terror \"no parent node name/label\"\n\t\t}\n\t\tif {[regexp \"^&.*\" \"$parent_label\" match]} {\n\t\t\tset ref_node \"${parent_label}\"\n\t\t} else {\n\t\t\tset ref_node \"&${parent_label}\"\n\t\t}\n\t\tset parent_ref_in_dts [check_node_in_dts \"${ref_node}\" ${dts_file}]\n\t\tif {${parent_ref_in_dts} != 1} {\n\t\t\tif {$auto_ref_parent} {\n\t\t\t\tset_cur_working_dts ${dts_file}\n\t\t\t\tset parent_obj [create_dt_node -n \"${ref_node}\"]\n\t\t\t}\n\t\t} else {\n\t\t\tset parent_obj [get_node_object ${ref_node} ${dts_file}]\n\t\t}\n\t}\n\n\t# if dt node in the target dts file\n\t# get the nodes in the current dts file\n\tset dts_nodes [get_all_tree_nodes $dts_file]\n\tforeach pattern ${search_pattern} {\n\t\tforeach node ${dts_nodes} {\n\t\t\tif {[regexp $pattern $node match]} {\n\t\t\t\tif {[dt_node_def_checking $node_label $node_name $node_unit_addr $node] == 0} {\n\t\t\t\t\tdtg_warning \"$pattern :: $node_label : $node_name @ $node_unit_addr, is differ to the node object $node\"\n\t\t\t\t}\n\t\t\t\tset node [update_dt_parent ${node} ${parent_obj} ${dts_file}]\n\t\t\t\tset_cur_working_dts ${cur_working_dts}\n\t\t\t\treturn $node\n\t\t\t}\n\t\t}\n\t}\n\t# clean up required\n\t# special search pattern for name only node\n\tset_cur_working_dts ${dts_file}\n\tforeach pattern \"^${node_name}$\" {\n\t\tforeach node ${dts_nodes} {\n\t\t\t# As there was cpu timer node already in dtsi file skipping to add ttc timer\n\t\t\t# to pcw.dtsi even if ip available. This check will skip that.\n\t\t\tif {[regexp $pattern $node match] && ![string match -nocase ${node_name} \"timer\"]} {\n\t\t\t\tset_cur_working_dts ${dts_file}\n\t\t\t\tset node [update_dt_parent ${node} ${parent_obj} ${dts_file}]\n\t\t\t\tset_cur_working_dts ${cur_working_dts}\n\t\t\t\treturn $node\n\t\t\t}\n\t\t}\n\t}\n\t# if dt node in other target dts files\n\t# create a reference node if required\n\tset found_node 0\n\tset tmp_dts_list [list_remove_element [get_dt_trees] ${dts_file}]\n\tforeach tmp_dts_file ${tmp_dts_list} {\n\t\tset dts_nodes [get_all_tree_nodes $tmp_dts_file]\n\t\t# TODO: better detection here\n\t\tforeach pattern ${search_pattern} {\n\t\t\tforeach node ${dts_nodes} {\n\t\t\t\tif {[regexp $pattern $node match]} {\n\t\t\t\t\tif {[string match -nocase $node \"port@0\"] || [string match -nocase $node \"port@1\"]\n\t\t\t\t\t\t|| [string match -nocase $node \"port@2\"]} {\n\t\t\t\t\t\tcontinue\n\t\t\t\t\t}\n\t\t\t\t\t# create reference node\n\t\t\t\t\tset found_node 1\n\t\t\t\t\tset found_node_obj [get_node_object ${node} $tmp_dts_file]\n\t\t\t\t\tbreak\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tif {$found_node == 1 && $force_create == 0} {\n\t\tif {$auto_ref == 0} {\n\t\t\t# return the object found on other dts files\n\t\t\tset_cur_working_dts ${cur_working_dts}\n\t\t\treturn $found_node_obj\n\t\t}\n\t\tdtg_debug \"INFO: Found node and create it as reference node &${node_label}\"\n\t\tif {[string equal -nocase ${node_label} ${def_string}]} {\n\t\t\terror \"Unable to create reference node as reference label is not provided\"\n\t\t}\n\n\t\tset node [create_dt_node -n \"&${node_label}\"]\n\t\tset_cur_working_dts ${cur_working_dts}\n\t\treturn $node\n\t}\n\n\t# Others - create the dt node\n\tset cmd \"\"\n\tif {![string equal -nocase ${node_name} ${def_string}]} {\n\t\tset cmd \"${cmd} -name ${node_name}\"\n\t}\n\tif {![string equal -nocase ${node_label} ${def_string}]} {\n\t\tif {[regexp \"pl-partial-.*.dtsi\" $parent_dts_file match] && \\\n\t\t\t[get_property CONFIG.no_labels [get_os]]} {\n\t\t\t# CONFIG.no_lables set to true and RpRm dtsi.\n\t\t\t# skip adding labels for Partial dt files.\n\t\t\tset cmd \"${cmd}\"\n\t\t} else {\n\t\t\tset cmd \"${cmd} -label ${node_label}\"\n\t\t}\n\t}\n\tif {![string equal -nocase ${node_unit_addr} ${def_string}]} {\n\t\tset cmd \"${cmd} -unit_addr ${node_unit_addr}\"\n\t}\n\tif {![string equal -nocase ${parent_obj} ${def_string}] && \\\n\t\t![string_is_empty ${parent_obj}]} {\n\t\t# temp solution for getting the right node object\n\t\t#set cmd \"${cmd} -objects \\[get_node_object ${parent_obj} $dts_file\\]\"\n\t\t#report_property [get_node_object ${parent_obj} $dts_file]\n\t\tset cmd \"${cmd} -objects \\[get_node_object ${parent_obj} $parent_dts_file\\]\"\n\t}\n\n\tdtg_debug \"create node command: create_dt_node ${cmd}\"\n\t# FIXME: create_dt_node fail detection here\n\tset node [eval \"create_dt_node ${cmd}\"]\n\tset_cur_working_dts ${cur_working_dts}\n\treturn $node\n}\n\nproc is_pl_ip {ip_inst} {\n\t# check if the IP is a soft IP (not PS7)\n\t# return 1 if it is soft ip\n\t# return 0 if not\n\tset ip_obj [get_cells -hier $ip_inst]\n\tif {[llength [get_cells -hier $ip_inst]] < 1} {\n\t\treturn 0\n\t}\n\tset ip_name [get_property IP_NAME $ip_obj]\n\tset nochk_list \"ai_engine noc_mc_ddr4\"\n\tif {[lsearch $nochk_list $ip_name] >= 0} {\n\t\treturn 1\n\t}\n\tif {[catch {set proplist [list_property [hsi::get_cells -hier $ip_inst]]} msg]} {\n\t} else {\n\t\tif {[lsearch -nocase $proplist \"IS_PL\"] >= 0} {\n\t\t\tset prop [get_property IS_PL [hsi::get_cells -hier $ip_inst]]\n\t\t\tif {$prop} {\n\t\t\t\treturn 1\n\t\t\t} else {\n\t\t\t\treturn 0\n\t\t\t}\n\t\t}\n\t}\n set ip_name [get_property IP_NAME $ip_obj]\n if {![regexp \"ps._*\" \"$ip_name\" match]} {\n return 1\n }\n return 0\n\n}\n\nproc is_ps_ip {ip_inst} {\n\t# check if the IP is a soft IP (not PS7)\n\t# return 1 if it is soft ip\n\t# return 0 if not\n\tset ip_obj [hsi::get_cells -hier $ip_inst]\n\tif {[catch {set proplist [list_property [hsi::get_cells -hier $ip_inst]]} msg]} {\n\t} else {\n\tif {[lsearch -nocase $proplist \"IS_PL\"] >= 0} {\n\t\tset prop [get_property IS_PL [hsi::get_cells -hier $ip_inst]]\n\t\tif {$prop} {\n\t\t\treturn 0\n\t\t}\n\t}\n\t}\n\tif {[llength [hsi::get_cells -hier $ip_inst]] < 1} {\n\t\treturn 0\n\t}\n\n\tset ip_name [get_property IP_NAME $ip_obj]\n\tif {[string match -nocase $ip_name \"axi_noc\"] || [string match -nocase $ip_name \"axi_noc2\"]} {\n\t\treturn 0\n\t}\n\tif {[regexp \"ps._*\" \"$ip_name\" match]} {\n\t\treturn 1\n\t}\n\treturn 0\n}\n\nproc get_node_name {drv_handle} {\n\t# FIXME: handle node that is not an ip\n\t# what about it is a bus node\n\tset ip [get_cells -hier $drv_handle]\n\t# node that is not a ip\n\tif {[string_is_empty $ip]} {\n\t\terror \"$drv_handle is not a valid IP\"\n\t}\n\tset unit_addr [get_baseaddr ${ip}]\n\tset dev_type [get_property CONFIG.dev_type $drv_handle]\n\tif {[string_is_empty $dev_type] == 1} {\n\t\tset dev_type $drv_handle\n\t}\n\tset dt_node [add_or_get_dt_node -n ${dev_type} -l ${drv_handle} -u ${unit_addr}]\n\treturn $dt_node\n}\n\nproc get_driver_conf_list {drv_handle} {\n\t# Assuming the driver property starts with CONFIG.\n\t# Returns all the property name that should be add to the node\n\tset dts_conf_list \"\"\n\t# handle no CONFIG parameter\n\tif {[catch {set rt [report_property -return_string -regexp $drv_handle \"CONFIG\\\\..*\"]} msg]} {\n\t\treturn \"\"\n\t}\n\tforeach line [split $rt \"\\n\"] {\n\t\tregsub -all {\\s+} $line { } line\n\t\tif {[regexp \"CONFIG\\\\..*\\\\.dts(i|)\" $line matched]} {\n\t\t\tcontinue\n\t\t}\n\t\tif {[regexp \"CONFIG\\\\..*\" $line matched]} {\n\t\t\tlappend dts_conf_list [lindex [split $line \" \"] 0]\n\t\t}\n\t}\n\t# Remove config based properties\n\t# currently it is not possible to different by type: Pending on HSI implementation\n\t# this is currently hard coded to remove CONFIG.def_dts CONFIG.dev_type CONFIG.dtg.alias CONFIG.dtg.ip_params\n\tset dts_conf_list [list_remove_element $dts_conf_list \"CONFIG.def_dts CONFIG.dev_type CONFIG.dtg.alias CONFIG.dtg.ip_params\"]\n\treturn $dts_conf_list\n}\n\nproc add_driver_prop {drv_handle dt_node prop} {\n\t# driver property to DT node\n\tset value [get_property ${prop} $drv_handle]\n\tif {[string_is_empty ${prop}] != 0} {\n\t\treturn -1\n\t}\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tif {[is_pl_ip $drv_handle] && $remove_pl} {\n\t\treturn\n\t}\n\tregsub -all {CONFIG.} $prop {} prop\n\tset conf_prop [lindex [get_comp_params ${prop} $drv_handle] 0 ]\n\tif {[string_is_empty ${conf_prop}] == 0} {\n\t\tset type [lindex [get_property CONFIG.TYPE $conf_prop] 0]\n\t} else {\n\t\terror \"Unable to add the $prop property for $drv_handle due to missing valid type\"\n\t}\n\tset ipname [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tif {[string match -nocase $ipname \"axi_mcdma\"] && [string match -nocase $conf_prop \"xlnx,sg-include-stscntrl-strm\"]&& [string match -nocase $type \"boolean\"]} {\n\t\tset type \"hexint\"\n\t}\n\tdtg_debug \"${dt_node} - ${prop} - ${value} - ${type}\"\n\n\t# only boolean allows empty string\n\tif {[string_is_empty ${value}] == 1 && ![regexp {boolean*} ${type} matched]} {\n\t\tdtg_warning \"Only boolean type can have empty value. Fail to add driver($drv_handle) property($prop) type($type) value($value)\"\n\t\tdtg_warning \"Please add the property manually\"\n\t\treturn 1\n\t}\n\t# TODO: sanity check is missing\n\thsi::utils::add_new_dts_param \"${dt_node}\" \"${prop}\" \"${value}\" \"${type}\"\n}\n\nproc create_dt_tree_from_dts_file {} {\n\tglobal def_string dtsi_fname\n\tset kernel_dtsi \"\"\n\tset mainline_dtsi \"\"\n\tset kernel_ver [get_property CONFIG.kernel_version [get_os]]\n\tset mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n\tset valid_mainline_kernel_list \"v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4\"\n if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } {\n\t\tforeach i [get_sw_cores device_tree] {\n\t\t\tset mainline_dtsi [file normalize \"[get_property \"REPOSITORY\" $i]/data/kernel_dtsi/${mainline_ker}/${dtsi_fname}\"]\n\t\t\tif {[file exists $mainline_dtsi]} {\n\t\t\t\tforeach file [glob [file normalize [file dirname ${mainline_dtsi}]/*]] {\n\t\t\t\t\t# NOTE: ./ works only if we did not change our directory\n\t\t\t\t\tfile copy -force $file ./\n\t\t\t\t}\n\t\t\t\tbreak\n\t\t\t}\n\t\t}\n\t} else {\n\t\tforeach i [get_sw_cores device_tree] {\n\t\t\tset kernel_dtsi [file normalize \"[get_property \"REPOSITORY\" $i]/data/kernel_dtsi/${kernel_ver}/${dtsi_fname}\"]\n\t\t\tif {[file exists $kernel_dtsi]} {\n\t\t\t\tforeach file [glob [file normalize [file dirname ${kernel_dtsi}]/*]] {\n\t\t\t\t\t# NOTE: ./ works only if we did not change our directory\n\t\t\t\t\tfile copy -force $file ./\n\t\t\t\t}\n\t\t\t\tbreak\n\t\t\t}\n\t\t}\n\n\t\tif {![file exists $kernel_dtsi] || [string_is_empty $kernel_dtsi]} {\n\t\t\terror \"Unable to find the dts file $kernel_dtsi\"\n\t\t}\n\t}\n\n\tglobal zynq_soc_dt_tree\n\tset default_dts [create_dt_tree -dts_file $zynq_soc_dt_tree]\n set valid_mainline_kernel_list \"v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4\"\n if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } {\n\t\tset fp [open $mainline_dtsi r]\n\t\tset file_data [read $fp]\n\t\tset data [split $file_data \"\\n\"]\n\t} else {\n\t\tset fp [open $kernel_dtsi r]\n\t\tset file_data [read $fp]\n\t\tset data [split $file_data \"\\n\"]\n\t}\n\n\tset node_level -1\n\tforeach line $data {\n\t\tset node_start_regexp \"\\{(\\\\s+|\\\\s|)$\"\n\t\tset node_end_regexp \"\\}(\\\\s+|\\\\s|);(\\\\s+|\\\\s|)$\"\n\t\tif {[regexp $node_start_regexp $line matched]} {\n\t\t\tregsub -all \"\\{| |\\t\" $line {} line\n\t\t\tincr node_level\n\t\t\tset cur_node [line_to_node $line $node_level $default_dts]\n\t\t} elseif {[regexp $node_end_regexp $line matched]} {\n\t\t\tset node_level [expr \"$node_level - 1\"]\n\t\t}\n\t\t# TODO (MAYBE): convert every property into dt node\n\t\tset status_regexp \"status(|\\\\s+)=\"\n\t\tset value \"\"\n\t\tif {[regexp $status_regexp $line matched]} {\n\t\t\tregsub -all \"\\{| |\\t|;|\\\"\" $line {} line\n\t\t\tset line_data [split $line \"=\"]\n\t\t\tset value [lindex $line_data 1]\n\t\t\thsi::utils::add_new_dts_param \"${cur_node}\" \"status\" $value string\n\t\t}\n\t\tset status_regexp \"compatible(|\\\\s+)=\"\n\t\tset value \"\"\n\t\tif {[regexp $status_regexp $line matched]} {\n\t\t\tregsub -all \"\\{| |\\t|;|\\\"\" $line {} line\n\t\t\tset line_data [split $line \"=\"]\n\t\t\tset value [lindex $line_data 1]\n\t\t\thsi::utils::add_new_dts_param \"${cur_node}\" \"compatible\" $value stringlist\n\t\t}\n\t}\n}\n\nproc line_to_node {line node_level default_dts} {\n\t# TODO: make dt_node_dict as global\n\tglobal dt_node_dict\n\tglobal def_string\n\tregsub -all \"\\{| |\\t\" $line {} line\n\tset parent_node $def_string\n\tset node_label $def_string\n\tset node_name $def_string\n\tset node_unit_addr $def_string\n\n\tset node_data [split $line \":\"]\n\tset node_data_size [llength $node_data]\n\tif {$node_data_size == 2} {\n\t\tset node_label [lindex $node_data 0]\n\t\tset tmp_data [split [lindex $node_data 1] \"@\"]\n\t\tset node_name [lindex $tmp_data 0]\n\t\tif {[llength $tmp_data] >= 2} {\n\t\t\tset node_unit_addr [lindex $tmp_data 1]\n\t\t}\n\t} elseif {$node_data_size == 1} {\n\t\tset node_name [lindex $node_data 0]\n\t} else {\n\t\terror \"invalid node found - $line\"\n\t}\n\n\tif {$node_level > 0} {\n\t\tset parent_node [dict get $dt_node_dict [expr $node_level - 1] parent_node]\n\t}\n\n\tset cur_node [add_or_get_dt_node -n ${node_name} -l ${node_label} -u ${node_unit_addr} -d ${default_dts} -p ${parent_node}]\n\tdict set dt_node_dict $node_level parent_node $cur_node\n\treturn $cur_node\n}\n\nproc gen_ps7_mapping {} {\n\t# TODO: check if it is target cpu is cortex a9\n\n\t# TODO: remove def_ps7_mapping\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\n\tset def_ps_mapping [dict create]\n\tif {[string match -nocase $proctype \"psv_cortexa72\"]} {\n\t\tdict set def_ps_mapping f9000000 label gic\n\t\tdict set def_ps_mapping fd4b0000 label gpu\n\t\tdict set def_ps_mapping ffa80000 label adma0\n\t\tdict set def_ps_mapping ffa90000 label adma1\n\t\tdict set def_ps_mapping ffaa0000 label adma2\n\t\tdict set def_ps_mapping ffab0000 label adma3\n\t\tdict set def_ps_mapping ffac0000 label adma4\n\t\tdict set def_ps_mapping ffad0000 label adma5\n\t\tdict set def_ps_mapping ffae0000 label adma6\n\t\tdict set def_ps_mapping ffaf0000 label adma7\n\t\tdict set def_ps_mapping ff100000 label nand0\n\t\tdict set def_ps_mapping ff0c0000 label gem0\n\t\tdict set def_ps_mapping ff0d0000 label gem1\n\t\tdict set def_ps_mapping ff0b0000 label gpio\n\t\tdict set def_ps_mapping ff020000 label i2c0\n\t\tdict set def_ps_mapping ff030000 label i2c1\n\t\tdict set def_ps_mapping f06f0000 label qspi\n\t\tdict set def_ps_mapping f1100000 label rtc\n\t\tdict set def_ps_mapping fd0c0000 label sata\n\t\tdict set def_ps_mapping f0760000 label sdhci0\n\t\tdict set def_ps_mapping f0770000 label sdhci1\n\t\tdict set def_ps_mapping fd800000 label smmu\n\t\tdict set def_ps_mapping ff040000 label spi0\n\t\tdict set def_ps_mapping ff050000 label spi1\n\t\tdict set def_ps_mapping ff0e0000 label ttc0\n\t\tdict set def_ps_mapping ff0f0000 label ttc1\n\t\tdict set def_ps_mapping ff100000 label ttc2\n\t\tdict set def_ps_mapping ff110000 label ttc3\n\t\tdict set def_ps_mapping ff000000 label uart0\n\t\tdict set def_ps_mapping ff010000 label uart1\n\t\tdict set def_ps_mapping fe200000 label usb0\n\t\tdict set def_ps_mapping ff120000 label watchdog0\n\t\tdict set def_ps_mapping fe5f0000 label dpdma\n\t\tdict set def_ps_mapping fd0e0000 label pcie\n\t\tdict set def_ps_mapping fca10000 label cpm_pciea\n\t\tdict set def_ps_mapping fcdd0000 label cpm5_pcie\n\t\tdict set def_ps_mapping ff060000 label can0\n\t\tdict set def_ps_mapping ff070000 label can1\n\t} elseif {[string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\tdict set def_ps_mapping e2000000 label gic\n\t\tdict set def_ps_mapping ebd00000 label adma0\n\t\tdict set def_ps_mapping ebd10000 label adma1\n\t\tdict set def_ps_mapping ebd20000 label adma2\n\t\tdict set def_ps_mapping ebd30000 label adma3\n\t\tdict set def_ps_mapping ebd40000 label adma4\n\t\tdict set def_ps_mapping ebd50000 label adma5\n\t\tdict set def_ps_mapping ebd60000 label adma6\n\t\tdict set def_ps_mapping ebd70000 label adma7\n\t\tdict set def_ps_mapping f1980000 label can0\n\t\tdict set def_ps_mapping f1990000 label can1\n\t\tdict set def_ps_mapping f19e0000 label gem0\n\t\tdict set def_ps_mapping f19f0000 label gem1\n\t\tdict set def_ps_mapping f19d0000 label gpio0\n\t\tdict set def_ps_mapping f1020000 label gpio1\n\t\tdict set def_ps_mapping f1940000 label i2c0\n\t\tdict set def_ps_mapping f1950000 label i2c1\n\t\tdict set def_ps_mapping f1948000 label i3c0\n\t\tdict set def_ps_mapping f1958000 label i3c1\n\t\tdict set def_ps_mapping f1010000 label ospi\n\t\tdict set def_ps_mapping f1030000 label qspi\n\t\tdict set def_ps_mapping f12a0000 label rtc\n\t\tdict set def_ps_mapping f1040000 label sdhci0\n\t\tdict set def_ps_mapping f1050000 label sdhci1\n\t\tdict set def_ps_mapping f1920000 label serial0\n\t\tdict set def_ps_mapping f1930000 label serial1\n\t\tdict set def_ps_mapping ec000000 label smmu\n\t\tdict set def_ps_mapping f1960000 label spi0\n\t\tdict set def_ps_mapping f1970000 label spi1\n\t\tdict set def_ps_mapping f1dc0000 label ttc0\n\t\tdict set def_ps_mapping f1dd0000 label ttc1\n\t\tdict set def_ps_mapping f1de0000 label ttc2\n\t\tdict set def_ps_mapping f1df0000 label ttc3\n\t\tdict set def_ps_mapping f1e00000 label usb0\n\t\tdict set def_ps_mapping f1e10000 label usb1\n\t\tdict set def_ps_mapping ecc10000 label wwdt0\n\t\tdict set def_ps_mapping ecd10000 label wwdt1\n\t\tdict set def_ps_mapping ece10000 label wwdt2\n\t\tdict set def_ps_mapping ecf10000 label wwdt3\n\t} elseif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\tdict set def_ps_mapping f9010000 label gic\n\t\tdict set def_ps_mapping ff060000 label can0\n\t\tdict set def_ps_mapping ff070000 label can1\n\t\tdict set def_ps_mapping fd500000 label gdma0\n\t\tdict set def_ps_mapping fd510000 label gdma1\n\t\tdict set def_ps_mapping fd520000 label gdma2\n\t\tdict set def_ps_mapping fd530000 label gdma3\n\t\tdict set def_ps_mapping fd540000 label gdma4\n\t\tdict set def_ps_mapping fd550000 label gdma5\n\t\tdict set def_ps_mapping fd560000 label gdma6\n\t\tdict set def_ps_mapping fd570000 label gdma7\n\t\tdict set def_ps_mapping fd4b0000 label gpu\n\t\tdict set def_ps_mapping ffa80000 label adma0\n\t\tdict set def_ps_mapping ffa90000 label adma0\n\t\tdict set def_ps_mapping ffaa0000 label adma2\n\t\tdict set def_ps_mapping ffab0000 label adma3\n\t\tdict set def_ps_mapping ffac0000 label adma4\n\t\tdict set def_ps_mapping ffad0000 label adma5\n\t\tdict set def_ps_mapping ffae0000 label adma6\n\t\tdict set def_ps_mapping ffaf0000 label adma7\n\t\tdict set def_ps_mapping ff100000 label nand0\n\t\tdict set def_ps_mapping ff0b0000 label gem0\n\t\tdict set def_ps_mapping ff0c0000 label gem1\n\t\tdict set def_ps_mapping ff0d0000 label gem2\n\t\tdict set def_ps_mapping ff0e0000 label gem3\n\t\tdict set def_ps_mapping ff0a0000 label gpio\n\t\tdict set def_ps_mapping ff020000 label i2c0\n\t\tdict set def_ps_mapping ff030000 label i2c1\n\t\tdict set def_ps_mapping ff0f0000 label qspi\n\t\tdict set def_ps_mapping ffa60000 label rtc\n\t\tdict set def_ps_mapping fd0c0000 label sata\n\t\tdict set def_ps_mapping ff160000 label sdhci0\n\t\tdict set def_ps_mapping ff170000 label sdhci1\n\t\tdict set def_ps_mapping fd800000 label smmu\n\t\tdict set def_ps_mapping ff040000 label spi0\n\t\tdict set def_ps_mapping ff050000 label spi1\n\t\tdict set def_ps_mapping ff110000 label ttc0\n\t\tdict set def_ps_mapping ff120000 label ttc1\n\t\tdict set def_ps_mapping ff130000 label ttc2\n\t\tdict set def_ps_mapping ff140000 label ttc3\n\t\tdict set def_ps_mapping ff000000 label uart0\n\t\tdict set def_ps_mapping ff010000 label uart1\n\t\tdict set def_ps_mapping fe200000 label usb0\n\t\tdict set def_ps_mapping fe300000 label usb1\n\t\tdict set def_ps_mapping fd4d0000 label watchdog0\n\t\tdict set def_ps_mapping 43c00000 label dp\n\t\tdict set def_ps_mapping 43c0a000 label dpsub\n\t\tdict set def_ps_mapping fd4c0000 label dpdma\n\t\tdict set def_ps_mapping fd0e0000 label pcie\n\t} else {\n\t\tdict set def_ps_mapping f8891000 label pmu\n\t\tdict set def_ps_mapping f8007100 label adc\n\t\tdict set def_ps_mapping e0008000 label can0\n\t\tdict set def_ps_mapping e0009000 label can1\n\t\tdict set def_ps_mapping e000a000 label gpio0\n\t\tdict set def_ps_mapping e0004000 label i2c0\n\t\tdict set def_ps_mapping e0005000 label i2c1\n\t\tdict set def_ps_mapping f8f01000 label intc\n\t\tdict set def_ps_mapping f8f00100 label intc\n\t\tdict set def_ps_mapping f8f02000 label L2\n\t\tdict set def_ps_mapping f8006000 label memory-controller\n\t\tdict set def_ps_mapping f800c000 label ocmc\n\t\tdict set def_ps_mapping e0000000 label uart0\n\t\tdict set def_ps_mapping e0001000 label uart1\n\t\tdict set def_ps_mapping e0006000 label spi0\n\t\tdict set def_ps_mapping e0007000 label spi1\n\t\tdict set def_ps_mapping e000d000 label qspi\n\t\tdict set def_ps_mapping e000e000 label smcc\n\t\tdict set def_ps_mapping e1000000 label nand0\n\t\tdict set def_ps_mapping e2000000 label nor\n\t\tdict set def_ps_mapping e000b000 label gem0\n\t\tdict set def_ps_mapping e000c000 label gem1\n\t\tdict set def_ps_mapping e0100000 label sdhci0\n\t\tdict set def_ps_mapping e0101000 label sdhci1\n\t\tdict set def_ps_mapping f8000000 label slcr\n\t\tdict set def_ps_mapping f8003000 label dmac_s\n\t\tdict set def_ps_mapping f8007000 label devcfg\n\t\tdict set def_ps_mapping f8f00200 label global_timer\n\t\tdict set def_ps_mapping f8001000 label ttc0\n\t\tdict set def_ps_mapping f8002000 label ttc1\n\t\tdict set def_ps_mapping f8f00600 label scutimer\n\t\tdict set def_ps_mapping f8005000 label watchdog0\n\t\tdict set def_ps_mapping f8f00620 label scuwatchdog\n\t\tdict set def_ps_mapping e0002000 label usb0\n\t\tdict set def_ps_mapping e0003000 label usb1\n\t}\n\n\tset ps_mapping [dict create]\n\tglobal zynq_soc_dt_tree\n\tif {[lsearch [get_dt_trees] $zynq_soc_dt_tree] >= 0} {\n\t\t# get nodes under bus\n\t\tforeach node [get_all_tree_nodes $zynq_soc_dt_tree] {\n\t\t\t# only care about the device with parent ambe\n\t\t\tset parent [get_property PARENT $node]\n\t\t\tset ignore_parent_list {(/|cpu)}\n\t\t\tif {[regexp $ignore_parent_list $parent matched]} {\n\t\t\t\tcontinue\n\t\t\t}\n\t\t\tset unit_addr [get_property UNIT_ADDRESS $node]\n\t\t\tif {[string length $unit_addr] <= 1} {\n\t\t\t\tset unit_addr \"\"\n\t\t\t}\n\t\t\tset node_name [get_property NODE_NAME $node]\n\t\t\tset node_label [get_property NODE_LABEL $node]\n\t\t\tif {[catch {set status_prop [get_property CONFIG.status $node]} msg]} {\n\t\t\t\tset status_prop \"enable\"\n\t\t\t}\n\t\t\tif {[string_is_empty $node_label] || \\\n\t\t\t\t[string_is_empty $unit_addr]} {\n\t\t\t\tcontinue\n\t\t\t}\n\t\t\tdict set ps_mapping $unit_addr label $node_label\n\t\t\tdict set ps_mapping $unit_addr name $node_name\n\t\t\tdict set ps_mapping $unit_addr status $status_prop\n\t\t}\n\t}\n\tif {[string_is_empty $ps_mapping]} {\n\t\treturn $def_ps_mapping\n\t} else {\n\t\treturn $ps_mapping\n\t}\n}\n\nproc ps_node_mapping {ip_name prop} {\n\tif {[is_ps_ip [get_drivers $ip_name]]} {\n\t\tset unit_addr [get_ps_node_unit_addr $ip_name]\n\t\tif {$unit_addr == -1} {return $ip_name}\n\t\tset ps7_mapping [gen_ps7_mapping]\n\n\t\tif {[catch {set tmp [dict get $ps7_mapping $unit_addr $prop]} msg]} {\n\t\t\tcontinue\n\t\t}\n\t\treturn $tmp\n\t}\n\treturn $ip_name\n}\n\nproc get_ps_node_unit_addr {ip_name {prop \"label\"}} {\n\tset ip [get_cells -hier $ip_name]\n\tset ip_mem_handle [hsi::utils::get_ip_mem_ranges [get_cells -hier $ip]]\n\n\t# loop through the base addresses: workaround for intc\n\tforeach handler ${ip_mem_handle} {\n\t\tset unit_addr [string tolower [get_property BASE_VALUE $handler]]\n\t\tregsub -all {^0x} $unit_addr {} unit_addr\n\t\tset ps7_mapping [gen_ps7_mapping]\n\t\tif {[is_ps_ip [get_drivers $ip_name]]} {\n\t\t\tif {[catch {set tmp [dict get $ps7_mapping $unit_addr $prop]} msg]} {\n\t\t\t\tcontinue\n\t\t\t}\n\t\t\treturn $unit_addr\n\t\t}\n\t}\n\treturn -1\n}\n\nproc remove_empty_reference_node {} {\n\t# check for ps_ips\n\tglobal zynq_soc_dt_tree\n\tset dts_files [list_remove_element [get_dt_trees] $zynq_soc_dt_tree]\n\tforeach dts_file $dts_files {\n\t\tset_cur_working_dts $dts_file\n\t\tforeach node [get_all_tree_nodes $dts_file] {\n\t\t\tif {[regexp \"^&.*\" $node matched]} {\n\t\t\t\t# check if it has child node\n\t\t\t\tset child_nodes [get_dt_nodes -of_objects $node]\n\t\t\t\tif {![string_is_empty $child_nodes]} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\tset prop_list [list_property -regexp $node \"CONFIG.*\"]\n\t\t\t\tif {[string_is_empty $prop_list]} {\n\t\t\t\t\tdtg_debug \"removing $node\"\n\t\t\t\t\tdelete_objs $node\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc add_dts_header {dts_file str_add} {\n\tset cur_dts [current_dt_tree]\n\tset dts_obj [set_cur_working_dts ${dts_file}]\n\tset header [get_property HEADER $dts_obj]\n\tappend header \"\\n\" $str_add\n\tset_property HEADER $header $dts_obj\n\tset_cur_working_dts $cur_dts\n}\n\nproc gen_fixed_factor_clk_node {misc_clk_node clk_freq} {\n\tset zynq_periph [get_cells -hier -filter {IP_NAME == zynq_ultra_ps_e}]\n\tset pl0_clk_val [get_property CONFIG.C_PL_CLK0_BUF [get_cells -hier $zynq_periph]]\n\tset pl1_clk_val [get_property CONFIG.C_PL_CLK1_BUF [get_cells -hier $zynq_periph]]\n\tset pl2_clk_val [get_property CONFIG.C_PL_CLK2_BUF [get_cells -hier $zynq_periph]]\n\tset pl3_clk_val [get_property CONFIG.C_PL_CLK3_BUF [get_cells -hier $zynq_periph]]\n\tset parent_freq \"\"\n\tset div \"\"\n\tset mult \"\"\n\tif {[string match -nocase $pl0_clk_val \"true\"]} {\n\t\tset parent_freq [get_property CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]]\n\t\tset parent_freq [expr $parent_freq * 1000000]\n\t\tset clock_name \"zynqmp_clk 71\"\n\t} elseif {[string match -nocase $pl1_clk_val \"true\"]} {\n\t\tset parent_freq [get_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]]\n\t\tset parent_freq [expr $parent_freq * 1000000]\n\t\tset clock_name \"zynqmp_clk 72\"\n\t} elseif {[string match -nocase $pl2_clk_val \"true\"]} {\n\t\tset parent_freq [get_property CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]]\n\t\tset parent_freq [expr $parent_freq * 1000000]\n\t\tset clock_name \"zynqmp_clk 73\"\n\t} elseif {[string match -nocase $pl3_clk_val \"true\"]} {\n\t\tset parent_freq [get_property CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]]\n\t\tset parent_freq [expr $parent_freq * 1000000]\n\t\tset clock_name \"zynqmp_clk 74\"\n\t}\n\n\tif {![string equal $parent_freq \"\"]} {\n\t\tif {$parent_freq >= $clk_freq} {\n\t\t\tset div [expr round($parent_freq / $clk_freq)]\n\t\t\tset mult 1\n\t\t} elseif {$parent_freq < $clk_freq} {\n\t\t\tset mult [expr round($clk_freq / $parent_freq)]\n\t\t\tset div 1\n\t\t}\n\t}\n\tif {![string equal $div \"\"] && ![string equal $mult \"\"]} {\n\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"compatible\" \"fixed-factor-clock\" stringlist\n\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"#clock-cells\" 0 int\n\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clocks\" $clock_name reference\n\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-div\" $div int\n\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-mult\" $mult int\n\t} else {\n\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"#clock-cells\" 0 int\n\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-frequency\" $clk_freq int\n\t}\n}\n\nproc zynq_gen_pl_clk_binding {drv_handle} {\n\t# add dts binding for required nodes\n\t# clock-names = \"ref_clk\";\n\t# clocks = <&clkc 0>;\n\tglobal bus_clk_list\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t# Assuming these device supports the clocks\n\tset mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n\tset valid_mainline_kernel_list \"v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4\"\n\tif {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } {\n\t\tset valid_ip_list \"axi_timer axi_uartlite axi_uart16550 axi_gpio axi_traffic_gen axi_ethernet axi_ethernet_buffer can canfd axi_iic xadc_wiz vcu\"\n\t} else {\n\t\tset valid_ip_list \"xadc_wiz\"\n\t}\n\tset valid_proc_list \"ps7_cortexa9 psu_cortexa53\"\n\tif {[lsearch -nocase $valid_proc_list $proctype] >= 0} {\n\t\tset iptype [get_property IP_NAME [get_cells -hier $drv_handle]]\n\t\tif {[lsearch $valid_ip_list $iptype] >= 0} {\n\t\t\t# FIXME: this is hardcoded - maybe dynamic detection\n\t\t\t# Keep the below logic, until we have clock frame work for ZynqMP\n\t\t\tif {[string match -nocase $iptype \"can\"] || [string match -nocase $iptype \"canfd\"]} {\n\t\t\t\tset clks \"can_clk s_axi_aclk\"\n\t\t\t} elseif {[string match -nocase $iptype \"vcu\"]} {\n\t\t\t\tset clks \"pll_ref_clk s_axi_lite_aclk\"\n\t\t\t} else {\n\t\t\t\tset clks \"s_axi_aclk\"\n\t\t\t}\n\t\t\tforeach pin $clks {\n\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] } {\n\t\t\t\tset dts_file [current_dt_tree]\n\t\t\t\tset bus_node [add_or_get_bus_node $drv_handle $dts_file]\n\t\t\t\tset clk_freq [get_clock_frequency [get_cells -hier $drv_handle] $pin]\n\t\t\t\tif {![string equal $clk_freq \"\"]} {\n\t\t\t\t\tif {[lsearch $bus_clk_list $clk_freq] < 0} {\n\t\t\t\t\t\tset bus_clk_list [lappend bus_clk_list $clk_freq]\n\t\t\t\t\t}\n\t\t\t\t\tset bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]\n\t\t\t\t\tset misc_clk_node [add_or_get_dt_node -n \"misc_clk_${bus_clk_cnt}\" -l \"misc_clk_${bus_clk_cnt}\" \\\n\t\t\t\t\t\t-d ${dts_file} -p ${bus_node}]\n\t\t\t\t\t# create the node and assuming reg 0 is taken by cpu\n\t\t\t\t\tset clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]\n\t\t\t\t\tgen_fixed_factor_clk_node ${misc_clk_node} ${clk_freq}\n\t\t\t\t\tif {[string match -nocase $iptype \"can\"] || [string match -nocase $iptype \"vcu\"] || [string match -nocase $iptype \"canfd\"]} {\n\t\t\t\t\t\tset clocks [lindex $clk_refs 0]\n\t\t\t\t\t\tappend clocks \">, <&[lindex $clk_refs 1]\"\n\t\t\t\t\t\tset_drv_prop $drv_handle \"clocks\" \"$clocks\" reference\n\t\t\t\t\t\tset_drv_prop_if_empty $drv_handle \"clock-names\" \"$clks\" stringlist\n\t\t\t\t\t} else {\n\t\t\t\t\t\tset_drv_prop_if_empty $drv_handle \"clocks\" $clk_refs reference\n\t\t\t\t\t\tset_drv_prop_if_empty $drv_handle \"clock-names\" \"$clks\" stringlist\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tset_drv_prop_if_empty $drv_handle \"clock-names\" \"ref_clk\" stringlist\n\t\t\t\tset_drv_prop_if_empty $drv_handle \"clocks\" \"clkc 0\" reference\n\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc gen_endpoint {drv_handle value} {\n\tglobal end_mappings\n\tdict append end_mappings $drv_handle $value\n\tset val [dict get $end_mappings $drv_handle]\n}\n\nproc gen_axis_switch_in_endpoint {drv_handle value} {\n\tglobal axis_switch_in_end_mappings\n\tdict append axis_switch_in_end_mappings $drv_handle $value\n\tset val [dict get $axis_switch_in_end_mappings $drv_handle]\n}\n\nproc gen_axis_switch_in_remo_endpoint {drv_handle value} {\n\tglobal axis_switch_in_remo_mappings\n\tdict append axis_switch_in_remo_mappings $drv_handle $value\n\tset val [dict get $axis_switch_in_remo_mappings $drv_handle]\n}\n\nproc gen_axis_switch_port1_endpoint {drv_handle value} {\n\tglobal axis_switch_port1_end_mappings\n\tdict append axis_switch_port1_end_mappings $drv_handle $value\n\tset val [dict get $axis_switch_port1_end_mappings $drv_handle]\n}\n\nproc gen_axis_switch_port2_endpoint {drv_handle value} {\n\tglobal axis_switch_port2_end_mappings\n\tdict append axis_switch_port2_end_mappings $drv_handle $value\n\tset val [dict get $axis_switch_port2_end_mappings $drv_handle]\n}\n\nproc gen_axis_switch_port3_endpoint {drv_handle value} {\n\tglobal axis_switch_port3_end_mappings\n\tdict append axis_switch_port3_end_mappings $drv_handle $value\n\tset val [dict get $axis_switch_port3_end_mappings $drv_handle]\n}\n\nproc gen_axis_switch_port4_endpoint {drv_handle value} {\n\tglobal axis_switch_port4_end_mappings\n\tdict append axis_switch_port4_end_mappings $drv_handle $value\n\tset val [dict get $axis_switch_port4_end_mappings $drv_handle]\n}\n\nproc gen_axis_switch_port1_remote_endpoint {drv_handle value} {\n\tglobal axis_switch_port1_remo_mappings\n\tdict append axis_switch_port1_remo_mappings $drv_handle $value\n\tset val [dict get $axis_switch_port1_remo_mappings $drv_handle]\n}\n\nproc gen_axis_switch_port2_remote_endpoint {drv_handle value} {\n\tglobal axis_switch_port2_remo_mappings\n\tdict append axis_switch_port2_remo_mappings $drv_handle $value\n\tset val [dict get $axis_switch_port2_remo_mappings $drv_handle]\n}\n\nproc gen_axis_switch_port3_remote_endpoint {drv_handle value} {\n\tglobal axis_switch_port3_remo_mappings\n\tdict append axis_switch_port3_remo_mappings $drv_handle $value\n\tset val [dict get $axis_switch_port3_remo_mappings $drv_handle]\n}\n\nproc gen_axis_switch_port4_remote_endpoint {drv_handle value} {\n\tglobal axis_switch_port4_remo_mappings\n\tdict append axis_switch_port4_remo_mappings $drv_handle $value\n\tset val [dict get $axis_switch_port4_remo_mappings $drv_handle]\n}\n\nproc gen_axis_port1_endpoint {drv_handle value} {\n\tglobal port1_end_mappings\n\tdict append port1_end_mappings $drv_handle $value\n\tset val [dict get $port1_end_mappings $drv_handle]\n}\n\nproc gen_axis_port2_endpoint {drv_handle value} {\n\tglobal port2_end_mappings\n\tdict append port2_end_mappings $drv_handle $value\n\tset val [dict get $port2_end_mappings $drv_handle]\n}\n\nproc gen_axis_port3_endpoint {drv_handle value} {\n\tglobal port3_end_mappings\n\tdict append port3_end_mappings $drv_handle $value\n\tset val [dict get $port3_end_mappings $drv_handle]\n}\n\nproc gen_axis_port4_endpoint {drv_handle value} {\n\tglobal port4_end_mappings\n\tdict append port4_end_mappings $drv_handle $value\n\tset val [dict get $port4_end_mappings $drv_handle]\n}\n\nproc gen_broad_endpoint_port1 {drv_handle value} {\n global port1_broad_end_mappings\n dict append port1_broad_end_mappings $drv_handle $value\n set val [dict get $port1_broad_end_mappings $drv_handle]\n}\n\nproc gen_broad_endpoint_port2 {drv_handle value} {\n global port2_broad_end_mappings\n dict append port2_broad_end_mappings $drv_handle $value\n set val [dict get $port2_broad_end_mappings $drv_handle]\n}\n\nproc gen_broad_endpoint_port3 {drv_handle value} {\n global port3_broad_end_mappings\n dict append port3_broad_end_mappings $drv_handle $value\n set val [dict get $port3_broad_end_mappings $drv_handle]\n}\n\nproc gen_broad_endpoint_port4 {drv_handle value} {\n global port4_broad_end_mappings\n dict append port4_broad_end_mappings $drv_handle $value\n set val [dict get $port4_broad_end_mappings $drv_handle]\n}\n\nproc gen_broad_endpoint_port5 {drv_handle value} {\n global port5_broad_end_mappings\n dict append port5_broad_end_mappings $drv_handle $value\n set val [dict get $port5_broad_end_mappings $drv_handle]\n}\n\nproc gen_broad_endpoint_port6 {drv_handle value} {\n global port6_broad_end_mappings\n dict append port6_broad_end_mappings $drv_handle $value\n set val [dict get $port6_broad_end_mappings $drv_handle]\n}\n\nproc gen_broad_endpoint_port7 {drv_handle value} {\n global port7_broad_end_mappings\n dict append port7_broad_end_mappings $drv_handle $value\n set val [dict get $port7_broad_end_mappings $drv_handle]\n}\n\nproc get_endpoint_mapping {inip mappings} {\n\t#search the inip in mappings and return value if found\n\tset endpoint \"\"\n\tif {[dict exists $mappings $inip]} {\n\t\tset endpoint [dict get $mappings $inip]\n\t}\n\treturn \"$endpoint\"\n}\n\nproc add_endpoint_mapping {drv_handle port_node in_end remo_in_end} {\n\t#Add the endpoint/remote-endpoint for given drv_handle\n\tif {[regexp -nocase $drv_handle \"$remo_in_end\" match]} {\n\t\tif {[llength $remo_in_end]} {\n\t\t\tset node [add_or_get_dt_node -n \"endpoint\" -l $remo_in_end -p $port_node]\n\t\t}\n\t\tif {[llength $in_end]} {\n\t\t\thsi::utils::add_new_dts_param \"$node\" \"remote-endpoint\" $in_end reference\n\t\t}\n\t}\n}\n\nproc update_axis_switch_endpoints {inip port_node drv_handle} {\n\t#Read all the non memorymapped axis_switch global variables to get the\n\t#inip value corresponding to drv_handle\n\tglobal port1_end_mappings\n\tglobal port2_end_mappings\n\tglobal port3_end_mappings\n\tglobal port4_end_mappings\n\tglobal axis_port1_remo_mappings\n\tglobal axis_port2_remo_mappings\n\tglobal axis_port3_remo_mappings\n\tglobal axis_port4_remo_mappings\n\tif {[info exists port1_end_mappings] && [info exists axis_port1_remo_mappings]} {\n\t\tset in1_end [get_endpoint_mapping $inip $port1_end_mappings]\n\t\tset remo_in1_end [get_endpoint_mapping $inip $axis_port1_remo_mappings]\n\t}\n\tif {[info exists port2_end_mappings] && [info exists axis_port2_remo_mappings]} {\n\t\tset in2_end [get_endpoint_mapping $inip $port2_end_mappings]\n\t\tset remo_in2_end [get_endpoint_mapping $inip $axis_port2_remo_mappings]\n\t}\n\tif {[info exists port3_end_mappings] && [info exists axis_port3_remo_mappings]} {\n\t\tset in3_end [get_endpoint_mapping $inip $port3_end_mappings]\n\t\tset remo_in3_end [get_endpoint_mapping $inip $axis_port3_remo_mappings]\n\t}\n\tif {[info exists port4_end_mappings] && [info exists axis_port4_remo_mappings]} {\n\t\tset in4_end [get_endpoint_mapping $inip $port4_end_mappings]\n\t\tset remo_in4_end [get_endpoint_mapping $inip $axis_port4_remo_mappings]\n\t}\n\n\tif {[info exists remo_in1_end] && [info exists in1_end]} {\n\t\tdtg_verbose \"$port_node $remo_in1_end\"\n\t\tadd_endpoint_mapping $drv_handle $port_node $in1_end $remo_in1_end\n\t}\n\tif {[info exists remo_in2_end] && [info exists in2_end]} {\n\t\tdtg_verbose \"$port_node $remo_in2_end\"\n\t\tadd_endpoint_mapping $drv_handle $port_node $in2_end $remo_in2_end\n\t}\n\tif {[info exists remo_in3_end] && [info exists in3_end]} {\n\t\tdtg_verbose \"$port_node $remo_in3_end\"\n\t\tadd_endpoint_mapping $drv_handle $port_node $in3_end $remo_in3_end\n\t}\n\tif {[info exists remo_in4_end] && [info exists in4_end]} {\n\t\tdtg_verbose \"$port_node $remo_in4_end\"\n\t\tadd_endpoint_mapping $drv_handle $port_node $in4_end $remo_in4_end\n\t}\n}\n\nproc update_endpoints {drv_handle} {\n\tglobal end_mappings\n\tglobal remo_mappings\n\tglobal set port1_end_mappings\n\tglobal set port2_end_mappings\n\tglobal set port3_end_mappings\n\tglobal set port4_end_mappings\n\tglobal set axis_port1_remo_mappings\n\tglobal set axis_port2_remo_mappings\n\tglobal set axis_port3_remo_mappings\n\tglobal set axis_port4_remo_mappings\n\tglobal set port1_broad_end_mappings\n\tglobal set port2_broad_end_mappings\n\tglobal set port3_broad_end_mappings\n\tglobal set port4_broad_end_mappings\n\tglobal set port5_broad_end_mappings\n\tglobal set port6_broad_end_mappings\n\tglobal set port7_broad_end_mappings\n\tglobal set broad_port1_remo_mappings\n\tglobal set broad_port2_remo_mappings\n\tglobal set broad_port3_remo_mappings\n\tglobal set broad_port4_remo_mappings\n\tglobal set broad_port5_remo_mappings\n\tglobal set broad_port6_remo_mappings\n\tglobal set broad_port7_remo_mappings\n\tglobal set axis_switch_in_end_mappings\n\tglobal set axis_switch_in_remo_mappings\n\tglobal set axis_switch_port1_end_mappings\n\tglobal set axis_switch_port2_end_mappings\n\tglobal set axis_switch_port3_end_mappings\n\tglobal set axis_switch_port4_end_mappings\n\tglobal set axis_switch_port1_remo_mappings\n\tglobal set axis_switch_port2_remo_mappings\n\tglobal set axis_switch_port3_remo_mappings\n\tglobal set axis_switch_port4_remo_mappings\n\n\tset broad [hsi::utils::get_os_parameter_value \"broad\"]\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n if {[is_pl_ip $drv_handle] && $remove_pl} {\n return 0\n }\n\n\tset node [gen_peripheral_nodes $drv_handle]\n\tset ip [get_cells -hier $drv_handle]\n\tif {[string match -nocase [get_property IP_NAME $ip] \"v_proc_ss\"]} {\n\t\tset topology [get_property CONFIG.C_TOPOLOGY [get_cells -hier $drv_handle]]\n\t\tif {$topology == 0} {\n\t\t\tset max_data_width [get_property CONFIG.C_MAX_DATA_WIDTH [get_cells -hier $drv_handle]]\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,video-width\" $max_data_width int\n\t\t\tset ports_node [add_or_get_dt_node -n \"ports\" -l scaler_ports$drv_handle -p $node]\n\t\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\t\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\t\t\tset port_node [add_or_get_dt_node -n \"port\" -l scaler_port0$drv_handle -u 0 -p $ports_node]\n\t\t\thsi::utils::add_new_dts_param \"${port_node}\" \"/* For xlnx,video-format user needs to fill as per their requirement */\" \"\" comment\n\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 0 int\n\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"xlnx,video-format\" 3 int\n\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"xlnx,video-width\" $max_data_width int\n\n\t\t\tset scaninip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis\"]\n\t\t\tif {[llength $scaninip] && \\\n\t\t\t\t[string match -nocase [get_property IP_NAME $scaninip] \"axis_switch\"]} {\n\t\t\t\t\tset axis_node [add_or_get_dt_node -n \"endpoint\" -l $drv_handle$scaninip -p $port_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"$axis_node\" \"remote-endpoint\" axis_switch_out1$scaninip reference\n\t\t\t\t\t}\n\t\t\t# Get next IN IP if axis_slice connected\n\t\t\tif {[llength \"$scaninip\"] && \\\n\t\t\t\t[string match -nocase [get_property IP_NAME $scaninip] \"axis_register_slice\"]} {\n\t\t\t\tset intf \"S_AXIS\"\n\t\t\t\tset scaninip [get_connected_stream_ip [get_cells -hier $scaninip] \"$intf\"]\n\t\t\t}\n\t\t\tforeach inip $scaninip {\n\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"ISPPipeline_accel\"]} {\n\t\t\t\t\t\tset port0_node [add_or_get_dt_node -n \"endpoint\" -l v_proc_ss$inip -p $port_node]\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$port0_node\" \"remote-endpoint\" $inip$drv_handle reference\n\t\t\t\t\t}\n\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip]\n\t\t\t\t\tif {![llength $ip_mem_handles]} {\n\t\t\t\t\t\t# Add endpoints if IN IP is axis_switch and non memory mapped\n\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"axis_switch\"]} {\n\t\t\t\t\t\t\tupdate_axis_switch_endpoints $inip $port_node $drv_handle\n\t\t\t\t\t\t}\n\t\t\t\t\t\tset broad_ip [get_broad_in_ip $inip]\n\t\t\t\t\t\tif {[llength $broad_ip]} {\n\t\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $broad_ip] \"axis_broadcaster\"]} {\n\t\t\t\t\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $broad_ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\t\t\t\t\t\t\tset intlen [llength $master_intf]\n\t\t\t\t\t\t\t\tset sca_in_end \"\"\n\t\t\t\t\t\t\t\tset sca_remo_in_end \"\"\n\t\t\t\t\t\t\t\tset sca_remo_in1_end \"\"\n\t\t\t\t\t\t\t\tset sca_remo_in2_end \"\"\n\t\t\t\t\t\t\t\tset sca_remo_in3_end \"\"\n\t\t\t\t\t\t\t\tswitch $intlen {\n\t\t\t\t\t\t\t\t\t\"1\" {\n\t\t\t\t\t\t\t\t\t\tif {[info exists port1_broad_end_mappings] && [dict exists $port1_broad_end_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\t\tset sca_in_end [dict get $port1_broad_end_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t\t\tdtg_verbose \"sca_in_end:$sca_in_end\"\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\tif {[info exists broad_port1_remo_mappings] && [dict exists $broad_port1_remo_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\t\tset sca_remo_in_end [dict get $broad_port1_remo_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\tif {[regexp -nocase $drv_handle \"$sca_remo_in_end\" match]} {\n\t\t\t\t\t\t\t\t\t\t\tif {[llength $sca_remo_in_end]} {\n\t\t\t\t\t\t\t\t\t\t\t\tset sca_node [add_or_get_dt_node -n \"endpoint\" -l $sca_remo_in_end -p $port_node]\n\t\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\t\tif {[llength $sca_in_end]} {\n\t\t\t\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$sca_node\" \"remote-endpoint\" $sca_in_end reference\n\t\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\t}\n\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\"2\" {\n\t\t\t\t\t\t\t\t\t\tif {[info exists port1_broad_end_mappings] && [dict exists $port1_broad_end_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\t\tset sca_in_end [dict get $port1_broad_end_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\tif {[info exists broad_port1_remo_mappings] && [dict exists $broad_port1_remo_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\t\tset sca_remo_in_end [dict get $broad_port1_remo_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\tif {[info exists port2_broad_end_mappings] && [dict exists $port2_broad_end_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\t\tset sca_in1_end [dict get $port2_broad_end_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\tif {[info exists broad_port2_remo_mappings] && [dict exists $broad_port2_remo_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\t\tset sca_remo_in1_end [dict get $broad_port2_remo_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\tif {[regexp -nocase $drv_handle \"$sca_remo_in_end\" match]} {\n\t\t\t\t\t\t\t\t\t\t\tif {[llength $sca_remo_in_end]} {\n\t\t\t\t\t\t\t\t\t\t\t\tset sca_node [add_or_get_dt_node -n \"endpoint\" -l $sca_remo_in_end -p $port_node]\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\t\tif {[llength $sca_in_end]} {\n\t\t\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$sca_node\" \"remote-endpoint\" $sca_in_end reference\n\t\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\tif {[regexp -nocase $drv_handle \"$sca_remo_in1_end\" match]} {\n\t\t\t\t\t\t\t\t\t\t\tif {[llength $sca_remo_in1_end]} {\n\t\t\t\t\t\t\t\t\t\t\t\tset sca_node [add_or_get_dt_node -n \"endpoint\" -l $sca_remo_in1_end -p $port_node]\n\t\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\t\tif {[llength $sca_in1_end]} {\n\t\t\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$sca_node\" \"remote-endpoint\" $sca_in1_end reference\n\t\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\"3\" {\n\t\t\t\t\t\t\t\t\tif {[info exists port1_broad_end_mappings] && [dict exists $port1_broad_end_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\tset sca_in_end [dict get $port1_broad_end_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\tif {[info exists broad_port1_remo_mappings] && [dict exists $broad_port1_remo_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\tset sca_remo_in_end [dict get $broad_port1_remo_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t}\n\n\t\t\t\t\t\t\t\t\tif {[info exists port2_broad_end_mappings] && [dict exists $port2_broad_end_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\tset sca_in1_end [dict get $port2_broad_end_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\tif {[info exists broad_port2_remo_mappings] && [dict exists $broad_port2_remo_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\tset sca_remo_in1_end [dict get $broad_port2_remo_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t}\n\n\t\t\t\t\t\t\t\t\tif {[info exists port3_broad_end_mappings] && [dict exists $port3_broad_end_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\tset sca_in2_end [dict get $port3_broad_end_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\tif {[info exists broad_port3_remo_mappings] && [dict exists $broad_port3_remo_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\tset sca_remo_in2_end [dict get $broad_port3_remo_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\tif {[regexp -nocase $drv_handle \"$sca_remo_in_end\" match]} {\n\t\t\t\t\t\t\t\t\t\tif {[llength $sca_remo_in_end]} {\n\t\t\t\t\t\t\t\t\t\t\tset sca_node [add_or_get_dt_node -n \"endpoint\" -l $sca_remo_in_end -p $port_node]\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\tif {[llength $sca_in_end]} {\n\t\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$sca_node\" \"remote-endpoint\" $sca_in_end reference\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\tif {[regexp -nocase $drv_handle \"$sca_remo_in1_end\" match]} {\n\t\t\t\t\t\t\t\t\t\tif {[llength $sca_remo_in1_end]} {\n\t\t\t\t\t\t\t\t\t\t\tset sca_node [add_or_get_dt_node -n \"endpoint\" -l $sca_remo_in1_end -p $port_node]\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\tif {[llength $sca_in1_end]} {\n\t\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$sca_node\" \"remote-endpoint\" $sca_in1_end reference\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\tif {[regexp -nocase $drv_handle \"$sca_remo_in2_end\" match]} {\n\t\t\t\t\t\t\t\t\t\tif {[llength $sca_remo_in2_end]} {\n\t\t\t\t\t\t\t\t\t\t\tset sca_node [add_or_get_dt_node -n \"endpoint\" -l $sca_remo_in2_end -p $port_node]\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\tif {[llength $sca_in2_end]} {\n\t\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$sca_node\" \"remote-endpoint\" $sca_in2_end reference\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\"4\" {\n\t\t\t\t\t\t\t\tif {[info exists port1_broad_end_mappings] && [dict exists $port1_broad_end_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\tset sca_in_end [dict get $port1_broad_end_mappings $broad_ip]\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\tif {[info exists broad_port1_remo_mappings] && [dict exists $broad_port1_remo_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\tset sca_remo_in_end [dict get $broad_port1_remo_mappings $broad_ip]\n\t\t\t\t\t\t\t\t}\n\n\t\t\t\t\t\t\t\tif {[info exists port2_broad_end_mappings] && [dict exists $port2_broad_end_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\tset sca_in1_end [dict get $port2_broad_end_mappings $broad_ip]\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\tif {[info exists broad_port2_remo_mappings] && [dict exists $broad_port2_remo_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\tset sca_remo_in1_end [dict get $broad_port2_remo_mappings $broad_ip]\n\t\t\t\t\t\t\t\t}\n\n\t\t\t\t\t\t\t\tif {[info exists port3_broad_end_mappings] && [dict exists $port3_broad_end_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\tset sca_in2_end [dict get $port3_broad_end_mappings $broad_ip]\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\tif {[info exists broad_port3_remo_mappings] && [dict exists $broad_port3_remo_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\tset sca_remo_in2_end [dict get $broad_port3_remo_mappings $broad_ip]\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\tif {[info exists port4_broad_end_mappings] && [dict exists $port4_broad_end_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\tset sca_in3_end [dict get $port4_broad_end_mappings $broad_ip]\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\tif {[info exists broad_port4_remo_mappings] && [dict exists $broad_port4_remo_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\tset sca_remo_in3_end [dict get $broad_port4_remo_mappings $broad_ip]\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\treturn\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t\tforeach inip $scaninip {\n\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"system_ila\"]} {\n\t\t\t\t\t\tcontinue\n\t\t\t\t\t}\n\t\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip]\n\t\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\t\t\t} else {\n\t\t\t\t\t\tset inip [get_in_connect_ip $inip $master_intf]\n\t\t\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"axi_vdma\"]} {\n\t\t\t\t\t\t\t\tgen_frmbuf_rd_node $inip $drv_handle $port_node\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\t\tset sca_in_end \"\"\n\t\t\t\t\t\tset sca_remo_in_end \"\"\n\t\t\t\t\t\tif {[info exists end_mappings] && [dict exists $end_mappings $inip]} {\n\t\t\t\t\t\t\tset sca_in_end [dict get $end_mappings $inip]\n\t\t\t\t\t\t\tdtg_verbose \"drv:$drv_handle inend:$sca_in_end\"\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} {\n\t\t\t\t\t\t\tset sca_remo_in_end [dict get $remo_mappings $inip]\n\t\t\t\t\t\t\tdtg_verbose \"drv:$drv_handle inremoend:$sca_remo_in_end\"\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[llength $sca_remo_in_end]} {\n\t\t\t\t\t\t\tset scainnode [add_or_get_dt_node -n \"endpoint\" -l $sca_remo_in_end -p $port_node]\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[llength $sca_in_end]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$scainnode\" \"remote-endpoint\" $sca_in_end reference\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tdtg_warning \"$drv_handle pin s_axis is not connected..check your design\"\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {$topology == 3} {\n\t\t\tset ports_node [add_or_get_dt_node -n \"ports\" -l csc_ports$drv_handle -p $node]\n\t\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\t\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\t\t\tset port_node [add_or_get_dt_node -n \"port\" -l csc_port0$drv_handle -u 0 -p $ports_node]\n\t\t\thsi::utils::add_new_dts_param \"${port_node}\" \"/* For xlnx,video-format user needs to fill as per their requirement */\" \"\" comment\n\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 0 int\n\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"xlnx,video-format\" 3 int\n\t\t\tset max_data_width [get_property CONFIG.C_MAX_DATA_WIDTH [get_cells -hier $drv_handle]]\n\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"xlnx,video-width\" $max_data_width int\n\n\t\t\tset cscinip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis\"]\n\t\t\tif {[llength $cscinip] && \\\n\t\t\t\t[string match -nocase [get_property IP_NAME $cscinip] \"axis_switch\"]} {\n\t\t\t\tset csc_node [add_or_get_dt_node -n \"endpoint\" -l $drv_handle$cscinip -p $port_node]\n\t\t\t\thsi::utils::add_new_dts_param \"$csc_node\" \"remote-endpoint\" axis_switch_out2$cscinip reference\n\t\t\t\t}\n\t\t\tif {[llength $cscinip]} {\n\t\t\t\tforeach inip $cscinip {\n\t\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip]\n\t\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"v_frmbuf_rd\"]} {\n\t\t\t\t\t\t\tgen_frmbuf_rd_node $inip $drv_handle $port_node\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tset inip [get_in_connect_ip $inip $master_intf]\n\t\t\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"system_ila\"]} {\n\t\t\t\t\t\t\t\tcontinue\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"v_frmbuf_rd\"]} {\n\t\t\t\t\t\t\t\tgen_frmbuf_rd_node $inip $drv_handle $port_node\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\t\tset csc_in_end \"\"\n\t\t\t\t\t\tset csc_remo_in_end \"\"\n\t\t\t\t\t\tif {[info exists end_mappings] && [dict exists $end_mappings $inip]} {\n\t\t\t\t\t\t\tset csc_in_end [dict get $end_mappings $inip]\n\t\t\t\t\t\t\tdtg_verbose \"drv:$drv_handle inend:$csc_in_end\"\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} {\n\t\t\t\t\t\t\tset csc_remo_in_end [dict get $remo_mappings $inip]\n\t\t\t\t\t\t\tdtg_verbose \"drv:$drv_handle inremoend:$csc_remo_in_end\"\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[llength $csc_remo_in_end]} {\n\t\t\t\t\t\t\tset cscinnode [add_or_get_dt_node -n \"endpoint\" -l $csc_remo_in_end -p $port_node]\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[llength $csc_in_end]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$cscinnode\" \"remote-endpoint\" $csc_in_end reference\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tdtg_warning \"$drv_handle pin s_axis is not connected..check your design\"\n\t\t\t}\n\t\t}\n\t}\n\tif {[string match -nocase [get_property IP_NAME $ip] \"v_demosaic\"]} {\n\t\tset ports_node [add_or_get_dt_node -n \"ports\" -l demosaic_ports$drv_handle -p $node]\n\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\t\tset port_node [add_or_get_dt_node -n \"port\" -l demosaic_port0$drv_handle -u 0 -p $ports_node]\n\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 0 int\n\t\tset demo_inip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video\"]\n\t\tset len [llength $demo_inip]\n\t\tif {$len > 1} {\n\t\t\tfor {set i 0 } {$i < $len} {incr i} {\n\t\t\t\tset temp_ip [lindex $demo_inip $i]\n\t\t\t\tif {[regexp -nocase \"ila\" $temp_ip match]} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\tset demo_inip \"$temp_ip\"\n\t\t\t}\n\t\t}\n\t\tforeach inip $demo_inip {\n\t\t\tif {[llength $inip]} {\n\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip]\n\t\t\t\tif {![llength $ip_mem_handles]} {\n\t\t\t\t\tset broad_ip [get_broad_in_ip $inip]\n\t\t\t\t\tif {[llength $broad_ip]} {\n\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $broad_ip] \"axis_broadcaster\"]} {\n\t\t\t\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $broad_ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\t\t\t\t\t\tset intlen [llength $master_intf]\n\t\t\t\t\t\t\tset mipi_in_end \"\"\n\t\t\t\t\t\t\tset mipi_remo_in_end \"\"\n\t\t\t\t\t\t\tswitch $intlen {\n\t\t\t\t\t\t\t\t\"1\" {\n\t\t\t\t\t\t\t\t\tif {[info exists port1_broad_end_mappings] && [dict exists $port1_broad_end_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\tset mipi_in_end [dict get $port1_broad_end_mappings $broad_ip]\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\tif {[info exists broad_port1_remo_mappings] && [dict exists $broad_port1_remo_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\tset mipi_remo_in_end [dict get $broad_port1_remo_mappings $broad_ip]\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\tif {[info exists sca_remo_in_end] && [regexp -nocase $drv_handle \"$sca_remo_in_end\" match]} {\n\t\t\t\t\t\t\t\t\tif {[llength $mipi_remo_in_end]} {\n\t\t\t\t\t\t\t\t\t\tset mipi_node [add_or_get_dt_node -n \"endpoint\" -l $mipi_remo_in_end -p $port_node]\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\tif {[llength $mipi_in_end]} {\n\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mipi_node\" \"remote-endpoint\" $mipi_in_end reference\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t}\n\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\"2\" {\n\t\t\t\t\t\t\t\t\tif {[info exists port1_broad_end_mappings] && [dict exists $port1_broad_end_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\tset mipi_in_end [dict get $port1_broad_end_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\tif {[info exists broad_port1_remo_mappings] && [dict exists $broad_port1_remo_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\tset mipi_remo_in_end [dict get $broad_port1_remo_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\tif {[info exists port2_broad_end_mappings] && [dict exists $port2_broad_end_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\tset mipi_in1_end [dict get $port2_broad_end_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\tif {[info exists broad_port2_remo_mappings] && [dict exists $broad_port2_remo_mappings $broad_ip]} {\n\t\t\t\t\t\t\t\t\t\tset mipi_remo_in1_end [dict get $broad_port2_remo_mappings $broad_ip]\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\tif {[info exists mipi_remo_in_end] && [regexp -nocase $drv_handle \"$mipi_remo_in_end\" match]} {\n\t\t\t\t\t\t\t\t\t\tif {[llength $mipi_remo_in_end]} {\n\t\t\t\t\t\t\t\t\t\t\tset mipi_node [add_or_get_dt_node -n \"endpoint\" -l $mipi_remo_in_end -p $port_node]\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\tif {[llength $mipi_in_end]} {\n\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mipi_node\" \"remote-endpoint\" $mipi_in_end reference\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\tif {[info exists mipi_remo_in1_end] && [regexp -nocase $drv_handle \"$mipi_remo_in1_end\" match]} {\n\t\t\t\t\t\t\t\t\t\tif {[llength $mipi_remo_in1_end]} {\n\t\t\t\t\t\t\t\t\t\t\tset mipi_node [add_or_get_dt_node -n \"endpoint\" -l $mipi_remo_in1_end -p $port_node]\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\tif {[llength $mipi_in1_end]} {\n\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mipi_node\" \"remote-endpoint\" $mipi_in1_end reference\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\treturn\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[llength $demo_inip]} {\n\t\t\tif {[string match -nocase [get_property IP_NAME $demo_inip] \"axis_switch\"]} {\n\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $demo_inip]\n\t\t\tif {![llength $ip_mem_handles]} {\n\t\t\t\tset demo_in_end \"\"\n\t\t\t\tset demo_remo_in_end \"\"\n\t\t\t\tif {[info exists port1_end_mappings] && [dict exists $port1_end_mappings $demo_inip]} {\n\t\t\t\t\tset demo_in_end [dict get $port1_end_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_in_end:$demo_in_end\"\n\t\t\t\t}\n\t\t\t\tif {[info exists axis_port1_remo_mappings] && [dict exists $axis_port1_remo_mappings $demo_inip]} {\n\t\t\t\t\tset demo_remo_in_end [dict get $axis_port1_remo_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_remo_in_end:$demo_remo_in_end\"\n\t\t\t\t}\n\t\t\t\tif {[info exists port2_end_mappings] && [dict exists $port2_end_mappings $demo_inip]} {\n\t\t\t\t\tset demo_in1_end [dict get $port2_end_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_in1_end:$demo_in1_end\"\n\t\t\t\t}\n\t\t\t\tif {[info exists axis_port2_remo_mappings] && [dict exists $axis_port2_remo_mappings $demo_inip]} {\n\t\t\t\t\tset demo_remo_in1_end [dict get $axis_port2_remo_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_remo_in1_end:$demo_remo_in1_end\"\n\t\t\t\t}\n\t\t\t\tif {[info exists port3_end_mappings] && [dict exists $port3_end_mappings $demo_inip]} {\n\t\t\t\t\tset demo_in2_end [dict get $port3_end_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_in2_end:$demo_in2_end\"\n\t\t\t\t}\n\t\t\t\tif {[info exists axis_port3_remo_mappings] && [dict exists $axis_port3_remo_mappings $demo_inip]} {\n\t\t\t\t\tset demo_remo_in2_end [dict get $axis_port3_remo_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_remo_in2_end:$demo_remo_in2_end\"\n\t\t\t\t}\n\t\t\t\tif {[info exists port4_end_mappings] && [dict exists $port4_end_mappings $demo_inip]} {\n\t\t\t\t\tset demo_in3_end [dict get $port4_end_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_in3_end:$demo_in3_end\"\n\t\t\t\t}\n\t\t\t\tif {[info exists axis_port4_remo_mappings] && [dict exists $axis_port4_remo_mappings $demo_inip]} {\n\t\t\t\t\tset demo_remo_in3_end [dict get $axis_port4_remo_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_remo_in3_end:$demo_remo_in3_end\"\n\t\t\t\t}\n\t\t\t\tset drv [split $demo_remo_in_end \"-\"]\n\t\t\t\tset handle [lindex $drv 0]\n\t\t\t\tif {[info exists demo_remo_in_end] && [regexp -nocase $drv_handle \"$demo_remo_in_end\" match]} {\n\t\t\t\t\tif {[llength $demo_remo_in_end]} {\n\t\t\t\t\t\tset demosaic_node [add_or_get_dt_node -n \"endpoint\" -l $demo_remo_in_end -p $port_node]\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $demo_in_end]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$demosaic_node\" \"remote-endpoint\" $demo_in_end reference\n\t\t\t\t\t}\n\t\t\t\t\tdtg_verbose \"****DEMO_END1****\"\n\t\t\t\t}\n\t\t\t\tif {[info exists demo_remo_in1_end] && [regexp -nocase $drv_handle \"$demo_remo_in1_end\" match]} {\n\t\t\t\t\tif {[llength $demo_remo_in1_end]} {\n\t\t\t\t\t\tset demosaic_node1 [add_or_get_dt_node -n \"endpoint\" -l $demo_remo_in1_end -p $port_node]\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $demo_in1_end]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$demosaic_node1\" \"remote-endpoint\" $demo_in1_end reference\n\t\t\t\t\t}\n\t\t\t\t\tdtg_verbose \"****DEMO_END2****\"\n\t\t\t\t}\n\t\t\t\tif {[info exists demo_remo_in2_end] && [regexp -nocase $drv_handle \"$demo_remo_in2_end\" match]} {\n\t\t\t\t\tif {[llength $demo_remo_in2_end]} {\n\t\t\t\t\t\tset demosaic_node2 [add_or_get_dt_node -n \"endpoint\" -l $demo_remo_in2_end -p $port_node]\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $demo_in2_end]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$demosaic_node2\" \"remote-endpoint\" $demo_in2_end reference\n\t\t\t\t\t}\n\t\t\t\t\tdtg_verbose \"****DEMO_END3****\"\n\t\t\t\t}\n\t\t\t\tif {[info exists demo_remo_in3_end] && [regexp -nocase $drv_handle \"$demo_remo_in3_end\" match]} {\n\t\t\t\t\tif {[llength $demo_remo_in3_end]} {\n\t\t\t\t\t\tset demosaic_node3 [add_or_get_dt_node -n \"endpoint\" -l $demo_remo_in3_end -p $port_node]\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $demo_in3_end]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$demosaic_node3\" \"remote-endpoint\" $demo_in3_end reference\n\t\t\t\t\t}\n\t\t\t\t\tdtg_verbose \"****DEMO_END3****\"\n\t\t\t\t}\n\t\t\t\treturn\n\t\t\t} else {\n\t\t\t\tset demo_in_end \"\"\n\t\t\t\tset demo_remo_in_end \"\"\n\t\t\t\tif {[info exists axis_switch_port1_end_mappings] && [dict exists $axis_switch_port1_end_mappings $demo_inip]} {\n\t\t\t\t\tset demo_in_end [dict get $axis_switch_port1_end_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_in_end:$demo_in_end\"\n\t\t\t\t}\n\t\t\t\tif {[info exists axis_switch_port1_remo_mappings] && [dict exists $axis_switch_port1_remo_mappings $demo_inip]} {\n\t\t\t\t\tset demo_remo_in_end [dict get $axis_switch_port1_remo_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_remo_in_end:$demo_remo_in_end\"\n\t\t\t\t}\n\t\t\t\tif {[info exists axis_switch_port2_end_mappings] && [dict exists $axis_switch_port2_end_mappings $demo_inip]} {\n\t\t\t\t\tset demo_in1_end [dict get $axis_switch_port2_end_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_in1_end:$demo_in1_end\"\n\t\t\t\t}\n\t\t\t\tif {[info exists axis_switch_port2_remo_mappings] && [dict exists $axis_switch_port2_remo_mappings $demo_inip]} {\n\t\t\t\t\tset demo_remo_in1_end [dict get $axis_switch_port2_remo_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_remo_in1_end:$demo_remo_in1_end\"\n\t\t\t\t}\n\t\t\t\tif {[info exists axis_switch_port3_end_mappings] && [dict exists $axis_switch_port3_end_mappings $demo_inip]} {\n\t\t\t\t\tset demo_in2_end [dict get $axis_switch_port3_end_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_in2_end:$demo_in2_end\"\n\t\t\t\t}\n\t\t\t\tif {[info exists axis_switch_port3_remo_mappings] && [dict exists $axis_switch_port3_remo_mappings $demo_inip]} {\n\t\t\t\t\tset demo_remo_in2_end [dict get $axis_switch_port3_remo_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_remo_in2_end:$demo_remo_in2_end\"\n\t\t\t\t}\n\t\t\t\tif {[info exists axis_switch_port4_end_mappings] && [dict exists $axis_switch_port4_end_mappings $demo_inip]} {\n\t\t\t\t\tset demo_in3_end [dict get $axis_switch_port4_end_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_in3_end:$demo_in3_end\"\n\t\t\t\t}\n\t\t\t\tif {[info exists axis_switch_port4_remo_mappings] && [dict exists $axis_switch_port4_remo_mappings $demo_inip]} {\n\t\t\t\t\tset demo_remo_in3_end [dict get $axis_switch_port4_remo_mappings $demo_inip]\n\t\t\t\t\tdtg_verbose \"demo_remo_in3_end:$demo_remo_in3_end\"\n\t\t\t\t}\n\t\t\t\tset drv [split $demo_remo_in_end \"-\"]\n\t\t\t\tset handle [lindex $drv 0]\n\t\t\t\tif {[regexp -nocase $drv_handle \"$demo_remo_in_end\" match]} {\n\t\t\t\t\tif {[llength $demo_remo_in_end]} {\n\t\t\t\t\t\tset demosaic_node [add_or_get_dt_node -n \"endpoint\" -l $demo_remo_in_end -p $port_node]\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $demo_in_end]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$demosaic_node\" \"remote-endpoint\" $demo_in_end reference\n\t\t\t\t\t}\n\t\t\t\t\tdtg_verbose \"****DEMO_END1****\"\n\t\t\t\t}\n\t\t\t\tif {[regexp -nocase $drv_handle \"$demo_remo_in1_end\" match]} {\n\t\t\t\t\tif {[llength $demo_remo_in1_end]} {\n\t\t\t\t\t\tset demosaic_node1 [add_or_get_dt_node -n \"endpoint\" -l $demo_remo_in1_end -p $port_node]\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $demo_in1_end]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$demosaic_node1\" \"remote-endpoint\" $demo_in1_end reference\n\t\t\t\t\t}\n\t\t\t\t\tdtg_verbose \"****DEMO_END2****\"\n\t\t\t\t}\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tset inip \"\"\n\t\tif {[llength $demo_inip]} {\n\t\t\tforeach inip $demo_inip {\n\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip]\n\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\t\t} else {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"system_ila\"]} {\n\t\t\t\t\t\tcontinue\n\t\t\t\t\t}\n\t\t\t\t\tset inip [get_in_connect_ip $inip $master_intf]\n\t\t\t\t}\n\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\tset demo_in_end \"\"\n\t\t\t\t\tset demo_remo_in_end \"\"\n\t\t\t\t\tif {[info exists end_mappings] && [dict exists $end_mappings $inip]} {\n\t\t\t\t\t\tset demo_in_end [dict get $end_mappings $inip]\n\t\t\t\t\t\tdtg_verbose \"demo_in_end:$demo_in_end\"\n\t\t\t\t\t}\n\t\t\t\t\tif {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} {\n\t\t\t\t\t\tset demo_remo_in_end [dict get $remo_mappings $inip]\n\t\t\t\t\t\tdtg_verbose \"demo_remo_in_end:$demo_remo_in_end\"\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $demo_remo_in_end]} {\n\t\t\t\t\t\tset demosaic_node [add_or_get_dt_node -n \"endpoint\" -l $demo_remo_in_end -p $port_node]\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $demo_in_end]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$demosaic_node\" \"remote-endpoint\" $demo_in_end reference\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle pin s_axis is not connected..check your design\"\n\t\t}\n\t\tdtg_verbose \"***************DEMOEND****************\"\n\t}\n\tif {[string match -nocase [get_property IP_NAME $ip] \"v_gamma_lut\"]} {\n\t\tset ports_node [add_or_get_dt_node -n \"ports\" -l gamma_ports$drv_handle -p $node]\n\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\n\t\tset port_node [add_or_get_dt_node -n \"port\" -l gamma_port0$drv_handle -u 0 -p $ports_node]\n\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 0 int\n\t\tset max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"$port_node\" \"xlnx,video-width\" $max_data_width int\n\t\tset gamma_inip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video\"]\n\t\tset inip \"\"\n\t\tif {[llength $gamma_inip]} {\n\t\t\tforeach inip $gamma_inip {\n\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip]\n\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\t\t} else {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"system_ila\"]} {\n\t\t\t\t\t\tcontinue\n\t\t\t\t\t}\n\t\t\t\t\tset inip [get_in_connect_ip $inip $master_intf]\n\t\t\t\t}\n\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\tset gamma_in_end \"\"\n\t\t\t\t\tset gamma_remo_in_end \"\"\n\t\t\t\t\tif {[info exists end_mappings] && [dict exists $end_mappings $inip]} {\n\t\t\t\t\t\tset gamma_in_end [dict get $end_mappings $inip]\n\t\t\t\t\t\tdtg_verbose \"gamma_in_end:$gamma_in_end\"\n\t\t\t\t\t}\n\t\t\t\t\tif {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} {\n\t\t\t\t\t\tset gamma_remo_in_end [dict get $remo_mappings $inip]\n\t\t\t\t\t\tdtg_verbose \"gamma_remo_in_end:$gamma_remo_in_end\"\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $gamma_remo_in_end]} {\n\t\t\t\t\t\tset gamma_node [add_or_get_dt_node -n \"endpoint\" -l $gamma_remo_in_end -p $port_node]\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $gamma_in_end]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$gamma_node\" \"remote-endpoint\" $gamma_in_end reference\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle pin s_axis_video is not connected..check your design\"\n\t\t}\n\t}\n\n\tif {[string match -nocase [get_property IP_NAME $ip] \"mipi_dsi_tx_subsystem\"]} {\n\t\tset dsitx_inip [get_connected_stream_ip [get_cells -hier $drv_handle] \"S_AXIS\"]\n\t\tif {![llength $dsitx_inip]} {\n\t\t\tdtg_warning \"$drv_handle pin S_AXIS is not connected ..check your design\"\n\t\t}\n\t\tset port_node [add_or_get_dt_node -n \"port\" -l encoder_dsi_port$drv_handle -u 0 -p $node]\n\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 0 int\n\t\tset inip \"\"\n\t\tforeach inip $dsitx_inip {\n\t\t\tif {[llength $inip]} {\n\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip]\n\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"v_frmbuf_rd\"]} {\n\t\t\t\t\t\tgen_frmbuf_rd_node $inip $drv_handle $port_node\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"system_ila\"]} {\n\t\t\t\t\t\tcontinue\n\t\t\t\t\t}\n\t\t\t\t\tputs \"******************dsitx****************\"\n\t\t\t\t\tset inip [get_in_connect_ip $inip $master_intf]\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"v_frmbuf_rd\"]} {\n\t\t\t\t\t\tgen_frmbuf_rd_node $inip $drv_handle $port_node\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[llength $inip]} {\n\t\t\tset dsitx_in_end \"\"\n\t\t\tset dsitx_remo_in_end \"\"\n\t\t\tif {[info exists end_mappings] && [dict exists $end_mappings $inip]} {\n\t\t\t\tset dsitx_in_end [dict get $end_mappings $inip]\n\t\t\t\tdtg_verbose \"dsitx_in_end:$dsitx_in_end\"\n\t\t\t}\n\t\t\tif {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} {\n\t\t\t\tset dsitx_remo_in_end [dict get $remo_mappings $inip]\n\t\t\t\tdtg_verbose \"dsitx_remo_in_end:$dsitx_remo_in_end\"\n\t\t\t}\n\t\t\tif {[llength $dsitx_remo_in_end]} {\n\t\t\t\tset dsitx_node [add_or_get_dt_node -n \"endpoint\" -l $dsitx_remo_in_end -p $port_node]\n\t\t\t}\n\t\t\tif {[llength $dsitx_in_end]} {\n\t\t\t\thsi::utils::add_new_dts_param \"$dsitx_node\" \"remote-endpoint\" $dsitx_in_end reference\n\t\t\t}\n\t\t}\n\t}\n\n\tif {[string match -nocase [get_property IP_NAME $ip] \"v_smpte_uhdsdi_tx_ss\"]} {\n\t\tset ports_node [add_or_get_dt_node -n \"ports\" -l sditx_ports$drv_handle -p $node]\n\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\t\tset sdi_port_node [add_or_get_dt_node -n \"port\" -l encoder_sdi_port$drv_handle -u 0 -p $ports_node]\n\t\thsi::utils::add_new_dts_param \"$sdi_port_node\" \"reg\" 0 int\n\t\tset sditx_in_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] \"VIDEO_IN\"]\n\t\tif {![llength $sditx_in_ip]} {\n\t\t\tdtg_warning \"$drv_handle pin VIDEO_IN is not connected...check your design\"\n\t\t}\n\t\tset inip \"\"\n\t\tforeach inip $sditx_in_ip {\n\t\t\tif {[llength $inip]} {\n\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip]\n\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"v_frmbuf_rd\"]} {\n\t\t\t\t\t\tgen_frmbuf_rd_node $inip $drv_handle $sdi_port_node\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"system_ila\"]} {\n\t\t\t\t\t\tcontinue\n\t\t\t\t\t}\n\t\t\t\t\tset inip [get_in_connect_ip $inip $master_intf]\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"v_frmbuf_rd\"]} {\n\t\t\t\t\t\tgen_frmbuf_rd_node $inip $drv_handle $sdi_port_node\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[llength $inip]} {\n\t\t\tset sditx_in_end \"\"\n\t\t\tset sditx_remo_in_end \"\"\n\t\t\tif {[info exists end_mappings] && [dict exists $end_mappings $inip]} {\n\t\t\t\tset sditx_in_end [dict get $end_mappings $inip]\n\t\t\t\tdtg_verbose \"sditx_in_end:$sditx_in_end\"\n\t\t\t}\n\t\t\tif {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} {\n\t\t\t\tset sditx_remo_in_end [dict get $remo_mappings $inip]\n\t\t\t\tdtg_verbose \"sditx_remo_in_end:$sditx_remo_in_end\"\n\t\t\t}\n\t\t\tif {[llength $sditx_remo_in_end]} {\n\t\t\t\tset sditx_node [add_or_get_dt_node -n \"endpoint\" -l $sditx_remo_in_end -p $sdi_port_node]\n\t\t\t}\n\t\t\tif {[llength $sditx_in_end]} {\n\t\t\t\thsi::utils::add_new_dts_param \"$sditx_node\" \"remote-endpoint\" $sditx_in_end reference\n\t\t\t}\n\t\t}\n\t}\n\tif {[string match -nocase [get_property IP_NAME $ip] \"v_hdmi_tx_ss\"] || [string match -nocase [get_property IP_NAME $ip] \"v_hdmi_txss1\"]} {\n\t\tset ports_node [add_or_get_dt_node -n \"ports\" -l hdmitx_ports$drv_handle -p $node]\n\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\t\tset hdmi_port_node [add_or_get_dt_node -n \"port\" -l encoder_hdmi_port$drv_handle -u 0 -p $ports_node]\n\t\thsi::utils::add_new_dts_param \"$hdmi_port_node\" \"reg\" 0 int\n\t\tset hdmitx_in_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] \"VIDEO_IN\"]\n\t\tif {![llength $hdmitx_in_ip]} {\n\t\t\tdtg_warning \"$drv_handle pin VIDEO_IN is not connected...check your design\"\n\t\t}\n\t\tset inip \"\"\n\t\tset axis_sw_nm \"\"\n\t\tforeach inip $hdmitx_in_ip {\n\t\t\tif {[llength $inip]} {\n\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $hdmitx_in_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip]\n\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"v_frmbuf_rd\"]} {\n\t\t\t\t\t\tgen_frmbuf_rd_node $inip $drv_handle $hdmi_port_node\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"system_ila\"]} {\n\t\t\t\t\t\tcontinue\n\t\t\t\t\t}\n\t\t\t\t\t# Check if slice is connected to axis_switch(NM)\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"axis_register_slice\"]} {\n\t\t\t\t\t\tset intf \"S_AXIS\"\n\t\t\t\t\t\tset streamin_ip [get_connected_stream_ip [get_cells -hier $inip] $intf]\n\t\t\t\t\t\tif {[llength $streamin_ip]} {\n\t\t\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $streamin_ip]\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {![llength $ip_mem_handles] && [string match -nocase [get_property IP_NAME $streamin_ip] \"axis_switch\"]} {\n\t\t\t\t\t\t\tset inip \"$streamin_ip\"\n\t\t\t\t\t\t\tset axis_sw_nm \"1\"\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tif {![llength $axis_sw_nm]} {\n\t\t\t\t\t\tset inip [get_in_connect_ip $inip $master_intf]\n\t\t\t\t\t}\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"v_frmbuf_rd\"]} {\n\t\t\t\t\t\tgen_frmbuf_rd_node $inip $drv_handle $hdmi_port_node\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[llength $inip]} {\n\t\t\tset hdmitx_in_end \"\"\n\t\t\tset hdmitx_remo_in_end \"\"\n\t\t\tif {[info exists end_mappings] && [dict exists $end_mappings $inip]} {\n\t\t\t\tset hdmitx_in_end [dict get $end_mappings $inip]\n\t\t\t\tdtg_verbose \"hdmitx_in_end:$hdmitx_in_end\"\n\t\t\t}\n\t\t\tif {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} {\n\t\t\t\tset hdmitx_remo_in_end [dict get $remo_mappings $inip]\n\t\t\t\tdtg_verbose \"hdmitx_remo_in_end:$hdmitx_remo_in_end\"\n\t\t\t}\n\t\t\tif {[llength $hdmitx_remo_in_end]} {\n\t\t\t\tset hdmitx_node [add_or_get_dt_node -n \"endpoint\" -l $hdmitx_remo_in_end -p $hdmi_port_node]\n\t\t\t}\n\t\t\tif {[llength $hdmitx_in_end]} {\n\t\t\t\thsi::utils::add_new_dts_param \"$hdmitx_node\" \"remote-endpoint\" $hdmitx_in_end reference\n\t\t\t}\n\t\t\t# Add endpoints if IN IP is axis_switch and NM\n\t\t\tif {[llength $axis_sw_nm]} {\n\t\t\t\tupdate_axis_switch_endpoints $inip $hdmi_port_node $drv_handle\n\t\t\t}\n\t\t}\n\t}\n\t if {[string match -nocase [get_property IP_NAME $ip] \"v_scenechange\"]} {\n\t\tset memory_scd [get_property CONFIG.MEMORY_BASED [get_cells -hier $drv_handle]]\n\t\tif {$memory_scd == 1} {\n\t\t\t#memory scd\n\t\t\treturn\n\t\t}\n\t\tset scd_ports_node [add_or_get_dt_node -n \"scd\" -l scd_ports$drv_handle -p $node]\n\t\thsi::utils::add_new_dts_param \"$scd_ports_node\" \"#address-cells\" 1 int\n\t\thsi::utils::add_new_dts_param \"$scd_ports_node\" \"#size-cells\" 0 int\n\t\tset port_node [add_or_get_dt_node -n \"port\" -l scd_port0$drv_handle -u 0 -p $scd_ports_node]\n\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 0 int\n\n\t\tset scd_inip [get_connected_stream_ip [get_cells -hier $drv_handle] \"S_AXIS_VIDEO\"]\n\t\tif {![llength $scd_inip]} {\n\t\t\tdtg_warning \"$drv_handle pin S_AXIS_VIDEO is not connected...check your design\"\n\t\t}\n\t\tset broad_ip [get_broad_in_ip $scd_inip]\n\t\tif {[llength $broad_ip]} {\n\t\tif {[string match -nocase [get_property IP_NAME $broad_ip] \"axis_broadcaster\"]} {\n\t\t\tset scd_in_end \"\"\n\t\t\tset scd_remo_in_end \"\"\n\t\t\tif {[info exists port1_broad_end_mappings] && [dict exists $port1_broad_end_mappings $broad_ip]} {\n\t\t\t\tset scd_in_end [dict get $port1_broad_end_mappings $broad_ip]\n\t\t\t}\n\t\t\tif {[info exists broad_port1_remo_mappings] && [dict exists $broad_port1_remo_mappings $broad_ip]} {\n\t\t\t\tset scd_remo_in_end [dict get $broad_port1_remo_mappings $broad_ip]\n\t\t\t}\n\t\t\tif {[info exists port2_broad_end_mappings] && [dict exists $port2_broad_end_mappings $broad_ip]} {\n\t\t\t\tset scd_in1_end [dict get $port2_broad_end_mappings $broad_ip]\n\t\t\t}\n\t\t\tif {[info exists broad_port2_remo_mappings] && [dict exists $broad_port2_remo_mappings $broad_ip]} {\n\t\t\t\tset scd_remo_in1_end [dict get $broad_port2_remo_mappings $broad_ip]\n\t\t\t}\n\t\t\tif {[info exists port3_broad_end_mappings] && [dict exists $port3_broad_end_mappings $broad_ip]} {\n\t\t\t\tset scd_in2_end [dict get $port3_broad_end_mappings $broad_ip]\n\t\t\t}\n\t\t\tif {[info exists broad_port3_remo_mappings] && [dict exists $broad_port3_remo_mappings $broad_ip]} {\n\t\t\t\tset scd_remo_in2_end [dict get $broad_port3_remo_mappings $broad_ip]\n\t\t\t}\n\t\t\tif {[info exists port4_broad_end_mappings] && [dict exists $port4_broad_end_mappings $broad_ip]} {\n\t\t\t\tset scd_in3_end [dict get $port4_broad_end_mappings $broad_ip]\n\t\t\t}\n\t\t\tif {[info exists broad_port4_remo_mappings] && [dict exists $broad_port4_remo_mappings $broad_ip]} {\n\t\t\t\tset scd_remo_in3_end [dict get $broad_port4_remo_mappings $broad_ip]\n\t\t\t}\n\t\t\tif {[info exists scd_remo_in_end] && [regexp -nocase $drv_handle \"$scd_remo_in_end\" match]} {\n\t\t\t\tif {[llength $scd_remo_in_end]} {\n\t\t\t\t\tset scd_node [add_or_get_dt_node -n \"endpoint\" -l $scd_remo_in_end -p $port_node]\n\t\t\t\t}\n\t\t\t\tif {[llength $scd_in_end]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$scd_node\" \"remote-endpoint\" $scd_in_end reference\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[info exists scd_remo_in1_end] && [regexp -nocase $drv_handle \"$scd_remo_in1_end\" match]} {\n\t\t\t\tif {[llength $scd_remo_in1_end]} {\n\t\t\t\t\tset scd_node [add_or_get_dt_node -n \"endpoint\" -l $scd_remo_in1_end -p $port_node]\n\t\t\t\t}\n\t\t\t\tif {[llength $scd_in1_end]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$scd_node\" \"remote-endpoint\" $scd_in1_end reference\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[info exists scd_remo_in2_end] && [regexp -nocase $drv_handle \"$scd_remo_in2_end\" match]} {\n\t\t\t\tif {[llength $scd_remo_in2_end]} {\n\t\t\t\t\tset scd_node [add_or_get_dt_node -n \"endpoint\" -l $scd_remo_in2_end -p $port_node]\n\t\t\t\t}\n\t\t\t\tif {[llength $scd_in2_end]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$scd_node\" \"remote-endpoint\" $scd_in2_end reference\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[info exists scd_remo_in3_end] && [regexp -nocase $drv_handle \"$scd_remo_in3_end\" match]} {\n\t\t\t\tif {[llength $scd_remo_in3_end]} {\n\t\t\t\t\tset scd_node [add_or_get_dt_node -n \"endpoint\" -l $scd_remo_in3_end -p $port_node]\n\t\t\t\t}\n\t\t\t\tif {[llength $scd_in3_end]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$scd_node\" \"remote-endpoint\" $scd_in3_end reference\n\t\t\t\t}\n\t\t\t}\n\t\t\treturn\n\t\t}\n\t\t}\n\t\tforeach inip $scd_inip {\n\t\t\tif {[llength $inip]} {\n\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip]\n\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\t\t} else {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $inip] \"system_ila\"]} {\n\t\t\t\t\t\tcontinue\n\t\t\t\t\t}\n\t\t\t\t\tset inip [get_in_connect_ip $inip $master_intf]\n\t\t\t\t}\n\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\tset scd_in_end \"\"\n\t\t\t\t\tset scd_remo_in_end \"\"\n\t\t\t\t\tif {[info exists end_mappings] && [dict exists $end_mappings $inip]} {\n\t\t\t\t\t\tset scd_in_end [dict get $end_mappings $inip]\n\t\t\t\t\t}\n\t\t\t\t\tif {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} {\n\t\t\t\t\t\tset scd_remo_in_end [dict get $remo_mappings $inip]\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $scd_remo_in_end]} {\n\t\t\t\t\t\tset scd_node [add_or_get_dt_node -n \"endpoint\" -l $scd_remo_in_end -p $port_node]\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $scd_in_end]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$scd_node\" \"remote-endpoint\" $scd_in_end reference\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tif {[string match -nocase [get_property IP_NAME $ip] \"v_tpg\"]} {\n\t\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\tif {[string match -nocase $proctype \"ps7_cortexa9\"]} {\n\t\t\t#TBF\n\t\t\treturn\n\t\t}\n\t\tset ports_node [add_or_get_dt_node -n \"ports\" -l tpg_ports$drv_handle -p $node]\n\t\tset port0_node [add_or_get_dt_node -n \"port\" -l tpg_port0$drv_handle -u 0 -p $ports_node]\n\t\thsi::utils::add_new_dts_param \"$port0_node\" \"reg\" 0 int\n\t\thsi::utils::add_new_dts_param \"${port0_node}\" \"/* Fill the field xlnx,video-format based on user requirement */\" \"\" comment\n\t\thsi::utils::add_new_dts_param \"$port0_node\" \"xlnx,video-format\" 2 int\n\t\tset max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"$port0_node\" \"xlnx,video-width\" $max_data_width int\n\t\tset tpg_inip [get_connected_stream_ip [get_cells -hier $drv_handle] \"S_AXIS_VIDEO\"]\n if {![llength $tpg_inip]} {\n dtg_warning \"$drv_handle pin S_AXIS_VIDEO is not connected...check your design\"\n } else {\n\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $tpg_inip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\tset inip [get_in_connect_ip $tpg_inip $master_intf]\n\t\t\t#if tpg is getting input from gamma ip then setting inip\n\t\t\t#to gamma as the get_in_connect_ip is traversing through\n\t\t\t#first input and which might not be correct. For each ip we should\n\t\t\t#have immediate input. As we are not sure about the history\n\t\t\t#handling for only gamma ip for now.\n\t\t\tif {[string match -nocase [get_property IP_NAME $tpg_inip] \"v_gamma_lut\"]} {\n\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $tpg_inip]\n\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\tset inip $tpg_inip\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[llength $inip]} {\n\t\t\t\tset tpg_in_end \"\"\n\t\t\t\tset tpg_remo_in_end \"\"\n\t\t\t\tif {[info exists end_mappings] && [dict exists $end_mappings $inip]} {\n\t\t\t\t\tset tpg_in_end [dict get $end_mappings $inip]\n\t\t\t\t}\n\t\t\t\tif {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} {\n\t\t\t\t\tset tpg_remo_in_end [dict get $remo_mappings $inip]\n\t\t\t\t}\n\t\t\t\tif {[llength $tpg_remo_in_end]} {\n\t\t\t\t\tset tpg_node [add_or_get_dt_node -n \"endpoint\" -l $tpg_remo_in_end -p $port0_node]\n\t\t\t\t}\n\t\t\t\tif {[llength $tpg_in_end]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$tpg_node\" \"remote-endpoint\" $tpg_in_end reference\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tset ips [get_cells -hier -filter {IP_NAME == \"axis_switch\"}]\n\tforeach ip $ips {\n\t\tif {[llength $ip]} {\n\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip]\n\t\t\tif {![llength $ip_mem_handles]} {\n\t\t\tset axis_ip [get_property IP_NAME $ip]\n\t\t\tset default_dts [set_drv_def_dts $ip]\n\t\t\tset unit_addr [get_baseaddr ${ip} no_prefix]\n\t\t\tif { ![string equal $unit_addr \"-1\"] } {\n\t\t\t\tbreak\n\t\t\t}\n\t\t\tset label $ip\n\t\t\tset bus_node [add_or_get_bus_node $ip $default_dts]\n\t\t\tset dev_type [get_property IP_NAME [get_cell -hier [get_cells -hier $ip]]]\n\t\t\tif {[llength $axis_ip]} {\n\t\t\t\tset intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\tset inip [get_in_connect_ip $ip $intf]\n\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\tset inipname [get_property IP_NAME $inip]\n\t\t\t\t\tset valid_mmip_list \"mipi_csi2_rx_subsystem v_tpg v_hdmi_rx_ss v_smpte_uhdsdi_rx_ss v_smpte_uhdsdi_tx_ss v_demosaic v_gamma_lut v_proc_ss v_frmbuf_rd v_frmbuf_wr v_hdmi_tx_ss v_hdmi_txss1 v_uhdsdi_audio audio_formatter i2s_receiver i2s_transmitter mipi_dsi_tx_subsystem v_mix v_multi_scaler v_scenechange\"\n\t\t\t\t\tif {[lsearch -nocase $valid_mmip_list $inipname] >= 0} {\n\t\t\t\t\t\tset rt_node [add_or_get_dt_node -n ${dev_type} -l ${label} -u 0 -d ${default_dts} -p $bus_node -auto_ref_parent]\n\t\t\t\t\t\tset ports_node [add_or_get_dt_node -n \"ports\" -l axis_switch_ports$ip -p $rt_node]\n\t\t\t\t\t\tgen_axis_switch_clk_property $ip $default_dts $rt_node\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\t\t\t\t\t\tset port_node [add_or_get_dt_node -n \"port\" -l axis_switch_port0$ip -u 0 -p $ports_node]\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 0 int\n\t\t\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\t\t\tset axis_switch_in_end \"\"\n\t\t\t\t\t\t\tset axis_switch_remo_in_end \"\"\n\t\t\t\t\t\t\tif {[info exists end_mappings] && [dict exists $end_mappings $inip]} {\n\t\t\t\t\t\t\t\tset axis_switch_in_end [dict get $end_mappings $inip]\n\t\t\t\t\t\t\t\tdtg_verbose \"drv:$ip inend:$axis_switch_in_end\"\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tif {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} {\n\t\t\t\t\t\t\t\tset axis_switch_remo_in_end [dict get $remo_mappings $inip]\n\t\t\t\t\t\t\t\tdtg_verbose \"drv:$ip inremoend:$axis_switch_remo_in_end\"\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tif {[llength $axis_switch_remo_in_end]} {\n\t\t\t\t\t\t\t\tset axisinnode [add_or_get_dt_node -n \"endpoint\" -l $axis_switch_remo_in_end -p $port_node]\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tif {[llength $axis_switch_in_end]} {\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$axisinnode\" \"remote-endpoint\" $axis_switch_in_end reference\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\t}\n\tset ip [get_cells -hier $drv_handle]\n\tif {[string match -nocase [get_property IP_NAME $ip] \"axis_switch\"]} {\n\t\tset axis_ip [get_property IP_NAME $ip]\n\t\tset default_dts [set_drv_def_dts $ip]\n\t\tset unit_addr [get_baseaddr ${ip} no_prefix]\n\t\tset bus_node [add_or_get_bus_node $ip $default_dts]\n\t\tset dev_type [get_property IP_NAME [get_cell -hier [get_cells -hier $ip]]]\n\t\tset intf \"S00_AXIS\"\n\t\tset inips [get_axis_switch_in_connect_ip $ip $intf]\n\t\tforeach inip $inips {\n\t\t\tif {[llength $inip]} {\n\t\t\t\tset inipname [get_property IP_NAME $inip]\n\t\t\t\tset valid_mmip_list \"mipi_csi2_rx_subsystem v_tpg v_hdmi_rx_ss v_smpte_uhdsdi_rx_ss v_smpte_uhdsdi_tx_ss v_demosaic v_gamma_lut v_proc_ss v_frmbuf_rd v_frmbuf_wr v_hdmi_tx_ss v_hdmi_txss1 v_uhdsdi_audio audio_formatter i2s_receiver i2s_transmitter mipi_dsi_tx_subsystem v_mix v_multi_scaler v_scenechange\"\n\t\t\t\t\tif {[lsearch -nocase $valid_mmip_list $inipname] >= 0} {\n\t\t\t\t\t\tset ports_node [add_or_get_dt_node -n \"ports\" -l axis_switch_ports$drv_handle -p $node]\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\t\t\t\t\t\tset port_node [add_or_get_dt_node -n \"port\" -l axis_switch_port0$ip -u 0 -p $ports_node]\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 0 int\n\t\t\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\t\t\tset axis_switch_in_end \"\"\n\t\t\t\t\t\t\tset axis_switch_remo_in_end \"\"\n\t\t\t\t\t\t\tif {[info exists axis_switch_in_end_mappings] && [dict exists $axis_switch_in_end_mappings $inip]} {\n\t\t\t\t\t\t\t\tset axis_switch_in_end [dict get $axis_switch_in_end_mappings $inip]\n\t\t\t\t\t\t\t\tdtg_verbose \"drv:$ip inend:$axis_switch_in_end\"\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tif {[info exists axis_switch_in_remo_mappings] && [dict exists $axis_switch_in_remo_mappings $inip]} {\n\t\t\t\t\t\t\t\tset axis_switch_remo_in_end [dict get $axis_switch_in_remo_mappings $inip]\n\t\t\t\t\t\t\t\tdtg_verbose \"drv:$ip inremoend:$axis_switch_remo_in_end\"\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tif {[llength $axis_switch_remo_in_end]} {\n\t\t\t\t\t\t\t\tset axisinnode [add_or_get_dt_node -n \"endpoint\" -l $axis_switch_remo_in_end -p $port_node]\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tif {[llength $axis_switch_in_end]} {\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$axisinnode\" \"remote-endpoint\" $axis_switch_in_end reference\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\tset ips [get_cells -hier -filter {IP_NAME == \"axis_broadcaster\"}]\n\tforeach ip $ips {\n if {[llength $ip]} {\n set axis_broad_ip [get_property IP_NAME $ip]\n set default_dts [set_drv_def_dts $ip]\n\t\t\t# broad_ip means broadcaster input ip is connected to another ip\n\t\t\tset broad_ip [get_broad_in_ip $ip]\n\t\t\tset validate_ip 1\n\t\t\tif {[llength $broad_ip]} {\n\t\t\t\tif { [get_property IP_NAME $broad_ip] in { \"v_proc_ss\" \"ISPPipeline_accel\" } } {\n\t\t\t\t# set validate ip is 0 when axis_broadcaster input ip is\n\t\t\t\t# connect to v_proc_ss or ISPPipeline_accel to skip the below checks\n\t\t\t\t\tset validate_ip 0\n\t\t\t\t}\n\t\t\t}\n\t\t\t# add unit_addr and ip_type check when axis_broadcaster input ip is connected with other ips\n\t\t\tif {$validate_ip} {\n\t\t\t\tset unit_addr [get_baseaddr ${ip} no_prefix]\n\t\t\t\tif { ![string equal $unit_addr \"-1\"] } {\n\t\t\t\t\tbreak\n\t\t\t\t}\n\t\t\t\tset ip_type [get_property IP_TYPE $ip]\n\t\t\t\tif {[string match -nocase $ip_type \"BUS\"]} {\n\t\t\t\t\tbreak\n\t\t\t\t}\n\t\t\t}\n set label $ip\n set bus_node [add_or_get_bus_node $ip $default_dts]\n set dev_type [get_property IP_NAME [get_cell -hier [get_cells -hier $ip]]]\n\t\t\tset rt_node [add_or_get_dt_node -n \"axis_broadcaster$ip\" -l ${label} -u 0 -d ${default_dts} -p $bus_node -auto_ref_parent]\n\t\t\tif {[llength $axis_broad_ip]} {\n\t\t\t\tset intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\tset inip [get_in_connect_ip $ip $intf]\n\t\t\t\tif {[llength $broad]} {\n\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\tset inipname [get_property IP_NAME $inip]\n\t\t\t\t\tset valid_mmip_list \"mipi_csi2_rx_subsystem v_tpg v_hdmi_rx_ss v_smpte_uhdsdi_rx_ss v_smpte_uhdsdi_tx_ss v_demosaic v_gamma_lut v_proc_ss v_frmbuf_rd v_frmbuf_wr v_hdmi_tx_ss v_hdmi_txss1 v_uhdsdi_audio audio_formatter i2s_receiver i2s_transmitter mipi_dsi_tx_subsystem v_mix v_multi_scaler v_scenechange ISPPipeline_accel\"\n\t\t\t\tif {[lsearch -nocase $valid_mmip_list $inipname] >= 0} {\n\t\t\t\tset ports_node [add_or_get_dt_node -n \"ports\" -l axis_broadcaster_ports$ip -p $rt_node]\n\t\t\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\t\t\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\t\t\t\tset port_node [add_or_get_dt_node -n \"port\" -l axis_broad_port0$ip -u 0 -p $ports_node]\n\t\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 0 int\n\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\tset axis_broad_in_end \"\"\n\t\t\t\t\tset axis_broad_remo_in_end \"\"\n\t\t\t\t\tif {[info exists end_mappings] && [dict exists $end_mappings $inip]} {\n\t\t\t\t\t\tset axis_broad_in_end [dict get $end_mappings $inip]\n\t\t\t\t\t\tdtg_verbose \"drv:$ip inend:$axis_broad_in_end\"\n\t\t\t\t\t}\n\t\t\t\t\tif {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} {\n\t\t\t\t\t\tset axis_broad_remo_in_end [dict get $remo_mappings $inip]\n\t\t\t\t\t\tdtg_verbose \"drv:$ip inremoend:$axis_broad_remo_in_end\"\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $axis_broad_remo_in_end]} {\n\t\t\t\t\t\tset axisinnode [add_or_get_dt_node -n \"endpoint\" -l $axis_broad_remo_in_end -p $port_node]\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $axis_broad_in_end]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$axisinnode\" \"remote-endpoint\" $axis_broad_in_end reference\n\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc get_axis_switch_in_connect_ip {ip intfpins} {\n\tglobal connectip \"\"\n\tforeach intf $intfpins {\n\t\tset connectip [get_connected_stream_ip [get_cells -hier $ip] $intf]\n\t\tforeach cip $connectip {\n\t\t\tif {[llength $cip]} {\n\t\t\t\tset ipname [get_property IP_NAME $cip]\n\t\t\t\t#puts \"ipname:$ipname\"\n\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $cip]\n\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\tbreak\n\t\t\t\t} else {\n\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $cip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\tget_axis_switch_in_connect_ip $cip $master_intf\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\treturn $connectip\n}\n\nproc gen_remoteendpoint {drv_handle value} {\n\tglobal remo_mappings\n\tdict append remo_mappings $drv_handle $value\n\tset val [dict get $remo_mappings $drv_handle]\n}\n\nproc gen_axis_port1_remoteendpoint {drv_handle value} {\n\tglobal axis_port1_remo_mappings\n\tdict append axis_port1_remo_mappings $drv_handle $value\n\tset val [dict get $axis_port1_remo_mappings $drv_handle]\n}\n\nproc gen_axis_port2_remoteendpoint {drv_handle value} {\n\tglobal axis_port2_remo_mappings\n\tdict append axis_port2_remo_mappings $drv_handle $value\n\tset val [dict get $axis_port2_remo_mappings $drv_handle]\n}\n\nproc gen_axis_port3_remoteendpoint {drv_handle value} {\n\tglobal axis_port3_remo_mappings\n\tdict append axis_port3_remo_mappings $drv_handle $value\n\tset val [dict get $axis_port3_remo_mappings $drv_handle]\n}\n\nproc gen_axis_port4_remoteendpoint {drv_handle value} {\n\tglobal axis_port4_remo_mappings\n\tdict append axis_port4_remo_mappings $drv_handle $value\n\tset val [dict get $axis_port4_remo_mappings $drv_handle]\n}\n\nproc gen_broad_remoteendpoint_port1 {drv_handle value} {\n global broad_port1_remo_mappings\n dict append broad_port1_remo_mappings $drv_handle $value\n set val [dict get $broad_port1_remo_mappings $drv_handle]\n}\n\nproc gen_broad_remoteendpoint_port2 {drv_handle value} {\n global broad_port2_remo_mappings\n dict append broad_port2_remo_mappings $drv_handle $value\n set val [dict get $broad_port2_remo_mappings $drv_handle]\n}\n\nproc gen_broad_remoteendpoint_port3 {drv_handle value} {\n global broad_port3_remo_mappings\n dict append broad_port3_remo_mappings $drv_handle $value\n set val [dict get $broad_port3_remo_mappings $drv_handle]\n}\n\nproc gen_broad_remoteendpoint_port4 {drv_handle value} {\n global broad_port4_remo_mappings\n dict append broad_port4_remo_mappings $drv_handle $value\n set val [dict get $broad_port4_remo_mappings $drv_handle]\n}\n\nproc gen_broad_remoteendpoint_port5 {drv_handle value} {\n global broad_port5_remo_mappings\n dict append broad_port5_remo_mappings $drv_handle $value\n set val [dict get $broad_port5_remo_mappings $drv_handle]\n}\n\nproc gen_broad_remoteendpoint_port6 {drv_handle value} {\n global broad_port6_remo_mappings\n dict append broad_port6_remo_mappings $drv_handle $value\n set val [dict get $broad_port6_remo_mappings $drv_handle]\n}\n\nproc gen_broad_remoteendpoint_port7 {drv_handle value} {\n global broad_port7_remo_mappings\n dict append broad_port7_remo_mappings $drv_handle $value\n set val [dict get $broad_port7_remo_mappings $drv_handle]\n}\n\nproc gen_frmbuf_rd_node {ip drv_handle sdi_port_node} {\n\tset frmbuf_rd_node [add_or_get_dt_node -n \"endpoint\" -l encoder$drv_handle -p $sdi_port_node]\n\thsi::utils::add_new_dts_param \"$frmbuf_rd_node\" \"remote-endpoint\" $ip$drv_handle reference\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n\tset pl_display [add_or_get_dt_node -n \"drm-pl-disp-drv$drv_handle\" -l \"v_pl_disp$drv_handle\" -p $bus_node]\n\thsi::utils::add_new_dts_param $pl_display \"compatible\" \"xlnx,pl-disp\" string\n\thsi::utils::add_new_dts_param $pl_display \"dmas\" \"$ip 0\" reference\n\thsi::utils::add_new_dts_param $pl_display \"dma-names\" \"dma0\" string\n\thsi::utils::add_new_dts_param \"${pl_display}\" \"/* Fill the field xlnx,vformat based on user requirement */\" \"\" comment\n\thsi::utils::add_new_dts_param $pl_display \"xlnx,vformat\" \"YUYV\" string\n\tset pl_display_port_node [add_or_get_dt_node -n \"port\" -l pl_display_port$drv_handle -u 0 -p $pl_display]\n\thsi::utils::add_new_dts_param \"$pl_display_port_node\" \"reg\" 0 int\n\tset pl_disp_crtc_node [add_or_get_dt_node -n \"endpoint\" -l $ip$drv_handle -p $pl_display_port_node]\n\thsi::utils::add_new_dts_param \"$pl_disp_crtc_node\" \"remote-endpoint\" encoder$drv_handle reference\n}\n\nproc gen_broadcaster {ip} {\n\tdtg_verbose \"+++++++++gen_broadcaster:$ip\"\n\tset count 0\n\tset inputip \"\"\n\tset outip \"\"\n\tset connectip \"\"\n\tset compatible [get_comp_str $ip]\n\tset intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\tset inip [get_connected_stream_ip [get_cells -hier $ip] $intf]\n\tset inip [get_in_connect_ip $ip $intf]\n\tset default_dts [set_drv_def_dts $ip]\n\tset bus_node [add_or_get_bus_node $ip $default_dts]\n\tset broad_node [add_or_get_dt_node -n \"axis_broadcaster$ip\" -l $ip -u 0 -p $bus_node]\n\tset ports_node [add_or_get_dt_node -n \"ports\" -l axis_broadcaster_ports$ip -p $broad_node]\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\thsi::utils::add_new_dts_param \"$broad_node\" \"compatible\" \"$compatible\" string\n\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\tset broad 10\n\thsi::utils::set_os_parameter_value \"broad\" $broad\n\tforeach intf $master_intf {\n\t\tset connectip [get_connected_stream_ip [get_cells -hier $ip] $intf]\n\t\tif {[llength $connectip]} {\n\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip]\n\t\t\tif {![llength $ip_mem_handles]} {\n\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\t\t\tset connectip [get_connected_stream_ip [get_cells -hier $connectip] $master_intf]\n\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip]\n\t\t\t\t\tif {![llength $ip_mem_handles]} {\n\t\t\t\t\t\tset master2_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\t\t\t\t\tset connectip [get_connected_stream_ip [get_cells -hier $connectip] $master2_intf]\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip]\n\t\t\t\t\t\tif {![llength $ip_mem_handles]} {\n\t\t\t\t\t\t\tset master3_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\t\t\t\t\t\tset connectip [get_connected_stream_ip [get_cells -hier $connectip] $master3_intf]\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tincr count\n\t\t\tset port_node [add_or_get_dt_node -n \"port\" -l axis_broad_port$count$ip -u $count -p $ports_node]\n\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" $count int\n\t\t\tset axis_node [add_or_get_dt_node -n \"endpoint\" -l axis_broad_out$count$ip -p $port_node]\n\t\t\thsi::utils::add_new_dts_param \"$axis_node\" \"remote-endpoint\" $connectip$ip reference\n\t\t\tset addbroadip \"1\"\n\t\t\tif {[get_property IP_NAME $connectip] in { \"v_scenechange\" \"v_frmbuf_wr\" }} {\n\t\t\t\tset addbroadip \"\"\n\t\t\t}\n\t\t\tif {[llength $addbroadip]} {\n\t\t\t\tgen_broad_endpoint_port$count $ip \"axis_broad_out$count$ip\"\n\t\t\t\tgen_broad_remoteendpoint_port$count $ip $connectip$ip\n\t\t\t}\n\t\t\tappend inputip \" \" $connectip\n\t\t\tappend outip \" \" $connectip$ip\n\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"v_frmbuf_wr\"]} {\n\t\t\t\tgen_broad_frmbuf_wr_node $inputip $outip $ip $count\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc gen_axis_switch {ip} {\n\tset compatible [get_comp_str $ip]\n\tdtg_verbose \"+++++++++gen_axis_switch:$ip\"\n\tset routing_mode [get_property CONFIG.ROUTING_MODE [get_cells -hier $ip]]\n\tif {$routing_mode == 1} {\n\t\t# Routing_mode is 1 means it is a memory mapped\n\t\treturn\n\t}\n\tset intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\tset inip [get_connected_stream_ip [get_cells -hier $ip] $intf]\n\tset intf1 [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\tset iip [get_connected_stream_ip [get_cells -hier $inip] $intf1]\n\tset inip [get_in_connect_ip $ip $intf]\n\tset default_dts [set_drv_def_dts $ip]\n\tset bus_node [add_or_get_bus_node $ip $default_dts]\n\tset switch_node [add_or_get_dt_node -n \"axis_switch_$ip\" -l $ip -u 0 -p $bus_node]\n\tset ports_node [add_or_get_dt_node -n \"ports\" -l axis_switch_ports$ip -p $switch_node]\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\thsi::utils::add_new_dts_param \"$switch_node\" \"xlnx,routing-mode\" $routing_mode int\n\tset num_si [get_property CONFIG.NUM_SI [get_cells -hier $ip]]\n\thsi::utils::add_new_dts_param \"$switch_node\" \"xlnx,num-si-slots\" $num_si int\n\tset num_mi [get_property CONFIG.NUM_MI [get_cells -hier $ip]]\n\thsi::utils::add_new_dts_param \"$switch_node\" \"xlnx,num-mi-slots\" $num_mi int\n\thsi::utils::add_new_dts_param \"$switch_node\" \"compatible\" \"$compatible\" string\n\tset count 0\n\tforeach intf $master_intf {\n\t\tset connectip [get_connected_stream_ip [get_cells -hier $ip] $intf]\n\t\t#Get next out IP if slice connected\n\t\tif {[llength $connectip] && \\\n\t\t\t[string match -nocase [get_property IP_NAME $connectip] \"axis_register_slice\"]} {\n\t\t\tset intf \"M_AXIS\"\n\t\t\tset connectip [get_connected_stream_ip [get_cells -hier $connectip] \"$intf\"]\n\t\t}\n\t\tset len [llength $connectip]\n\t\tif {$len > 1} {\n\t\t\tfor {set i 0 } {$i < $len} {incr i} {\n\t\t\t\tset temp_ip [lindex $connectip $i]\n\t\t\t\tif {[regexp -nocase \"ila\" $temp_ip match]} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\tset connectip \"$temp_ip\"\n\t\t\t}\n\t\t}\n\t\tif {[llength $connectip]} {\n\t\t\tincr count\n\t\t}\n\t\tif {$count == 1} {\n\t\t\tset port_node [add_or_get_dt_node -n \"port\" -l axis_switch_port1$ip -u 1 -p $ports_node]\n\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 1 int\n\t\t\tset axis_node [add_or_get_dt_node -n \"endpoint\" -l axis_switch_out1$ip -p $port_node]\n\t\t\tgen_axis_port1_endpoint $ip \"axis_switch_out1$ip\"\n\t\t\thsi::utils::add_new_dts_param \"$axis_node\" \"remote-endpoint\" $connectip$ip reference\n\t\t\tgen_axis_port1_remoteendpoint $ip $connectip$ip\n\t\t}\n\t\tif {$count == 2} {\n\t\t\tset port_node [add_or_get_dt_node -n \"port\" -l axis_switch_port2$ip -u 2 -p $ports_node]\n\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 2 int\n\t\t\tset axis_node [add_or_get_dt_node -n \"endpoint\" -l axis_switch_out2$ip -p $port_node]\n\t\t\tgen_axis_port2_endpoint $ip \"axis_switch_out2$ip\"\n\t\t\thsi::utils::add_new_dts_param \"$axis_node\" \"remote-endpoint\" $connectip$ip reference\n\t\t\tgen_axis_port2_remoteendpoint $ip $connectip$ip\n\t\t}\n\t\tif {$count == 3} {\n\t\t\tset port_node [add_or_get_dt_node -n \"port\" -l axis_switch_port3$ip -u 3 -p $ports_node]\n\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 3 int\n\t\t\tset axis_node [add_or_get_dt_node -n \"endpoint\" -l axis_switch_out3$ip -p $port_node]\n\t\t\tgen_axis_port3_endpoint $ip \"axis_switch_out3$ip\"\n\t\t\thsi::utils::add_new_dts_param \"$axis_node\" \"remote-endpoint\" $connectip$ip reference\n\t\t\tgen_axis_port3_remoteendpoint $ip $connectip$ip\n\t\t}\n\t\tif {$count == 4} {\n\t\t\tset port_node [add_or_get_dt_node -n \"port\" -l axis_switch_port4$ip -u 4 -p $ports_node]\n\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 4 int\n\t\t\tset axis_node [add_or_get_dt_node -n \"endpoint\" -l axis_switch_out4$ip -p $port_node]\n\t\t\tgen_axis_port4_endpoint $ip \"axis_switch_out4$ip\"\n\t\t\thsi::utils::add_new_dts_param \"$axis_node\" \"remote-endpoint\" $connectip$ip reference\n\t\t\tgen_axis_port4_remoteendpoint $ip $connectip$ip\n\t\t}\n\t}\n}\n\nproc gen_broad_frmbuf_wr_node {inputip outip drv_handle count} {\n set dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tset dts_file [current_dt_tree]\n\tset bus_node [add_or_get_bus_node $drv_handle $dts_file]\n\tset vcap [add_or_get_dt_node -n \"vcapaxis_broad_out1$drv_handle\" -p $bus_node]\n hsi::utils::add_new_dts_param $vcap \"compatible\" \"xlnx,video\" string\n\tset inputip [split $inputip \" \"]\n\tset j 0\n\tforeach ip $inputip {\n\t\tif {[llength $ip]} {\n\t\t\tif {$j < $count} {\n\t\t\t\tappend dmasip \"<&$ip 0>,\" \" \"\n\t\t\t}\n\t\t}\n\t\tincr j\n\t}\n\tappend dmasip \"<&$ip 0>\"\n hsi::utils::add_new_dts_param $vcap \"dmas\" \"$dmasip\" string\n\tset prt \"\"\n\tfor {set i 0} {$i < $count} {incr i} {\n\t\tappend prt \" \" \"port$i\"\n\t}\n hsi::utils::add_new_dts_param $vcap \"dma-names\" $prt stringlist\n set vcap_ports_node [add_or_get_dt_node -n \"ports\" -l \"vcap_portsaxis_broad_out1$drv_handle\" -p $vcap]\n hsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#address-cells\" 1 int\n hsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#size-cells\" 0 int\n\tset outip [split $outip \" \"]\n\tset b 0\n\tfor {set a 1} {$a <= $count} {incr a} {\n\t\tset vcap_port_node [add_or_get_dt_node -n \"port\" -l \"vcap_portaxis_broad_out$a$drv_handle\" -u \"$b\" -p \"$vcap_ports_node\"]\n\t\thsi::utils::add_new_dts_param \"$vcap_port_node\" \"reg\" $b int\n\t\thsi::utils::add_new_dts_param \"$vcap_port_node\" \"direction\" input string\n\t\tset vcap_in_node [add_or_get_dt_node -n \"endpoint\" -l [lindex $outip $a] -p \"$vcap_port_node\"]\n\t\thsi::utils::add_new_dts_param \"$vcap_in_node\" \"remote-endpoint\" axis_broad_out$a$drv_handle reference\n\t\tincr b\n\t}\n}\n\nproc get_connect_ip {ip intfpins} {\n dtg_verbose \"get_con_ip:$ip pins:$intfpins\"\n\tif {[llength $intfpins]== 0} {\n\t\treturn\n\t}\n\tif {[llength $ip]== 0} {\n\t\treturn\n\t}\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $ip]] \"axis_broadcaster\"]} {\n\t\tgen_broadcaster $ip\n\t\treturn\n\t}\n\tglobal connectip \"\"\n\tforeach intf $intfpins {\n\t\tset connectip [get_connected_stream_ip [get_cells -hier $ip] $intf]\n\t\tif {[llength $connectip]} {\n\t\t\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $connectip]] \"axis_broadcaster\"]} {\n\t\t\t\tgen_broadcaster $connectip\n\t\t\t\tbreak\n\t\t\t}\n\t\t\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $connectip]] \"axis_switch\"]} {\n\t\t\t\tgen_axis_switch $connectip\n\t\t\t\tbreak\n\t\t\t}\n\t\t}\n\t\tset len [llength $connectip]\n\t\tif {$len > 1} {\n\t\t\tfor {set i 0 } {$i < $len} {incr i} {\n\t\t\t\tset ip [lindex $connectip $i]\n\t\t\t\tif {[regexp -nocase \"ila\" $ip match]} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\tset connectip \"$ip\"\n\t\t\t}\n\t\t}\n\t\tif {[llength $connectip]} {\n\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip]\n\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\tbreak\n\t\t\t} else {\n\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\t\t\tget_connect_ip $connectip $master_intf\n\t\t\t}\n\t\t}\n\t}\n\treturn $connectip\n}\n\nproc get_in_connect_ip {ip intfpins} {\n dtg_verbose \"get_in_con_ip:$ip pins:$intfpins\"\n\tif {[llength $intfpins]== 0} {\n\t\treturn\n\t}\n\tif {[llength $ip]== 0} {\n\t\treturn\n\t}\n\tglobal connectip \"\"\n\tforeach intf $intfpins {\n\t\t\tset connectip [get_connected_stream_ip [get_cells -hier $ip] $intf]\n\t\t\tif {[llength $connectip]} {\n\t\t\tset extip [get_property IP_NAME $connectip]\n\t\t\tif {[string match -nocase $extip \"dfe_glitch_protect\"] || [string match -nocase $extip \"axi_interconnect\"] || [string match -nocase $extip \"axi_crossbar\"]} {\n\t\t\t\treturn\n\t\t\t}\n\t\t\t}\n\t\t\tset len [llength $connectip]\n\t\t\tif {$len > 1} {\n\t\t\t\tfor {set i 0 } {$i < $len} {incr i} {\n\t\t\t\t\tset ip [lindex $connectip $i]\n\t\t\t\t\tif {[regexp -nocase \"ila\" $ip match]} {\n\t\t\t\t\t\tcontinue\n\t\t\t\t\t}\n\t\t\t\t\tset connectip \"$ip\"\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[llength $connectip]} {\n\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip]\n\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\t\tbreak\n\t\t\t\t} else {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"system_ila\"]} {\n\t\t\t\t\t\t\tcontinue\n\t\t\t\t\t}\n\t\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\t\tget_in_connect_ip $connectip $master_intf\n\t\t\t\t}\n\t\t\t}\n\t}\n\treturn $connectip\n}\n\nproc get_broad_in_ip {ip} {\n\tdtg_verbose \"get_braod_in_ip:$ip\"\n\tif {[llength $ip]== 0} {\n\t\treturn\n\t}\n\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\tset connectip \"\"\n\tforeach intf $master_intf {\n\t\tset connect [get_connected_stream_ip [get_cells -hier $ip] $intf]\n\t\tforeach connectip $connect {\n\t\t\tif {[llength $connectip]} {\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"axis_broadcaster\"]} {\n\t\t\t\t\treturn $connectip\n\t\t\t\t}\n\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip]\n\t\t\t\tif {![llength $ip_mem_handles]} {\n\t\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\t\tforeach intf $master_intf {\n\t\t\t\t\t\tset connectip [get_connected_stream_ip [get_cells -hier $connectip] $intf]\n\t\t\t\t\t\tset len [llength $connectip]\n\t\t\t\t\t\tif {$len > 1} {\n\t\t\t\t\t\t\tfor {set i 0 } {$i < $len} {incr i} {\n\t\t\t\t\t\t\tset ip [lindex $connectip $i]\n\t\t\t\t\t\t\tif {[regexp -nocase \"ila\" $ip match]} {\n\t\t\t\t\t\t\t\tcontinue\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tset connectip \"$ip\"\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tforeach connect $connectip {\n\t\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"axis_broadcaster\"]} {\n\t\t\t\t\t\t\t\treturn $connectip\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip]\n\t\t\t\t\t\tif {![llength $ip_mem_handles]} {\n\t\t\t\t\t\t\tset master2_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\t\t\t\tforeach intf $master2_intf {\n\t\t\t\t\t\t\t\tset connectip [get_connected_stream_ip [get_cells -hier $connectip] $intf]\n\t\t\t\t\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"axis_broadcaster\"]} {\n\t\t\t\t\t\t\t\t\t\treturn $connectip\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip]\n\t\t\t\t\t\t\tif {![llength $ip_mem_handles]} {\n\t\t\t\t\t\t\t\tset master3_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\t\t\t\t\tset connectip [get_connected_stream_ip [get_cells -hier $connectip] $master3_intf]\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\treturn $connectip\n}\n\nproc get_connected_stream_ip { ip_name intf_name } {\n set ip [::hsi::get_cells -hier $ip_name]\n if { [llength $ip] == 0 } {\n return \"\"\n }\n set intf [::hsi::get_intf_pins -of_objects $ip \"$intf_name\"]\n if { [llength $intf] == 0 } {\n return \"\"\n }\n set intf_type [common::get_property TYPE $intf]\n\n set intf_net [::hsi::get_intf_nets -of_objects $intf]\n if { [llength $intf_net] == 0 } {\n return \"\"\n }\n set connected_intf_pins [::hsi::utils::get_other_intf_pin $intf_net $intf]\n set connected_intf_pin [::hsi::utils::get_intf_pin_oftype $connected_intf_pins $intf_type 0]\n\n if { [llength $connected_intf_pin] } {\n set connected_ip [::hsi::get_cells -of_objects $connected_intf_pin]\n return $connected_ip\n }\n return \"\"\n}\n\nproc gen_dfx_reg_property {drv_handle dfx_node} {\n\tset ip_name [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tset reg \"\"\n\tset slave [get_cells -hier ${drv_handle}]\n\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $slave]\n\tforeach mem_handle ${ip_mem_handles} {\n\t\tset base [string tolower [get_property BASE_VALUE $mem_handle]]\n\t\tset high [string tolower [get_property HIGH_VALUE $mem_handle]]\n\t\tset size [format 0x%x [expr {${high} - ${base} + 1}]]\n\t\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\tif {[string_is_empty $reg]} {\n\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\t# check if base address is 64bit and split it as MSB and LSB\n\t\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$base\" match]} {\n\t\t\t\t\tset temp $base\n\t\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\t\tset len [string length $temp]\n\t\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\t\tset high_base \"0x[string range $temp $rem $len]\"\n\t\t\t\t\tset low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\t\tset low_base [format 0x%08x $low_base]\n\t\t\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$size\" match]} {\n\t\t\t\t\t\tset temp $size\n\t\t\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\t\t\tset len [string length $temp]\n\t\t\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\t\t\tset high_size \"0x[string range $temp $rem $len]\"\n\t\t\t\t\t\tset low_size \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\t\t\tset low_size [format 0x%08x $low_size]\n\t\t\t\t\t\tset reg \"$low_base $high_base $low_size $high_size\"\n\t\t\t\t\t} else {\n\t\t\t\t\t\tset reg \"$low_base $high_base 0x0 $size\"\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tset reg \"0x0 $base 0x0 $size\"\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tset reg \"$base $size\"\n\t\t\t}\n\t\t} else {\n\t\t\tif {[string match -nocase $proctype \"ps7_cortexa9\"] || [string match -nocase $proctype \"microblaze\"]} {\n\t\t\t\tset index [check_base $reg $base $size]\n\t\t\t\tif {$index == \"true\"} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\t\tset index [check_64_base $reg $base $size]\n\t\t\t\tif {$index == \"true\"} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t}\n\t\t\t# ensure no duplication\n\t\t\tif {![regexp \".*${reg}.*\" \"$base $size\" matched]} {\n\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\t\t\tset base1 \"0x0 $base\"\n\t\t\t\t\tset size1 \"0x0 $size\"\n\t\t\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$base\" match]} {\n\t\t\t\t\t\tset temp $base\n\t\t\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\t\t\tset len [string length $temp]\n\t\t\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\t\t\tset high_base \"0x[string range $temp $rem $len]\"\n\t\t\t\t\t\tset low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\t\t\tset low_base [format 0x%08x $low_base]\n\t\t\t\t\t\tset base1 \"$low_base $high_base\"\n\t\t\t\t\t}\n\t\t\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$size\" match]} {\n\t\t\t\t\t\tset temp $size\n\t\t\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\t\t\tset len [string length $temp]\n\t\t\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\t\t\tset high_size \"0x[string range $temp $rem $len]\"\n\t\t\t\t\t\tset low_size \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\t\t\tset low_size [format 0x%08x $low_size]\n\t\t\t\t\t\tset size1 \"$low_size $high_size\"\n\t\t\t\t\t}\n\t\t\t\t\tset reg \"$reg $base1 $size1\"\n\t\t\t\t} else {\n\t\t\t\t\tset reg \"$reg $base $size\"\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\thsi::utils::add_new_dts_param \"$dfx_node\" \"reg\" \"$reg\" intlist\n}\n\nproc gen_dfx_clk_property {drv_handle dts_file child_node dfx_node} {\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tif {[is_pl_ip $drv_handle] && $remove_pl} {\n\t\treturn 0\n\t}\n\tset mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n\tset valid_mainline_kernel_list \"v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4\"\n\tif {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } {\n\t\treturn 0\n\t}\n\tset clocks \"\"\n\tset axi 0\n\tset is_clk_wiz 0\n\tset is_pl_clk 0\n\tset updat \"\"\n\tglobal bus_clk_list\n\tset clocknames \"\"\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tif {[string match -nocase $proctype \"microblaze\"]} {\n\t\treturn\n\t}\n\tset clk_pins [get_pins -of_objects [get_cells -hier $drv_handle] -filter {TYPE==clk&&DIRECTION==I}]\n\tset ip [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tforeach clk $clk_pins {\n\t\tset ip [get_cells -hier $drv_handle]\n\t\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] $clk]]\n\t\tset valid_clk_list \"clk_out0 clk_out1 clk_out2 clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 clk_out8 clk_out9\"\n\t\tset pl_clk \"\"\n\t\tset clkout \"\"\n\t\tforeach pin $pins {\n\t\t\tif {[lsearch $valid_clk_list $pin] >= 0} {\n\t\t\t\tset clkout $pin\n\t\t\t\tset is_clk_wiz 1\n\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t}\n\t\t}\n\t\tif {[llength $clkout]} {\n\t\t\tset number [regexp -all -inline -- {[0-9]+} $clkout]\n\t\t\tset clk_wiz [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk]\n\t\t\tset axi_clk \"s_axi_aclk\"\n\t\t\tforeach clk1 $clk_wiz {\n\t\t\t\tif {[regexp $axi_clk $clk1 match]} {\n\t\t\t\t\tset axi 1\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[string match -nocase $axi \"0\"]} {\n\t\t\t\tdtg_warning \"no s_axi_aclk for clockwizard IP block: \\\" $periph\\\"\\n\\r\"\n\t\t\t\tset pins [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk]\n\t\t\t\tset clk_list \"pl_clk*\"\n\t\t\t\tset clk_pl \"\"\n\t\t\t\tset num \"\"\n\t\t\t\tforeach clk_wiz_pin $pins {\n\t\t\t\t\tset clk_wiz_pins [get_pins -of_objects [get_nets -of_objects $clk_wiz_pin]]\n\t\t\t\t\tforeach pin $clk_wiz_pins {\n\t\t\t\t\t\tif {[regexp $clk_list $pin match]} {\n\t\t\t\t\t\t\tset clk_pl $pin\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"$clk\"]\n\t\t\t\tif {[llength $clk_freq] == 0} {\n\t\t\t\t\tdtg_warning \"clock frequency for the $clk is NULL of IP block: \\\" $drv_handle\\\"\\n\\r\"\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\t# if clk_freq is float convert it to int\n\t\t\t\tset clk_freq [expr int($clk_freq)]\n\t\t\t\tset iptype [get_property IP_NAME [get_cells -hier $drv_handle]]\n\t\t\t\tif {![string equal $clk_freq \"\"]} {\n\t\t\t\t\tif {[lsearch $bus_clk_list $clk_freq] < 0} {\n\t\t\t\t\t\tset bus_clk_list [lappend bus_clk_list $clk_freq]\n\t\t\t\t\t}\n\t\t\t\t\tset bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]\n\t\t\t\t\tset misc_clk_node [add_or_get_dt_node -n \"misc_clk_${bus_clk_cnt}\" -l \"misc_clk_${bus_clk_cnt}\" \\\n\t\t\t\t\t\t-d ${dts_file} -p ${child_node}]\n\t\t\t\t\tset clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]\n\t\t\t\t\tset updat [lappend updat misc_clk_${bus_clk_cnt}]\n\t\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\t\t\t\tgen_fixed_factor_clk_node ${misc_clk_node} ${clk_freq}\n\t\t\t\t\t} else {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-frequency\" $clk_freq int\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {![string match -nocase $axi \"0\"]} {\n\t\t\t\tswitch $number {\n\t\t\t\t\t\"1\" {\n\t\t\t\t\t\tset peri \"$periph 0\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"2\" {\n\t\t\t\t\t\tset peri \"$periph 1\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"3\" {\n\t\t\t\t\t\tset peri \"$periph 2\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"4\" {\n\t\t\t\t\t\tset peri \"$periph 3\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"5\" {\n\t\t\t\t\t\tset peri \"$periph 4\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"6\" {\n\t\t\t\t\t\tset peri \"$periph 5\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"7\" {\n\t\t\t\t\t\tset peri \"$periph 6\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\tset clklist \"pl_clk0 pl_clk1 pl_clk2 pl_clk3\"\n\t\t}\n\t\tforeach pin $pins {\n\t\t\tif {[lsearch $clklist $pin] >= 0} {\n\t\t\t\tset pl_clk $pin\n\t\t\t\tset is_pl_clk 1\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\tswitch $pl_clk {\n\t\t\t\t\"pl_clk0\" {\n\t\t\t\t\tset pl_clk0 \"versal_clk 65\"\n\t\t\t\t\tset clocks [lappend clocks $pl_clk0]\n\t\t\t\t\tset updat [lappend updat $pl_clk0]\n\t\t\t\t}\n\t\t\t\t\"pl_clk1\" {\n\t\t\t\t\t\tset pl_clk1 \"versal_clk 66\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk1]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk1]\n\t\t\t\t}\n\t\t\t\t\"pl_clk2\" {\n\t\t\t\t\t\tset pl_clk2 \"versal_clk 67\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk2]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk2]\n\t\t\t\t}\n\t\t\t\t\"pl_clk3\" {\n\t\t\t\t\t\tset pl_clk3 \"versal_clk 68\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk3]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk3]\n\t\t\t\t}\n\t\t\t\tdefault {\n\t\t\t\t\t\tdtg_debug \"not supported pl_clk:$pl_clk\"\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\tswitch $pl_clk {\n\t\t\t\t\"pl_clk0\" {\n\t\t\t\t\t\tset pl_clk0 \"zynqmp_clk 71\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk0]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk0]\n\t\t\t\t}\n\t\t\t\t\"pl_clk1\" {\n\t\t\t\t\t\tset pl_clk1 \"zynqmp_clk 72\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk1]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk1]\n\t\t\t\t}\n\t\t\t\t\"pl_clk2\" {\n\t\t\t\t\t\tset pl_clk2 \"zynqmp_clk 73\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk2]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk2]\n\t\t\t\t}\n\t\t\t\t\"pl_clk3\" {\n\t\t\t\t\t\tset pl_clk3 \"zynqmp_clk 74\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk3]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk3]\n\t\t\t\t}\n\t\t\t\tdefault {\n\t\t\t\t\tdtg_debug \"not supported pl_clk:$pl_clk\"\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $is_clk_wiz \"0\"]&& [string match -nocase $is_pl_clk \"0\"]} {\n\t\t\tset clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"$clk\"]\n\t\t\tif {[llength $clk_freq] == 0} {\n\t\t\t\tdtg_warning \"clock frequency for the $clk is NULL of IP block: \\\"$drv_handle\\\"\\n\\r\"\n\t\t\t\tcontinue\n\t\t\t}\n\t\t\t# if clk_freq is float convert it to int\n\t\t\tset clk_freq [expr int($clk_freq)]\n\t\t\tset iptype [get_property IP_NAME [get_cells -hier $drv_handle]]\n\t\t\tif {![string equal $clk_freq \"\"]} {\n\t\t\t\tif {[lsearch $bus_clk_list $clk_freq] < 0} {\n\t\t\t\t\tset bus_clk_list [lappend bus_clk_list $clk_freq]\n\t\t\t\t}\n\t\t\t\tset bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]\n\t\t\t\tset misc_clk_node [add_or_get_dt_node -n \"misc_clk_${bus_clk_cnt}\" -l \"misc_clk_${bus_clk_cnt}\" \\\n\t\t\t\t-d ${dts_file} -p ${child_node}]\n\t\t\t\tset clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]\n\t\t\t\tset updat [lappend updat misc_clk_${bus_clk_cnt}]\n\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\t\t\tgen_fixed_factor_clk_node ${misc_clk_node} ${clk_freq}\n\t\t\t\t} else {\n\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-frequency\" $clk_freq int\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tappend clocknames \" \" \"$clk\"\n\t\tset is_pl_clk 0\n\t\tset is_clk_wiz 0\n\t\tset axi 0\n\t}\n\thsi::utils::add_new_dts_param \"${dfx_node}\" \"clock-names\" \"$clocknames\" stringlist\n\tset ip [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tset len [llength $updat]\n\tswitch $len {\n\t\t\"1\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\thsi::utils::add_new_dts_param \"${dfx_node}\" \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"2\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]\"\n\t\t\thsi::utils::add_new_dts_param \"${dfx_node}\" \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"3\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]\"\n\t\t\thsi::utils::add_new_dts_param \"${dfx_node}\" \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"4\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]\"\n\t\t\thsi::utils::add_new_dts_param \"${dfx_node}\" \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"5\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]\"\n\t\t\thsi::utils::add_new_dts_param \"${dfx_node}\" \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"6\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]\"\n\t\t\thsi::utils::add_new_dts_param \"${dfx_node}\" \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"7\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]\"\n\t\t\thsi::utils::add_new_dts_param \"${dfx_node}\" \"clocks\" \"$refs\" reference\n\t\t}\n\t}\n}\n\nproc gen_axis_switch_clk_property {drv_handle dts_file node} {\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tif {[is_pl_ip $drv_handle] && $remove_pl} {\n\t\treturn 0\n\t}\n\tset mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n\tset valid_mainline_kernel_list \"v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4\"\n\tif {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } {\n\t\treturn 0\n\t}\n\tset clocks \"\"\n\tset axi 0\n\tset is_clk_wiz 0\n\tset is_pl_clk 0\n\tset updat \"\"\n\tglobal bus_clk_list\n\tset clocknames \"\"\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tif {[string match -nocase $proctype \"microblaze\"]} {\n\t\treturn\n\t}\n\tset clk_pins [get_pins -of_objects [get_cells -hier $drv_handle] -filter {TYPE==clk&&DIRECTION==I}]\n\tset ip [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tforeach clk $clk_pins {\n\t\tset ip [get_cells -hier $drv_handle]\n\t\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] $clk]]\n\t\tset valid_clk_list \"clk_out0 clk_out1 clk_out2 clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 clk_out8 clk_out9\"\n\t\tset pl_clk \"\"\n\t\tset clkout \"\"\n\t\tforeach pin $pins {\n\t\t\tif {[lsearch $valid_clk_list $pin] >= 0} {\n\t\t\t\tset clkout $pin\n\t\t\t\tset is_clk_wiz 1\n\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t}\n\t\t}\n\t\tif {[llength $clkout]} {\n\t\t\tset number [regexp -all -inline -- {[0-9]+} $clkout]\n\t\t\tset clk_wiz [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk]\n\t\t\tset axi_clk \"s_axi_aclk\"\n\t\t\tforeach clk1 $clk_wiz {\n\t\t\t\tif {[regexp $axi_clk $clk1 match]} {\n\t\t\t\t\tset axi 1\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[string match -nocase $axi \"0\"]} {\n\t\t\t\tdtg_warning \"no s_axi_aclk for clockwizard IP block: \\\" $periph\\\"\\n\\r\"\n\t\t\t\tset pins [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk]\n\t\t\t\tset clk_list \"pl_clk*\"\n\t\t\t\tset clk_pl \"\"\n\t\t\t\tset num \"\"\n\t\t\t\tforeach clk_wiz_pin $pins {\n\t\t\t\t\tset clk_wiz_pins [get_pins -of_objects [get_nets -of_objects $clk_wiz_pin]]\n\t\t\t\t\tforeach pin $clk_wiz_pins {\n\t\t\t\t\t\tif {[regexp $clk_list $pin match]} {\n\t\t\t\t\t\t\tset clk_pl $pin\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"$clk\"]\n\t\t\t\tif {[llength $clk_freq] == 0} {\n\t\t\t\t\tdtg_warning \"clock frequency for the $clk is NULL of IP block: \\\" $drv_handle\\\"\\n\\r\"\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\tset bus_node [add_or_get_bus_node $drv_handle $dts_file]\n\t\t\t\t# if clk_freq is float convert it to int\n\t\t\t\tset clk_freq [expr int($clk_freq)]\n\t\t\t\tset iptype [get_property IP_NAME [get_cells -hier $drv_handle]]\n\t\t\t\tif {![string equal $clk_freq \"\"]} {\n\t\t\t\t\tif {[lsearch $bus_clk_list $clk_freq] < 0} {\n\t\t\t\t\t\tset bus_clk_list [lappend bus_clk_list $clk_freq]\n\t\t\t\t\t}\n\t\t\t\t\tset bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]\n\t\t\t\t\tset misc_clk_node [add_or_get_dt_node -n \"misc_clk_${bus_clk_cnt}\" -l \"misc_clk_${bus_clk_cnt}\" \\\n\t\t\t\t\t\t-d ${dts_file} -p ${bus_node}]\n\t\t\t\t\tset clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]\n\t\t\t\t\tset updat [lappend updat misc_clk_${bus_clk_cnt}]\n\t\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\t\t\t\tgen_fixed_factor_clk_node ${misc_clk_node} ${clk_freq}\n\t\t\t\t\t} else {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-frequency\" $clk_freq int\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {![string match -nocase $axi \"0\"]} {\n\t\t\t\tswitch $number {\n\t\t\t\t\t\"1\" {\n\t\t\t\t\t\tset peri \"$periph 0\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"2\" {\n\t\t\t\t\t\tset peri \"$periph 1\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"3\" {\n\t\t\t\t\t\tset peri \"$periph 2\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"4\" {\n\t\t\t\t\t\tset peri \"$periph 3\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"5\" {\n\t\t\t\t\t\tset peri \"$periph 4\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"6\" {\n\t\t\t\t\t\tset peri \"$periph 5\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"7\" {\n\t\t\t\t\t\tset peri \"$periph 6\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\tset clklist \"pl_clk0 pl_clk1 pl_clk2 pl_clk3\"\n\t\t}\n\t\tforeach pin $pins {\n\t\t\tif {[lsearch $clklist $pin] >= 0} {\n\t\t\t\tset pl_clk $pin\n\t\t\t\tset is_pl_clk 1\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\tswitch $pl_clk {\n\t\t\t\t\"pl_clk0\" {\n\t\t\t\t\tset pl_clk0 \"versal_clk 65\"\n\t\t\t\t\tset clocks [lappend clocks $pl_clk0]\n\t\t\t\t\tset updat [lappend updat $pl_clk0]\n\t\t\t\t}\n\t\t\t\t\"pl_clk1\" {\n\t\t\t\t\t\tset pl_clk1 \"versal_clk 66\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk1]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk1]\n\t\t\t\t}\n\t\t\t\t\"pl_clk2\" {\n\t\t\t\t\t\tset pl_clk2 \"versal_clk 67\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk2]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk2]\n\t\t\t\t}\n\t\t\t\t\"pl_clk3\" {\n\t\t\t\t\t\tset pl_clk3 \"versal_clk 68\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk3]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk3]\n\t\t\t\t}\n\t\t\t\tdefault {\n\t\t\t\t\t\tdtg_debug \"not supported pl_clk:$pl_clk\"\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\tswitch $pl_clk {\n\t\t\t\t\"pl_clk0\" {\n\t\t\t\t\t\tset pl_clk0 \"zynqmp_clk 71\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk0]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk0]\n\t\t\t\t}\n\t\t\t\t\"pl_clk1\" {\n\t\t\t\t\t\tset pl_clk1 \"zynqmp_clk 72\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk1]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk1]\n\t\t\t\t}\n\t\t\t\t\"pl_clk2\" {\n\t\t\t\t\t\tset pl_clk2 \"zynqmp_clk 73\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk2]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk2]\n\t\t\t\t}\n\t\t\t\t\"pl_clk3\" {\n\t\t\t\t\t\tset pl_clk3 \"zynqmp_clk 74\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk3]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk3]\n\t\t\t\t}\n\t\t\t\tdefault {\n\t\t\t\t\tdtg_debug \"not supported pl_clk:$pl_clk\"\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $is_clk_wiz \"0\"]&& [string match -nocase $is_pl_clk \"0\"]} {\n\t\t\tset clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"$clk\"]\n\t\t\tif {[llength $clk_freq] == 0} {\n\t\t\t\tdtg_warning \"clock frequency for the $clk is NULL of IP block: \\\"$drv_handle\\\"\\n\\r\"\n\t\t\t\tcontinue\n\t\t\t}\n\t\t\tset bus_node [add_or_get_bus_node $drv_handle $dts_file]\n\t\t\t# if clk_freq is float convert it to int\n\t\t\tset clk_freq [expr int($clk_freq)]\n\t\t\tset iptype [get_property IP_NAME [get_cells -hier $drv_handle]]\n\t\t\tif {![string equal $clk_freq \"\"]} {\n\t\t\t\tif {[lsearch $bus_clk_list $clk_freq] < 0} {\n\t\t\t\t\tset bus_clk_list [lappend bus_clk_list $clk_freq]\n\t\t\t\t}\n\t\t\t\tset bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]\n\t\t\t\tset misc_clk_node [add_or_get_dt_node -n \"misc_clk_${bus_clk_cnt}\" -l \"misc_clk_${bus_clk_cnt}\" \\\n\t\t\t\t-d ${dts_file} -p ${bus_node}]\n\t\t\t\tset clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]\n\t\t\t\tset updat [lappend updat misc_clk_${bus_clk_cnt}]\n\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\t\t\tgen_fixed_factor_clk_node ${misc_clk_node} ${clk_freq}\n\t\t\t\t} else {\n\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-frequency\" $clk_freq int\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tappend clocknames \" \" \"$clk\"\n\t\tset is_pl_clk 0\n\t\tset is_clk_wiz 0\n\t\tset axi 0\n\t}\n\thsi::utils::add_new_dts_param \"${node}\" \"clock-names\" \"$clocknames\" stringlist\n\tset ip [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tset len [llength $updat]\n\tswitch $len {\n\t\t\"1\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"2\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]\"\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"3\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]\"\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"4\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]\"\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"5\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]\"\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"6\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]\"\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"7\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]\"\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"clocks\" \"$refs\" reference\n\t\t}\n\t}\n}\n\nproc gen_clk_property {drv_handle} {\n\tif {[is_ps_ip $drv_handle]} {\n\t\treturn 0\n\t}\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tif {[is_pl_ip $drv_handle] && $remove_pl} {\n\t\treturn 0\n\t}\n\tset mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n\tset valid_mainline_kernel_list \"v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4\"\n if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } {\n\t\treturn 0\n\t}\n\tset clocks \"\"\n\tset axi 0\n\tset is_clk_wiz 0\n\tset is_pl_clk 0\n\tset updat \"\"\n\tglobal bus_clk_list\n\tset clocknames \"\"\n\tdtg_verbose \"gen_clk_property:$drv_handle\"\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tif {[string match -nocase $proctype \"microblaze\"]} {\n\t\treturn\n\t}\n\tset clk_pins [get_pins -of_objects [get_cells -hier $drv_handle] -filter {TYPE==clk&&DIRECTION==I}]\n\tdtg_verbose \"clk_pins:$clk_pins\"\n\tset ip [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tset ignore_list \"lmb_bram_if_cntlr PERIPHERAL axi_noc axi_noc2 mrmac\"\n\tif {[lsearch $ignore_list $ip] >= 0 } {\n\t\treturn 0\n }\n\tif {[string match -nocase $ip \"vcu\"]} {\n\t\tset clk_pins \"pll_ref_clk s_axi_lite_aclk\"\n\t}\n\tforeach clk $clk_pins {\n\t\tset ip [get_cells -hier $drv_handle]\n\t\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] $clk]]\n\t\tset valid_clk_list \"clk_out0 clk_out1 clk_out2 clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 clk_out8 clk_out9\"\n\t\tset pl_clk \"\"\n\t\tset clkout \"\"\n\t\tforeach pin $pins {\n\t\t\tif {[lsearch $valid_clk_list $pin] >= 0} {\n\t\t\t\tset clkout $pin\n\t\t\t\tset is_clk_wiz 1\n\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t}\n\t\t}\n\t\tif {[llength $clkout]} {\n\t\t\tset number [regexp -all -inline -- {[0-9]+} $clkout]\n\t\t\tset clk_wiz [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk]\n\t\t\tset axi_clk \"s_axi_aclk\"\n\t\t\tforeach clk1 $clk_wiz {\n\t\t\t\tif {[regexp $axi_clk $clk1 match]} {\n\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $periph]\n\t\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\t\tset axi 1\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif {[string match -nocase $axi \"0\"]} {\n\t\t\t\tdtg_warning \"no s_axi_aclk for clockwizard IP block: \\\" $periph\\\"\\n\\r\"\n\t\t\t\tset pins [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk]\n\t\t\t\tset clk_list \"pl_clk*\"\n\t\t\t\tset clk_pl \"\"\n\t\t\t\tset num \"\"\n\t\t\t\tforeach clk_wiz_pin $pins {\n\t\t\t\t\tset clk_wiz_pins [get_pins -of_objects [get_nets -of_objects $clk_wiz_pin]]\n\t\t\t\t\tforeach pin $clk_wiz_pins {\n\t\t\t\t\t\tif {[regexp $clk_list $pin match]} {\n\t\t\t\t\t\t\tset clk_pl $pin\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {[llength $clk_pl]} {\n\t\t\t\t\tset num [regexp -all -inline -- {[0-9]+} $clk_pl]\n\t\t\t\t}\n\n\t\t\t\tset RpRm [get_rp_rm_for_drv $drv_handle]\n\t\t\t\tregsub -all { } $RpRm \"\" RpRm\n\t\t\t\tif {[llength $RpRm]} {\n\t\t\t\t\tset dts_file \"pl-partial-$RpRm.dtsi\"\n\t\t\t\t} else {\n\t\t\t\t\tset dts_file \"pl.dtsi\"\n\t\t\t\t}\n\n\t\t\t\tset bus_node [add_or_get_bus_node $drv_handle $dts_file]\n\t\t\t\tset clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"$clk\"]\n\t\t\t\tif {[llength $clk_freq] == 0} {\n\t\t\t\t\tdtg_warning \"clock frequency for the $clk is NULL of IP block: \\\" $drv_handle\\\"\\n\\r\"\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\t# if clk_freq is float convert it to int\n\t\t\t\tset clk_freq [expr int($clk_freq)]\n\t\t\t\tset iptype [get_property IP_NAME [get_cells -hier $drv_handle]]\n\t\t\t\tif {![string equal $clk_freq \"\"]} {\n\t\t\t\t\tif {[lsearch $bus_clk_list $clk_freq] < 0} {\n\t\t\t\t\t\tset bus_clk_list [lappend bus_clk_list $clk_freq]\n\t\t\t\t\t}\n\t\t\t\t\tset bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]\n\t\t\t\t\tif {[llength $RpRm]} {\n\t\t\t\t\t\tset misc_clk_node [add_or_get_dt_node -n \"misc_clk$RpRm${bus_clk_cnt}\" -l \"misc_clk_$RpRm${bus_clk_cnt}\" \\\n\t\t\t\t\t\t-d ${dts_file} -p ${bus_node}]\n\t\t\t\t\t} else {\n\t\t\t\t\t\tset misc_clk_node [add_or_get_dt_node -n \"misc_clk_${bus_clk_cnt}\" -l \"misc_clk_${bus_clk_cnt}\" \\\n\t\t\t\t\t\t-d ${dts_file} -p ${bus_node}]\n\t\t\t\t\t}\n\n\t\t\t\t\tset clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]\n\t\t\t\t\tif {[llength $RpRm]} {\n\t\t\t\t\t\tset updat [lappend updat misc_clk_$RpRm${bus_clk_cnt}]\n\t\t\t\t\t} else {\n\t\t\t\t\t\tset updat [lappend updat misc_clk_${bus_clk_cnt}]\n\t\t\t\t\t}\n\t\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\t\t\t\tgen_fixed_factor_clk_node ${misc_clk_node} ${clk_freq}\n\t\t\t\t\t} else {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-frequency\" $clk_freq int\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {![string match -nocase $axi \"0\"]} {\n\t\t\t\tswitch $number {\n\t\t\t\t\t\"1\" {\n\t\t\t\t\t\tset peri \"$periph 0\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"2\" {\n\t\t\t\t\t\tset peri \"$periph 1\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"3\" {\n\t\t\t\t\t\tset peri \"$periph 2\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"4\" {\n\t\t\t\t\t\tset peri \"$periph 3\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"5\" {\n\t\t\t\t\t\tset peri \"$periph 4\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"6\" {\n\t\t\t\t\t\tset peri \"$periph 5\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"7\" {\n\t\t\t\t\t\tset peri \"$periph 6\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] } {\n\t\t\tset clklist \"pl_clk0 pl_clk1 pl_clk2 pl_clk3\"\n\t\t} elseif {[string match -nocase $proctype \"ps7_cortexa9\"]} {\n\t\t\tset clklist \"FCLK_CLK0 FCLK_CLK1 FCLK_CLK2 FCLK_CLK3\"\n\t\t}\n\t\tif {[string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\tif {[string match -nocase $proctype \"psv_cortexa72\"]} {\n\t\t\t\tset versal_periph [get_cells -hier -filter {IP_NAME == versal_cips || IP_NAME == ps_wizard}]\n\t\t\t} else {\n\t\t\t\tset versal_periph [get_cells -hier -filter {IP_NAME == psx_wizard}]\n\t\t\t}\n\t\t\tset ver [get_comp_ver $versal_periph]\n\t\t\tif {$ver >= 3.0} {\n\t\t\t\tset clklist \"pl0_ref_clk pl1_ref_clk pl2_ref_clk pl3_ref_clk\"\n\t\t\t} else {\n\t\t\t\tset clklist \"pl_clk0 pl_clk1 pl_clk2 pl_clk3\"\n\t\t\t}\n\t\t}\n\t\tforeach pin $pins {\n\t\t\tif {[lsearch $clklist $pin] >= 0} {\n\t\t\t\tset pl_clk $pin\n\t\t\t\tset is_pl_clk 1\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\tif {[string match -nocase $proctype \"psv_cortexa72\"]} {\n\t\t\t\tset versal_periph [get_cells -hier -filter {IP_NAME == versal_cips || IP_NAME == ps_wizard}]\n\t\t\t} else {\n\t\t\t\tset versal_periph [get_cells -hier -filter {IP_NAME == psx_wizard}]\n\t\t\t}\n\n\t\t\tset ver [get_comp_ver $versal_periph]\n\t\t\tif {$ver >= 3.0} {\n\t\t\tswitch $pl_clk {\n\t\t\t\t\"pl0_ref_clk\" {\n\t\t\t\t\t\tset pl_clk0 \"versal_clk 65\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk0]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk0]\n\t\t\t\t}\n\t\t\t\t\"pl1_ref_clk\" {\n\t\t\t\t\t\tset pl_clk1 \"versal_clk 66\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk1]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk1]\n\t\t\t\t}\n\t\t\t\t\"pl2_ref_clk\" {\n\t\t\t\t\t\tset pl_clk2 \"versal_clk 67\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk2]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk2]\n\t\t\t\t}\n\t\t\t\t\"pl3_ref_clk\" {\n\t\t\t\t\t\tset pl_clk3 \"versal_clk 68\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk3]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk3]\n\t\t\t\t}\n\t\t\t\tdefault {\n\t\t\t\t\t\tdtg_warning \"Clock pin \\\"$clk\\\" of IP block \\\"$drv_handle\\\" is not connected to any of the pl_clk\\\"\\n\\r\"\n\t\t\t\t}\n\t\t\t}\n\t\t\t} else {\n\t\t\tswitch $pl_clk {\n\t\t\t\t\"pl_clk0\" {\n\t\t\t\t\t\tset pl_clk0 \"versal_clk 65\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk0]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk0]\n\t\t\t\t}\n\t\t\t\t\"pl_clk1\" {\n\t\t\t\t\t\tset pl_clk1 \"versal_clk 66\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk1]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk1]\n\t\t\t\t}\n\t\t\t\t\"pl_clk2\" {\n\t\t\t\t\t\tset pl_clk2 \"versal_clk 67\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk2]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk2]\n\t\t\t\t}\n\t\t\t\t\"pl_clk3\" {\n\t\t\t\t\t\tset pl_clk3 \"versal_clk 68\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk3]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk3]\n\t\t\t\t}\n\t\t\t\tdefault {\n\t\t\t\t\t\tdtg_warning \"Clock pin \\\"$clk\\\" of IP block \\\"$drv_handle\\\" is not connected to any of the pl_clk\\\"n\\r\"\n\t\t\t\t}\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\tswitch $pl_clk {\n\t\t\t\t\"pl_clk0\" {\n\t\t\t\t\t\tset pl_clk0 \"zynqmp_clk 71\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk0]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk0]\n\t\t\t\t}\n\t\t\t\t\"pl_clk1\" {\n\t\t\t\t\t\tset pl_clk1 \"zynqmp_clk 72\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk1]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk1]\n\t\t\t\t}\n\t\t\t\t\"pl_clk2\" {\n\t\t\t\t\t\tset pl_clk2 \"zynqmp_clk 73\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk2]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk2]\n\t\t\t\t}\n\t\t\t\t\"pl_clk3\" {\n\t\t\t\t\t\tset pl_clk3 \"zynqmp_clk 74\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk3]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk3]\n\t\t\t\t}\n\t\t\t\tdefault {\n\t\t\t\t\t\tdtg_warning \"Clock pin \\\"$clk\\\" of IP block \\\"$drv_handle\\\" is not connected to any of the pl_clk\\\"\\n\\r\"\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $proctype \"ps7_cortexa9\"]} {\n\t\t\tswitch $pl_clk {\n\t\t\t\t\"FCLK_CLK0\" {\n\t\t\t\t\t\tset pl_clk0 \"clkc 15\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk0]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk0]\n\t\t\t\t}\n\t\t\t\t\"FCLK_CLK1\" {\n\t\t\t\t\t\tset pl_clk1 \"clkc 16\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk1]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk1]\n\t\t\t\t}\n\t\t\t\t\"FCLK_CLK2\" {\n\t\t\t\t\t\tset pl_clk2 \"clkc 17\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk2]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk2]\n\t\t\t\t}\n\t\t\t\t\"FCLK_CLK3\" {\n\t\t\t\t\t\tset pl_clk3 \"clkc 18\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk3]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk3]\n\t\t\t\t}\n\t\t\t\tdefault {\n\t\t\t\t\t\tdtg_warning \"Clock pin \\\"$clk\\\" of IP block \\\"$drv_handle\\\" is not connected to any of the pl_clk\\\"\\n\\r\"\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $is_clk_wiz \"0\"]&& [string match -nocase $is_pl_clk \"0\"]} {\n\t\t\tset RpRm [get_rp_rm_for_drv $drv_handle]\n\t\t\tregsub -all { } $RpRm \"\" RpRm\n\t\t\tif {[llength $RpRm]} {\n\t\t\t\tset dts_file \"pl-partial-$RpRm.dtsi\"\n\t\t\t} else {\n\t\t\t\tset dts_file \"pl.dtsi\"\n }\n\t\t\tset bus_node [add_or_get_bus_node $drv_handle $dts_file]\n\t\t\tset clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"$clk\"]\n\t\t\tif {[llength $clk_freq] == 0} {\n\t\t\t\tdtg_warning \"clock frequency for the $clk is NULL of IP block: \\\"$drv_handle\\\"\\n\\r\"\n\t\t\t\tcontinue\n\t\t\t}\n\t\t\t# if clk_freq is float convert it to int\n\t\t\tset clk_freq [expr int($clk_freq)]\n\t\t\tset iptype [get_property IP_NAME [get_cells -hier $drv_handle]]\n\t\t\tif {![string equal $clk_freq \"\"]} {\n\t\t\t\tif {[lsearch $bus_clk_list $clk_freq] < 0} {\n\t\t\t\t\tset bus_clk_list [lappend bus_clk_list $clk_freq]\n\t\t\t\t}\n\t\t\t\tset bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]\n\t\t\t\tif {[llength $RpRm]} {\n\t\t\t\t\tset misc_clk_node [add_or_get_dt_node -n \"misc_clk_$RpRm${bus_clk_cnt}\" -l \"misc_clk_$RpRm${bus_clk_cnt}\" \\\n\t\t\t\t\t\t-d ${dts_file} -p ${bus_node}]\n\t\t\t\t} else {\n\t\t\t\t\tset misc_clk_node [add_or_get_dt_node -n \"misc_clk_${bus_clk_cnt}\" -l \"misc_clk_${bus_clk_cnt}\" \\\n\t\t\t\t\t\t-d ${dts_file} -p ${bus_node}]\n\t\t\t\t}\n\t\t\t\tset clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]\n\t\t\t\tif {[llength $RpRm]} {\n\t\t\t\t\tset updat [lappend updat misc_clk_$RpRm${bus_clk_cnt}]\n\t\t\t\t} else {\n\t\t\t\t\tset updat [lappend updat misc_clk_${bus_clk_cnt}]\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\t\t\tgen_fixed_factor_clk_node ${misc_clk_node} ${clk_freq}\n\t\t\t\t} else {\n\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-frequency\" $clk_freq int\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tappend clocknames \" \" \"$clk\"\n\t\tset is_pl_clk 0\n\t\tset is_clk_wiz 0\n\t\tset axi 0\n\t}\n\tset ip [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tif {[string match -nocase $ip \"dfx_axi_shutdown_manager\"]} {\n\t\t# DFX axi shutdown manager driver expecting aclk as clock name\n\t\t# but IP has clk pin name. We cannot update this in Driver as it\n\t\t# breaks the backward compatiblity. so rename clk -> aclk\n\t\tset clocknames [string map {clk aclk} $clocknames]\n\t}\n\tset_drv_prop_if_empty $drv_handle \"clock-names\" $clocknames stringlist\n\tif {[string match -nocase $ip \"vcu\"]} {\n\t\tset vcu_label $drv_handle\n\t\tset vcu_clk1 \"$drv_handle 0\"\n\t\tset updat [lappend updat $vcu_clk1]\n\t\tset vcu_clk2 \"$drv_handle 1\"\n\t\tset updat [lappend updat $vcu_clk2]\n\t\tset vcu_clk3 \"$drv_handle 2\"\n\t\tset updat [lappend updat $vcu_clk3]\n\t\tset vcu_clk4 \"$drv_handle 3\"\n\t\tset updat [lappend updat $vcu_clk4]\n\t\tset len [llength $updat]\n\t\tset refs [lindex $updat 0]\n\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]\"\n\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\treturn\n\t}\n\tset len [llength $updat]\n\tswitch $len {\n\t\t\"1\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"2\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]\"\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"3\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]\"\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"4\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]\"\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"5\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]\"\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"6\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]\"\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"7\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]\"\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"8\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]\"\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"9\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]\"\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"10\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]>, <&[lindex $updat 9]\"\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"11\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]>, <&[lindex $updat 9]>, <&[lindex $updat 10]\"\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"12\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]>, <&[lindex $updat 9]>, <&[lindex $updat 10]>, <&[lindex $updat 11]\"\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"13\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]>, <&[lindex $updat 9]>, <&[lindex $updat 10]>, <&[lindex $updat 11]>, <&[lindex $updat 12]\"\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"14\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]>, <&[lindex $updat 9]>, <&[lindex $updat 10]>, <&[lindex $updat 11]>, <&[lindex $updat 12]>, <&[lindex $updat 13]\"\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"15\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]>, <&[lindex $updat 9]>, <&[lindex $updat 10]>, <&[lindex $updat 11]>, <&[lindex $updat 12]>, <&[lindex $updat 13]>, <&[lindex $updat 14]\"\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t\t\"16\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]>, <&[lindex $updat 9]>, <&[lindex $updat 10]>, <&[lindex $updat 11]>, <&[lindex $updat 12]>, <&[lindex $updat 13]>, <&[lindex $updat 14]>, <&[lindex $updat 15]\"\n\t\t\tset_drv_prop $drv_handle \"clocks\" \"$refs\" reference\n\t\t}\n\t}\n}\n\nproc overwrite_clknames {clknames drv_handle} {\n\tset_drv_prop $drv_handle \"clock-names\" $clknames stringlist\n}\nproc get_comp_ver {drv_handle} {\n\tset slave [get_cells -hier ${drv_handle}]\n\tset vlnv [split [get_property VLNV $slave] \":\"]\n\tset ver [lindex $vlnv 3]\n\treturn $ver\n}\n\nproc get_comp_str {drv_handle} {\n\tset slave [get_cells -hier ${drv_handle}]\n\tset vlnv [split [get_property VLNV $slave] \":\"]\n\tset ver [lindex $vlnv 3]\n\tset name [lindex $vlnv 2]\n\tset ver [lindex $vlnv 3]\n\tset comp_prop \"xlnx,${name}-${ver}\"\n\tregsub -all {_} $comp_prop {-} comp_prop\n\treturn $comp_prop\n}\n\nproc get_intr_type {intc_name ip_name port_name} {\n\tset intc [get_cells -hier $intc_name]\n\tset ip [get_cells -hier $ip_name]\n\tif {[llength $intc] == 0 && [llength $ip] == 0} {\n\t\treturn -1\n\t}\n\tif {[llength $intc] == 0} {\n\t\treturn -1\n\t}\n\tset intr_pin [get_pins -of_objects $ip $port_name]\n\tset sensitivity \"\"\n\tif {[llength $intr_pin] >= 1} {\n\t\t# TODO: check with HSM dev and see if this is a bug\n\t\tset sensitivity [get_property SENSITIVITY $intr_pin]\n\t}\n\tset intc_type [get_property IP_NAME $intc ]\n\tset valid_intc_list \"ps7_scugic psu_acpu_gic psv_acpu_gic psx_acpu_gic\"\n\tif {[lsearch -nocase $valid_intc_list $intc_type] >= 0} {\n\t\tif {[string match -nocase $sensitivity \"EDGE_FALLING\"]} {\n\t\t\t\treturn 2;\n\t\t} elseif {[string match -nocase $sensitivity \"EDGE_RISING\"]} {\n\t\t\t\treturn 1;\n\t\t} elseif {[string match -nocase $sensitivity \"LEVEL_HIGH\"]} {\n\t\t\t\treturn 4;\n\t\t} elseif {[string match -nocase $sensitivity \"LEVEL_LOW\"]} {\n\t\t\t\treturn 8;\n\t\t}\n\t} else {\n\t\t# Follow the openpic specification\n\t\tif {[string match -nocase $sensitivity \"EDGE_FALLING\"]} {\n\t\t\t\treturn 3;\n\t\t} elseif {[string match -nocase $sensitivity \"EDGE_RISING\"]} {\n\t\t\t\treturn 0;\n\t\t} elseif {[string match -nocase $sensitivity \"LEVEL_HIGH\"]} {\n\t\t\t\treturn 2;\n\t\t} elseif {[string match -nocase $sensitivity \"LEVEL_LOW\"]} {\n\t\t\t\treturn 1;\n\t\t}\n\t}\n\treturn -1\n}\n\nproc get_drv_conf_prop_list {ip_name {def_pattern \"CONFIG.*\"}} {\n\tset drv_handle [get_ip_handler $ip_name]\n\tif {[catch {set rt [list_property -regexp $drv_handle ${def_pattern}]} msg]} {\n\t\tset rt \"\"\n\t}\n\treturn $rt\n}\n\nproc get_ip_conf_prop_list {ip_name {def_pattern \"CONFIG.*\"}} {\n\tset ip [get_cells -hier $ip_name]\n\tif {[catch {set rt [list_property -regexp $ip ${def_pattern}]} msg]} {\n\t\tset rt \"\"\n\t}\n\treturn $rt\n}\n\nproc get_ip_handler {ip_name} {\n\t# check if it is processor\n\tif {[string equal -nocase [get_sw_processor] $ip_name]} {\n\t\treturn [get_sw_processor]\n\t}\n\t# check if it is the target processor\n\t# get it from drvers\n\treturn [get_drivers $ip_name]\n}\n\nproc set_drv_prop args {\n\tset drv_handle [lindex $args 0]\n\tset prop_name [lindex $args 1]\n\tset value [lindex $args 2]\n\n\t# check if property exists if not create it\n\tset list [get_drv_conf_prop_list $drv_handle]\n\tif {[lsearch -glob ${list} ${prop_name}] < 0} {\n\t\thsi::utils::add_new_property $drv_handle $prop_name string \"$value\"\n\t}\n\n\tif {[llength $args] >= 4} {\n\t\tset type [lindex $args 3]\n\t\tset_property ${prop_name} $value $drv_handle\n\t\tset prop [get_comp_params ${prop_name} $drv_handle]\n\t\tset_property CONFIG.TYPE $type $prop\n\t} else {\n\t\tset_property ${prop_name} $value $drv_handle\n\t}\n\treturn 0\n}\n\nproc set_drv_prop_if_empty args {\n\tset drv_handle [lindex $args 0]\n\tset prop_name [lindex $args 1]\n\tset value [lindex $args 2]\n\tset cur_prop_value [get_property CONFIG.$prop_name $drv_handle]\n\tif {[string_is_empty $cur_prop_value] == 0} {\n\t\tdtg_debug \"$drv_handle $prop_name property is not empty, current value is '$cur_prop_value'\"\n\t\treturn -1\n\t}\n\tif {[llength $args] >= 4} {\n\t\tset type [lindex $args 3]\n\t\tset_drv_prop $drv_handle $prop_name $value $type\n\t} else {\n\t\tset_drv_prop $drv_handle $prop_name $value\n\t}\n\treturn 0\n}\n\nproc gen_mb_interrupt_property {cpu_handle {intr_port_name \"\"}} {\n\t# generate interrupts and interrupt-parent properties for soft IP\n\tproc_called_by\n\tif {[is_ps_ip $cpu_handle]} {\n\t\treturn 0\n\t}\n\n\tset slave [get_cells -hier ${cpu_handle}]\n\tset intc \"\"\n\n\tif {[string_is_empty $intr_port_name]} {\n\t\tset intr_port_name [get_pins -of_objects $slave -filter {TYPE==INTERRUPT}]\n\t}\n\tset cpin [hsi::utils::get_interrupt_sources [get_cells -hier $cpu_handle]]\n\tset intc [get_cells -of_objects $cpin]\n if { [::hsi::utils::is_intr_cntrl $intc] != 1 } {\n\t\tset intf_pins [::hsi::get_intf_pins -of_objects $intc]\n\t\tforeach intp $intf_pins {\n\t\t\tset connectip [get_connected_stream_ip [get_cells -hier $intc] $intp]\n\t\t\tif { [::hsi::utils::is_intr_cntrl $connectip] == 1 } {\n\t\t\t\tset intc $connectip\n\t\t\t}\n\t\t}\n\t}\n\tif {[string_is_empty $intc]} {\n\t\terror \"no interrupt controller found\"\n\t}\n\n\tset_drv_prop $cpu_handle interrupt-handle $intc reference\n}\n\nproc get_interrupt_parent { periph_name intr_pin_name } {\n lappend intr_cntrl\n if { [llength $intr_pin_name] == 0 } {\n return $intr_cntrl\n }\n\n if { [llength $periph_name] != 0 } {\n set periph [::hsi::get_cells -hier -filter \"NAME==$periph_name\"]\n if { [llength $periph] == 0 } {\n return $intr_cntrl\n }\n set intr_pin [::hsi::get_pins -of_objects $periph -filter \"NAME==$intr_pin_name\"]\n if { [llength $intr_pin] == 0 } {\n return $intr_cntrl\n }\n set pin_dir [common::get_property DIRECTION $intr_pin]\n if { [string match -nocase $pin_dir \"I\"] } {\n return $intr_cntrl\n }\n } else {\n set intr_pin [::hsi::get_ports $intr_pin_name]\n if { [llength $intr_pin] == 0 } {\n return $intr_cntrl\n }\n set pin_dir [common::get_property DIRECTION $intr_pin]\n if { [string match -nocase $pin_dir \"O\"] } {\n return $intr_cntrl\n }\n }\n set intr_sink_pins [::hsi::utils::get_sink_pins $intr_pin]\n foreach intr_sink $intr_sink_pins {\n set sink_periph [lindex [::hsi::get_cells -of_objects $intr_sink] 0]\n if { [llength $sink_periph ] && [::hsi::utils::is_intr_cntrl $sink_periph] == 1 } {\n lappend intr_cntrl $sink_periph\n } elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"xlconcat\"] } {\n set intr_cntrl [list {*}$intr_cntrl {*}[::hsi::utils::get_connected_intr_cntrl $sink_periph \"dout\"]]\n } elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"xlslice\"] } {\n set intr_cntrl [list {*}$intr_cntrl {*}[::hsi::utils::get_connected_intr_cntrl $sink_periph \"Dout\"]]\n } elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"util_reduced_logic\"] } {\n set intr_cntrl [list {*}$intr_cntrl {*}[::hsi::utils::get_connected_intr_cntrl $sink_periph \"Res\"]]\n } elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"dfx_decoupler\"] } {\n\t\t set intr [get_pins -of_objects $sink_periph -filter {TYPE==INTERRUPT&&DIRECTION==O}]\n\t\t set intr_cntrl [list {*}$intr_cntrl {*}[::hsi::utils::get_connected_intr_cntrl $sink_periph \"$intr\"]]\n\t } elseif {[llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"util_ff\"]} {\n set intr_cntrl [list {*}$intr_cntrl {*}[::hsi::utils::get_connected_intr_cntrl $sink_periph \"Q\"]]\n }\n }\n return $intr_cntrl\n}\n\n\nproc gen_interrupt_property {drv_handle {intr_port_name \"\"}} {\n\t# generate interrupts and interrupt-parent properties for soft IP\n\tproc_called_by\n\tif {[is_ps_ip $drv_handle]} {\n\t\treturn 0\n\t}\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tset slave [get_cells -hier ${drv_handle}]\n\tset intr_id -1\n\tset intc \"\"\n\tset intr_info \"\"\n\tset intc_names \"\"\n\tset intr_par \"\"\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tif {[is_pl_ip $drv_handle] && $remove_pl} {\n\t\treturn 0\n\t}\n\tif {[string_is_empty $intr_port_name]} {\n\t\tif {[string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] \"axi_intc\"]} {\n\t\t\tset val [get_pins -of_objects $slave -filter {TYPE==INTERRUPT}]\n\t\t\tset intr_port_name [get_pins -of_objects $slave -filter {TYPE==INTERRUPT&&DIRECTION==O}]\n\t\t\tset single [get_property CONFIG.C_IRQ_CONNECTION [get_cells -hier $slave]]\n\t\t\tif {$single == 0} {\n\t\t\t\tdtg_warning \"The axi_intc Interrupt Output connection is Bus. Change it to Single\"\n\t\t\t}\n\t\t} else {\n\t\t\tset intr_port_name [get_pins -of_objects $slave -filter {TYPE==INTERRUPT}]\n\t\t}\n\t}\n\t# TODO: consolidation with get_intr_id proc\n\tforeach pin ${intr_port_name} {\n\t\tset connected_intc [get_intr_cntrl_name $drv_handle $pin]\n\t\tregsub -all {\\{|\\}} $connected_intc \"\" connected_intc\n\t\tif {[llength $connected_intc] == 0 } {\n\t\t\tif {![string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] \"axi_intc\"]} {\n\t\t\t\tdtg_warning \"Interrupt pin \\\"$pin\\\" of IP block: \\\"$drv_handle\\\" is not connected to any interrupt controller\\n\\r\"\n\t\t\t}\n\t\t\tcontinue\n\t\t}\n\t\tset connected_intc [get_cells -hier $connected_intc]\n\t\tset connected_intc_name [get_property IP_NAME $connected_intc]\n\t\tset valid_gpio_list \"ps7_gpio axi_gpio\"\n\t\tset valid_cascade_proc \"microblaze ps7_cortexa9 psu_cortexa53 psv_cortexa72 psx_cortexa78\"\n\t\t# check whether intc is gpio or other\n\t\tif {[lsearch -nocase $valid_gpio_list $connected_intc_name] >= 0} {\n\t\t\tset cur_intr_info \"\"\n\t\t\tgenerate_gpio_intr_info $connected_intc $drv_handle $pin\n\t\t} else {\n\t\t\tset intc [get_interrupt_parent $drv_handle $pin]\n\t\t\tif { [string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] \"axi_intc\"] && [lsearch -nocase $valid_cascade_proc $proctype] >= 0 } {\n\t\t\t\tset pins [::hsi::get_pins -of_objects [::hsi::get_cells -hier -filter \"NAME==$drv_handle\"] -filter \"NAME==irq\"]\n\t\t\t\tset intc [get_interrupt_parent $drv_handle $pins]\n\t\t\t} else {\n\t\t\t\tset intc [get_interrupt_parent $drv_handle $pin]\n\t\t\t}\n\t\t\tif {[string_is_empty $intc] == 1} {\n\t\t\t\tdtg_warning \"Interrupt pin \\\"$pin\\\" of IP block: \\\"$drv_handle\\\" is not connected\\n\\r\"\n\t\t\t\tcontinue\n\t\t\t}\n\t\t\tset ip_name $intc\n\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || \\\n\t\t\t\t[string match -nocase $proctype \"psx_cortexa78\"] || [string match -nocase $proctype \"microblaze\"]} {\n\t\t\t\tif {[llength $intc] > 1} {\n\t\t\t\t\tforeach intr_cntr $intc {\n\t\t\t\t\t\tif { [::hsi::utils::is_ip_interrupting_current_proc $intr_cntr] } {\n\t\t\t\t\t\t\tset intc $intr_cntr\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] \"psu_cortexa53\"] && [string match -nocase $intc \"axi_intc\"] } {\n\t\t\t\t\tset intc [::hsi::utils::get_interrupt_parent $drv_handle $pin]\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] \"psv_cortexa72\"] && [string match -nocase $intc \"axi_intc\"] } {\n\t\t\t\t\tset intc [get_interrupt_parent $drv_handle $pin]\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] \"psx_cortexa78\"] && [string match -nocase $intc \"axi_intc\"] } {\n\t\t\t\t\tset intc [get_interrupt_parent $drv_handle $pin]\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\t\tif { [string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] \"axi_intc\"] } {\n\t\t\t\t\tset intr_id [get_psu_interrupt_id $drv_handle \"irq\"]\n\t\t\t\t} else {\n\t\t\t\t\tset intr_id [get_psu_interrupt_id $drv_handle $pin]\n\t\t\t\t}\n\t\t\t}\n\t\t\tif { [string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] \"ps7_cortexa9\"]} {\n\t\t\t\tif { [string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] \"axi_intc\"] } {\n\t\t\t\t\tset intr_id [::hsi::utils::get_interrupt_id $drv_handle \"irq\"]\n\t\t\t\t} else {\n\t\t\t\t\tset intr_id [::hsi::utils::get_interrupt_id $drv_handle $pin]\n\t\t\t\t}\n\t\t\t}\n\t\t\tif { [string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] \"microblaze\"]} {\n\t\t\t\tif {[string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] \"axi_intc\"] } {\n\t\t\t\t\tset intr_id [get_psu_interrupt_id $drv_handle \"irq\"]\n\t\t\t\t} else {\n\t\t\t\t\tset intr_id [get_psu_interrupt_id $drv_handle $pin]\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif {[string match -nocase $intr_id \"-1\"] && ![string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] \"axi_intc\"]} {\n\t\t\t\tcontinue\n\t\t\t}\n\t\t\tset intr_type [get_intr_type $intc $slave $pin]\n\t\t\tif {[string match -nocase $intr_type \"-1\"]} {\n\t\t\t\tcontinue\n\t\t\t}\n\n\t\t\tset cur_intr_info \"\"\n\t\t\tset valid_intc_list \"ps7_scugic psu_acpu_gic psv_acpu_gic psx_acpu_gic\"\n\t\t\tglobal intrpin_width\n\t\t\tif { [string match -nocase $proctype \"ps7_cortexa9\"] } {\n\t\t\t\tif {[string match \"[get_property IP_NAME $intc]\" \"ps7_scugic\"] } {\n\t\t\t\t\tif {$intr_id > 32} {\n\t\t\t\t\t\tset intr_id [expr $intr_id - 32]\n\t\t\t\t\t}\n\t\t\t\t\tset cur_intr_info \"0 $intr_id $intr_type\"\n\t\t\t\t} elseif {[string match \"[get_property IP_NAME $intc]\" \"axi_intc\"] } {\n\t\t\t\t\tset cur_intr_info \"$intr_id $intr_type\"\n\t\t\t\t}\n\t\t\t} elseif {[string match -nocase $intc \"psu_acpu_gic\"] \\\n\t\t\t\t|| [string match -nocase [get_property IP_NAME $intc] \"psv_acpu_gic\"] \\\n\t\t\t\t|| [string match -nocase [get_property IP_NAME $intc] \"psx_acpu_gic\"]} {\n\t\t\t set cur_intr_info \"0 $intr_id $intr_type\"\n\t\t\t for { set i 1 } {$i < $intrpin_width} {incr i} {\n\t\t\t\t set intr_id_inc [expr $intr_id + $i]\n\t\t\t\t append cur_intr_info \">, <0 $intr_id_inc $intr_type\"\n\t\t }\n\t\t\t} else {\n\t\t\t\tset cur_intr_info \"$intr_id $intr_type\"\n\t\t\t\tfor { set i 1 } {$i < $intrpin_width} {incr i} {\n\t\t\t\t\tset intr_id_inc [expr $intr_id + $i]\n\t\t\t\t\tappend cur_intr_info \">, <$intr_id_inc $intr_type\"\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[string_is_empty $intr_info]} {\n\t\t\t\tset intr_info \"$cur_intr_info\"\n\t\t\t} else {\n\t\t\t\tappend intr_info \" \" $cur_intr_info\n\t\t\t}\n\t\t}\n\t\t\tappend intr_names \" \" \"$pin\"\n\t\t\tappend intr_par \" \" \"$intc\"\n\t\t\tlappend intc_names \"$intc\" \"$cur_intr_info\"\n\t}\n\tif {[llength $intr_par] > 1 } {\n\t\tset int_ext 0\n\t\tset intc0 [lindex $intr_par 0]\n\t\tfor {set i 1} {$i < [llength $intr_par]} {incr i} {\n\t\t\tset intc [lindex $intr_par $i]\n\t\t\tif {![string match -nocase $intc0 $intc]} {\n\t\t\t\tset int_ext 1\n\t\t\t}\n\t\t}\n\t\tif {$int_ext == 1} {\n\t\t\tset intc_names [string map {psu_acpu_gic gic} $intc_names]\n\t\t\tset ref [lindex $intc_names 0]\n\t\t\tappend ref \" [lindex $intc_names 1]>, <&[lindex $intc_names 2] [lindex $intc_names 3]>, <&[lindex $intc_names 4] [lindex $intc_names 5]>,<&[lindex $intc_names 6] [lindex $intc_names 7]>, <&[lindex $intc_names 8] [lindex $intc_names 9]\"\n\t\t\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"v_hdmi_tx_ss\"] \\\n\t\t\t\t|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"v_hdmi_txss1\"]} {\n\t\t\t\tset_drv_prop_if_empty $drv_handle \"interrupts-extended\" $ref reference\n\t\t\t}\n\t\t}\n\t}\n\n\tif {[string_is_empty $intr_info]} {\n\t\treturn -1\n\t}\n global drv_handlers_mapping\n if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"vdu\"]} {\n dict lappend drv_handlers_mapping $drv_handle \"interrupts\" \"$intr_info\"\n } else {\n\t set_drv_prop $drv_handle interrupts $intr_info intlist\n }\n\n\tif {[string_is_empty $intc]} {\n\t\treturn -1\n\t}\n\tset intc [ps_node_mapping $intc label]\n\n\tif { $intc in { \"psu_acpu_gic\" \"psv_acpu_gic\" \"psx_acpu_gic\" }} {\n\t\tset intc \"gic\"\n\t}\n\tset add_intr_parent \"\"\n\tif { $intc == \"gic\" && ([string match -nocase $proctype \"psu_cortexa53\"] \\\n\t\t\t\t|| [string match -nocase $proctype \"psv_cortexa72\"] \\\n\t\t\t\t|| [string match -nocase $proctype \"psx_cortexa78\"])} {\n\t\tset add_intr_parent \"1\"\n\t} elseif { $intc == \"intc\" && [string match -nocase $proctype \"ps7_cortexa9\" ] } {\n\t\tset add_intr_parent \"1\"\n\t} else {\n\t\tset index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $intc]\n\t\tif {$index != -1 } {\n\t\t set add_intr_parent \"1\"\n\t\t}\n\t}\n if {[llength $add_intr_parent]} {\n if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"vdu\"]} {\n dict lappend drv_handlers_mapping $drv_handle \"interrupt-parent\" \"$intc\"\n } else {\n set_drv_prop $drv_handle interrupt-parent $intc reference\n }\n }\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"xdma\"]} {\n\t\tset msi_rx_pin_en [get_property CONFIG.msi_rx_pin_en [get_cells -hier $drv_handle]]\n\t\tif {[string match -nocase $msi_rx_pin_en \"true\"]} {\n\t\t\tset_drv_prop_if_empty $drv_handle \"interrupt-names\" $intr_names stringlist\n\t\t}\n\t} elseif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"vdu\"]} {\n dict lappend drv_handlers_mapping $drv_handle \"interrupt-names\" \"$intr_names\"\n } else {\n\t\tset_drv_prop_if_empty $drv_handle \"interrupt-names\" $intr_names stringlist\n\t}\n}\n\nproc gen_reg_property {drv_handle {skip_ps_check \"\"}} {\n\tproc_called_by\n\n\tif {[string_is_empty $skip_ps_check]} {\n\t\tif {[is_ps_ip $drv_handle]} {\n\t\t\treturn 0\n\t\t}\n\t}\n\tset ip_name [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tif { $ip_name in { \"xxv_ethernet\" \"ddr4\" \"mrmac\" \"dcmac\" \"vdu\" }} {\n\t\treturn\n\t}\n\n\tset reg \"\"\n\t#set ip_skip_list \"ddr4_*\"\n\tset slave [get_cells -hier ${drv_handle}]\n\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $slave]\n\tset base_val 0\n\tset high_val 0\n\tset size_val 0\n\tforeach mem_handle ${ip_mem_handles} {\n\t\tif {[string match -nocase $ip_name \"ai_engine\"]} {\n\t\t\tset base [string tolower [get_property BASE_VALUE $mem_handle]]\n\t\t\tset high [string tolower [get_property HIGH_VALUE $mem_handle]]\n\t\t\tset size [format 0x%x [expr {${high} - ${base} + 1}]]\n\t\t\tif { $base_val == 0 } {\n\t\t\t\tset base_val $base\n\t\t\t}\n\t\t\tif { $high > $high_val } {\n\t\t\t\tset high_val $high\n\t\t\t}\n\t\t}\n\t}\n\tforeach mem_handle ${ip_mem_handles} {\n\t#\tif {![regexp $ip_skip_list $mem_handle match]} {\n\t\t\tset base [string tolower [get_property BASE_VALUE $mem_handle]]\n\t\t\tset ips [get_cells -hier -filter {IP_NAME == \"mrmac\"}]\n\t\t\tif {[llength $ips]} {\n\t\t\t\tif {[string match -nocase $base \"0xa4010000\"] && $ip_name == \"axi_gpio\"} {\n\t\t\t\t\treturn\n\t\t\t\t}\n\t\t\t}\n\t\t\tset high [string tolower [get_property HIGH_VALUE $mem_handle]]\n\t\t\tset size [format 0x%x [expr {${high} - ${base} + 1}]]\n\t\t\tif {[string match -nocase $ip_name \"ai_engine\"]} {\n\t\t\t\tset ip [get_cells -hier $drv_handle]\n\t\t\t\tset high $high_val\n\t\t\t\tset base $base_val\n\t\t\t\tset size [format 0x%x [expr {${high_val} - ${base} + 1}]]\n\t\t\t}\n\t\t\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\t\tif {[string_is_empty $reg]} {\n\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\t\t\t# check if base address is 64bit and split it as MSB and LSB\n\t\t\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$base\" match]} {\n\t\t\t\t\t\tset temp $base\n\t\t\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\t\t\tset len [string length $temp]\n\t\t\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\t\t\tset high_base \"0x[string range $temp $rem $len]\"\n\t\t\t\t\t\tset low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\t\t\tset low_base [format 0x%08x $low_base]\n\t\t\t\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$size\" match]} {\n\t\t\t\t\t\t\tset temp $size\n\t\t\t\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\t\t\t\tset len [string length $temp]\n\t\t\t\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\t\t\t\tset high_size \"0x[string range $temp $rem $len]\"\n\t\t\t\t\t\t\tset low_size \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\t\t\t\tset low_size [format 0x%08x $low_size]\n\t\t\t\t\t\t\tset reg \"$low_base $high_base $low_size $high_size\"\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tset reg \"$low_base $high_base 0x0 $size\"\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tset reg \"0x0 $base 0x0 $size\"\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tset reg \"$base $size\"\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif {[string match -nocase $proctype \"ps7_cortexa9\"] || [string match -nocase $proctype \"microblaze\"]} {\n\t\t\t\t\tset index [check_base $reg $base $size]\n\t\t\t\t\tif {$index == \"true\"} {\n\t\t\t\t\t\tcontinue\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\t\t\tset index [check_64_base $reg $base $size]\n\t\t\t\t\tif {$index == \"true\"} {\n\t\t\t\t\t\tcontinue\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t# ensure no duplication\n\t\t\t\tif {![regexp \".*${reg}.*\" \"$base $size\" matched]} {\n\t\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\t\t\t\tset base1 \"0x0 $base\"\n\t\t\t\t\t\tset size1 \"0x0 $size\"\n\t\t\t\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$base\" match]} {\n\t\t\t\t\t set temp $base\n\t\t\t\t\t set temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\t\t set len [string length $temp]\n\t\t\t\t\t set rem [expr {${len} - 8}]\n\t\t\t\t\t set high_base \"0x[string range $temp $rem $len]\"\n\t\t\t\t\t set low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\t\t set low_base [format 0x%08x $low_base]\n\t\t\t\t\t\t\tset base1 \"$low_base $high_base\"\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$size\" match]} {\n\t\t\t\t\t\t\tset temp $size\n\t\t\t\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\t\t\t\tset len [string length $temp]\n\t\t\t\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\t\t\t\tset high_size \"0x[string range $temp $rem $len]\"\n\t\t\t\t\t\t\tset low_size \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\t\t\t\tset low_size [format 0x%08x $low_size]\n\t\t\t\t\t\t\tset size1 \"$low_size $high_size\"\n\t\t\t\t\t\t}\n\t\t\t\t\t\tset reg \"$reg $base1 $size1\"\n\t\t\t\t\t} else {\n\t\t\t\t\t\tset reg \"$reg $base $size\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t#\t}\n\t}\n\tset_drv_prop_if_empty $drv_handle reg $reg intlist\n}\n\nproc check_64_base {reg base size} {\n\tset high_base 0xdeadbeef\n\tset low_base 0\n\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$base\" match]} {\n\t\tset temp $base\n\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\tset len [string length $temp]\n\t\tset rem [expr {${len} - 8}]\n\t\tset high_base \"0x[string range $temp $rem $len]\"\n\t\tset low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\tset low_base [format 0x%08x $low_base]\n\t}\n\tset len [llength $reg]\n\tswitch $len {\n\t\t\"4\" {\n\t\t\tset base_index0 [lindex $reg 0]\n\t\t\tset base_index1 [lindex $reg 1]\n\t\t\tif {$high_base != 0xdeadbeef} {\n\t\t\t\tif {$base_index0 == $low_base && $base_index1 == $high_base} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif {$base_index1 == $base} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t\"8\" {\n\t\t\tset base_index0 [lindex $reg 0]\n\t\t\tset base_index1 [lindex $reg 1]\n\t\t\tset base_index4 [lindex $reg 4]\n\t\t\tset base_index5 [lindex $reg 5]\n\t\t\tif {$high_base != 0xdeadbeef} {\n\t\t\t\tif {$base_index0 == $low_base && $base_index1 == $high_base} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t\tif {$base_index4 == $low_base && $base_index5 == $high_base} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif {$base_index1 == $base} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t\tif {$base_index5 == $base} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t\"12\" {\n\t\t\tset base_index0 [lindex $reg 0]\n\t\t\tset base_index1 [lindex $reg 1]\n\t\t\tset base_index4 [lindex $reg 4]\n\t\t\tset base_index5 [lindex $reg 5]\n\t\t\tset base_index8 [lindex $reg 8]\n\t\t\tset base_index9 [lindex $reg 9]\n\t\t\tif {$high_base != 0xdeadbeef} {\n\t\t\t\tif {$base_index0 == $low_base && $base_index1 == $high_base} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t\tif {$base_index4 == $low_base && $base_index5 == $high_base} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t\tif {$base_index8 == $low_base && $base_index9 == $high_base} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif {$base_index1 == $base} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t\tif {$base_index5 == $base} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t\tif {$base_index9 == $base} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc check_base {reg base size} {\n\tset len [llength $reg]\n\tswitch $len {\n\t\t\"2\" {\n\t\t\tset base_index0 [lindex $reg 0]\n\t\t\tset size_index0 [lindex $reg 1]\n\t\t\tif {$base_index0 == $base || $size_index0 == $size} {\n\t\t\t\treturn true\n\t\t\t}\n\t\t}\n\t\t\"4\" {\n\t\t\tset base_index0 [lindex $reg 0]\n\t\t\tset size_index0 [lindex $reg 1]\n\t\t\tset base_index1 [lindex $reg 2]\n\t\t\tset size_index1 [lindex $reg 3]\n\t\t\tif {$base_index0 == $base || $base_index1 == $base} {\n\t\t\t\tif {$size_index0 == $size || $size_index1 == $size} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t\"6\" {\n\t\t\tset base_index0 [lindex $reg 0]\n\t\t\tset size_index0 [lindex $reg 1]\n\t\t\tset base_index1 [lindex $reg 2]\n\t\t\tset size_index1 [lindex $reg 3]\n\t\t\tset base_index2 [lindex $reg 4]\n\t\t\tset size_index2 [lindex $reg 5]\n\t\t\tif {$base_index0 == $base || $base_index1 == $base || $base_index2 == $base} {\n\t\t\t\tif {$size_index0 == $size || $size_index1 == $size || $size_index2 == $size} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t\"8\" {\n\t\t\tset base_index0 [lindex $reg 0]\n\t\t\tset size_index0 [lindex $reg 1]\n\t\t\tset base_index1 [lindex $reg 2]\n\t\t\tset size_index1 [lindex $reg 3]\n\t\t\tset base_index2 [lindex $reg 4]\n\t\t\tset size_index2 [lindex $reg 5]\n\t\t\tset base_index3 [lindex $reg 6]\n\t\t\tset size_index3 [lindex $reg 7]\n\t\t\tif {$base_index0 == $base || $base_index1 == $base || $base_index2 == $base || $base_index3 == $base} {\n\t\t\t\tif {$size_index0 == $size || $size_index1 == $size || $size_index2 == $size || $size_index3 == $size} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t\"10\" {\n\t\t\tset base_index0 [lindex $reg 0]\n\t\t\tset size_index0 [lindex $reg 1]\n\t\t\tset base_index1 [lindex $reg 2]\n\t\t\tset size_index1 [lindex $reg 3]\n\t\t\tset base_index2 [lindex $reg 4]\n\t\t\tset size_index2 [lindex $reg 5]\n\t\t\tset base_index3 [lindex $reg 6]\n\t\t\tset size_index3 [lindex $reg 7]\n\t\t\tset base_index4 [lindex $reg 8]\n\t\t\tset size_index4 [lindex $reg 9]\n\t\t\tif {$base_index0 == $base || $base_index1 == $base || $base_index2 == $base || $base_index3 == $base || $base_index4 == $base} {\n\t\t\t\tif {$size_index0 == $size || $size_index1 == $size || $size_index2 == $size || $size_index3 == $size || $size_index4 == $size} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t\"12\" {\n\t\t\tset base_index0 [lindex $reg 0]\n\t\t\tset size_index0 [lindex $reg 1]\n\t\t\tset base_index1 [lindex $reg 2]\n\t\t\tset size_index1 [lindex $reg 3]\n\t\t\tset base_index2 [lindex $reg 4]\n\t\t\tset size_index2 [lindex $reg 5]\n\t\t\tset base_index3 [lindex $reg 6]\n\t\t\tset size_index3 [lindex $reg 7]\n\t\t\tset base_index4 [lindex $reg 8]\n\t\t\tset size_index4 [lindex $reg 9]\n\t\t\tset base_index5 [lindex $reg 10]\n\t\t\tset size_index5 [lindex $reg 11]\n\t\t\tif {$base_index0 == $base || $base_index1 == $base || $base_index2 == $base || $base_index3 == $base || $base_index4 == $base || $base_index5 == $base} {\n\t\t\t\tif {$size_index0 == $size || $size_index1 == $size || $size_index2 == $size || $size_index3 == $size || $size_index4 == $size || $size_index5 == $size} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t\"14\" {\n\t\t\tset base_index0 [lindex $reg 0]\n\t\t\tset size_index0 [lindex $reg 1]\n\t\t\tset base_index1 [lindex $reg 2]\n\t\t\tset size_index1 [lindex $reg 3]\n\t\t\tset base_index2 [lindex $reg 4]\n\t\t\tset size_index2 [lindex $reg 5]\n\t\t\tset base_index3 [lindex $reg 6]\n\t\t\tset size_index3 [lindex $reg 7]\n\t\t\tset base_index4 [lindex $reg 8]\n\t\t\tset size_index4 [lindex $reg 9]\n\t\t\tset base_index5 [lindex $reg 10]\n\t\t\tset size_index5 [lindex $reg 11]\n\t\t\tset base_index6 [lindex $reg 12]\n\t\t\tset size_index6 [lindex $reg 13]\n\t\t\tif {$base_index0 == $base || $base_index1 == $base || $base_index2 == $base || $base_index3 == $base || $base_index4 == $base || $base_index5 == $base || $base_index6 == $base} {\n\t\t\t\tif {$size_index0 == $size || $size_index1 == $size || $size_index2 == $size || $size_index3 == $size || $size_index4 == $size || $size_index5 == $size || $size_index6 == $size} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t\"16\" {\n\t\t\tset base_index0 [lindex $reg 0]\n\t\t\tset size_index0 [lindex $reg 1]\n\t\t\tset base_index1 [lindex $reg 2]\n\t\t\tset size_index1 [lindex $reg 3]\n\t\t\tset base_index2 [lindex $reg 4]\n\t\t\tset size_index2 [lindex $reg 5]\n\t\t\tset base_index3 [lindex $reg 6]\n\t\t\tset size_index3 [lindex $reg 7]\n\t\t\tset base_index4 [lindex $reg 8]\n\t\t\tset size_index4 [lindex $reg 9]\n\t\t\tset base_index5 [lindex $reg 10]\n\t\t\tset size_index5 [lindex $reg 11]\n\t\t\tset base_index6 [lindex $reg 12]\n\t\t\tset size_index6 [lindex $reg 13]\n\t\t\tset base_index7 [lindex $reg 14]\n\t\t\tset size_index7 [lindex $reg 15]\n\t\t\tif {$base_index0 == $base || $base_index1 == $base || $base_index2 == $base || $base_index3 == $base || $base_index4 == $base || $base_index5 == $base || $base_index6 == $base || $base_index7 == $base} {\n\t\t\t\tif {$size_index0 == $size || $size_index1 == $size || $size_index2 == $size || $size_index3 == $size || $size_index4 == $size || $size_index5 == $size || $size_index6 == $size || $size_index7 == $size} {\n\t\t\t\t\treturn true\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc gen_compatible_property {drv_handle} {\n\tproc_called_by\n\n\tif {[is_ps_ip $drv_handle]} {\n\t\treturn 0\n\t}\n\n\tset reg \"\"\n\tset slave [get_cells -hier ${drv_handle}]\n\tset vlnv [split [get_property VLNV $slave] \":\"]\n\tset name [lindex $vlnv 2]\n\tset ver [lindex $vlnv 3]\n\tset comp_prop \"xlnx,${name}-${ver}\"\n\tregsub -all {_} $comp_prop {-} comp_prop\n\tset_drv_prop_if_empty $drv_handle compatible $comp_prop stringlist\n}\n\nproc is_property_set {value} {\n if {[string compare -nocase $value \"true\"] == 0} {\n return 1\n }\n return 0\n}\n\nproc ip2drv_prop {ip_name ip_prop_name} {\n\tset drv_handle [get_ip_handler $ip_name]\n\tset ip [get_cells -hier $ip_name]\n\tset emac [get_property IP_NAME $ip]\n\n\tif { $emac == \"axi_ethernet\"} {\n\t\t# remove CONFIG.\n\t\tset prop [get_property $ip_prop_name [get_cells -hier $ip_name]]\n\t\tset drv_prop_name $ip_prop_name\n\t\tregsub -all {CONFIG.} $drv_prop_name {xlnx,} drv_prop_name\n\t\tregsub -all {_} $drv_prop_name {-} drv_prop_name\n\t\tset drv_prop_name [string tolower $drv_prop_name]\n\t\tadd_cross_property $ip $ip_prop_name $drv_handle ${drv_prop_name} hexint\n\t\treturn\n\t}\n\n\t# remove CONFIG.C_\n\tset drv_prop_name $ip_prop_name\n\tregsub -all {CONFIG.C_} $drv_prop_name {xlnx,} drv_prop_name\n\tregsub -all {_} $drv_prop_name {-} drv_prop_name\n\tset drv_prop_name [string tolower $drv_prop_name]\n\tadd_cross_property $ip $ip_prop_name $drv_handle ${drv_prop_name} hexint\n}\n\nproc gen_drv_prop_from_ip {drv_handle} {\n\t# check if we should generating the ip properties or not\n\tset gen_ip_prop [get_drv_conf_prop_list $drv_handle \"CONFIG.dtg.ip_params\"]\n\tif {[string_is_empty $gen_ip_prop]} {\n\t\treturn 0\n\t}\n\tset prop_name_list [default_parameters $drv_handle]\n\tforeach prop_name ${prop_name_list} {\n\t\tip2drv_prop $drv_handle $prop_name\n\t}\n}\n\n# based on libgen dtg\nproc default_parameters {ip_handle {dont_generate \"\"}} {\n\tset par_handles [get_ip_conf_prop_list $ip_handle \"CONFIG.C_.*\"]\n\tset valid_prop_names {}\n\tforeach par $par_handles {\n\t\tregsub -all {CONFIG.} $par {} tmp_par\n\t\t# Ignore some parameters that are always handled specially\n\t\tswitch -glob $tmp_par {\n\t\t\t$dont_generate - \\\n\t\t\t\"INSTANCE\" - \\\n\t\t\t\"C_INSTANCE\" - \\\n\t\t\t\"*BASEADDR\" - \\\n\t\t\t\"*HIGHADDR\" - \\\n\t\t\t\"C_SPLB*\" - \\\n\t\t\t\"C_DPLB*\" - \\\n\t\t\t\"C_IPLB*\" - \\\n\t\t\t\"C_PLB*\" - \\\n\t\t\t\"M_AXI*\" - \\\n\t\t\t\"C_M_AXI*\" - \\\n\t\t\t\"S_AXI_ADDR_WIDTH\" - \\\n\t\t\t\"C_S_AXI_ADDR_WIDTH\" - \\\n\t\t\t\"S_AXI_DATA_WIDTH\" - \\\n\t\t\t\"C_S_AXI_DATA_WIDTH\" - \\\n\t\t\t\"S_AXI_ACLK_FREQ_HZ\" - \\\n\t\t\t\"C_S_AXI_ACLK_FREQ_HZ\" - \\\n\t\t\t\"S_AXI_LITE*\" - \\\n\t\t\t\"C_S_AXI_LITE*\" - \\\n\t\t\t\"S_AXI_PROTOCOL\" - \\\n\t\t\t\"C_S_AXI_PROTOCOL\" - \\\n\t\t\t\"*INTERCONNECT_?_AXI*\" - \\\n\t\t\t\"*S_AXI_ACLK_PERIOD_PS\" - \\\n\t\t\t\"M*_AXIS*\" - \\\n\t\t\t\"C_M*_AXIS*\" - \\\n\t\t\t\"S*_AXIS*\" - \\\n\t\t\t\"C_S*_AXIS*\" - \\\n\t\t\t\"PRH*\" - \\\n\t\t\t\"C_FAMILY\" - \\\n\t\t\t\"FAMILY\" - \\\n\t\t\t\"*CLK_FREQ_HZ\" - \\\n\t\t\t\"*ENET_SLCR_*Mbps_DIV?\" - \\\n\t\t\t\"HW_VER\" { } \\\n\t\t\tdefault {\n\t\t\t\tlappend valid_prop_names $par\n\t\t\t}\n\t\t}\n\t}\n\treturn $valid_prop_names\n}\n\nproc ps7_reset_handle {drv_handle reset_pram conf_prop} {\n\tset src_ip -1\n\tset value -1\n\tset ip [get_cells -hier $drv_handle]\n\tset value [get_property ${reset_pram} $ip]\n\t# workaround for reset not been selected and show as \"\" $value \"\" value\n\tif {[llength $value]} {\n\t\t# if MIO, assume gpio0 (bad assumption as this needs to match zynq-7000.dtsi)\n\t\tif {[regexp \"^MIO\" $value matched]} {\n\t\t\t# switch with kernel version\n\t\t\tset kernel_ver [get_property CONFIG.kernel_version [get_os]]\n\t\t\tswitch -exact $kernel_ver {\n\t\t\t\tdefault {\n\t\t\t\t\tset src_ip \"gpio0\"\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tregsub -all \"MIO( |)\" $value \"\" value\n\t\tif {$src_ip != \"-1\"} {\n\t\t\tif {$value != \"-1\" && [llength $value] !=0} {\n\t\t\t\tregsub -all \"CONFIG.\" $conf_prop \"\" conf_prop\n\t\t\t\tset_drv_property $drv_handle ${conf_prop} \"$src_ip $value 0\" reference\n\t\t\t}\n\t\t}\n\t} else {\n\t\tdtg_warning \"$drv_handle: No reset found\"\n\t\treturn -1\n\t}\n}\n\nproc gen_peripheral_nodes {drv_handle {node_only \"\"}} {\n\t# Check if the peripheral is in Secure or Non-secure zone\n\tif {[check_ip_trustzone_state $drv_handle] == 1} {\n\t\treturn\n\t}\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tif {[is_pl_ip $drv_handle] && $remove_pl} {\n\t\treturn 0\n\t}\n\tset status_enable_flow 0\n\tset ip [get_cells -hier $drv_handle]\n\t# TODO: check if the base address is correct\n\tset unit_addr [get_baseaddr ${ip} no_prefix]\n\tif { [string equal $unit_addr \"-1\"] } {\n\t\treturn 0\n\t}\n\tset label $drv_handle\n\tset label_len [string length $label]\n\tif {$label_len >= 31} {\n\t\t# As per the device tree specification the label length should be maximum of 31 characters\n\t\tdtg_verbose \"the label \\\"$label\\\" length is $label_len characters which is greater than default 31 characters as per DT SPEC...user need to fix the label\\n\\r\"\n\t}\n\tset dev_type [get_property CONFIG.dev_type $drv_handle]\n\tif {[string_is_empty $dev_type] == 1} {\n\t\tset dev_type [get_property IP_NAME [get_cell -hier $ip]]\n\t}\n\tset proc_type [get_sw_proc_prop IP_NAME]\n\tif {[string match -nocase $proc_type \"psv_cortexa72\"] } {\n\t\tset ip_type [get_property IP_NAME $ip]\n\t\t# For psv_cpm BASE_VALUE is different than the node unitaddr from versal.dtsi\n\t\t# So reading proper xsct configs to add status okay\n\t\tif {[string match -nocase $ip_type \"psv_cpm\"]} {\n\t\t\tset rev_num -1\n\t\t\tset cpm_unit_addr \"\"\n\t\t\tforeach drv [get_cells -hier -filter IP_NAME==psv_cpm] {\n\t\t\t\tif {![regexp \"pspmc.*\" \"$drv\" match]} {\n\t\t\t\t\tset rev_num [llength [get_cells -hier $drv -filter CONFIG.CPM_REVISION_NUMBER==1]]\n\t\t\t\t}\n\t\t\t}\n\t\t\t#for CPM4 designs the revision number will be 0\n\t\t\t#for CPM5 designs the revision number will be 1\n\t\t\tif {$rev_num == 0} {\n\t\t\t\t# CONFIG.CPM_SLCR is for cpm4\n\t\t\t\tset cpm_unit_addr [get_property CONFIG.CPM_SLCR [get_cells -hier $ip]]\n\t\t\t} elseif {$rev_num == 1} {\n\t\t\t\t# CONFIG.CPM5_SLCR_ADDR is for cpm5\n\t\t\t\tset cpm_unit_addr [get_property CONFIG.CPM5_SLCR_ADDR [get_cells -hier $ip]]\n\t\t\t}\n\t\t\tif {[llength $cpm_unit_addr]} {\n\t\t\t\tset unit_addr [string tolower $cpm_unit_addr]\n\t\t\t\tregsub -all {^0x} $unit_addr {} unit_addr\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $ip_type \"psv_cpm_slcr\"]} {\n\t\t\tset versal_periph [get_cells -hier -filter {IP_NAME == versal_cips || IP_NAME == ps_wizard}]\n\t\t\tif {[llength $versal_periph]} {\n\t\t\t\tset avail_param [list_property [get_cells -hier $versal_periph]]\n\t\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.CPM_PCIE0_PORT_TYPE\"] >= 0} {\n\t\t\t\t\tset val [get_property CONFIG.CPM_PCIE0_PORT_TYPE [get_cells -hier $versal_periph]]\n\t\t\t\t\tif {[string match -nocase $val \"Root_Port_of_PCI_Express_Root_Complex\"]} {\n\t\t\t\t\t\t#For Root port device tree entry should be set Okay\n\t\t\t\t\t} else {\n\t\t\t\t\t\t# For Non-Root port(PCI_Express_Endpoint_device) there should not be any device tree entry in DTS\n\t\t\t\t\t\treturn 0\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\t# TODO: more ignore ip list?\n\tset ip_type [get_property IP_NAME $ip]\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset ignore_list \"lmb_bram_if_cntlr PERIPHERAL axi_noc axi_noc2\"\n\t} else {\n\t\tset ignore_list \"lmb_bram_if_cntlr PERIPHERAL axi_noc axi_noc2\"\n\t}\n\tif {[string match -nocase $ip_type \"psu_pcie\"]} {\n\t\tset pcie_config [get_property CONFIG.C_PCIE_MODE [get_cells -hier $drv_handle]]\n\t\tif {[string match -nocase $pcie_config \"Endpoint Device\"]} {\n\t\t\tlappend ignore_list $ip_type\n\t\t}\n\t}\n\tif {[lsearch $ignore_list $ip_type] >= 0 \\\n\t\t} {\n\t\treturn 0\n\t}\n\tset default_dts [set_drv_def_dts $drv_handle]\n\n\tset ps7_mapping [gen_ps7_mapping]\n\tset bus_node [add_or_get_bus_node $ip $default_dts]\n\n\tset status_enable_flow 0\n\tset status_disabled 0\n\tif {[is_ps_ip $drv_handle]} {\n\t\tset tmp [get_ps_node_unit_addr $drv_handle]\n\t\tif {$tmp != -1} {set unit_addr $tmp}\n\t\tif {[catch {set tmp [dict get $ps7_mapping $unit_addr label]} msg]} {\n\t\t\t# CHK: if PS IP that's not in the zynq-7000 dtsi, do not generate it\n\t\t\treturn 0\n\t\t}\n\t\tif {![string_is_empty $tmp]} {\n\t\t\tset status_enable_flow 1\n\t\t}\n\t\tif {[catch {set tmp [dict get $ps7_mapping $unit_addr status]} msg]} {\n\t\t\tset status_disabled 0\n\t\t}\n\t\tif {[string equal -nocase \"disabled\" $tmp]} {\n\t\t\tset status_disabled 1\n\t\t}\n\t}\n\tif {$status_enable_flow} {\n\t\tset label [dict get $ps7_mapping $unit_addr label]\n\t\tset dev_type [dict get $ps7_mapping $unit_addr name]\n\t\tset bus_node \"\"\n\t\t# check if it has status property\n\t\tset rt_node [add_or_get_dt_node -n ${dev_type} -l ${label} -u ${unit_addr} -d ${default_dts} -p $bus_node -auto_ref_parent]\n\t\tif {[string match -nocase $rt_node \"&dwc3_0\"]} {\n\t\t\tset proc_type [get_sw_proc_prop IP_NAME]\n\t\t\t\tif {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n\t\t\t\t\tset zynq_periph [get_cells -hier -filter {IP_NAME == zynq_ultra_ps_e}]\n\t\t\t\t\tset avail_param [list_property [get_cells -hier $zynq_periph]]\n\t\t\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__USB0__PERIPHERAL__ENABLE\"] >= 0} {\n\t\t\t\t\t\tset value [get_property CONFIG.PSU__USB0__PERIPHERAL__ENABLE [get_cells -hier $zynq_periph]]\n\t\t\t\t\t\tif {$value == 1} {\n\t\t\t\t\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE\"] >= 0} {\n\t\t\t\t\t\t\t\tset val [get_property CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE [get_cells -hier $zynq_periph]]\n\t\t\t\t\t\t\t\tif {$val == 0} {\n\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${rt_node}\" \"maximum-speed\" \"high-speed\" stringlist\n\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${rt_node}\" \"snps,dis_u2_susphy_quirk\" \"\" boolean\n\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${rt_node}\" \"snps,dis_u3_susphy_quirk\" \"\" boolean\n\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${rt_node}\" \"/delete-property/ phy-names\" \"\" boolean\n\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${rt_node}\" \"/delete-property/ phys\" \"\" boolean\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $rt_node \"&dwc3_1\"]} {\n\t\t\tset proc_type [get_sw_proc_prop IP_NAME]\n\t\t\t\tif {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n\t\t\t\t\tset zynq_periph [get_cells -hier -filter {IP_NAME == zynq_ultra_ps_e}]\n\t\t\t\t\tset avail_param [list_property [get_cells -hier $zynq_periph]]\n\t\t\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__USB1__PERIPHERAL__ENABLE\"] >= 0} {\n\t\t\t\t\t\tset value [get_property CONFIG.PSU__USB1__PERIPHERAL__ENABLE [get_cells -hier $zynq_periph]]\n\t\t\t\t\t\tif {$value == 1} {\n\t\t\t\t\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE\"] >= 0} {\n\t\t\t\t\t\t\t\tset val [get_property CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE [get_cells -hier $zynq_periph]]\n\t\t\t\t\t\t\t\tif {$val == 0} {\n\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${rt_node}\" \"maximum-speed\" \"high-speed\" stringlist\n\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${rt_node}\" \"snps,dis_u2_susphy_quirk\" \"\" boolean\n\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${rt_node}\" \"snps,dis_u3_susphy_quirk\" \"\" boolean\n\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${rt_node}\" \"/delete-property/ phy-names\" \"\" boolean\n\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${rt_node}\" \"/delete-property/ phys\" \"\" boolean\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t}\n\t\tif {$status_disabled} {\n\t\t\tif {[string match -nocase $ip_type \"psu_smmu_gpv\"]} {\n\t\t\t\treturn\n\t\t\t}\n\t\t\thsi::utils::add_new_dts_param \"${rt_node}\" \"status\" \"okay\" string\n\t\t}\n\t} else {\n\t\tif {[string match -nocase $ip_type \"tsn_endpoint_ethernet_mac\"]} {\n\t\t\tset rt_node [add_or_get_dt_node -n tsn_endpoint_ip_0 -l tsn_endpoint_ip_0 -d ${default_dts} -p $bus_node -auto_ref_parent]\n\t\t} else {\n\t\t\tset rt_node [add_or_get_dt_node -n ${dev_type} -l ${label} -u ${unit_addr} -d ${default_dts} -p $bus_node -auto_ref_parent]\n\t\t}\n\t}\n\n\tif {![string_is_empty $node_only]} {\n\t\treturn $rt_node\n\t}\n\n\tzynq_gen_pl_clk_binding $drv_handle\n\t# generate mb ccf node\n\tgenerate_mb_ccf_node $drv_handle\n\n\tgenerate_cci_node $drv_handle $rt_node\n\tset dts_file_list \"\"\n\tif {[catch {set rt [report_property -return_string -regexp $drv_handle \"CONFIG.*\\\\.dts(i|)\"]} msg]} {\n\t\tset rt \"\"\n\t}\n\tforeach line [split $rt \"\\n\"] {\n\t\tregsub -all {\\s+} $line { } line\n\t\tif {[regexp \"CONFIG.*\\\\.dts(i|)\" $line matched]} {\n\t\t\tlappend dts_file_list [lindex [split $line \" \"] 0]\n\t\t}\n\t}\n\tregsub -all {CONFIG.} $dts_file_list {} dts_file_list\n\n\tset drv_dt_prop_list [get_driver_conf_list $drv_handle]\n\tforeach dts_file ${dts_file_list} {\n\t\tset dts_prop_list [get_property CONFIG.${dts_file} $drv_handle]\n\t\tset dt_node \"\"\n\t\tif {[string_is_empty ${dts_prop_list}] == 0} {\n\t\t\tset dt_node [add_or_get_dt_node -n ${dev_type} -l ${label} -u ${unit_addr} -d ${dts_file} -p $bus_node]\n\t\t\tforeach prop ${dts_prop_list} {\n\t\t\t\tadd_driver_prop $drv_handle $dt_node CONFIG.${prop}\n\t\t\t\t# remove from default list\n\t\t\t\tset drv_dt_prop_list [list_remove_element $drv_dt_prop_list \"CONFIG.${prop}\"]\n\t\t\t}\n\t\t}\n\t}\n\n\t# update rest of properties to dt node\n\tforeach drv_prop_name $drv_dt_prop_list {\n\t\tadd_driver_prop $drv_handle $rt_node ${drv_prop_name}\n\t}\n\treturn $rt_node\n}\n\nproc detect_bus_label {bus_name} {\n\t# Using amba_pl as label for pl-bus node\n\t# to support backward compatibility\n\tif {[regexp \"pl-bus\" $bus_name match]} {\n\t\treturn \"amba_pl\"\n\t}\n\treturn $bus_name\n}\n\nproc detect_fpga_noderef {} {\n\tset proc_name [get_property IP_NAME [get_cell -hier [get_sw_processor]]]\n\tif {[string match -nocase $proc_name \"psv_cortexa72\"] || [string match -nocase $proc_name \"psx_cortexa78\"]} {\n\t\tset targets \"&fpga\"\n\t} else {\n\t\tset targets \"&fpga_full\"\n\t}\n\treturn $targets\n}\n\nproc detect_bus_name {ip_drv} {\n\t# FIXME: currently use single bus assumption\n\t# TODO: detect bus connection\n\t# \tzynq: uses amba base zynq-7000.dtsi\n\t#\t\tpl ip creates amba_pl\n\t# \tmb: detection is required (currently always call amba_pl)\n\tset valid_buses [get_cells -hier -filter { IP_TYPE == \"BUS\" && IP_NAME != \"axi_protocol_converter\" && IP_NAME != \"lmb_v10\"}]\n\n\tset proc_name [get_property IP_NAME [get_cell -hier [get_sw_processor]]]\n\tset valid_proc_list \"ps7_cortexa9 psu_cortexa53 psv_cortexa72 psx_cortexa78\"\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {[is_pl_ip $ip_drv] && $remove_pl} {\n\t\treturn 0\n\t}\n\tif {[lsearch -nocase $valid_proc_list $proc_name] >= 0} {\n\t\tif {[is_pl_ip $ip_drv]} {\n\t\t\t# create the parent_node for pl.dtsi\n\t\t\tset default_dts [set_drv_def_dts $ip_drv]\n\t\t\tif {!$dt_overlay} {\n\t\t\t\tset root_node [add_or_get_dt_node -n / -d ${default_dts}]\n\t\t\t}\n\t\t\treturn \"pl-bus\"\n\t\t}\n\t\treturn \"amba\"\n\t}\n\n\treturn \"pl-bus\"\n}\n\nproc get_afi_val {val} {\n\tset afival \"\"\n\tswitch $val {\n\t\t\"128\" {\n\t\t\tset afival 0\n\t\t} \"64\" {\n\t\t\tset afival 1\n\t\t} \"32\" {\n\t\t\tset afival 2\n\t\t} default {\n\t\t\tdtg_warning \"invalid value:$val\"\n\t\t}\n\t}\n\treturn $afival\n}\n\nproc get_max_afi_val {val} {\n\tset max_afival \"\"\n\tswitch $val {\n\t\t\"128\" {\n\t\t\tset max_afival 2\n\t\t} \"64\" {\n\t\t\tset max_afival 1\n\t\t} \"32\" {\n\t\t\tset max_afival 0\n\t\t} default {\n\t\t\tdtg_warning \"invalid value:$val\"\n\t\t}\n\t}\n\treturn $max_afival\n}\n\nproc get_axi_datawidth {val} {\n\tset data_width \"\"\n\tswitch $val {\n\t\t\"32\" {\n\t\t\tset data_width 1\n\t\t} \"64\" {\n\t\t\tset data_width 0\n\t\t} default {\n\t\t\tdtg_warning \"invalid data_width:$val\"\n\t\t}\n\t}\n\treturn $data_width\n}\n\nproc add_or_get_bus_node {ip_drv dts_file} {\n\tset bus_name [detect_bus_name $ip_drv]\n\tset bus_label [detect_bus_label $bus_name]\n\tdtg_debug \"bus_name: $bus_name\"\n\tdtg_debug \"bus_label: $bus_label\"\n\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tif {[is_pl_ip $ip_drv] && $remove_pl} {\n\t\treturn 0\n\t}\n\tif {$dt_overlay && [string match -nocase $dts_file \"pl.dtsi\"]} {\n\t\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\tset zynq_periph [get_cells -hier -filter {IP_NAME == zynq_ultra_ps_e}]\n\t\t\tset avail_param [list_property [get_cells -hier $zynq_periph]]\n\t\t\tset targets \"amba\"\n\t\t\tset fpga_node [add_or_get_dt_node -n \"&$targets\" -d [get_dt_tree ${dts_file}]]\n\t\t\tset bus_node \"$fpga_node\"\n\t\t\tset RpRm [get_rp_rm_for_drv $ip_drv]\n\t\t\tregsub -all { } $RpRm \"\" RpRm\n\t\t\tset config_afi \" \"\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_SAXIGP0_DATA_WIDTH\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_SAXIGP0_DATA_WIDTH [get_cells -hier $zynq_periph]]\n\t\t\t\tset afival [get_afi_val $val]\n\t\t\t\tappend config_afi \"0 $afival>, <1 $afival>,\"\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_SAXIGP1_DATA_WIDTH\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_SAXIGP1_DATA_WIDTH [get_cells -hier $zynq_periph]]\n\t\t\t\tset afival [get_afi_val $val]\n\t\t\t\tappend config_afi \" <2 $afival>, <3 $afival>,\"\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_SAXIGP2_DATA_WIDTH\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_SAXIGP2_DATA_WIDTH [get_cells -hier $zynq_periph]]\n\t\t\t\tset afival [get_afi_val $val]\n\t\t\t\tappend config_afi \" <4 $afival>, <5 $afival>,\"\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_SAXIGP3_DATA_WIDTH\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_SAXIGP3_DATA_WIDTH [get_cells -hier $zynq_periph]]\n\t\t\t\tset afival [get_afi_val $val]\n\t\t\t\tappend config_afi \" <6 $afival>, <7 $afival>,\"\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_SAXIGP4_DATA_WIDTH\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_SAXIGP4_DATA_WIDTH [get_cells -hier $zynq_periph]]\n\t\t\t\tset afival [get_afi_val $val]\n\t\t\t\tappend config_afi \" <8 $afival>, <9 $afival>,\"\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_SAXIGP5_DATA_WIDTH\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_SAXIGP5_DATA_WIDTH [get_cells -hier $zynq_periph]]\n\t\t\t\tset afival [get_afi_val $val]\n\t\t\t\tappend config_afi \" <10 $afival>, <11 $afival>,\"\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_SAXIGP6_DATA_WIDTH\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_SAXIGP6_DATA_WIDTH [get_cells -hier $zynq_periph]]\n\t\t\t\tset afival [get_afi_val $val]\n\t\t\t\tappend config_afi \" <12 $afival>, <13 $afival>,\"\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_MAXIGP0_DATA_WIDTH\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_MAXIGP0_DATA_WIDTH [get_cells -hier $zynq_periph]]\n\t\t\t\tset afival0 [get_max_afi_val $val]\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_MAXIGP1_DATA_WIDTH\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_MAXIGP1_DATA_WIDTH [get_cells -hier $zynq_periph]]\n\t\t\t\tset afival1 [get_max_afi_val $val]\n\t\t\t}\n\t\t\tset afi0 [expr $afival0 <<8]\n\t\t\tset afi1 [expr $afival1 << 10]\n\t\t\tset afival [expr {$afi0} | {$afi1}]\n\t\t\tset afi_hex [format %x $afival]\n\t\t\tappend config_afi \" <14 0x$afi_hex>,\"\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_MAXIGP2_DATA_WIDTH\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_MAXIGP2_DATA_WIDTH [get_cells -hier $zynq_periph]]\n\t\t\t\tswitch $val {\n\t\t\t\t\t\"128\" {\n\t\t\t\t\t\tset afival 0x200\n\t\t\t\t\t} \"64\" {\n\t\t\t\t\t\tset afival 0x100\n\t\t\t\t\t} \"32\" {\n\t\t\t\t\t\tset afival 0x000\n\t\t\t\t\t} default {\n\t\t\t\t\t\tdtg_warning \"invalid value:$val\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tappend config_afi \" <15 $afival\"\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_PL_CLK0_BUF\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_PL_CLK0_BUF [get_cells -hier $zynq_periph]]\n\t\t\t\tif {[string match -nocase $val \"true\"]} {\n\t\t\t\t\tset clocking_node [add_or_get_dt_node -n \"clocking0\" -l \"clocking0\" -p $bus_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"compatible\" \"xlnx,fclk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clocks\" \"zynqmp_clk 71\" reference\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clock-output-names\" \"fabric_clk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clocks\" \"zynqmp_clk 71\" reference\n\t\t\t\t\tset freq [get_property CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clock-rates\" [scan [expr $freq * 1000000] \"%d\"] int\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_PL_CLK1_BUF\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_PL_CLK1_BUF [get_cells -hier $zynq_periph]]\n\t\t\t\tif {[string match -nocase $val \"true\"]} {\n\t\t\t\t\tset clocking_node [add_or_get_dt_node -n \"clocking1\" -l \"clocking1\" -p $bus_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"compatible\" \"xlnx,fclk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clocks\" \"zynqmp_clk 72\" reference\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clock-output-names\" \"fabric_clk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clocks\" \"zynqmp_clk 72\" reference\n\t\t\t\t\tset freq [get_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clock-rates\" [scan [expr $freq * 1000000] \"%d\"] int\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_PL_CLK2_BUF\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_PL_CLK2_BUF [get_cells -hier $zynq_periph]]\n\t\t\t\tif {[string match -nocase $val \"true\"]} {\n\t\t\t\t\tset clocking_node [add_or_get_dt_node -n \"clocking2\" -l \"clocking2\" -p $bus_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"compatible\" \"xlnx,fclk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clocks\" \"zynqmp_clk 73\" reference\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clock-output-names\" \"fabric_clk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clocks\" \"zynqmp_clk 73\" reference\n\t\t\t\t\tset freq [get_property CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clock-rates\" [scan [expr $freq * 1000000] \"%d\"] int\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_PL_CLK3_BUF\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_PL_CLK3_BUF [get_cells -hier $zynq_periph]]\n\t\t\t\tif {[string match -nocase $val \"true\"]} {\n\t\t\t\t\tset clocking_node [add_or_get_dt_node -n \"clocking3\" -l \"clocking3\" -p $bus_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"compatible\" \"xlnx,fclk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clocks\" \"zynqmp_clk 74\" reference\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clock-output-names\" \"fabric_clk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clocks\" \"zynqmp_clk 74\" reference\n\t\t\t\t\tset freq [get_property CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clock-rates\" [scan [expr $freq * 1000000] \"%d\"] int\n\t\t\t\t}\n\t\t\t}\n\t\t\tset afi_node [add_or_get_dt_node -n \"afi0\" -l \"afi0\" -p $bus_node]\n\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"compatible\" \"xlnx,afi-fpga\" string\n\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"config-afi\" \"$config_afi\" int\n\t\t\tset resets \"zynqmp_reset 116>, <&zynqmp_reset 117>, <&zynqmp_reset 118>, <&zynqmp_reset 119\"\n\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"resets\" \"$resets\" reference\n\t\t}\n\t\tif {[string match -nocase $proctype \"ps7_cortexa9\"]} {\n\t\t\tset zynq_periph [get_cells -hier -filter {IP_NAME == processing_system7}]\n\t\t\tset avail_param [list_property [get_cells -hier $zynq_periph]]\n\t\t\tset targets \"amba\"\n\t\t\tset fpga_node [add_or_get_dt_node -n \"&$targets\" -d [get_dt_tree ${dts_file}]]\n\t\t\tset bus_node \"$fpga_node\"\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_USE_S_AXI_HP0\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_USE_S_AXI_HP0 [get_cells -hier $zynq_periph]]\n\t\t\t\tif {$val == 1} {\n\t\t\t\t\tset afi0 [get_cells -hier -filter {NAME == \"ps7_afi_0\"}]\n\t\t\t\t\tset afi0_param [list_property [get_cells -hier $afi0]]\n\t\t\t\t\tif {[lsearch -nocase $afi0_param \"CONFIG.C_S_AXI_BASEADDR\"] >= 0} {\n\t\t\t\t\t\tset base_addr [get_property CONFIG.C_S_AXI_BASEADDR [get_cells -hier $afi0]]\n\t\t\t\t\t}\n\t\t\t\t\tif {[lsearch -nocase $afi0_param \"CONFIG.C_S_AXI_HIGHADDR\"] >= 0} {\n\t\t\t\t\t\tset high_addr [get_property CONFIG.C_S_AXI_HIGHADDR [get_cells -hier $afi0]]\n\t\t\t\t\t}\n\t\t\t\t\tset size [format 0x%x [expr {${high_addr} - ${base_addr} + 1}]]\n\t\t\t\t\tset reg \"$base_addr $size\"\n\t\t\t\t\tregsub -all {^0x} $base_addr {} addr\n\t\t\t\t\tset addr [string tolower $addr]\n\t\t\t\t\tset afi_node [add_or_get_dt_node -n \"afi0\" -l \"afi0\" -u $addr -p $bus_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"compatible\" \"xlnx,afi-fpga\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"#address-cells\" \"1\" int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"#size-cells\" \"0\" int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"reg\" \"$reg\" intlist\n\t\t\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_S_AXI_HP0_DATA_WIDTH\"] >= 0} {\n\t\t\t\t\t\tset val [get_property CONFIG.C_S_AXI_HP0_DATA_WIDTH [get_cells -hier $zynq_periph]]\n\t\t\t\t\t\tset bus_width [get_axi_datawidth $val]\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"xlnx,afi-width\" \"$bus_width\" int\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_USE_S_AXI_HP1\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_USE_S_AXI_HP1 [get_cells -hier $zynq_periph]]\n\t\t\t\tif {$val == 1} {\n\t\t\t\t\tset afi1 [get_cells -hier -filter {NAME == \"ps7_afi_1\"}]\n\t\t\t\t\tset afi1_param [list_property [get_cells -hier $afi1]]\n\t\t\t\t\tif {[lsearch -nocase $afi1_param \"CONFIG.C_S_AXI_BASEADDR\"] >= 0} {\n\t\t\t\t\t\tset base_addr [get_property CONFIG.C_S_AXI_BASEADDR [get_cells -hier $afi1]]\n\t\t\t\t\t}\n\t\t\t\t\tif {[lsearch -nocase $afi1_param \"CONFIG.C_S_AXI_HIGHADDR\"] >= 0} {\n\t\t\t\t\t\tset high_addr [get_property CONFIG.C_S_AXI_HIGHADDR [get_cells -hier $afi1]]\n\t\t\t\t\t}\n\t\t\t\t\tset size [format 0x%x [expr {${high_addr} - ${base_addr} + 1}]]\n\t\t\t\t\tset reg \"$base_addr $size\"\n\t\t\t\t\tregsub -all {^0x} $base_addr {} addr\n\t\t\t\t\tset addr [string tolower $addr]\n\t\t\t\t\tset afi_node [add_or_get_dt_node -n \"afi1\" -l \"afi1\" -u $addr -p $bus_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"compatible\" \"xlnx,afi-fpga\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"#address-cells\" \"1\" int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"#size-cells\" \"0\" int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"reg\" \"$reg\" intlist\n\t\t\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_S_AXI_HP1_DATA_WIDTH\"] >= 0} {\n\t\t\t\t\t\tset val [get_property CONFIG.C_S_AXI_HP1_DATA_WIDTH [get_cells -hier $zynq_periph]]\n\t\t\t\t\t\tset bus_width [get_axi_datawidth $val]\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"xlnx,afi-width\" \"$bus_width\" int\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_USE_S_AXI_HP2\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_USE_S_AXI_HP2 [get_cells -hier $zynq_periph]]\n\t\t\t\tif {$val == 1} {\n\t\t\t\t\tset afi2 [get_cells -hier -filter {NAME == \"ps7_afi_2\"}]\n\t\t\t\t\tset afi2_param [list_property [get_cells -hier $afi2]]\n\t\t\t\t\tif {[lsearch -nocase $afi2_param \"CONFIG.C_S_AXI_BASEADDR\"] >= 0} {\n\t\t\t\t\t\tset base_addr [get_property CONFIG.C_S_AXI_BASEADDR [get_cells -hier $afi2]]\n\t\t\t\t\t}\n\t\t\t\t\tif {[lsearch -nocase $afi2_param \"CONFIG.C_S_AXI_HIGHADDR\"] >= 0} {\n\t\t\t\t\t\tset high_addr [get_property CONFIG.C_S_AXI_HIGHADDR [get_cells -hier $afi2]]\n\t\t\t\t\t}\n\t\t\t\t\tset size [format 0x%x [expr {${high_addr} - ${base_addr} + 1}]]\n\t\t\t\t\tset reg \"$base_addr $size\"\n\t\t\t\t\tregsub -all {^0x} $base_addr {} addr\n\t\t\t\t\tset addr [string tolower $addr]\n\t\t\t\t\tset afi_node [add_or_get_dt_node -n \"afi2\" -l \"afi2\" -u $addr -p $bus_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"compatible\" \"xlnx,afi-fpga\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"#address-cells\" \"1\" int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"#size-cells\" \"0\" int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"reg\" \"$reg\" intlist\n\t\t\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_S_AXI_HP2_DATA_WIDTH\"] >= 0} {\n\t\t\t\t\t\tset val [get_property CONFIG.C_S_AXI_HP2_DATA_WIDTH [get_cells -hier $zynq_periph]]\n\t\t\t\t\t\tset bus_width [get_axi_datawidth $val]\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"xlnx,afi-width\" \"$bus_width\" int\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_USE_S_AXI_HP3\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.C_USE_S_AXI_HP3 [get_cells -hier $zynq_periph]]\n\t\t\t\tif {$val == 1} {\n\t\t\t\t\tset afi3 [get_cells -hier -filter {NAME == \"ps7_afi_3\"}]\n\t\t\t\t\tset afi3_param [list_property [get_cells -hier $afi3]]\n\t\t\t\t\tif {[lsearch -nocase $afi3_param \"CONFIG.C_S_AXI_BASEADDR\"] >= 0} {\n\t\t\t\t\t\tset base_addr [get_property CONFIG.C_S_AXI_BASEADDR [get_cells -hier $afi2]]\n\t\t\t\t\t}\n\t\t\t\t\tif {[lsearch -nocase $afi3_param \"CONFIG.C_S_AXI_HIGHADDR\"] >= 0} {\n\t\t\t\t\t\tset high_addr [get_property CONFIG.C_S_AXI_HIGHADDR [get_cells -hier $afi2]]\n\t\t\t\t\t}\n\t\t\t\t\tset size [format 0x%x [expr {${high_addr} - ${base_addr} + 1}]]\n\t\t\t\t\tset reg \"$base_addr $size\"\n\t\t\t\t\tregsub -all {^0x} $base_addr {} addr\n\t\t\t\t\tset addr [string tolower $addr]\n\t\t\t\t\tset afi_node [add_or_get_dt_node -n \"afi3\" -l \"afi3\" -u $addr -p $bus_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"compatible\" \"xlnx,afi-fpga\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"#address-cells\" \"1\" int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"#size-cells\" \"0\" int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"reg\" \"$reg\" intlist\n\t\t\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.C_S_AXI_HP3_DATA_WIDTH\"] >= 0} {\n\t\t\t\t\t\tset val [get_property CONFIG.C_S_AXI_HP3_DATA_WIDTH [get_cells -hier $zynq_periph]]\n\t\t\t\t\t\tset bus_width [get_axi_datawidth $val]\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${afi_node}\" \"xlnx,afi-width\" \"$bus_width\" int\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PCW_FPGA_FCLK0_ENABLE\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.PCW_FPGA_FCLK0_ENABLE [get_cells -hier $zynq_periph]]\n\t\t\t\tif {[string match -nocase $val \"1\"]} {\n\t\t\t\t\tset clocking_node [add_or_get_dt_node -n \"clocking0\" -l \"clocking0\" -p $bus_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"compatible\" \"xlnx,fclk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clocks\" \"clkc 15\" reference\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clock-output-names\" \"fabric_clk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clocks\" \"clkc 15\" reference\n\t\t\t\t\tset freq [get_property CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ [get_cells -hier $zynq_periph]]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clock-rates\" [scan [expr $freq * 1000000] \"%d\"] int\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PCW_FPGA_FCLK1_ENABLE\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.PCW_FPGA_FCLK1_ENABLE [get_cells -hier $zynq_periph]]\n\t\t\t\tif {[string match -nocase $val \"1\"]} {\n\t\t\t\t\tset clocking_node [add_or_get_dt_node -n \"clocking1\" -l \"clocking1\" -p $bus_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"compatible\" \"xlnx,fclk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clocks\" \"clkc 16\" reference\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clock-output-names\" \"fabric_clk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clocks\" \"clkc 16\" reference\n\t\t\t\t\tset freq [get_property CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ [get_cells -hier $zynq_periph]]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clock-rates\" [scan [expr $freq * 1000000] \"%d\"] int\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PCW_FPGA_FCLK2_ENABLE\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.PCW_FPGA_FCLK2_ENABLE [get_cells -hier $zynq_periph]]\n\t\t\t\tif {[string match -nocase $val \"1\"]} {\n\t\t\t\t\tset clocking_node [add_or_get_dt_node -n \"clocking2\" -l \"clocking2\" -p $bus_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"compatible\" \"xlnx,fclk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clocks\" \"clkc 17\" reference\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clock-output-names\" \"fabric_clk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clocks\" \"clkc 17\" reference\n\t\t\t\t\tset freq [get_property CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ [get_cells -hier $zynq_periph]]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clock-rates\" [scan [expr $freq * 1000000] \"%d\"] int\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PCW_FPGA_FCLK3_ENABLE\"] >= 0} {\n\t\t\t\tset val [get_property CONFIG.PCW_FPGA_FCLK3_ENABLE [get_cells -hier $zynq_periph]]\n\t\t\t\tif {[string match -nocase $val \"1\"]} {\n\t\t\t\t\tset clocking_node [add_or_get_dt_node -n \"clocking3\" -l \"clocking3\" -p $bus_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"compatible\" \"xlnx,fclk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clocks\" \"clkc 18\" reference\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"clock-output-names\" \"fabric_clk\" string\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clocks\" \"clkc 18\" reference\n\t\t\t\t\tset freq [get_property CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ [get_cells -hier $zynq_periph]]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${clocking_node}\" \"assigned-clock-rates\" [scan [expr $freq * 1000000] \"%d\"] int\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tif {[is_pl_ip $ip_drv] && $dt_overlay} {\n\t\tset targets \"amba\"\n\t\tset fpga_node [add_or_get_dt_node -n \"&$targets\" -d [get_dt_tree ${dts_file}]]\n\t\tset RpRm [get_rp_rm_for_drv $ip_drv]\n\t\tregsub -all { } $RpRm \"\" RpRm\n\t\tif {[llength $RpRm]} {\n\t\t\tset default_dts \"pl-partial-$RpRm.dtsi\"\n\t\t}\n\t\tset bus_node \"$fpga_node\"\n\t\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\thsi::utils::add_new_dts_param \"${bus_node}\" \"#address-cells\" 2 int\n\t\t\thsi::utils::add_new_dts_param \"${bus_node}\" \"#size-cells\" 2 int\n\t\t} else {\n\t\t\thsi::utils::add_new_dts_param \"${bus_node}\" \"#address-cells\" 1 int\n\t\t\thsi::utils::add_new_dts_param \"${bus_node}\" \"#size-cells\" 1 int\n\t\t}\n\t} else {\n\t\tset bus_node [add_or_get_dt_node -n ${bus_name} -l ${bus_label} -d [get_dt_tree ${dts_file}] -p \"/\" -disable_auto_ref -auto_ref_parent]\n\n\t\tif {![string match \"&*\" $bus_node]} {\n\t\t\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\t\thsi::utils::add_new_dts_param \"${bus_node}\" \"#address-cells\" 2 int\n\t\t\t\thsi::utils::add_new_dts_param \"${bus_node}\" \"#size-cells\" 2 int\n\t\t\t} else {\n\t\t\t\thsi::utils::add_new_dts_param \"${bus_node}\" \"#address-cells\" 1 int\n\t\t\t\thsi::utils::add_new_dts_param \"${bus_node}\" \"#size-cells\" 1 int\n\t\t\t}\n\t\t\thsi::utils::add_new_dts_param \"${bus_node}\" \"compatible\" \"simple-bus\" stringlist\n\t\t\thsi::utils::add_new_dts_param \"${bus_node}\" \"ranges\" \"\" boolean\n\t\t}\n\t}\n\treturn $bus_node\n}\n\nproc gen_root_node {drv_handle} {\n\tset default_dts [set_drv_def_dts $drv_handle]\n\t# add compatible\n\tset ip_name [get_property IP_NAME [get_cell -hier ${drv_handle}]]\n\tswitch $ip_name {\n\t\t\"ps7_cortexa9\" {\n\t\t\tcreate_dt_tree_from_dts_file\n\t\t\tglobal dtsi_fname\n\t\t\tupdate_system_dts_include [file tail ${dtsi_fname}]\n\t\t\t# no root_node required as zynq-7000.dtsi\n\t\t\treturn 0\n\t\t}\n\t\t\"psu_cortexa53\" {\n\t\t\tcreate_dt_tree_from_dts_file\n\t\t\tglobal dtsi_fname\n\t\t\tset mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n\t\t\tset valid_mainline_kernel_list \"v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4\"\n\t\t\tif {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } {\n\t\t\t\tupdate_system_dts_include [file tail ${dtsi_fname}]\n\t\t\t\tupdate_system_dts_include [file tail \"zynqmp-clk.dtsi\"]\n\t\t\t\treturn 0\n\t\t\t}\n\t\t\tupdate_system_dts_include [file tail ${dtsi_fname}]\n\t\t\tupdate_system_dts_include [file tail \"zynqmp-clk-ccf.dtsi\"]\n\t\t\t# no root_node required as zynqmp.dtsi\n\t\t\treturn 0\n\t\t}\n\t\t\"psv_cortexa72\" {\n\t\t\tcreate_dt_tree_from_dts_file\n\t\t\tglobal dtsi_fname\n\t\t\tupdate_system_dts_include [file tail ${dtsi_fname}]\n\t\t\tset overrides [get_property CONFIG.periph_type_overrides [get_os]]\n\t\t\tset dtsi_file \" \"\n\t\t\tforeach override $overrides {\n\t\t\t\tif {[lindex $override 0] == \"BOARD\"} {\n\t\t\t\t\tset dtsi_file [lindex $override 1]\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[string match -nocase $dtsi_file \"versal-spp-itr8-cn13940875\"] || [string match -nocase $dtsi_file \"versal-vc-p-a2197-00-reva-x-prc-01-reva-pm\"]} {\n\t\t\t\tupdate_system_dts_include [file tail \"versal-spp-pm.dtsi\"]\n\t\t\t} else {\n\t\t\t\tupdate_system_dts_include [file tail \"versal-clk.dtsi\"]\n\t\t\t}\n\t\t\treturn 0\n\t\t}\n\t\t\"psx_cortexa78\" {\n\t\t\tcreate_dt_tree_from_dts_file\n\t\t\tglobal dtsi_fname\n update_system_dts_include [file tail ${dtsi_fname}]\n\t\t\tset overrides [get_property CONFIG.periph_type_overrides [get_os]]\n\t\t\tset dtsi_file \" \"\n set board_dtsi_file \"\"\n\t\t\tforeach override $overrides {\n\t\t\t\tif {[lindex $override 0] == \"BOARD\"} {\n\t\t\t\t\tset board_dtsi_file [lindex $override 1]\n\t\t\t\t}\n\t\t\t}\n #TMP fix to support ipp fixed clocks\n if {[string match -nocase $board_dtsi_file \"versal-net-ipp-rev1.9\"]} {\n set dtsi_file $board_dtsi_file\n } else {\n update_system_dts_include [file tail \"versal-net-clk-ccf.dtsi\"]\n }\n\t\t\treturn 0\n\t\t}\n\t\t\"microblaze\" {\n\t\t\tset compatible \"xlnx,microblaze\"\n\t\t\tset model \"Xilinx MicroBlaze\"\n\t\t}\n\t\tdefault {\n\t\t\treturn -code error \"Unknown arch\"\n\t\t}\n\t}\n\tset root_node [add_or_get_dt_node -n / -d ${default_dts}]\n\thsi::utils::add_new_dts_param \"${root_node}\" \"#address-cells\" 1 int \"\"\n\thsi::utils::add_new_dts_param \"${root_node}\" \"#size-cells\" 1 int \"\"\n\thsi::utils::add_new_dts_param \"${root_node}\" model $model string \"\"\n\thsi::utils::add_new_dts_param \"${root_node}\" compatible $compatible string \"\"\n\n\treturn $root_node\n}\n\nproc cortexa9_opp_gen {drv_handle} {\n\t# generate opp overlay for cpu\n\tif {[catch {set cpu_max_freq [get_property CONFIG.C_CPU_CLK_FREQ_HZ [get_cells -hier $drv_handle]]} msg]} {\n\t\tset cpu_max_freq \"\"\n\t}\n\tif {[string_is_empty ${cpu_max_freq}]} {\n\t\tdtg_warning \"DTG failed to detect the CPU clock frequency\"\n\t\treturn -1\n\t}\n\tset cpu_max_freq [expr int([expr $cpu_max_freq/1000])]\n\tset processor [get_sw_processor]\n\tset default_dts [set_drv_def_dts $processor]\n\tset root_node [add_or_get_dt_node -n / -d ${default_dts}]\n\n\tset cpu_root_node [add_or_get_dt_node -n cpus -d ${default_dts} -p $root_node]\n\tset cpu_node [add_or_get_dt_node -n cpu -u 0 -d ${default_dts} -p ${cpu_root_node} -disable_auto_ref -force]\n\n\tset tmp_opp $cpu_max_freq\n\tset opp \"\"\n\tset i 0\n\t# do not generate opp for freq lower than 200MHz and use fix voltage\n\t# 1000000uv\n\twhile {$tmp_opp >= 200000} {\n\t\tappend opp \" \" \"$tmp_opp 1000000\"\n\t\tincr i\n\t\tset tmp_opp [expr int([expr $cpu_max_freq / pow(2, $i)])]\n\t}\n\tif {![string_is_empty $opp]} {\n\t\thsi::utils::add_new_dts_param $cpu_node \"operating-points\" \"$opp\" intlist\n\t}\n}\n\n# Q: common function for all processor or one for each driver lib\nproc gen_cpu_nodes {drv_handle} {\n\tset ip_name [get_property IP_NAME [get_cell -hier [get_sw_processor]]]\n\tswitch $ip_name {\n\t\t\"ps7_cortexa9\" {\n\t\t\t# skip node generation for static zynq-7000 dtsi\n\t\t\t# TODO: this needs to be fixed to allow override\n\t\t\tcortexa9_opp_gen $drv_handle\n\t\t\treturn 0\n\t\t}\n\t\t\"psu_cortexa53\" {\n\t\t\t# skip node generation for static zynqmp dtsi\n\t\t\treturn 0\n\t\t}\n\t\t\"psv_cortexa72\" {\n\t\t\treturn 0\n\t\t}\n\t\t\"psx_cortexa78\" {\n\t\t\treturn 0\n\t\t} \"microblaze\" {}\n\t\tdefault {\n\t\t\terror \"Unknown arch\"\n\t\t}\n\t}\n\n\tset processor [get_sw_processor]\n\tset dev_type [get_property CONFIG.dev_type $processor]\n\tif {[string_is_empty $dev_type] == 1} {\n\t\tset dev_type $drv_handle\n\t}\n\tgen_compatible_property $processor\n\tgen_mb_interrupt_property $processor\n\tgen_drv_prop_from_ip $processor\n\n\tset default_dts [set_drv_def_dts $processor]\n\tset cpu_root_node [add_or_get_dt_node -n cpus -d ${default_dts} -p /]\n\thsi::utils::add_new_dts_param \"${cpu_root_node}\" \"#address-cells\" 1 int \"\"\n\thsi::utils::add_new_dts_param \"${cpu_root_node}\" \"#size-cells\" 0 int \"\"\n\n\tset processor_type [get_property IP_NAME [get_cell -hier ${processor}]]\n\tset processor_list [eval \"get_cells -hier -filter { IP_TYPE == \\\"PROCESSOR\\\" && IP_NAME == \\\"${processor_type}\\\" }\"]\n\n\tset drv_dt_prop_list [get_driver_conf_list $processor]\n\n\t# generate mb ccf node\n\tgenerate_mb_ccf_node $processor\n\n\tset bus_node [add_or_get_bus_node $drv_handle $default_dts]\n\tset cpu_no 0\n\tforeach cpu ${processor_list} {\n\t\t# Generate the node only for the single core\n\t\tif {$cpu_no >= 1} {\n\t\t\tbreak\n\t\t}\n\t\tset bus_label [get_property NODE_LABEL $bus_node]\n\t\tset cpu_node [add_or_get_dt_node -n ${dev_type} -l ${cpu} -u ${cpu_no} -d ${default_dts} -p ${cpu_root_node}]\n\t\thsi::utils::add_new_dts_param \"${cpu_node}\" \"bus-handle\" $bus_label reference\n\t\tforeach drv_prop_name $drv_dt_prop_list {\n\t\t\tadd_driver_prop $processor $cpu_node ${drv_prop_name}\n\t\t}\n\t\t\thsi::utils::add_new_dts_param \"${cpu_node}\" \"reg\" $cpu_no int \"\"\n\t\tincr cpu_no\n\t}\n\thsi::utils::add_new_dts_param \"${cpu_root_node}\" \"#cpus\" $cpu_no int \"\"\n}\n\nproc remove_all_tree {} {\n\t# for testing\n\tset test_dummy \"for_test_dummy.dts\"\n\tif {[lsearch [get_dt_trees] ${test_dummy}] < 0} {\n\t\tcreate_dt_tree -dts_file $test_dummy\n\t}\n\tset_cur_working_dts $test_dummy\n\n\tforeach tree [get_dt_trees] {\n\t\tif {[string equal -nocase $test_dummy $tree]} {\n\t\t\tcontinue\n\t\t}\n\t\tcatch {delete_objs $tree} msg\n\t}\n}\n\nproc gen_mdio_node {drv_handle parent_node} {\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tif {[is_pl_ip $drv_handle] && $remove_pl} {\n\t\treturn\n\t}\n\tset mdio_node [add_or_get_dt_node -l ${drv_handle}_mdio -n mdio -p $parent_node]\n\thsi::utils::add_new_dts_param \"${mdio_node}\" \"#address-cells\" 1 int \"\"\n\thsi::utils::add_new_dts_param \"${mdio_node}\" \"#size-cells\" 0 int \"\"\n\treturn $mdio_node\n}\n\nproc add_memory_node {drv_handle} {\n\tset master_dts [get_property CONFIG.master_dts [get_os]]\n\tset cur_dts [current_dt_tree]\n\tset master_dts_obj [get_dt_trees ${master_dts}]\n\tset_cur_working_dts $master_dts\n\n\t# assuming single memory region\n\t# - single memory region\n\t# - / node is created\n\t# - reg property is generated\n\t# CHECK node naming\n\tset ddr_ip \"\"\n\tset main_memory [get_property CONFIG.main_memory [get_os]]\n\tif {![string match -nocase $main_memory \"none\"]} {\n\t\tset ddr_ip [get_property IP_NAME [get_cells -hier -nocase $main_memory]]\n\t}\n\tset ddr_list \"psu_ddr ps7_ddr axi_emc mig_7series psv_ddr\"\n\tif {[lsearch -nocase $ddr_list $ddr_ip] >= 0} {\n\t\tset parent_node [add_or_get_dt_node -n / -d ${master_dts}]\n set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\tset reg_value [get_property CONFIG.reg $drv_handle]\n # Append base address to memory node.\n if {[llength \"$reg_value\"]} {\n if {[string match -nocase $proctype \"psu_cortexa53\"] || \\\n [string match -nocase $proctype \"psv_cortexa72\"] || \\\n [string match -nocase $proctype \"psx_cortexa78\"]} {\n set higheraddr [expr [lindex $reg_value 0] << 32]\n set loweraddr [lindex $reg_value 1]\n set unitaddr [format 0x%x [expr {${higheraddr} + ${loweraddr}}]]\n } else {\n set unitaddr [lindex $reg_value 0]\n }\n regsub -all {^0x} $unitaddr {} unitaddr\n set memory_node [add_or_get_dt_node -n memory -p $parent_node -u $unitaddr]\n hsi::utils::add_new_dts_param \"${memory_node}\" \"reg\" $reg_value inthexlist\n }\n\t\t# maybe hardcoded\n\t\tif {[catch {set dev_type [get_property CONFIG.device_type $drv_handle]} msg]} {\n\t\t\tset dev_type memory\n\t\t}\n\t\tif {[string_is_empty $dev_type]} {set dev_type memory}\n\t\thsi::utils::add_new_dts_param \"${memory_node}\" \"device_type\" $dev_type string\n\n\t\tset_cur_working_dts $cur_dts\n\t\treturn $memory_node\n\t}\n}\n\nproc gen_mb_ccf_subnode {drv_handle name freq reg} {\n\tset cur_dts [current_dt_tree]\n\tset default_dts [set_drv_def_dts $drv_handle]\n\n\tset clk_node [add_or_get_dt_node -n clocks -p / -d ${default_dts}]\n\thsi::utils::add_new_dts_param \"${clk_node}\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"${clk_node}\" \"#size-cells\" 0 int\n\n\tset clk_subnode_name \"clk_${name}\"\n\tset clk_subnode [add_or_get_dt_node -l ${clk_subnode_name} -n ${clk_subnode_name} -u $reg -p ${clk_node} -d ${default_dts}]\n\t# clk subnode data\n\thsi::utils::add_new_dts_param \"${clk_subnode}\" \"compatible\" \"fixed-clock\" stringlist\n\thsi::utils::add_new_dts_param \"${clk_subnode}\" \"#clock-cells\" 0 int\n\n\thsi::utils::add_new_dts_param $clk_subnode \"clock-output-names\" $clk_subnode_name string\n\thsi::utils::add_new_dts_param $clk_subnode \"reg\" $reg int\n\thsi::utils::add_new_dts_param $clk_subnode \"clock-frequency\" $freq int\n\n\tset_cur_working_dts $cur_dts\n}\n\nproc generate_mb_ccf_node {drv_handle} {\n\tglobal bus_clk_list\n\n\tset sw_proc [get_sw_processor]\n\tset proc_ip [get_cells -hier $sw_proc]\n\tset proctype [get_property IP_NAME $proc_ip]\n\tif {[string match -nocase $proctype \"microblaze\"]} {\n\t\tset cpu_clk_freq [get_clock_frequency $proc_ip \"CLK\"]\n\t\t# issue:\n\t\t# - hardcoded reg number cpu clock node\n\t\t# - assume clk_cpu for mb cpu\n\t\t# - only applies to master mb cpu\n\t\tgen_mb_ccf_subnode $sw_proc cpu $cpu_clk_freq 0\n\t}\n}\n\nproc gen_dev_ccf_binding args {\n\tset drv_handle [lindex $args 0]\n\tset pins [lindex $args 1]\n\tset binding_list \"clocks clock-frequency\"\n\tif {[llength $args] >= 3} {\n\t\tset binding_list [lindex $args 2]\n\t}\n\t# list of ip should have the clocks property\n\tglobal bus_clk_list\n\n\tset sw_proc [get_sw_processor]\n\tset proc_ip [get_cells -hier $sw_proc]\n\tset proctype [get_property IP_NAME $proc_ip]\n\tif {[string match -nocase $proctype \"microblaze\"]} {\n\t\tset clk_refs \"\"\n\t\tset clk_names \"\"\n\t\tset clk_freqs \"\"\n\t\tforeach p $pins {\n\t\t\tset clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"$p\"]\n\t\t\tif {![string equal $clk_freq \"\"]} {\n\t\t\t\t# FIXME: bus clk source count should based on the clock generator not based on clk freq diff\n\t\t\t\tif {[lsearch $bus_clk_list $clk_freq] < 0} {\n\t\t\t\t\tset bus_clk_list [lappend bus_clk_list $clk_freq]\n\t\t\t\t}\n\t\t\t\tset bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]\n\t\t\t\t# create the node and assuming reg 0 is taken by cpu\n\t\t\t\tgen_mb_ccf_subnode $drv_handle bus_${bus_clk_cnt} $clk_freq [expr ${bus_clk_cnt} + 1]\n\t\t\t\tset clk_refs [lappend clk_refs &clk_bus_${bus_clk_cnt}]\n\t\t\t\tset clk_names [lappend clk_names \"$p\"]\n\t\t\t\tset clk_freqs [lappend clk_freqs \"$clk_freq\"]\n\t\t\t}\n\t\t}\n\t\tif {[lsearch $binding_list \"clocks\"] >= 0} {\n\t\t\thsi::utils::add_new_property $drv_handle \"clocks\" referencelist $clk_refs\n\t\t}\n\t\tif {[lsearch $binding_list \"clock-names\"] >= 0} {\n\t\t\thsi::utils::add_new_property $drv_handle \"clock-names\" stringlist $clk_names\n\t\t}\n\t\tif {[lsearch $binding_list \"clock-frequency\"] >= 0} {\n\t\t\thsi::utils::add_new_property $drv_handle \"clock-frequency\" hexintlist $clk_freqs\n\t\t}\n\t}\n}\n\nproc update_eth_mac_addr {drv_handle} {\n\tset eth_count [get_os_dev_count \"eth_mac_count\"]\n\tset tmp [list_property $drv_handle CONFIG.local-mac-address]\n\tif {![string_is_empty $tmp]} {\n\t\tset def_mac [get_property CONFIG.local-mac-address $drv_handle]\n\t} else {\n\t\tset def_mac \"\"\n\t}\n\tif {[string_is_empty $def_mac]} {\n\t\tset def_mac \"00 0a 35 00 00 00\"\n\t}\n\tset mac_addr_data [split $def_mac \" \"]\n\tset last_value [format %02x [expr [lindex $mac_addr_data 5] + $eth_count ]]\n\tset mac_addr [lreplace $mac_addr_data 5 5 $last_value]\n\tdtg_debug \"${drv_handle}:set mac addr to $mac_addr\"\n\tincr eth_count\n\thsi::utils::set_os_parameter_value \"eth_mac_count\" $eth_count\n\thsi::utils::add_new_property $drv_handle \"local-mac-address\" bytelist ${mac_addr}\n}\n\nproc get_os_dev_count {count_para {drv_handle \"\"} {os_para \"\"}} {\n\tset dev_count [hsi::utils::get_os_parameter_value \"${count_para}\"]\n\tif {[llength $dev_count] == 0} {\n\t\tset dev_count 0\n\t}\n\tif {[string_is_empty $os_para] || [string_is_empty $drv_handle]} {\n\t\treturn $dev_count\n\t}\n\tset ip [get_cells -hier $drv_handle]\n\tset chosen_ip [hsi::utils::get_os_parameter_value \"${os_para}\"]\n\tif {[string match -nocase \"$ip\" \"$chosen_ip\"]} {\n\t\thsi::utils::set_os_parameter_value $count_para 1\n\t\treturn 0\n\t} else {\n\t\treturn $dev_count\n\t}\n}\n\nproc get_hw_version {} {\n\tset hw_ver_data [split [get_property VIVADO_VERSION [get_hw_designs]] \".\"]\n\tset hw_ver [lindex $hw_ver_data 0].[lindex $hw_ver_data 1]\n\treturn $hw_ver\n}\n\nproc get_hsi_version {} {\n\tset hsi_ver_data [split [version -short] \".\"]\n\tset hsi_ver [lindex $hsi_ver_data 0].[lindex $hsi_ver_data 1]\n\treturn $hsi_ver\n}\n\nproc get_sw_proc_prop {prop_name} {\n\tset sw_proc [get_sw_processor]\n\tset proc_ip [get_cells -hier $sw_proc]\n\tset property_value [get_property $prop_name $proc_ip]\n\treturn $property_value\n}\n\n# Get the interrupt controller name, which the ip is connected\nproc get_intr_cntrl_name { periph_name intr_pin_name } {\n\tlappend intr_cntrl\n\tif { [llength $intr_pin_name] == 0 } {\n\t\treturn $intr_cntrl\n\t}\n\tif { [llength $periph_name] != 0 } {\n\t# This is the case where IP pin is interrupting\n\tset periph [::hsi::get_cells -hier -filter \"NAME==$periph_name\"]\n\n\tif { [llength $periph] == 0 } {\n\t\treturn $intr_cntrl\n\t}\n\tset intr_pin [::hsi::get_pins -of_objects $periph -filter \"NAME==$intr_pin_name\"]\n\tif { [llength $intr_pin] == 0 } {\n\t\treturn $intr_cntrl\n\t}\n\tset valid_cascade_proc \"microblaze ps7_cortexa9 psu_cortexa53 psv_cortexa72 psx_cortexa78\"\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tif { [string match -nocase [common::get_property IP_NAME $periph] \"axi_intc\"] && [lsearch -nocase $valid_cascade_proc $proctype] >= 0 } {\n\t\tset sinks [::hsi::utils::get_sink_pins $intr_pin]\n\t\tforeach intr_sink ${sinks} {\n\t\t\tset sink_periph [::hsi::get_cells -of_objects $intr_sink]\n\t\t\tif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"axi_intc\"] } {\n\t\t\t\t# this the case where interrupt port is connected to axi_intc.\n\t\t\t\tlappend intr_cntrl [get_intr_cntrl_name $sink_periph \"irq\"]\n\t\t\t} elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"xlconcat\"] } {\n\t\t\t\t# this the case where interrupt port is connected to XLConcat IP.\n\t\t\t\tlappend intr_cntrl [get_intr_cntrl_name $sink_periph \"dout\"]\n\t\t\t} elseif { [llength $sink_periph ] && [::hsi::utils::is_intr_cntrl $sink_periph] == 1 } {\n\t\t\t\tlappend intr_cntrl $sink_periph\n\t\t\t} elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"microblaze\"] } {\n\t\t\t\tlappend intr_cntrl $sink_periph\n\t\t\t} elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"tmr_voter\"] } {\n\t\t\t\tlappend intr_cntrl $sink_periph\n\t\t\t} elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"dfx_decoupler\"] } {\n\t\t\t\tset intr [get_pins -of_objects $sink_periph -filter {TYPE==INTERRUPT&&DIRECTION==O}]\n\t\t\t\tlappend intr_cntrl [get_intr_cntrl_name $sink_periph \"$intr\"]\n\t\t\t}\n\t\t\tif {[llength $intr_cntrl] > 1} {\n\t\t\t\tforeach intc $intr_cntrl {\n\t\t\t\t\tif { [::hsi::utils::is_ip_interrupting_current_proc $intc] } {\n\t\t\t\t\t\tset intr_cntrl $intc\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\treturn $intr_cntrl\n\t}\n\tset pin_dir [common::get_property DIRECTION $intr_pin]\n\tif { [string match -nocase $pin_dir \"I\"] } {\n\t\treturn $intr_cntrl\n\t}\n\t} else {\n\t\t# This is the case where External interrupt port is interrupting\n\t\tset intr_pin [::hsi::get_ports $intr_pin_name]\n\t\tif { [llength $intr_pin] == 0 } {\n\t\t\treturn $intr_cntrl\n\t\t}\n\t\tset pin_dir [common::get_property DIRECTION $intr_pin]\n\t\tif { [string match -nocase $pin_dir \"O\"] } {\n\t\t\treturn $intr_cntrl\n\t\t}\n\t}\n\n\tset intr_sink_pins [::hsi::utils::get_sink_pins $intr_pin]\n\tif { [llength $intr_sink_pins] == 0 || [string match $intr_sink_pins \"{}\"]} {\n\t\treturn $intr_cntrl\n\t}\n\tset valid_cascade_proc \"microblaze ps7_cortexa9 psu_cortexa53 psv_cortexa72 psx_cortexa78\"\n\tforeach intr_sink ${intr_sink_pins} {\n\t\tif {[llength $intr_sink] == 0} {\n\t\t\tcontinue\n\t\t}\n\t\tset sink_periph [::hsi::get_cells -of_objects $intr_sink]\n\t\tif { [llength $sink_periph ] && [::hsi::utils::is_intr_cntrl $sink_periph] == 1 } {\n\t\t\tif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"axi_intc\"] && [lsearch -nocase $valid_cascade_proc $proctype] >= 0} {\n\t\t\t\tlappend intr_cntrl [get_intr_cntrl_name $sink_periph \"irq\"]\n\t\t\t} else {\n\t\t\t\tlappend intr_cntrl $sink_periph\n\t\t\t}\n\t\t} elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"xlconcat\"] } {\n\t\t\t# this the case where interrupt port is connected to XLConcat IP.\n\t\t\tlappend intr_cntrl [get_intr_cntrl_name $sink_periph \"dout\"]\n\t\t} elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"xlslice\"]} {\n\t\t\tlappend intr_cntrl [get_intr_cntrl_name $sink_periph \"Dout\"]\n\t\t} elseif {[llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"util_reduced_logic\"]} {\n\t\t\tlappend intr_cntrl [get_intr_cntrl_name $sink_periph \"Res\"]\n\t\t} elseif {[llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"axi_gpio\"]} {\n\t\t\tset intr_present [get_property CONFIG.C_INTERRUPT_PRESENT $sink_periph]\n\t\t\tif {$intr_present == 1} {\n\t\t\t\tlappend intr_cntrl $sink_periph\n\t\t\t}\n\t\t} elseif {[llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"util_ff\"]} {\n\t\t\tlappend intr_cntrl [get_intr_cntrl_name $sink_periph \"Q\"]\n\t\t} elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"dfx_decoupler\"] } {\n\t\t\tset intr [get_pins -of_objects $sink_periph -filter {TYPE==INTERRUPT&&DIRECTION==O}]\n\t\t\tlappend intr_cntrl [get_intr_cntrl_name $sink_periph \"$intr\"]\n\t\t}\n\t\tif {[llength $intr_cntrl] > 1} {\n\t\t\tforeach intc $intr_cntrl {\n\t\t\t\tif { [::hsi::utils::is_ip_interrupting_current_proc $intc] } {\n\t\t\t\t\tset intr_cntrl $intc\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tset val [string trim $intr_cntrl \\{\\}]\n\tif {[llength $val] == 0} {\n\t\treturn\n\t}\n\treturn $intr_cntrl\n}\n\n# Generate interrupt info for the ips which are using gpio\n# as interrupt.\nproc generate_gpio_intr_info {connected_intc drv_handle pin} {\n\tset intr_info \"\"\n\tglobal ps_gpio_pincount\n\tif {[string_is_empty $connected_intc]} {\n\t\treturn -1\n\t}\n\t# Get the gpio channel number to which the ip is connected\n\tset channel_nr [get_gpio_channel_nr $drv_handle $pin]\n\tset slave [get_cells -hier ${drv_handle}]\n\tset ip_name $connected_intc\n\tset intr_type [get_intr_type $connected_intc $slave $pin]\n\tif {[string match -nocase $intr_type \"-1\"]} {\n\t\treturn -1\n\t}\n\tset sinkpin [::hsi::utils::get_sink_pins [get_pins -of [get_cells -hier $drv_handle] -filter {TYPE==INTERRUPT}]]\n\tset dual [get_property CONFIG.C_IS_DUAL $connected_intc]\n\tregsub -all {[^0-9]} $sinkpin \"\" gpio_pin_count\n\tset gpio_cho_pin_lcnt [get_property LEFT [get_pins -of_objects [get_cells -hier $connected_intc] gpio_io_i]]\n\tset gpio_cho_pin_rcnt [get_property RIGHT [get_pins -of_objects [get_cells -hier $connected_intc] gpio_io_i]]\n\tset gpio_cho_pin_rcnt [expr $gpio_cho_pin_rcnt + 1]\n\tset gpio_ch0_pin_cnt [expr {$gpio_cho_pin_lcnt + $gpio_cho_pin_rcnt}]\n\tif {[string match $channel_nr \"0\"]} {\n\t\t# Check for ps7_gpio else check for axi_gpio\n\t\tif {[string match $sinkpin \"GPIO_I\"]} {\n\t\t\tset intr_info \"$ps_gpio_pincount $intr_type\"\n\t\t\texpr ps_gpio_pincount 1\n\t\t} elseif {[regexp \"gpio_io_i\" $sinkpin match]} {\n\t\t\tset intr_info \"0 $intr_type\"\n\t\t} else {\n\t\t\t# if channel width is more than one\n\t\t\tset intr_info \"$gpio_pin_count $intr_type \"\n\t\t}\n\t} else {\n\t\tif {[string match $dual \"1\"]} {\n\t\t\t# gpio channel 2 width is one\n\t\t\tif {[regexp \"gpio2_io_i\" $sinkpin match]} {\n\t\t\t\tset intr_info \"32 $intr_type\"\n\t\t\t} else {\n\t\t\t\t# if channel width is more than one\n\t\t\t\tset intr_pin [::hsi::get_pins -of_objects $connected_intc -filter \"NAME==$pin\"]\n\t\t\t\tset gpio_channel [::hsi::utils::get_sink_pins $intr_pin]\n\t\t\t\tset intr_id [expr $gpio_pin_count + $gpio_ch0_pin_cnt]\n\t\t\t\tset intr_info \"$intr_id $intr_type\"\n\t\t\t}\n\t\t}\n\t}\n\tset intc $connected_intc\n\tif {[string_is_empty $intr_info]} {\n\t\treturn -1\n\t}\n\tset_drv_prop $drv_handle interrupts $intr_info intlist\n\tif {[string_is_empty $intc]} {\n\t\treturn -1\n\t}\n\tset intc [ps_node_mapping $intc label]\n\tset_drv_prop $drv_handle interrupt-parent $intc reference\n}\n\n# Get the gpio channel number to which the ip is connected\n# if pin is gpio_io_* then channel is 1\n# if pin is gpio2_io_* then channel is 2\nproc get_gpio_channel_nr { periph_name intr_pin_name } {\n\tlappend intr_cntrl\n\tif { [llength $intr_pin_name] == 0 } {\n\t\treturn $intr_cntrl\n\t}\n\tif { [llength $periph_name] != 0 } {\n\t\tset periph [::hsi::get_cells -hier -filter \"NAME==$periph_name\"]\n\n\t\tif { [llength $periph] == 0 } {\n\t\t\treturn $intr_cntrl\n\t\t}\n\t\tset intr_pin [::hsi::get_pins -of_objects $periph -filter \"NAME==$intr_pin_name\"]\n\t\tif { [llength $intr_pin] == 0 } {\n\t\t\treturn $intr_cntrl\n\t\t}\n\t\tset pin_dir [common::get_property DIRECTION $intr_pin]\n\t\tif { [string match -nocase $pin_dir \"I\"] } {\n\t\t\treturn $intr_cntrl\n\t\t}\n\t\tset intr_sink_pins [::hsi::utils::get_sink_pins $intr_pin]\n\t\tset sink_periph [::hsi::get_cells -of_objects $intr_sink_pins]\n\t\tif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] \"xlconcat\"] } {\n\t\t\t# this the case where interrupt port is connected to XLConcat IP.\n\t\t\treturn [get_gpio_channel_nr $sink_periph \"dout\"]\n\t\t}\n\t\tif {[regexp \"gpio[2]_*\" $intr_sink_pins match]} {\n\t\t\treturn 1\n\t\t} else {\n\t\t\treturn 0\n\t\t}\n\t}\n}\n\nproc is_interrupt { IP_NAME } {\n\tif { [string match -nocase $IP_NAME \"ps7_scugic\"] } {\n\t\treturn true\n\t} elseif { [string match -nocase $IP_NAME \"psu_acpu_gic\"] || [string match -nocase $IP_NAME \"psv_acpu_gic\"] || [string match -nocase $IP_NAME \"psx_acpu_gic\"]} {\n\t\treturn true\n\t} elseif { [string match -nocase $IP_NAME \"psu_rcpu_gic\"] } {\n\t\treturn true\n\t}\n\treturn false;\n\n}\n\nproc is_orgate { intc_src_port ip_name} {\n\tset ret -1\n\n\tset intr_sink_pins [::hsi::utils::get_sink_pins $intc_src_port]\n\tset sink_periph [::hsi::get_cells -of_objects $intr_sink_pins]\n\tset ipname [get_property IP_NAME $sink_periph]\n\tif { $ipname == \"xlconcat\" } {\n\t\tset intf \"dout\"\n\t\tset intr1_pin [::hsi::get_pins -of_objects $sink_periph -filter \"NAME==$intf\"]\n\t\tset intr_sink_pins [::hsi::utils::get_sink_pins $intr1_pin]\n\t\tset sink_periph [::hsi::get_cells -of_objects $intr_sink_pins]\n\t\tset ipname [get_property IP_NAME $sink_periph]\n\t\tif {$ipname == \"util_reduced_logic\"} {\n\t\t\tset width [get_property CONFIG.C_SIZE $sink_periph]\n\t\t\treturn $width\n\t\t}\n\t}\n\n\treturn $ret\n}\n\nproc get_psu_interrupt_id { ip_name port_name } {\n global or_id\n global or_cnt\n\n set ret -1\n set periph \"\"\n set intr_pin \"\"\n if { [llength $port_name] == 0 } {\n return $ret\n }\n global pl_ps_irq1\n global pl_ps_irq0\n if { [llength $ip_name] != 0 } {\n #This is the case where IP pin is interrupting\n set periph [::hsi::get_cells -hier -filter \"NAME==$ip_name\"]\n if { [llength $periph] == 0 } {\n return $ret\n }\n set intr_pin [::hsi::get_pins -of_objects $periph -filter \"NAME==$port_name\"]\n if { [llength $intr_pin] == 0 } {\n return $ret\n }\n set pin_dir [common::get_property DIRECTION $intr_pin]\n if { [string match -nocase $pin_dir \"I\"] } {\n return $ret\n }\n } else {\n #This is the case where External interrupt port is interrupting\n set intr_pin [::hsi::get_ports $port_name]\n if { [llength $intr_pin] == 0 } {\n return $ret\n }\n set pin_dir [common::get_property DIRECTION $intr_pin]\n if { [string match -nocase $pin_dir \"O\"] } {\n return $ret\n }\n }\n set intc_periph [get_interrupt_parent $ip_name $port_name]\n if {[llength $intc_periph] > 1} {\n foreach intr_cntr $intc_periph {\n if { [::hsi::utils::is_ip_interrupting_current_proc $intr_cntr] } {\n set intc_periph $intr_cntr\n }\n }\n }\n if { [llength $intc_periph] == 0 } {\n return $ret\n }\n\n set intc_type [common::get_property IP_NAME $intc_periph]\n #set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n if {[llength $intc_type] > 1} {\n foreach intr_cntr $intc_type {\n if { [::hsi::utils::is_ip_interrupting_current_proc $intr_cntr] } {\n set intc_type $intr_cntr\n }\n }\n }\n\n set intc_src_ports [::hsi::utils::get_interrupt_sources $intc_periph]\n\n #Special Handling for cascading case of axi_intc Interrupt controller\n set cascade_id 0\n\n set i $cascade_id\n set found 0\n set j $or_id\n foreach intc_src_port $intc_src_ports {\n\t# Check whether externel port is interrupting not peripheral\n # like externel[7:0] port to gic\n set pin_dir [common::get_property DIRECTION $intc_src_port]\n if { [string match -nocase $pin_dir \"I\"] } {\n\t\tincr i\n continue\n }\n if { [llength $intc_src_port] == 0 } {\n incr i\n continue\n }\n set intr_width [::hsi::utils::get_port_width $intc_src_port]\n set intr_periph [::hsi::get_cells -of_objects $intc_src_port]\n if { [llength $intr_periph] && [is_interrupt $intc_type] } {\n if {[common::get_property IS_PL $intr_periph] == 0 } {\n continue\n }\n }\n set width [is_orgate $intc_src_port $ip_name]\n if { [string compare -nocase \"$port_name\" \"$intc_src_port\" ] == 0 } {\n if { [string compare -nocase \"$intr_periph\" \"$periph\"] == 0 && $width != -1} {\n\t\tset or_cnt [expr $or_cnt + 1]\n if { $or_cnt == $width} {\n set or_cnt 0\n set or_id [expr $or_id + 1]\n }\n set ret $i\n set found 1\n break\n } elseif { [string compare -nocase \"$intr_periph\" \"$periph\"] == 0 } {\n set ret $i\n set found 1\n break\n }\n }\n if { $width != -1} {\n set i [expr $or_id]\n } else {\n set i [expr $i + $intr_width]\n }\n }\n set intr_list_irq0 [list 89 90 91 92 93 94 95 96]\n set intr_list_irq1 [list 104 105 106 107 108 109 110 111]\n set sink_pins [::hsi::utils::get_sink_pins $intr_pin]\n if { [llength $sink_pins] == 0 } {\n return\n }\n set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n if {[string match -nocase $proctype \"microblaze\"]} {\n if {[string match -nocase \"[get_property IP_NAME $periph]\" \"axi_intc\"]} {\n set ip [get_property IP_NAME $periph]\n set cascade_master [get_property CONFIG.C_CASCADE_MASTER [get_cells -hier $periph]]\n set en_cascade_mode [get_property CONFIG.C_EN_CASCADE_MODE [get_cells -hier $periph]]\n set sink_pn [::hsi::utils::get_sink_pins $intr_pin]\n set peri [::hsi::get_cells -of_objects $sink_pn]\n set periph_ip [get_property IP_NAME [get_cells -hier $peri]]\n if {[string match -nocase $periph_ip \"xlconcat\"]} {\n set dout \"dout\"\n set intr_pin [::hsi::get_pins -of_objects $peri -filter \"NAME==$dout\"]\n set pins [::hsi::utils::get_sink_pins \"$intr_pin\"]\n set perih [::hsi::get_cells -of_objects $pins]\n if {[string match -nocase \"[get_property IP_NAME $perih]\" \"axi_intc\"]} {\n set cascade_master [get_property CONFIG.C_CASCADE_MASTER [get_cells -hier $perih]]\n set en_cascade_mode [get_property CONFIG.C_EN_CASCADE_MODE [get_cells -hier $perih]]\n }\n }\n set number [regexp -all -inline -- {[0-9]+} $sink_pn]\n return $number\n }\n }\n\n if {[string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psu_cortexa53\"]\n\t|| [string match -nocase $proctype \"ps7_cortexa9\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\tif {[string match -nocase \"[get_property IP_NAME $periph]\" \"axi_intc\"]} {\n\t\tset ip [get_property IP_NAME $periph]\n\t\tset cascade_master [get_property CONFIG.C_CASCADE_MASTER [get_cells -hier $periph]]\n\t\tset en_cascade_mode [get_property CONFIG.C_EN_CASCADE_MODE [get_cells -hier $periph]]\n\t\tset sink_pn [::hsi::utils::get_sink_pins $intr_pin]\n\t\tset peri [::hsi::get_cells -of_objects $sink_pn]\n\t\tset periph_ip [get_property IP_NAME [get_cells -hier $peri]]\n\t\tif {[string match -nocase $periph_ip \"xlconcat\"]} {\n\t\t\tset dout \"dout\"\n\t\t\tset intr_pin [::hsi::get_pins -of_objects $peri -filter \"NAME==$dout\"]\n\t\t\tset pins [::hsi::utils::get_sink_pins \"$intr_pin\"]\n\t\t\tset periph [::hsi::get_cells -of_objects $pins]\n\t\t\tif {[string match -nocase \"[get_property IP_NAME $periph]\" \"axi_intc\"]} {\n\t\t\t\tset cascade_master [get_property CONFIG.C_CASCADE_MASTER [get_cells -hier $periph]]\n\t\t\t\tset en_cascade_mode [get_property CONFIG.C_EN_CASCADE_MODE [get_cells -hier $periph]]\n\t\t\t}\n\t\t\tif {$en_cascade_mode == 1} {\n\t\t\t\tset number [regexp -all -inline -- {[0-9]+} $sink_pn]\n\t\t\t\treturn $number\n\t\t\t}\n\t\t}\n\t}\n }\n\n set concat_block 0\n foreach sink_pin $sink_pins {\n set sink_periph [::hsi::get_cells -of_objects $sink_pin]\n\tif {[llength $sink_periph] == 0 } {\n\t\tcontinue\n\t}\n set connected_ip [get_property IP_NAME [get_cells -hier $sink_periph]]\n\tif {[llength $connected_ip]} {\n\t\tif {[string compare -nocase \"$connected_ip\" \"dfx_decoupler\"] == 0} {\n\t\t\tset dfx_intr [get_pins -of_objects $sink_periph -filter {TYPE==INTERRUPT&&DIRECTION==O}]\n\t\t\tset intr_pin [::hsi::get_pins -of_objects $sink_periph -filter \"NAME==$dfx_intr\"]\n\t\t\tset sink_pins [::hsi::utils::get_sink_pins \"$intr_pin\"]\n\t\t\tforeach pin $sink_pins {\n\t\t\t\tset sink_pin $pin\n\t\t\t\tif {[string match -nocase $sink_pin \"IRQ0_F2P\"]} {\n\t\t\t\t\tset sink_pin \"IRQ0_F2P\"\n\t\t\t\t\tbreak\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase $sink_pin \"IRQ1_F2P\"]} {\n\t\t\t\t\tset sink_pin \"IRQ1_F2P\"\n\t\t\t\t\tbreak\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tif {[llength $connected_ip]} {\n\t\t# check for direct connection or concat block connected\n\t\tif { [string compare -nocase \"$connected_ip\" \"xlconcat\"] == 0 } {\n\t\t\tset pin_number [regexp -all -inline -- {[0-9]+} $sink_pin]\n\t\t\tset number 0\n\t\t\tglobal intrpin_width\n\t\t\tfor { set i 0 } {$i <= $pin_number} {incr i} {\n\t\t\t\tset pin_wdth [get_property LEFT [ lindex [ get_pins -of_objects [get_cells -hier $sink_periph ] ] $i ] ]\n\t\t\t\tif { $i == $pin_number } {\n\t\t\t\t\tset intrpin_width [expr $pin_wdth + 1]\n\t\t\t\t} else {\n\t\t\t\t\tset number [expr $number + {$pin_wdth + 1}]\n\t\t\t\t}\n\t\t\t}\n\t\t\tdtg_debug \"Full pin width for $sink_periph of $sink_pin:$number intrpin_width:$intrpin_width\"\n\t\t\tset dout \"dout\"\n\t\t\tset concat_block 1\n\t\t\tset intr_pin [::hsi::get_pins -of_objects $sink_periph -filter \"NAME==$dout\"]\n\t\t\tset sink_pins [::hsi::utils::get_sink_pins \"$intr_pin\"]\n\t\t\tset sink_periph [::hsi::get_cells -of_objects $sink_pins]\n\t\t\tset connected_ip [get_property IP_NAME [get_cells -hier $sink_periph]]\n\t\t\twhile {[llength $connected_ip]} {\n\t\t\t\tif {![string match -nocase \"$connected_ip\" \"xlconcat\"]} {\n\t\t\t\t\tbreak\n\t\t\t\t}\n\t\t\t\tset dout \"dout\"\n\t\t\t\tset intr_pin [::hsi::get_pins -of_objects $sink_periph -filter \"NAME==$dout\"]\n\t\t\t\tset sink_pins [::hsi::utils::get_sink_pins $intr_pin]\n\t\t\t\tset sink_periph [::hsi::get_cells -of_objects $sink_pins]\n\t\t\t\tset connected_ip [get_property IP_NAME [get_cells -hier $sink_periph]]\n\t\t\t}\n\t\t\tforeach pin $sink_pins {\n\t\t\t\tset sink_pin $pin\n\t\t\t\tif {[string match -nocase $sink_pin \"IRQ0_F2P\"]} {\n\t\t\t\t\tset sink_pin \"IRQ0_F2P\"\n\t\t\t\t\tbreak\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase $sink_pin \"IRQ1_F2P\"]} {\n\t\t\t\t\tset sink_pin \"IRQ1_F2P\"\n\t\t\t\t\tbreak\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\t# check for ORgate or util_ff\n\tif { [string compare -nocase \"$sink_pin\" \"Op1\"] == 0 || [string compare -nocase \"$sink_pin\" \"D\"] == 0 } {\n if { [string compare -nocase \"$sink_pin\" \"Op1\"] == 0 } {\n\t\t set dout \"Res\"\n } elseif { [string compare -nocase \"$sink_pin\" \"D\"] == 0 } {\n set dout \"Q\"\n }\n\t\tset sink_periph [::hsi::get_cells -of_objects $sink_pin]\n\t\tif {[llength $sink_periph]} {\n\t\t\tset intr_pin [::hsi::get_pins -of_objects $sink_periph -filter \"NAME==$dout\"]\n\t\t\tif {[llength $intr_pin]} {\n\t\t\t\tset sink_pins [::hsi::utils::get_sink_pins \"$intr_pin\"]\n\t\t\t\tforeach pin $sink_pins {\n\t\t\t\t\tset sink_pin $pin\n\t\t\t\t}\n\t\t\t\tset sink_periph [::hsi::get_cells -of_objects $sink_pin]\n\t\t\t\tif {[llength $sink_periph]} {\n\t\t\t\t\tset connected_ip [get_property IP_NAME [get_cells -hier $sink_periph]]\n\t\t\t\t\tif { [string compare -nocase \"$connected_ip\" \"xlconcat\"] == 0 } {\n\t\t\t\t\t\tset number [regexp -all -inline -- {[0-9]+} $sink_pin]\n\t\t\t\t\t\tset dout \"dout\"\n\t\t\t\t\t\tset concat_block 1\n\t\t\t\t\t\tset intr_pin [::hsi::get_pins -of_objects $sink_periph -filter \"NAME==$dout\"]\n\t\t\t\t\t\tif {[llength $intr_pin]} {\n\t\t\t\t\t\t\tset sink_pins [::hsi::utils::get_sink_pins \"$intr_pin\"]\n\t\t\t\t\t\t\tforeach pin $sink_pins {\n\t\t\t\t\t\t\t\tset sink_pin $pin\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n # generate irq id for IRQ1_F2P\n if { [string compare -nocase \"$sink_pin\" \"IRQ1_F2P\"] == 0 } {\n if {$found == 1} {\n set irqval $pl_ps_irq1\n set pl_ps_irq1 [expr $pl_ps_irq1 + 1]\n if {$concat_block == \"0\"} {\n return [lindex $intr_list_irq1 $irqval]\n } else {\n set ret [expr 104 + $number]\n return $ret\n }\n }\n } elseif { [string compare -nocase \"$sink_pin\" \"IRQ0_F2P\"] == 0 } {\n # generate irq id for IRQ0_F2P\n if {$found == 1} {\n set irqval $pl_ps_irq0\n set pl_ps_irq0 [expr $pl_ps_irq0 + 1]\n if {$concat_block == \"0\"} {\n return [lindex $intr_list_irq0 $irqval]\n } else {\n set ret [expr 89 + $number]\n return $ret\n }\n }\n\t} elseif {[regexp \"^pl_ps_irq.*\" \"$sink_pin\" match] && \\\n\t\t\t[expr [string trim \"$sink_pin\" \"pl_ps_irq\"] <= 15]} {\n if {$concat_block == \"0\"} {\n\t\t\tset intr_index [string trim \"$sink_pin\" \"pl_ps_irq\"]\n\t\t\tset ret [expr 84 + $intr_index]\n\t\t} else {\n\t\t\tset ret [expr 84 + $number]\n\t\t}\n\t} elseif {[regexp \"^pl_psx_irq.*\" \"$sink_pin\" match] && \\\n\t\t\t[expr [string trim \"$sink_pin\" \"pl_psx_irq\"] <= 15]} {\n if {$concat_block == \"0\"} {\n\t\t\tset intr_index [string trim \"$sink_pin\" \"pl_psx_irq\"]\n\t\t\tset ret [expr 104 + $intr_index]\n\t\t} else {\n\t\t\tset ret [expr 104 + $number]\n\t\t}\n } else {\n set sink_periph [::hsi::get_cells -of_objects $sink_pin]\n\t if {[llength $sink_periph] == 0 } {\n\t\tbreak\n\t }\n set connected_ip [get_property IP_NAME [get_cells -hier $sink_periph]]\n if {[string match -nocase $connected_ip \"axi_intc\"] } {\n set sink_pin [::hsi::get_pins -of_objects $periph -filter {TYPE==INTERRUPT && DIRECTION==O}]\n }\n if {[llength $sink_pin] == 1} {\n set port_width [::hsi::utils::get_port_width $sink_pin]\n } else {\n\t foreach pin $sink_pin {\n set port_width [::hsi::utils::get_port_width $pin]\n\t }\n }\n }\n }\n\n set id $ret\n return $ret\n}\n\nproc check_ip_trustzone_state { drv_handle } {\n set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n if {[string match -nocase $proctype \"psu_cortexa53\"]} {\n set index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $drv_handle]\n\tif {$index == -1 } {\n\t\treturn 0\n\t}\n set avail_param [list_property [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]]\n if {[lsearch -nocase $avail_param \"TRUSTZONE\"] >= 0} {\n set state [get_property TRUSTZONE [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]]\n # Don't generate status okay when the peripheral is in Secure Trustzone\n if {[string match -nocase $state \"Secure\"]} {\n return 1\n }\n }\n } elseif {[string match -nocase $proctype \"psv_cortexa72\"]} {\n set index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $drv_handle]\n\tif {$index == -1 } {\n\t\treturn 0\n\t}\n set avail_param [list_property [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]]\n if {[lsearch -nocase $avail_param \"TRUSTZONE\"] >= 0} {\n set state [get_property TRUSTZONE [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]]\n # Don't generate status okay when the peripheral is in Secure Trustzone\n if {[string match -nocase $state \"Secure\"]} {\n return 1\n }\n }\n } elseif {[string match -nocase $proctype \"psx_cortexa78\"]} {\n set index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $drv_handle]\n\tif {$index == -1 } {\n\t\treturn 0\n\t}\n set avail_param [list_property [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]]\n if {[lsearch -nocase $avail_param \"TRUSTZONE\"] >= 0} {\n set state [get_property TRUSTZONE [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]]\n # Don't generate status okay when the peripheral is in Secure Trustzone\n if {[string match -nocase $state \"Secure\"]} {\n return 1\n }\n }\n } else {\n\treturn 0\n }\n}\n\nproc generate_cci_node { drv_handle rt_node} {\n\tset avail_param [list_property [get_cells -hier $drv_handle]]\n\tif {[lsearch -nocase $avail_param \"CONFIG.IS_CACHE_COHERENT\"] >= 0} {\n\t\tset cci_enable [get_property CONFIG.IS_CACHE_COHERENT [get_cells -hier $drv_handle]]\n\t\tset iptype [get_property IP_NAME [get_cells -hier $drv_handle]]\n\t\tset nodma_coherent_list \"psu_sata\"\n\t\tif {[lsearch $nodma_coherent_list $iptype] >= 0} {\n\t\t\t#CR 974156, as per 2017.1 PCW update\n\t\t\treturn\n\t\t}\n\t\tif {[string match -nocase $cci_enable \"1\"]} {\n\t\t\thsi::utils::add_new_dts_param $rt_node \"dma-coherent\" \"\" boolean\n\t\t}\n\t}\n}\n\n#This function is used to generate the reg property\n#by passing baseaddr and highaddr.\n#In case if we want rewrite the existing reg property\n#or 64bit addressing we want to do in reg, we can use this\n#function.\nproc generate_reg_property {base high} {\n\tset size [format 0x%x [expr {${high} - ${base} + 1}]]\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tif { $proctype in { \"psu_cortexa53\" \"psv_cortexa72\" \"psx_cortexa78\" }} {\n\t\t# When both base and size are 64 bit\n\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$base\" match]} {\n\t\t\tset temp $base\n\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\tset len [string length $temp]\n\t\t\tset rem [expr {${len} - 8}]\n\t\t\tset high_base \"0x[string range $temp $rem $len]\"\n\t\t\tset low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\tset low_base [format 0x%08x $low_base]\n\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$size\" match]} {\n\t\t\t\tset temp $size\n\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\tset len [string length $temp]\n\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\tset high_size \"0x[string range $temp $rem $len]\"\n\t\t\t\tset low_size \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\tset low_size [format 0x%08x $low_size]\n\t\t\t\tset reg \"$low_base $high_base $low_size $high_size\"\n\t\t\t} else {\n\t\t\t\tset reg \"$low_base $high_base 0x0 $size\"\n\t\t\t}\n\t\t# When base has 32 bit and size has 64 bit\n\t\t} elseif {[regexp -nocase {0x([0-9a-f]{9})} \"$size\" match]} {\n\t\t\tset temp $size\n\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\tset len [string length $temp]\n\t\t\tset rem [expr {${len} - 8}]\n\t\t\tset high_size \"0x[string range $temp $rem $len]\"\n\t\t\tset low_size \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\tset low_size [format 0x%08x $low_size]\n\t\t\tset reg \"0x0 $base $low_size $high_size\"\n\t\t} else {\n\t\t\tset reg \"0x0 $base 0x0 $size\"\n\t\t}\n\t} else {\n\t\tset reg \"$base $size\"\n\t}\n\treturn $reg\n}\n\n# Generating static vtc node\n# As it is subcore inside subsystem(ex:hdmi_tx)\nproc generate_vtc_node {drv_handle base_addr} {\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tset dts_file [current_dt_tree]\n\tset baseaddr_v_tc [format 0x%x [expr $base_addr + 0x10000]]\n\tset regval \"0x0 $baseaddr_v_tc 0x0 0x10000\"\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n\tset vtc_node [add_or_get_dt_node -n \"v_tc_$drv_handle\" -l \"v_tc_$drv_handle\" -u ${baseaddr_v_tc} -d ${dts_file} -p $bus_node]\n\thsi::utils::add_new_dts_param \"${vtc_node}\" \"clock-names\" \"clk, s_axi_aclk\" stringlist\n\thsi::utils::add_new_dts_param \"${vtc_node}\" \"clocks\" \"misc_clk_2\" reference\n\thsi::utils::add_new_dts_param \"${vtc_node}\" \"compatible\" \"xlnx,bridge-v-tc-6.1\" string\n\thsi::utils::add_new_dts_param \"${vtc_node}\" \"reg\" $regval intlist\n}\n" }, { "path": "device_tree/data/device_tree.mld", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\n#\n# The Device-Tree BSP generator\n#\nOPTION psf_version = 2.1;\n\nBEGIN OS device_tree\nOPTION DRC = device_tree_drc;\nOPTION OS_TYPE = DTS\nOPTION SUPPORTED_PERIPHERALS = (microblaze ps7_cortexa9 psu_cortexa53 psv_cortexa72 psx_cortexa78);\nOPTION DESC = \"Generate flat device tree\";\nOPTION COMPILE_BSP = FALSE;\n\nPARAMETER name = dtg_version, desc = \"DTG version\", default = \"2014.4\";\n\nPARAMETER name = partial_image, desc = \"Partial image Support\", type = bool, default = false;\n\nPARAMETER name = dt_overlay, desc = \"Enable Device-tree Overlay support\", type = bool, default = false;\n\nPARAMETER name = dt_setbaud, desc = \"Set the baud rate\", type = int, default = false;\n\nPARAMETER name = dt_zocl, desc = \"Enable ZOCL Accelerator platform support\", type = bool, default = false;\n\nPARAMETER name = firmware_name, desc = \"Device-tree Overlay Firmware name\", type = string, default = \"\";\n\nPARAMETER name = remove_pl, desc = \"Remove PL Support\", type = bool, default = false;\n\nPARAMETER name = dt_verbose, desc = \"VERBOSE logging Support\", type = bool, default = false;\n\nPARAMETER name = no_alias, desc = \"No Alias Support\", type = bool, default = false;\n\nPARAMETER name = dtg_alias, desc = \"DTG generated Alias Support\", type = bool, default = false;\n\nPARAMETER name = no_labels, desc = \"Dont generate the Lables\", type = bool, default = false;\n\nPARAMETER name = mainline_kernel, desc = \"Kernel mainline version\", type = enum, values = (\"none\" = none, \"v4.17\" = v4.17, \"v4.18\" = v4.18, \"v4.19\" = v4.19, \"v5.0\" = v5.0, \"v5.1\" = v5.1, \"v5.2\" = v5.2, \"v5.3\" = v5.3, \"v5.4\" = v5.4), default = none;\n\nPARAMETER name = overlay_custom_dts, desc = \"Overlay custom dts filename\", type = string, default =\"\";\n\nPARAMETER name = partial_overlay_custom_dts, desc = \"Partial overlay custom dts filename\", type = string, default =\"\";\n\nPARAMETER name = bootargs, desc = \"Booting arguments\", type = string, default = \"\";\n\nPARAMETER name = console_device, desc = \"Instance name of IP core for boot console (e.g. RS232_Uart_1, not xps_uart16550)\", type = peripheral_instance, range = (axi_uart16550, axi_uartlite, ps7_uart, psu_uart, psv_sbsauart, psx_sbsauart), default = none;\n\nPARAMETER name = periph_type_overrides, desc = \"List of peripheral type overrides\", type = string, default = \"\";\nPARAMETER name = main_memory, desc = \"Name of Main Memory used with PetaLinux\", type = peripheral_instance, range = (ps7_ddr, psu_ddr, mpmc, mig_7series, axi_emc), default = none;\nPARAMETER name = kernel_version, desc = \"Target kernel version\", type = enum, values = (\"2014.4\" = 2014.4, \"2015.1\" = 2015.1, \"2015.2\" = 2015.2, \"2015.3\" = 2015.3, \"2015.4\" = 2015.4, \"2016.1\" = 2016.1, \"2016.2\" = 2016.2, \"2016.3\" = 2016.3, \"2016.4\" = 2016.4, \"2017.1\" = 2017.1, \"2017.2\" = 2017.2, \"2017.3\" = 2017.3, \"2017.4\" = 2017.4, \"2018.1\" = 2018.1, \"2018.2\" = 2018.2, \"2018.3\" = 2018.3, \"2019.1\" = 2019.1, \"2019.2\" = 2019.2, \"2020.1\" = 2020.1, \"2020.2\" = 2020.2, \"2021.1\" = 2021.1, \"2021.2\" = 2021.2, \"2022.1\" = 2022.1, \"2022.2\" = 2022.2, \"2023.1\" = 2023.1, \"2023.2\" = 2023.2, \"2024.1\" = 2024.1, \"2024.2\" = 2024.2), default = 2024.2;\nPARAMETER name = pcw_dts, desc = \"Target dts filename for PCW configurations\", type = string, default = pcw.dtsi;\nPARAMETER name = master_dts, desc = \"Master dts filename\", type = string, default = system-top.dts;\nPARAMETER name = classic_soc, desc = \"To diff classic and dfx flow\", type = bool, default = false;\nEND OS\n" }, { "path": "device_tree/data/device_tree.mss", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nPARAMETER VERSION = 2.2.0\n\nBEGIN OS\n PARAMETER OS_NAME = device_tree\n PARAMETER console_device = *\n PARAMETER main_memory = *\nEND\n" }, { "path": "device_tree/data/device_tree.tcl", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nforeach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n}\n\nproc get_ip_prop {drv_handle pram} {\n set ip [get_cells -hier $drv_handle]\n set value [get_property ${pram} $ip]\n return $value\n}\n\nproc inc_os_prop {drv_handle os_conf_dev_var var_name conf_prop} {\n set ip_check \"False\"\n set os_ip [get_property ${os_conf_dev_var} [get_os]]\n if {![string match -nocase \"\" $os_ip]} {\n set os_ip [get_property ${os_conf_dev_var} [get_os]]\n set ip_check \"True\"\n }\n\n set count [hsi::utils::get_os_parameter_value $var_name]\n if {[llength $count] == 0} {\n if {[string match -nocase \"True\" $ip_check]} {\n set count 1\n } else {\n set count 0\n }\n }\n\n if {[string match -nocase \"True\" $ip_check]} {\n set ip [get_cells -hier $drv_handle]\n if {[string match -nocase $os_ip $ip]} {\n set ip_type [get_property IP_NAME $ip]\n set_property ${conf_prop} 0 $drv_handle\n return\n }\n }\n\n set_property $conf_prop $count $drv_handle\n incr count\n ::hsi::utils::set_os_parameter_value $var_name $count\n}\n\nproc gen_count_prop {drv_handle data_dict} {\n dict for {dev_type dev_conf_mapping} [dict get $data_dict] {\n set os_conf_dev_var [dict get $data_dict $dev_type \"os_device\"]\n set valid_ip_list [dict get $data_dict $dev_type \"ip\"]\n set drv_conf [dict get $data_dict $dev_type \"drv_conf\"]\n set os_count_name [dict get $data_dict $dev_type \"os_count_name\"]\n\n set slave [get_cells -hier $drv_handle]\n set iptype [get_property IP_NAME $slave]\n if {[lsearch $valid_ip_list $iptype] < 0} {\n continue\n }\n\n set irq_chk [dict get $data_dict $dev_type \"irq_chk\"]\n if {![string match -nocase \"false\" $irq_chk]} {\n set irq_id [::hsi::utils::get_interrupt_id $slave $irq_chk]\n if {[llength $irq_id] < 0} {\n dtg_warning \"Fail to located interrupt pin - $irq_chk. The $drv_conf is not set for $dev_type\"\n continue\n }\n }\n\n inc_os_prop $drv_handle $os_conf_dev_var $os_count_name $drv_conf\n }\n}\n\nproc gen_dev_conf {} {\n # data to populated certain configs for different devices\n set data_dict {\n uart {\n os_device \"CONFIG.console_device\"\n ip \"axi_uartlite axi_uart16550 ps7_uart psu_uart psv_uart psx_sbsauart\"\n os_count_name \"serial_count\"\n drv_conf \"CONFIG.port-number\"\n irq_chk \"false\"\n }\n mdm_uart {\n os_device \"CONFIG.console_device\"\n ip \"mdm\"\n os_count_name \"serial_count\"\n drv_conf \"CONFIG.port-number\"\n irq_chk \"Interrupt\"\n }\n syace {\n os_device \"sysace_device\"\n ip \"axi_sysace\"\n os_count_name \"sysace_count\"\n drv_conf \"CONFIG.port-number\"\n irq_chk \"false\"\n }\n traffic_gen {\n os_device \"trafficgen_device\"\n ip \"axi_traffic_gen\"\n os_count_name \"trafficgen_count\"\n drv_conf \"CONFIG.xlnx,device-id\"\n irq_chk \"false\"\n }\n }\n # update CONFIG. for each driver when match driver is found\n foreach drv [get_drivers] {\n gen_count_prop $drv $data_dict\n }\n}\n\n# For calling from top level BSP\nproc bsp_drc {os_handle} {\n}\n\n# If standalone purpose\nproc device_tree_drc {os_handle} {\n bsp_drc $os_handle\n hsi::utils::add_new_child_node $os_handle \"global_params\"\n}\n\nproc extract_dts_name {override value} {\n set idx [lsearch -exact $override $value]\n set var [lreplace $override $idx $idx]\n return $var\n}\n\nproc gen_edac_node {} {\n\tset dts_file [get_property CONFIG.pcw_dts [get_os]]\n\tset edac_node [add_or_get_dt_node -n &xilsem_edac -d $dts_file]\n\tset pspmc [get_cells -hier -filter {IP_NAME == \"pspmc\"}]\n\tif {[llength $pspmc]} {\n\t\tif { [get_property CONFIG.SEM_MEM_SCAN $pspmc] || [get_property CONFIG.SEM_NPI_SCAN $pspmc] } {\n\t\t\thsi::utils::add_new_dts_param \"${edac_node}\" \"status\" \"okay\" string\n\t\t}\n\t}\n}\n\nproc gen_ddrmc_node {} {\n\tset dts_file [get_property CONFIG.pcw_dts [get_os]]\n\tset ddrmc [get_cells -hier -filter {IP_NAME == \"noc_mc_ddr4\"}]\n\tif {[llength $ddrmc]} {\n\t\tset i 0\n\t\tforeach mc $ddrmc {\n\t\t\tset ddrmc_node [add_or_get_dt_node -n &mc$i -d $dts_file]\n\t\t\tif { [get_property CONFIG.MC_ECC $mc] } {\n\t\t\t\thsi::utils::add_new_dts_param \"${ddrmc_node}\" \"status\" \"okay\" string\n\t\t\t}\n\t\t\tincr i\n\t\t}\n\t}\n\n}\n\nproc gen_sata_laneinfo {} {\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tif {$remove_pl} {\n\t\treturn 0\n\t}\n\n\tforeach ip [get_cells] {\n\t\tset slane 0\n\t\tset freq {}\n\t\tset ip_type [get_property IP_TYPE [get_cells $ip]]\n\t\t#if {$ip_type eq \"\"} {\n\t\t#\tset ps $ip\n\t\t#}\n\t\tset ps $ip\n\t}\n\n\tset param0 \"/bits/ 8 <0x18 0x40 0x18 0x28>\"\n\tset param1 \"/bits/ 8 <0x06 0x14 0x08 0x0E>\"\n\tset param2 \"/bits/ 8 <0x13 0x08 0x4A 0x06>\"\n\tset param3 \"/bits/ 16 <0x96A4 0x3FFC>\"\n\n\tset param4 \"/bits/ 8 <0x1B 0x4D 0x18 0x28>\"\n\tset param5 \"/bits/ 8 <0x06 0x19 0x08 0x0E>\"\n\tset param6 \" /bits/ 8 <0x13 0x08 0x4A 0x06>\"\n\tset param7 \"/bits/ 16 <0x96A4 0x3FFC>\"\n\n\tset param_list \"ceva,p%d-cominit-params ceva,p%d-comwake-params ceva,p%d-burst-params ceva,p%d-retry-params\"\n\twhile {$slane < 2} {\n\t\tif {[get_property CONFIG.PSU__SATA__LANE$slane\\__ENABLE [get_cells $ps]] == 1} {\n\t\t\tset gt_lane [get_property CONFIG.PSU__SATA__LANE$slane\\__IO [get_cells $ps]]\n\t\t\tregexp [0-9] $gt_lane gt_lane\n\t\t\tlappend freq [get_property CONFIG.PSU__SATA__REF_CLK_FREQ [get_cells $ps]]\n\t\t} else {\n\t\t\tlappend freq 0\n\t\t\t}\n\t\tincr slane\n\t}\n\n\tforeach {i j} $freq {\n\t\tset i [expr {$i ? $i : $j}]\n\t\tset j [expr {$j ? $j : $i}]\n\t}\n\n\tlset freq 0 $i\n\tlset freq 1 $j\n\tset dts_file [get_property CONFIG.pcw_dts [get_os]]\n\tset sata_node [add_or_get_dt_node -n &sata -d $dts_file]\n\tset hsi_version [get_hsi_version]\n\tset ver [split $hsi_version \".\"]\n\tset version [lindex $ver 0]\n\n\tset slane 0\n\twhile {$slane < 2} {\n\t\tset f [lindex $freq $slane]\n\t\tset count 0\n\t\tif {$f != 0} {\n\t\t\twhile {$count < 4} {\n\t\t\t\tif {$version < 2018} {\n\t\t\t\t\tdtg_warning \"quotes to be removed or use 2018.1 version for $sata_node params param0..param7\"\n\t\t\t\t}\n\t\t\t\tset val_name [format [lindex $param_list $count] $slane]\n\t\t\t\tswitch $count {\n\t\t\t\t\t\"0\" {\n\t\t\t\t\thsi::utils::add_new_dts_param $sata_node $val_name $param0 noformating\n\t\t\t\t\t}\n\t\t\t\t\t\"1\" {\n\t\t\t\t\thsi::utils::add_new_dts_param $sata_node $val_name $param1 noformating\n\t\t\t\t\t}\n\t\t\t\t\t\"2\" {\n\t\t\t\t\thsi::utils::add_new_dts_param $sata_node $val_name $param2 noformating\n\t\t\t\t\t}\n\t\t\t\t\t\"3\" {\n\t\t\t\t\thsi::utils::add_new_dts_param $sata_node $val_name $param3 noformating\n\t\t\t\t\t}\n\t\t\t\t\t\"4\" {\n\t\t\t\t\thsi::utils::add_new_dts_param $sata_node $val_name $param4 noformating\n\t\t\t\t\t}\n\t\t\t\t\t\"5\" {\n\t\t\t\t\thsi::utils::add_new_dts_param $sata_node $val_name $param5 noformating\n\t\t\t\t\t}\n\t\t\t\t\t\"6\" {\n\t\t\t\t\thsi::utils::add_new_dts_param $sata_node $val_name $param6 noformating\n\t\t\t\t\t}\n\t\t\t\t\t\"7\" {\n\t\t\t\t\thsi::utils::add_new_dts_param $sata_node $val_name $param7 noformating\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\tincr count\n\t\t\t}\n\t\t}\n\tincr slane\n\t}\n}\n\nproc gen_ext_axi_interface {} {\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tif {$remove_pl} {\n\t\treturn 0\n\t}\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\tset ext_axi_intf [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]] -filter {INSTANCE ==\"\"}]\n\t\tset hsi_version [get_hsi_version]\n\t\tset ver [split $hsi_version \".\"]\n\t\tset version [lindex $ver 0]\n\t\tset intf_count 0\n\t\tforeach drv_handle $ext_axi_intf {\n\t\t\tset base [string tolower [get_property BASE_VALUE $drv_handle]]\n\t\t\tset high [string tolower [get_property HIGH_VALUE $drv_handle]]\n\t\t\tset size [format 0x%x [expr {${high} - ${base} + 1}]]\n\t\t\tset default_dts [get_property CONFIG.pcw_dts [get_os]]\n\t\t\tset root_node [add_or_get_dt_node -n / -d ${default_dts}]\n\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$base\" match]} {\n\t\t\t\tset temp $base\n\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\tset len [string length $temp]\n\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\tset high_base \"0x[string range $temp $rem $len]\"\n\t\t\t\tset low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\tset low_base [format 0x%08x $low_base]\n\t\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$size\" match]} {\n\t\t\t\t\tset temp $size\n\t\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\t\tset len [string length $temp]\n\t\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\t\tset high_size \"0x[string range $temp $rem $len]\"\n\t\t\t\t\tset low_size \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\t\tset low_size [format 0x%08x $low_size]\n\t\t\t\t\tset reg \"$low_base $high_base $low_size $high_size\"\n\t\t\t\t} else {\n\t\t\t\t\tset reg \"$low_base $high_base 0x0 $size\"\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tset reg \"0x0 $base 0x0 $size\"\n\t\t\t}\n\t\t\tregsub -all {^0x} $base {} base\n\t\t\tset ext_int_node [add_or_get_dt_node -n $drv_handle -l $drv_handle$intf_count -u $base -d $default_dts -p $root_node]\n\t\t\thsi::utils::add_new_dts_param $ext_int_node \"reg\" \"$reg\" intlist\n\t\t\tincr intf_count\n\t\t\tif {$version >= 2018} {\n\t\t\t\thsi::utils::add_new_dts_param \"${ext_int_node}\" \"/* This is a external AXI interface, user may need to update the entries */\" \"\" comment\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc gen_include_headers {} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\tset kernel_ver [get_property CONFIG.kernel_version [get_os]]\n\t\tset includes_dir [file normalize \"[get_property \"REPOSITORY\" $i]/data/kernel_dtsi/${kernel_ver}/include\"]\n\t\tset dir_path \"./\"\n\t\t# Copy full include directory to dt WS\n\t\tif {[file exists $includes_dir]} {\n\t\t\tfile delete -force -- $dir_path/include\n\t\t\tfile copy -force $includes_dir $dir_path\n\t\t}\n\t}\n}\n\nproc gen_include_dtfile {args} {\n\tset kernel_dtsi [lindex $args 0]\n\tset fp [open $kernel_dtsi r]\n\tset file_data [read $fp]\n\tset data [split $file_data \"\\n\"]\n\tset include_regexp {^#include \\\".*\\.dts.*\\\"$}\n\tforeach line $data {\n\t\tif {[regexp $include_regexp $line matched]} {\n\t\t\tset include_dt [lindex [split $line \" \"] 1]\n\t\t\tregsub -all \" |\\t|;|\\\"\" $include_dt {} include_dt\n\t\t\tforeach file [glob [file normalize [file dirname ${kernel_dtsi}]/*]] {\n\t\t\t\t# NOTE: ./ works only if we did not change our directory\n\t\t\t\tif {[regexp $include_dt $file match]} {\n\t\t\t\t\tfile copy -force $file ./\n\t\t\t\t\tgen_include_dtfile \"$file\"\n break\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc gen_board_info {} {\n # periph_type_overrides = {BOARD KC705 full/lite} or {BOARD ZYNQ} or {BOARD ZC1751 ES2/ES1}\n set overrides [get_property CONFIG.periph_type_overrides [get_os]]\n if {[string match $overrides \"\"]} {\n\t\treturn\n }\n foreach i [get_sw_cores device_tree] {\n foreach override $overrides {\n\tif {[lindex $override 0] == \"BOARD\"} {\n\t\tset first_element [lindex $override 0]\n\t\tset dtsi_file [lindex $override 1]\n\t\tif {[file exists $dtsi_file]} {\n\t\t\tset dir [pwd]\n\t\t\tset pathtype [file pathtype $dtsi_file]\n\t\t\tif {[string match -nocase $pathtype \"relative\"]} {\n\t\t\t\tdtg_warning \"checking file:$dtsi_file pwd:$dir\"\n\t\t\t\t#Get the absolute path from relative path\n\t\t\t\tset dtsi_file [file normalize $dtsi_file]\n\t\t\t}\n\t\t\tfile copy -force $dtsi_file ./\n\t\t\tupdate_system_dts_include [file tail $dtsi_file]\n\t\t\treturn\n\t\t}\n\t\tset kernel_ver [get_property CONFIG.kernel_version [get_os]]\n\t\tset includes_dir [file normalize \"[get_property \"REPOSITORY\" $i]/data/kernel_dtsi/${kernel_ver}/include\"]\n\t\tset dir_path \"./\"\n\t\t# Copy full include directory to dt WS\n\t\tif {[file exists $includes_dir]} {\n\t\t\tfile delete -force -- $dir_path/include\n\t\t\tfile copy -force $includes_dir $dir_path\n\t\t}\n\t\tset dts_name [string tolower [lindex $override 1]]\n\t\tif {[string match -nocase $dts_name \"template\"]} {\n\t\t\treturn\n\t\t}\n\t\tif {[llength $dts_name] == 0} {\n\t\t\treturn\n\t\t}\n\t\tset mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n\t\tset valid_mainline_kernel_list \"v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4\"\n\t\tif {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } {\n\t\t\tset mainline_dtsi [file normalize \"[get_property \"REPOSITORY\" $i]/data/kernel_dtsi/${mainline_ker}/board\"]\n\t\t\tif {[file exists $mainline_dtsi]} {\n\t\t\t\tset mainline_board_file 0\n\t\t\t\tforeach file [glob [file normalize [file dirname ${mainline_dtsi}]/board/*]] {\n\t\t\t\t\tset dtsi_name \"$dts_name.dtsi\"\n\t\t\t\t\t# NOTE: ./ works only if we did not change our directory\n\t\t\t\t\tif {[regexp $dtsi_name $file match]} {\n\t\t\t\t\t\tfile copy -force $file ./\n\t\t\t\t\t\tupdate_system_dts_include [file tail $file]\n\t\t\t\t\t\tset mainline_board_file 1\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {$mainline_board_file == 0} {\n\t\t\t\t\terror \"Error:$dtsi_name board file is not present in DTG. Please add a vaild board.\"\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tset kernel_dtsi [file normalize \"[get_property \"REPOSITORY\" $i]/data/kernel_dtsi/${kernel_ver}/BOARD\"]\n\t\t\tif {[file exists $kernel_dtsi]} {\n\t\t\t\tset valid_board_file 0\n\t\t\t\tforeach file [glob [file normalize [file dirname ${kernel_dtsi}]/BOARD/*]] {\n\t\t\t\t\tset dtsi_name \"$dts_name.dtsi\"\n\t\t\t\t\t# NOTE: ./ works only if we did not change our directory\n\t\t\t\t\tif {[regexp $dtsi_name $file match]} {\n\t\t\t\t\t\tfile copy -force $file ./\n\t\t\t\t\t\tupdate_system_dts_include [file tail $file]\n\t\t\t\t\t\tset valid_board_file 1\n\t\t\t\t\t\tgen_include_dtfile \"${file}\"\n\t\t\t\t\t\tbreak\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {$valid_board_file == 0} {\n\t\t\t\t\terror \"Error:$dtsi_name board file is not present in DTG. Please add a valid board.\"\n\t\t\t\t}\n\t\t\t\tset default_dts [get_property CONFIG.master_dts [get_os]]\n\t\t\t\tset root_node [add_or_get_dt_node -n / -d ${default_dts}]\n\t\t\t} else {\n\t\t\t\tputs \"File not found\\n\\r\"\n\t\t\t}\n\t\t}\n }\n }\n }\n}\n\nproc gen_zynqmp_ccf_clk {} {\n\tset default_dts [get_property CONFIG.pcw_dts [get_os]]\n\tset ccf_node [add_or_get_dt_node -n \"&pss_ref_clk\" -d $default_dts]\n\tset periph_list [get_cells -hier]\n\tforeach periph $periph_list {\n\t\tset zynq_ultra_ps [get_property IP_NAME $periph]\n\t\tif {[string match -nocase $zynq_ultra_ps \"zynq_ultra_ps_e\"] } {\n\t\t\tset avail_param [list_property [get_cells -hier $periph]]\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__PSS_REF_CLK__FREQMHZ\"] >= 0} {\n\t\t\t\tset freq [get_property CONFIG.PSU__PSS_REF_CLK__FREQMHZ [get_cells -hier $periph]]\n\t\t\t\tif {[string match -nocase $freq \"33.333\"]} {\n\t\t\t\t\treturn\n\t\t\t\t} else {\n\t\t\t\t\tdtg_warning \"Frequency $freq used instead of 33.333\"\n\t\t\t\t\thsi::utils::add_new_dts_param \"${ccf_node}\" \"clock-frequency\" [scan [expr $freq * 1000000] \"%d\"] int\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tset ccf_node [add_or_get_dt_node -n \"&video_clk\" -d $default_dts]\n\tset periph_list [get_cells -hier]\n\tforeach periph $periph_list {\n\t\tset zynq_ultra_ps [get_property IP_NAME $periph]\n\t\tif {[string match -nocase $zynq_ultra_ps \"zynq_ultra_ps_e\"] } {\n\t\t\tset avail_param [list_property [get_cells -hier $periph]]\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ\"] >= 0} {\n\t\t\t\tset freq [get_property CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ [get_cells -hier $periph]]\n\t\t\t\tif {[string match -nocase $freq \"27\"]} {\n\t\t\t\t\treturn\n\t\t\t\t} else {\n\t\t\t\t\tdtg_warning \"Frequency $freq used instead of 27.00\"\n\t\t\t\t\thsi::utils::add_new_dts_param \"${ccf_node}\" \"clock-frequency\" [scan [expr $freq * 1000000] \"%d\"] int\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n}\n\nproc gen_opp_freq {} {\n\tset default_dts [get_property CONFIG.pcw_dts [get_os]]\n\tset cpu_opp_table [add_or_get_dt_node -n \"&cpu_opp_table\" -d $default_dts]\n\tset periph_list [get_cells -hier]\n\tset opp_freq \"\"\n\tset add_opp_prop \"\"\n\tforeach periph $periph_list {\n\t\tset proc_ps [get_property IP_NAME $periph]\n\t\tif {[string match -nocase $proc_ps \"zynq_ultra_ps_e\"] } {\n\t\t\tset avail_param [list_property [get_cells -hier $periph]]\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ\"] >= 0} {\n\t\t\t\tset act_freq \"\"\n\t\t\t\tset div \"\"\n\t\t\t\tset freq [get_property CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ [get_cells -hier $periph]]\n\t\t\t\tif {[string match -nocase $freq \"1200\"]} {\n\t\t\t\t\t# This is the default value set, so no need to calcualte\n\t\t\t\t\treturn\n\t\t\t\t}\n\t\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ\"] >= 0} {\n\t\t\t\t\tset act_freq [get_property CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ [get_cells -hier $periph]]\n\t\t\t\t\tset act_freq [expr $act_freq * 1000000]\n\t\t\t\t}\n\t\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0\"] >= 0} {\n\t\t\t\t\tset div [get_property CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 [get_cells -hier $periph]]\n\t\t\t\t}\n\t\t\t\tif {[llength $act_freq] && [llength $div]} {\n\t\t\t\t\tset opp_freq [expr $act_freq * $div]\n\t\t\t\t}\n\t\t\t\t# if design don't have clock configs then skip adding new opps\n\t\t\t\tif {$opp_freq == \"\"} {\n\t\t\t\t\treturn\n\t\t\t\t}\n\t\t\t\t# Remove default opps\n\t\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp00\" \"\" boolean\n\t\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp01\" \"\" boolean\n\t\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp02\" \"\" boolean\n\t\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp03\" \"\" boolean\n\t\t\t}\n\t\t}\n\t\tif { $proc_ps in { \"versal_cips\" \"ps_wizard\" }} {\n\t\t\tset ps_pmc_params [get_property CONFIG.PS_PMC_CONFIG [get_cells -hier $periph]]\n\t\t\tif {[llength $ps_pmc_params ]} {\n\t\t\t\tset act_freq \"\"\n\t\t\t\tset div \"\"\n\t\t\t\tset clkoutdiv \"\"\n\t\t\t\tif {[dict exists $ps_pmc_params \"PMC_REF_CLK_FREQMHZ\"]} {\n\t\t\t\t\tset act_freq [dict get $ps_pmc_params PMC_REF_CLK_FREQMHZ]\n\t\t\t\t}\n\t\t\t\tif {[dict exists $ps_pmc_params \"PS_CRF_APLL_CTRL_FBDIV\"]} {\n\t\t\t\t\tset div [dict get $ps_pmc_params PS_CRF_APLL_CTRL_FBDIV]\n\t\t\t\t}\n\t\t\t\tif {[dict exists $ps_pmc_params \"PS_CRF_APLL_CTRL_CLKOUTDIV\"]} {\n\t\t\t\t\tset clkoutdiv [dict get $ps_pmc_params PS_CRF_APLL_CTRL_CLKOUTDIV]\n\t\t\t\t}\n\t\t\t\tif {[llength $act_freq] && [llength $div] && [llength $clkoutdiv]} {\n\t\t\t\t\tset opp_freq [expr round([expr ($act_freq * $div) / $clkoutdiv]) * 1000000]\n\t\t\t\t}\n\t\t\t\t# if design don't have clock configs then skip adding new opps\n\t\t\t\tif {$opp_freq == \"\"} {\n\t\t\t\t\treturn\n\t\t\t\t}\n\t\t\t}\n\t\t\t# Remove default opps\n\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp00\" \"\" boolean\n\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp01\" \"\" boolean\n\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp02\" \"\" boolean\n\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp03\" \"\" boolean\n\t\t}\n\t\tif {[string match -nocase $proc_ps \"psx_wizard\"] } {\n\t\t\tset overrides [get_property CONFIG.periph_type_overrides [get_os]]\n\t\t\tset board_dtsi_file \"\"\n\t\t\tforeach override $overrides {\n\t\t\t\tif {[lindex $override 0] == \"BOARD\"} {\n\t\t\t\t\tset board_dtsi_file [lindex $override 1]\n\t\t\t\t}\n\t\t\t}\n\t\t\t#TMP fix to support ipp fixed clocks\n\t\t\tif {[string match -nocase $board_dtsi_file \"versal-net-ipp-rev1.9\"]} {\n\t\t\t\treturn\n\t\t\t}\n\t\t\t#NOTE: CONFIG.PSX_PMCX_CONFIG_INTERNAL this may change\n\t\t\tset psx_pmcx_params [get_property CONFIG.PSX_PMCX_CONFIG_INTERNAL [get_cells -hier $periph]]\n\t\t\tif {[llength $psx_pmcx_params]} {\n\t\t\t\tset act_freq \"\"\n\t\t\t\tset div \"\"\n\t\t\t\tset clkoutdiv \"\"\n\t\t\t\tif {[dict exists $psx_pmcx_params \"PMCX_REF_CLK_FREQMHZ\"]} {\n\t\t\t\t\tset act_freq [dict get $psx_pmcx_params PMCX_REF_CLK_FREQMHZ]\n\t\t\t\t}\n\t\t\t\tif {[dict exists $psx_pmcx_params \"PSX_CRF_APLL1_CTRL_FBDIV\"]} {\n\t\t\t\t\tset div [dict get $psx_pmcx_params PSX_CRF_APLL1_CTRL_FBDIV]\n\t\t\t\t}\n\t\t\t\tif {[dict exists $psx_pmcx_params \"PSX_CRF_APLL1_CTRL_CLKOUTDIV\"]} {\n\t\t\t\t\tset clkoutdiv [dict get $psx_pmcx_params PSX_CRF_APLL1_CTRL_CLKOUTDIV]\n\t\t\t\t}\n\t\t\t\tif {[llength $act_freq] && [llength $div] && [llength $clkoutdiv]} {\n\t\t\t\t\tset opp_freq [expr round([expr ($act_freq * $div) / $clkoutdiv]) * 1000000]\n\t\t\t\t}\n\t\t\t}\n\t\t\t# if design don't have clock configs then skip adding new opps\n\t\t\tif {$opp_freq == \"\"} {\n\t\t\t\treturn\n\t\t\t}\n\t\t\t# Remove default opps\n\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp-1066000000\" \"\" boolean\n\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp-1866000000\" \"\" boolean\n\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp-1900000000\" \"\" boolean\n\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp-1999000000\" \"\" boolean\n\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp-2050000000\" \"\" boolean\n\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp-2100000000\" \"\" boolean\n\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp-2200000000\" \"\" boolean\n\t\t\thsi::utils::add_new_dts_param \"$cpu_opp_table\" \"/delete-node/ opp-2400000000\" \"\" boolean\n\t\t}\n\t}\n\n\tif {[llength $opp_freq]} {\n\t\tset opp00_result [expr int ([expr $opp_freq / 1])]\n\t\tset opp01_result [expr int ([expr $opp_freq / 2])]\n\t\tset opp02_result [expr int ([expr $opp_freq / 3])]\n\t\tset opp03_result [expr int ([expr $opp_freq / 4])]\n\t\tset opp00 \"/bits/ 64 <$opp00_result>\"\n\t\tset opp01 \"/bits/ 64 <$opp01_result>\"\n\t\tset opp02 \"/bits/ 64 <$opp02_result>\"\n\t\tset opp03 \"/bits/ 64 <$opp03_result>\"\n\t\tset opp_microvolt \"<1000000>\"\n\t\tset clock_latency \"<500000>\"\n\t\t# Create opp table as per dt-bindings\n\t\tset opp00_table [add_or_get_dt_node -n \"opp-${opp00_result}\" -d $default_dts -p $cpu_opp_table]\n\t\thsi::utils::add_new_dts_param \"$opp00_table\" \"opp-hz\" $opp00 noformating\n\t\thsi::utils::add_new_dts_param \"$opp00_table\" \"opp-microvolt\" $opp_microvolt noformating\n\t\thsi::utils::add_new_dts_param \"$opp00_table\" \"clock-latency-ns\" $clock_latency noformating\n\t\tset opp01_table [add_or_get_dt_node -n \"opp-${opp01_result}\" -d $default_dts -p $cpu_opp_table]\n\t\thsi::utils::add_new_dts_param \"$opp01_table\" \"opp-hz\" $opp01 noformating\n\t\thsi::utils::add_new_dts_param \"$opp01_table\" \"opp-microvolt\" $opp_microvolt noformating\n\t\thsi::utils::add_new_dts_param \"$opp01_table\" \"clock-latency-ns\" $clock_latency noformating\n\t\tset opp02_table [add_or_get_dt_node -n \"opp-${opp02_result}\" -d $default_dts -p $cpu_opp_table]\n\t\thsi::utils::add_new_dts_param \"$opp02_table\" \"opp-hz\" $opp02 noformating\n\t\thsi::utils::add_new_dts_param \"$opp02_table\" \"opp-microvolt\" $opp_microvolt noformating\n\t\thsi::utils::add_new_dts_param \"$opp02_table\" \"clock-latency-ns\" $clock_latency noformating\n\t\tset opp03_table [add_or_get_dt_node -n \"opp-${opp03_result}\" -d $default_dts -p $cpu_opp_table]\n\t\thsi::utils::add_new_dts_param \"$opp03_table\" \"opp-hz\" $opp03 noformating\n\t\thsi::utils::add_new_dts_param \"$opp03_table\" \"opp-microvolt\" $opp_microvolt noformating\n\t\thsi::utils::add_new_dts_param \"$opp03_table\" \"clock-latency-ns\" $clock_latency noformating\n\t}\n}\n\nproc gen_versal_clk {} {\n\tset default_dts [get_property CONFIG.pcw_dts [get_os]]\n\tset ref_node [add_or_get_dt_node -n \"&ref_clk\" -d $default_dts]\n\tset pl_alt_ref_node [add_or_get_dt_node -n \"&pl_alt_ref_clk\" -d $default_dts]\n\tset periph_list [get_cells -hier]\n\tforeach periph $periph_list {\n\t\tset versal_ps [get_property IP_NAME $periph]\n\t\tif { $versal_ps in { \"versal_cips\" \"ps_wizard\" }} {\n\t\t\tset ver [get_comp_ver $periph]\n\t\t\tif {$ver < 3.0} {\n\t\t\t\tset avail_param [list_property [get_cells -hier $periph]]\n\t\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PMC_REF_CLK_FREQMHZ\"] >= 0} {\n\t\t\t\t\tset freq [get_property CONFIG.PMC_REF_CLK_FREQMHZ [get_cells -hier $periph]]\n\t\t\t\t\tif {![string match -nocase $freq \"33.333\"]} {\n\t\t\t\t\t\tdtg_warning \"Frequency $freq used instead of 33.333\"\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${ref_node}\" \"clock-frequency\" [scan [expr $freq * 1000000] \"%d\"] int\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PMC_PL_ALT_REF_CLK_FREQMHZ\"] >= 0} {\n\t\t\t\t\tset freq [get_property CONFIG.PMC_PL_ALT_REF_CLK_FREQMHZ [get_cells -hier $periph]]\n\t\t\t\t\tif {![string match -nocase $freq \"33.333\"]} {\n\t\t\t\t\t\tdtg_warning \"Frequency $freq used instead of 33.333\"\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${pl_alt_ref_node}\" \"clock-frequency\" [scan [expr $freq * 1000000] \"%d\"] int\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $versal_ps \"pspmc\"] } {\n\t\t\tset avail_param [list_property [get_cells -hier $periph]]\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PMC_REF_CLK_FREQMHZ\"] >= 0} {\n\t\t\t\tset freq [get_property CONFIG.PMC_REF_CLK_FREQMHZ [get_cells -hier $periph]]\n\t\t\t\tif {![string match -nocase $freq \"33.333\"]} {\n\t\t\t\t\tdtg_warning \"Frequency $freq used instead of 33.333\"\n\t\t\t\t\thsi::utils::add_new_dts_param \"${ref_node}\" \"clock-frequency\" [scan [expr $freq * 1000000] \"%d\"] int\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PMC_PL_ALT_REF_CLK_FREQMHZ\"] >= 0} {\n\t\t\t\tset freq [get_property CONFIG.PMC_PL_ALT_REF_CLK_FREQMHZ [get_cells -hier $periph]]\n\t\t\t\tif {![string match -nocase $freq \"33.333\"]} {\n\t\t\t\t\tdtg_warning \"Frequency $freq used instead of 33.333\"\n\t\t\t\t\thsi::utils::add_new_dts_param \"${pl_alt_ref_node}\" \"clock-frequency\" [scan [expr $freq * 1000000] \"%d\"] int\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n}\n\nproc gen_zynqmp_pinctrl {} {\n\tset default_dts [get_property CONFIG.pcw_dts [get_os]]\n\tset pinctrl_node [add_or_get_dt_node -n \"&pinctrl0\" -d $default_dts]\n\tset periph_list [get_cells -hier]\n\tforeach periph $periph_list {\n\t\tset zynq_ultra_ps [get_property IP_NAME $periph]\n\t\tif {[string match -nocase $zynq_ultra_ps \"zynq_ultra_ps_e\"] } {\n\t\t\tset avail_param [list_property [get_cells -hier $periph]]\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__UART1__PERIPHERAL__IO\"] >= 0} {\n\t\t\t\tset uart1_io [get_property CONFIG.PSU__UART1__PERIPHERAL__IO [get_cells -hier $periph]]\n\t\t\t\tif {[string match -nocase $uart1_io \"EMIO\"]} {\n\t\t\t\t\tset pinctrl_uart1_default [add_or_get_dt_node -n \"uart1-default\" -d $default_dts -p $pinctrl_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_uart1_default\" \"/delete-node/ mux\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_uart1_default\" \"/delete-node/ conf\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_uart1_default\" \"/delete-node/ conf-rx\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_uart1_default\" \"/delete-node/ conf-tx\" \"\" boolean\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__UART0__PERIPHERAL__IO\"] >= 0} {\n\t\t\t\tset uart0_io [get_property CONFIG.PSU__UART0__PERIPHERAL__IO [get_cells -hier $periph]]\n\t\t\t\tif {[string match -nocase $uart0_io \"EMIO\"]} {\n\t\t\t\t\tset pinctrl_uart0_default [add_or_get_dt_node -n \"uart0-default\" -d $default_dts -p $pinctrl_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_uart0_default\" \"/delete-node/ mux\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_uart0_default\" \"/delete-node/ conf\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_uart0_default\" \"/delete-node/ conf-rx\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_uart0_default\" \"/delete-node/ conf-tx\" \"\" boolean\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__CAN1__PERIPHERAL__IO\"] >= 0} {\n\t\t\t\tset can1_io [get_property CONFIG.PSU__CAN1__PERIPHERAL__IO [get_cells -hier $periph]]\n\t\t\t\tif {[string match -nocase $can1_io \"EMIO\"]} {\n\t\t\t\t\tset pinctrl_can1_default [add_or_get_dt_node -n \"can1-default\" -d $default_dts -p $pinctrl_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_can1_default\" \"/delete-node/ mux\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_can1_default\" \"/delete-node/ conf\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_can1_default\" \"/delete-node/ conf-rx\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_can1_default\" \"/delete-node/ conf-tx\" \"\" boolean\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__SD1__PERIPHERAL__IO\"] >= 0} {\n\t\t\t\tset sd1_io [get_property CONFIG.PSU__SD1__PERIPHERAL__IO [get_cells -hier $periph]]\n\t\t\t\tif {[string match -nocase $sd1_io \"EMIO\"]} {\n\t\t\t\t\tset pinctrl_sdhci1_default [add_or_get_dt_node -n \"sdhci1-default\" -d $default_dts -p $pinctrl_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_sdhci1_default\" \"/delete-node/ mux\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_sdhci1_default\" \"/delete-node/ conf\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_sdhci1_default\" \"/delete-node/ conf-cd\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_sdhci1_default\" \"/delete-node/ mux-cd\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_sdhci1_default\" \"/delete-node/ conf-wp\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_sdhci1_default\" \"/delete-node/ mux-wp\" \"\" boolean\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__ENET3__PERIPHERAL__IO\"] >= 0} {\n\t\t\t\tset gem3_io [get_property CONFIG.PSU__ENET3__PERIPHERAL__IO [get_cells -hier $periph]]\n\t\t\t\tif {[string match -nocase $gem3_io \"EMIO\"]} {\n\t\t\t\t\tset pinctrl_gem3_default [add_or_get_dt_node -n \"gem3-default\" -d $default_dts -p $pinctrl_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_gem3_default\" \"/delete-node/ mux\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_gem3_default\" \"/delete-node/ conf\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_gem3_default\" \"/delete-node/ conf-rx\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_gem3_default\" \"/delete-node/ conf-tx\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_gem3_default\" \"/delete-node/ conf-mdio\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_gem3_default\" \"/delete-node/ mux-mdio\" \"\" boolean\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[lsearch -nocase $avail_param \"CONFIG.PSU__I2C1__PERIPHERAL__IO\"] >= 0} {\n\t\t\t\tset i2c1_io [get_property CONFIG.PSU__I2C1__PERIPHERAL__IO [get_cells -hier $periph]]\n\t\t\t\tif {[string match -nocase $i2c1_io \"EMIO\"]} {\n\t\t\t\t\tset pinctrl_i2c1_default [add_or_get_dt_node -n \"i2c1-default\" -d $default_dts -p $pinctrl_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_i2c1_default\" \"/delete-node/ mux\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_i2c1_default\" \"/delete-node/ conf\" \"\" boolean\n\t\t\t\t\tset pinctrl_i2c1_gpio [add_or_get_dt_node -n \"i2c1-gpio\" -d $default_dts -p $pinctrl_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_i2c1_gpio\" \"/delete-node/ mux\" \"\" boolean\n\t\t\t\t\thsi::utils::add_new_dts_param \"$pinctrl_i2c1_gpio\" \"/delete-node/ conf\" \"\" boolean\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc gen_zocl_node {} {\n\tset zocl [get_property CONFIG.dt_zocl [get_os]]\n\tputs \"zocl:$zocl\"\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tset ext_platform [get_property platform.extensible [get_os]]\n\tputs \"ext_platform:$ext_platform\"\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tif {$remove_pl} {\n\t\treturn\n\t}\n\tif {!$zocl} {\n\t\treturn\n\t}\n\t#Check if design has any PL ip's\n\tset ip_count 0\n\tforeach ip [get_drivers] {\n\t\tif {[is_pl_ip $ip]} {\n\t\t\tincr ip_count\n\t\t\tbreak\n\t\t}\n\t}\n\tif {$ip_count == 0} {\n\t\tdtg_warning \"dt_zocl enabled and No PL ip's found in specified design, skip adding zocl node\"\n\t\treturn\n\t}\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n\tset default_dts pl.dtsi\n\tset zocl_node [add_or_get_dt_node -n \"zyxclmm_drm\" -d ${default_dts} -p $bus_node]\n\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"ps7_cortexa9\"]} {\n\t\thsi::utils::add_new_dts_param $zocl_node \"compatible\" \"xlnx,zocl\" string\n\t} else {\n\t\thsi::utils::add_new_dts_param $zocl_node \"compatible\" \"xlnx,zocl-versal\" string\n\t}\n\t#if axi_intc exists in the design then add 0 to 31 extended interrupts.\n\tset axi_intr_ctrl [get_cells -hier -filter {IP_NAME == axi_intc}]\n\tif {[llength $axi_intr_ctrl]} {\n\t\tset intr_ctrl_len [llength $axi_intr_ctrl]\n\t\tputs \"intr_ctrl_len:$intr_ctrl_len\"\n\t\tset int0 [lindex $axi_intr_ctrl 0]\n\t\tforeach ip [get_drivers] {\n\t\t\tif {[string compare -nocase $ip $int0] == 0} {\n\t\t\t\tset target_handle $ip\n\t\t\t}\n\t\t}\n\t\tset intr [get_property CONFIG.interrupt-parent $target_handle]\n\t\tset int1 [lindex $axi_intr_ctrl 1]\n\t\tforeach ip [get_drivers] {\n\t\t\tif {[string compare -nocase $ip $int1] == 0} {\n\t\t\t\tset target_handle $ip\n\t\t\t}\n\t\t}\n\t\tset intr [get_property CONFIG.interrupt-parent $target_handle]\n\t\tswitch $intr_ctrl_len {\n\t\t\t\"1\" {\n\t\t\t\tset ref [lindex $axi_intr_ctrl 0]\n\t\t\t\tappend ref \" 0 4>, <&[lindex $axi_intr_ctrl 0] 1 4>, <&[lindex $axi_intr_ctrl 0] 2 4>, <&[lindex $axi_intr_ctrl 0] 3 4>, <&[lindex $axi_intr_ctrl 0] 4 4>, <&[lindex $axi_intr_ctrl 0] 5 4>, <&[lindex $axi_intr_ctrl 0] 6 4>, <&[lindex $axi_intr_ctrl 0] 7 4>, <&[lindex $axi_intr_ctrl 0] 8 4>, <&[lindex $axi_intr_ctrl 0] 9 4>,\n<&[lindex $axi_intr_ctrl 0] 10 4>, <&[lindex $axi_intr_ctrl 0] 11 4>, <&[lindex $axi_intr_ctrl 0] 12 4>, <&[lindex $axi_intr_ctrl 0] 13 4>, <&[lindex $axi_intr_ctrl 0] 14 4>,\n<&[lindex $axi_intr_ctrl 0] 15 4>, <&[lindex $axi_intr_ctrl 0] 16 4>, <&[lindex $axi_intr_ctrl 0] 17 4>, <&[lindex $axi_intr_ctrl 0] 18 4>, <&[lindex $axi_intr_ctrl 0] 19 4>,\n<&[lindex $axi_intr_ctrl 0] 20 4>, <&[lindex $axi_intr_ctrl 0] 21 4>, <&[lindex $axi_intr_ctrl 0] 22 4>, <&[lindex $axi_intr_ctrl 0] 23 4>, <&[lindex $axi_intr_ctrl 0] 24 4>,\n<&[lindex $axi_intr_ctrl 0] 25 4>, <&[lindex $axi_intr_ctrl 0] 26 4>, <&[lindex $axi_intr_ctrl 0] 27 4>, <&[lindex $axi_intr_ctrl 0] 28 4>, <&[lindex $axi_intr_ctrl 0] 29 4>,\n<&[lindex $axi_intr_ctrl 0] 30 4>, <&[lindex $axi_intr_ctrl 0] 31 4 \"\n\t\t\t\thsi::utils::add_new_dts_param $zocl_node \"interrupts-extended\" $ref reference\n\t\t\t}\n\t\t\t\"2\" {\n\t\t\t\tset ref [lindex $axi_intr_ctrl 0]\n\t\t\t\tappend ref \" 0 4>, <&[lindex $axi_intr_ctrl 0] 1 4>, <&[lindex $axi_intr_ctrl 0] 2 4>, <&[lindex $axi_intr_ctrl 0] 3 4>, <&[lindex $axi_intr_ctrl 0] 4 4>, <&[lindex $axi_intr_ctrl 0] 5 4>, <&[lindex $axi_intr_ctrl 0] 6 4>, <&[lindex $axi_intr_ctrl 0] 7 4>, <&[lindex $axi_intr_ctrl 0] 8 4>, <&[lindex $axi_intr_ctrl 0] 9 4>, <&[lindex $axi_intr_ctrl 0] 10 4>, <&[lindex $axi_intr_ctrl 0] 11 4>, <&[lindex $axi_intr_ctrl 0] 12 4>, <&[lindex $axi_intr_ctrl 0] 13 4>, <&[lindex $axi_intr_ctrl 0] 14 4>, <&[lindex $axi_intr_ctrl 0] 15 4>, <&[lindex $axi_intr_ctrl 0] 16 4>, <&[lindex $axi_intr_ctrl 0] 17 4>, <&[lindex $axi_intr_ctrl 0] 18 4>, <&[lindex $axi_intr_ctrl 0] 19 4>, <&[lindex $axi_intr_ctrl 0] 20 4>, <&[lindex $axi_intr_ctrl 0] 21 4>, <&[lindex $axi_intr_ctrl 0] 22 4>, <&[lindex $axi_intr_ctrl 0] 23 4>, <&[lindex $axi_intr_ctrl 0] 24 4>, <&[lindex $axi_intr_ctrl 0] 25 4>, <&[lindex $axi_intr_ctrl 0] 26 4>, <&[lindex $axi_intr_ctrl 0] 27 4>, <&[lindex $axi_intr_ctrl 0] 28 4>, <&[lindex $axi_intr_ctrl 0] 29 4>, <&[lindex $axi_intr_ctrl 0] 30 4>, <&[lindex $axi_intr_ctrl 0] 31 4>, <&[lindex $axi_intr_ctrl 1] 0 4>, <&[lindex $axi_intr_ctrl 1] 1 4>, <&[lindex $axi_intr_ctrl 1] 2 4>, <&[lindex $axi_intr_ctrl 1] 3 4>, <&[lindex $axi_intr_ctrl 1] 4 4>, <&[lindex $axi_intr_ctrl 1] 5 4>, <&[lindex $axi_intr_ctrl 1] 6 4>, <&[lindex $axi_intr_ctrl 1] 7 4>, <&[lindex $axi_intr_ctrl 1] 8 4>, <&[lindex $axi_intr_ctrl 1] 9 4>, <&[lindex $axi_intr_ctrl 1] 10 4>, <&[lindex $axi_intr_ctrl 1] 11 4>, <&[lindex $axi_intr_ctrl 1] 12 4>, <&[lindex $axi_intr_ctrl 1] 13 4>, <&[lindex $axi_intr_ctrl 1] 14 4>, <&[lindex $axi_intr_ctrl 1] 15 4>, <&[lindex $axi_intr_ctrl 1] 16 4>, <&[lindex $axi_intr_ctrl 1] 17 4>, <&[lindex $axi_intr_ctrl 1] 18 4>, <&[lindex $axi_intr_ctrl 1] 19 4>, <&[lindex $axi_intr_ctrl 1] 20 4>, <&[lindex $axi_intr_ctrl 1] 21 4>, <&[lindex $axi_intr_ctrl 1] 22 4>, <&[lindex $axi_intr_ctrl 1] 23 4>, <&[lindex $axi_intr_ctrl 1] 24 4>, <&[lindex $axi_intr_ctrl 1] 25 4>, <&[lindex $axi_intr_ctrl 1] 26 4>, <&[lindex $axi_intr_ctrl 1] 27 4>, <&[lindex $axi_intr_ctrl 1] 28 4>, <&[lindex $axi_intr_ctrl 1] 29 4>, <&[lindex $axi_intr_ctrl 1] 30 4 \"\n\t\t\t\thsi::utils::add_new_dts_param $zocl_node \"interrupts-extended\" $ref reference\n\t\t\t}\n\t\t\t\"3\" {\n\t\t\t\tset ref [lindex $axi_intr_ctrl 0]\n\t\t\t\tappend ref \" 0 4>, <&[lindex $axi_intr_ctrl 0] 1 4>, <&[lindex $axi_intr_ctrl 0] 2 4>, <&[lindex $axi_intr_ctrl 0] 3 4>, <&[lindex $axi_intr_ctrl 0] 4 4>, <&[lindex $axi_intr_ctrl 0] 5 4>, <&[lindex $axi_intr_ctrl 0] 6 4>, <&[lindex $axi_intr_ctrl 0] 7 4>, <&[lindex $axi_intr_ctrl 0] 8 4>, <&[lindex $axi_intr_ctrl 0] 9 4>, <&[lindex $axi_intr_ctrl 0] 10 4>, <&[lindex $axi_intr_ctrl 0] 11 4>, <&[lindex $axi_intr_ctrl 0] 12 4>, <&[lindex $axi_intr_ctrl 0] 13 4>, <&[lindex $axi_intr_ctrl 0] 14 4>, <&[lindex $axi_intr_ctrl 0] 15 4>, <&[lindex $axi_intr_ctrl 0] 16 4>, <&[lindex $axi_intr_ctrl 0] 17 4>, <&[lindex $axi_intr_ctrl 0] 18 4>, <&[lindex $axi_intr_ctrl 0] 19 4>, <&[lindex $axi_intr_ctrl 0] 20 4>, <&[lindex $axi_intr_ctrl 0] 21 4>, <&[lindex $axi_intr_ctrl 0] 22 4>, <&[lindex $axi_intr_ctrl 0] 23 4>, <&[lindex $axi_intr_ctrl 0] 24 4>, <&[lindex $axi_intr_ctrl 0] 25 4>, <&[lindex $axi_intr_ctrl 0] 26 4>, <&[lindex $axi_intr_ctrl 0] 27 4>, <&[lindex $axi_intr_ctrl 0] 28 4>, <&[lindex $axi_intr_ctrl 0] 29 4>, <&[lindex $axi_intr_ctrl 0] 30 4>, <&[lindex $axi_intr_ctrl 0] 31 4>, <&[lindex $axi_intr_ctrl 1] 0 4>, <&[lindex $axi_intr_ctrl 1] 1 4>, <&[lindex $axi_intr_ctrl 1] 2 4>, <&[lindex $axi_intr_ctrl 1] 2 4>, <&[lindex $axi_intr_ctrl 1] 3 4>, <&[lindex $axi_intr_ctrl 1] 4 4>, <&[lindex $axi_intr_ctrl 1] 5 4>, <&[lindex $axi_intr_ctrl 1] 6 4>, <&[lindex $axi_intr_ctrl 1] 7 4>, <&[lindex $axi_intr_ctrl 1] 8 4>, <&[lindex $axi_intr_ctrl 1] 9 4>, <&[lindex $axi_intr_ctrl 1] 10 4>, <&[lindex $axi_intr_ctrl 1] 11 4>, <&[lindex $axi_intr_ctrl 1] 12 4>, <&[lindex $axi_intr_ctrl 1] 13 4>, <&[lindex $axi_intr_ctrl 1] 14 4>, <&[lindex $axi_intr_ctrl 1] 15 4>, <&[lindex $axi_intr_ctrl 1] 16 4>, <&[lindex $axi_intr_ctrl 1] 17 4>, <&[lindex $axi_intr_ctrl 1] 18 4>, <&[lindex $axi_intr_ctrl 1] 19 4>, <&[lindex $axi_intr_ctrl 1] 20 4>, <&[lindex $axi_intr_ctrl 1] 21 4>, <&[lindex $axi_intr_ctrl 1] 22 4>, <&[lindex $axi_intr_ctrl 1] 23 4>, <&[lindex $axi_intr_ctrl 1] 24 4>, <&[lindex $axi_intr_ctrl 1] 25 4>, <&[lindex $axi_intr_ctrl 1] 26 4>, <&[lindex $axi_intr_ctrl 1] 27 4>, <&[lindex $axi_intr_ctrl 1] 28 4>, <&[lindex $axi_intr_ctrl 1] 29 4>, <&[lindex $axi_intr_ctrl 1] 30 4>, <&[lindex $axi_intr_ctrl 1] 31 4>, <&[lindex $axi_intr_ctrl 2] 0 4>, <&[lindex $axi_intr_ctrl 2] 1 4>, <&[lindex $axi_intr_ctrl 2] 2 4>, <&[lindex $axi_intr_ctrl 2] 3 4>, <&[lindex $axi_intr_ctrl 2] 4 4>, <&[lindex $axi_intr_ctrl 2] 5 4>, <&[lindex $axi_intr_ctrl 2] 6 4>, <&[lindex $axi_intr_ctrl 2] 7 4>, <&[lindex $axi_intr_ctrl 2] 8 4>, <&[lindex $axi_intr_ctrl 2] 9 4>, <&[lindex $axi_intr_ctrl 2] 10 4>, <&[lindex $axi_intr_ctrl 2] 11 4>, <&[lindex $axi_intr_ctrl 2] 12 4>, <&[lindex $axi_intr_ctrl 2] 13 4>, <&[lindex $axi_intr_ctrl 2] 14 4>, <&[lindex $axi_intr_ctrl 2] 15 4>, <&[lindex $axi_intr_ctrl 2] 16 4>, <&[lindex $axi_intr_ctrl 2] 17 4>, <&[lindex $axi_intr_ctrl 2] 18 4>, <&[lindex $axi_intr_ctrl 2] 19 4>, <&[lindex $axi_intr_ctrl 2] 20 4>, <&[lindex $axi_intr_ctrl 2] 21 4>, <&[lindex $axi_intr_ctrl 2] 22 4 >, <&[lindex $axi_intr_ctrl 2] 23 4>, <&[lindex $axi_intr_ctrl 2] 24 4>, <&[lindex $axi_intr_ctrl 2] 25 4>, <&[lindex $axi_intr_ctrl 2] 26 4>, <&[lindex $axi_intr_ctrl 2] 27 4>, <&[lindex $axi_intr_ctrl 2] 28 4>, <&[lindex $axi_intr_ctrl 2] 29 4>, <&[lindex $axi_intr_ctrl 2] 30 4 \"\n\t\t\t\thsi::utils::add_new_dts_param $zocl_node \"interrupts-extended\" $ref reference\n\t\t\t}\n\t\t}\n\t} else {\n\t\t# if axi_intc not found then use gic controller\n\t\tset intr_num \"0x0 0x89 0x4>, <0x0 0x90 0x4>, <0x0 0x91 0x4>, <0x0 0x92 0x4>, <0x0 0x93 0x4>, <0x0 0x94 0x4>, <0x0 0x95 0x4>, <0x0 0x96 0x4\"\n\t\thsi::utils::add_new_dts_param $zocl_node \"interrupt-parent\" gic reference\n\t\thsi::utils::add_new_dts_param $zocl_node \"interrupts\" $intr_num intlist\n\t}\n\tset decouplers [get_cells -hier -filter {IP_NAME == \"dfx_decoupler\"}]\n\tset count 1\n\tforeach decoupler $decouplers {\n\t\tif { $count == 1 } {\n\t\t\thsi::utils::add_new_dts_param \"$zocl_node\" \"xlnx,pr-decoupler\" \"\" boolean\n\t\t} else {\n\t\t\t#zocl driver not supporting multiple decouplers so display warning.\n\t\t\tdtg_warning \"Multiple dfx_decoupler IPs found in the design,\\\n\t\t\t\tusing pr-isolation-addr from [lindex [split $decouplers \" \"] 0] IP\"\n\t\t\tbreak\n\t\t}\n\t\tset baseaddr [get_property CONFIG.C_BASEADDR [get_cells -hier $decoupler]]\n\t\tif {[llength $baseaddr]} {\n\t\t\tset baseaddr \"0x0 $baseaddr\"\n\t\t\thsi::utils::add_new_dts_param \"$zocl_node\" \"xlnx,pr-isolation-addr\" \"$baseaddr\" intlist\n\t\t}\n\t\tincr count\n\t}\n}\n\nproc generate {lib_handle} {\n\tadd_skeleton\n\tforeach drv_handle [get_drivers] {\n\t\tif {[string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] \"axi_intc\"]} {\n\t\t\tgen_peripheral_nodes $drv_handle \"create_node_only\"\n\t\t}\n\t}\n\tforeach drv_handle [get_drivers] {\n\t\t# generate the default properties\n\t\tif {![string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] \"axi_intc\"]} {\n\t\t\tgen_peripheral_nodes $drv_handle \"create_node_only\"\n\t\t}\n\t\tgen_reg_property $drv_handle\n\t\tgen_compatible_property $drv_handle\n\t\tgen_drv_prop_from_ip $drv_handle\n\t\tgen_interrupt_property $drv_handle\n\t\tgen_clk_property $drv_handle\n\t}\n\tgen_board_info\n\tgen_include_headers\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\tset mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n\t\tif {[string match -nocase $mainline_ker \"none\"]} {\n\t\t\tgen_sata_laneinfo\n\t\t\tgen_zynqmp_ccf_clk\n\t\t\tgen_versal_clk\n\t\t\tgen_opp_freq\n\t\t\tgen_zynqmp_pinctrl\n\t\t\tgen_zocl_node\n\t\t\tif {[string match -nocase $proctype \"psv_cortexa72\"]} {\n\t\t\t\tgen_edac_node\n\t\t\t\tgen_ddrmc_node\n\t\t\t}\n\t\t}\n\t}\n\tif {[string match -nocase $proctype \"ps7_cortexa9\"]} {\n\t\tset mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n\t\tif {[string match -nocase $mainline_ker \"none\"]} {\n\t\t\tgen_zocl_node\n\t\t}\n\t}\n\tgen_ext_axi_interface\n}\n\nproc update_nonregnodes {} {\n\t# Check the each node and if any node doesnot have\n\t# reg property move them to root node or fpga node\n\tset dts_files [get_dt_trees]\n\tforeach dts_file $dts_files {\n\t\tif {[regexp \"pl.*.dtsi\" $dts_file match]} {\n\t\t\tcurrent_dt_tree $dts_file\n\t\t\tset dts_nodes [get_all_tree_nodes $dts_file]\n\t\t\tset overlay_parent \"[detect_fpga_noderef]\"\n\t\t\tforeach dts_node $dts_nodes {\n\t\t\t\t# Using firmware-name prop to detect the fpga node\n\t\t\t\tif {[llength [get_property CONFIG.firmware-name $dts_node]]} {\n\t\t\t\t\tset overlay_parent \"${dts_node}\"\n\t\t\t\t}\n\t\t\t}\n\t\t\tforeach dts_node $dts_nodes {\n\t\t\t\tif {[regexp \"/\" $dts_node match]} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\tset current_parent [get_property PARENT $dts_node]\n\t\t\t\tset reg_prop [get_property CONFIG.reg $dts_node]\n\t\t\t\t# If no reg prop in node move them from amba or amba_pl to\n\t\t\t\t# fpga node if its overlay else root(/) node\n\t\t\t\tif {![llength \"${reg_prop}\"]} {\n\t\t\t\t\tif {[regexp \"&amba\" ${current_parent} match]} {\n\t\t\t\t\t\t# Overlay cases\n\t\t\t\t\t\tif {[lsearch $dts_nodes $overlay_parent] >= 0} {\n\t\t\t\t\t\t\tset_property PARENT \"${overlay_parent}\" $dts_node\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tdtg_debug \"Fpga parent not found $overlay_parent in $dts_file\"\n\t\t\t\t\t\t}\n\t\t\t\t\t} elseif {[regexp \"amba_pl:pl-bus\" ${current_parent} match]} {\n\t\t\t\t\t\t# Non Overlay cases\n\t\t\t\t\t\tset_property PARENT \"/\" $dts_node\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc post_generate {os_handle} {\n update_chosen $os_handle\n update_alias $os_handle\n update_cpu_node $os_handle\n gen_dev_conf\n foreach drv_handle [get_drivers] {\n gen_peripheral_nodes $drv_handle\n\tupdate_endpoints $drv_handle\n }\n global zynq_soc_dt_tree\n delete_objs [get_dt_tree $zynq_soc_dt_tree]\n remove_empty_reference_node\n remove_main_memory_node\n update_nonregnodes\n}\n\nproc add_skeleton {} {\n set default_dts [get_property CONFIG.master_dts [get_os]]\n set system_root_node [add_or_get_dt_node -n \"/\" -d ${default_dts}]\n set chosen_node [add_or_get_dt_node -n \"chosen\" -d ${default_dts} -p ${system_root_node}]\n set alias_node [add_or_get_dt_node -n \"aliases\" -d ${default_dts} -p ${system_root_node}]\n}\n\nproc update_chosen {os_handle} {\n set default_dts [get_property CONFIG.master_dts [get_os]]\n set system_root_node [add_or_get_dt_node -n \"/\" -d ${default_dts}]\n set chosen_node [add_or_get_dt_node -n \"chosen\" -d ${default_dts} -p ${system_root_node}]\n\n #getting boot arguments\n set bootargs [get_property CONFIG.bootargs $os_handle]\n set console [hsi::utils::get_os_parameter_value \"console\"]\n set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n if {[llength $bootargs]} {\n append bootargs \" earlycon\"\n } else {\n\tset bootargs \"earlycon\"\n }\n if {[string match -nocase $proctype \"psv_cortexa72\"]} {\n\t#as the early params are defined in board dts files\n\treturn\n }\n if {[string match -nocase $proctype \"psx_cortexa78\"]} {\n\t#as the early params are defined in board dts files\n\treturn\n }\n hsi::utils::add_new_dts_param \"${chosen_node}\" \"bootargs\" \"$bootargs\" string\n set consoleip [get_property CONFIG.console_device $os_handle]\n if {![string match -nocase $consoleip \"none\"]} {\n set consoleip [ps_node_mapping $consoleip label]\n set index [string first \",\" $console]\n set baud [string range $console [expr $index + 1] [string length $console]]\n hsi::utils::add_new_dts_param \"${chosen_node}\" \"stdout-path\" \"serial0:${baud}n8\" string\n }\n}\n\nproc update_cpu_node {os_handle} {\n set default_dts [get_property CONFIG.master_dts [get_os]]\n set system_root_node [add_or_get_dt_node -n \"/\" -d ${default_dts}]\n set avail_cpu_cores 0\n set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n if {[string match -nocase $proctype \"psv_cortexa72\"] } {\n set current_proc \"psv_cortexa72_\"\n set total_cores 2\n } elseif {[string match -nocase $proctype \"psx_cortexa78\"] } {\n set current_proc \"psx_cortexa78_\"\n set total_cores 16\n } elseif {[string match -nocase $proctype \"psu_cortexa53\"] } {\n set current_proc \"psu_cortexa53_\"\n set total_cores 4\n\tset avail_cpu_cores [llength [get_cells -hier -filter {IP_NAME == \"psu_cortexa53\"}]]\n } elseif {[string match -nocase $proctype \"ps7_cortexa9\"] } {\n set current_proc \"ps7_cortexa9_\"\n set total_cores 2\n } else {\n set current_proc \"\"\n }\n\n if {[string compare -nocase $current_proc \"\"] == 0} {\n return\n }\n if {[string match -nocase $proctype \"psv_cortexa72\"]} {\n set procs [get_cells -hier -filter {IP_TYPE==PROCESSOR}]\n set pnames \"\"\n\tforeach proc_name $procs {\n if {[regexp \"psv_cortexa72*\" $proc_name match]} {\n\t append pnames \" \" $proc_name\n }\n }\n set a72cores [llength $pnames]\n if {[string match -nocase $a72cores $total_cores]} {\n\t return\n }\n }\n if {[string match -nocase $proctype \"psx_cortexa78\"]} {\n set procs [get_cells -hier -filter {IP_TYPE==PROCESSOR}]\n set pnames \"\"\n\tforeach proc_name $procs {\n if {[regexp \"psx_cortexa78*\" $proc_name match]} {\n\t append pnames \" \" $proc_name\n }\n }\n set a78cores [llength $pnames]\n if {[string match -nocase $a78cores $total_cores]} {\n\t return\n }\n }\n\n for {set i 0} {$i < $total_cores} {incr i} {\n set proc_name [lindex [get_cells -hier -filter {IP_TYPE==PROCESSOR} *$proctype*] $i]\n if {[llength $proc_name] == 0} {\n set cpu_node [add_or_get_dt_node -n \"cpus\" -d ${default_dts} -p ${system_root_node}]\n hsi::utils::add_new_dts_param \"${cpu_node}\" \"/delete-node/ cpu@$i\" \"\" boolean\n continue\n }\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $proc_name]] \"microblaze\"]} {\n\t\treturn\n\t}\n\tif {[regexp \".*${current_proc}${i}\" $proc_name match]} {\n continue\n } else {\n set cpu_node [add_or_get_dt_node -n \"cpus\" -d ${default_dts} -p ${system_root_node}]\n hsi::utils::add_new_dts_param \"${cpu_node}\" \"/delete-node/ cpu@$i\" \"\" boolean\n }\n }\n\n # zynqmp.dtsi pmu node has cpu references hense generating them as per design\n set pmc_prop_value \"\"\n if { $avail_cpu_cores < $total_cores } {\n for {set i 0} {$i < $avail_cpu_cores} {incr i} {\n\t if { $i > 0 } {\n\t append pmc_prop_value \">, <&cpu$i\"\n\t } else {\n\t\tappend pmc_prop_value \"&cpu$i\"\n\t }\n }\n }\n if {[llength $pmc_prop_value]} {\n set pmu_node [add_or_get_dt_node -n \"pmu\" -d ${default_dts} -p ${system_root_node}]\n hsi::utils::add_new_dts_param \"${pmu_node}\" \"interrupt-affinity\" \"$pmc_prop_value\" intlist\n }\n}\n\nproc update_alias {os_handle} {\n set mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n set valid_mainline_kernel_list \"v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4\"\n if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } {\n return\n }\n set no_alias [get_property CONFIG.no_alias [get_os]]\n if {$no_alias} {\n #Don't generate the alias node when no_alias is set to true\n\treturn\n }\n set default_dts [get_property CONFIG.master_dts [get_os]]\n set system_root_node [add_or_get_dt_node -n \"/\" -d ${default_dts}]\n set all_labels [get_all_dt_labels]\n\tset all_drivers [get_drivers]\n\n\t# Search for ps_qspi, if it is there then interchange this with first driver\n\t# because to have correct internal u-boot commands qspi has to be listed in aliases as the first for spi0\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tif {[string match -nocase $proctype \"ps7_cortexa9\"]} {\n\t\tset pos [lsearch $all_drivers \"ps7_qspi*\"]\n\t} elseif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\tset pos [lsearch $all_drivers \"psu_qspi*\"]\n\t} elseif {[string match -nocase $proctype \"psv_cortexa72\"]} {\n\t\tset pos [lsearch $all_drivers \"psv_pmc_qspi*\"]\n\t} elseif {[string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\tset pos [lsearch $all_drivers \"psx_pmc_qspi*\"]\n\t} else {\n\t\tset pos [lsearch $all_drivers \"psu_qspi*\"]\n\t}\n\tif { $pos >= 0 } {\n\t\tset first_element [lindex $all_drivers 0]\n\t\tset qspi_element [lindex $all_drivers $pos]\n\t\tset all_drivers [lreplace $all_drivers 0 0 $qspi_element]\n\t\tset all_drivers [lreplace $all_drivers $pos $pos $first_element]\n }\n\t# Update all_drivers list such that console device should be the first\n\t# uart device in the list.\n\tset console_ip [get_property CONFIG.console_device [get_os]]\n\tif {![string match -nocase $console_ip \"none\"]} {\n\t\tset valid_console [lsearch $all_drivers $console_ip]\n\t\tif { $valid_console < 0 } {\n\t\t\terror \"Trying to assign a console::$console_ip which doesn't exists !!!\"\n\t\t}\n\t}\n\tset dt_overlay [get_property CONFIG.DT_Overlay [get_os]]\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tforeach drv_handle $all_drivers {\n\t\tif {[is_pl_ip $drv_handle] && $remove_pl} {\n\t\t\tcontinue\n\t\t}\n\t\tset alias_str [get_property CONFIG.dtg.alias $drv_handle]\n\t\tif {[string match -nocase $alias_str \"serial\"]} {\n\t\t\tif {![string match -nocase $console_ip \"none\"]} {\n\t\t\t\tif {[string match $console_ip $drv_handle] == 0} {\n\t\t\t\t\t# break the loop After swaping console device and uart device\n\t\t\t\t\t# found in list\n\t\t\t\t\tset consoleip_pos [lsearch $all_drivers $console_ip]\n\t\t\t\t\tset first_occur_pos [lsearch $all_drivers $drv_handle]\n\t\t\t\t\tset console_element [lindex $all_drivers $consoleip_pos]\n\t\t\t\t\tset uart_element [lindex $all_drivers $first_occur_pos]\n\t\t\t\t\tset all_drivers [lreplace $all_drivers $consoleip_pos $consoleip_pos $uart_element]\n\t\t\t\t\tset all_drivers [lreplace $all_drivers $first_occur_pos $first_occur_pos $console_element]\n\t\t\t\t\tbreak\n\t\t\t\t} else {\n\t\t\t\t\t# if the first uart device in the list is console device\n\t\t\t\t\tbreak\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tset psi2clist \"\"\n\tset pli2clist \"\"\n\tset i2clen \"\"\n\tset alias_node \"\"\n\tset psuartlist \"\"\n\tset pluartlist \"\"\n\tset uartlen \"\"\n\tset psspilist \"\"\n\tset plspilist \"\"\n\tset spilen \"\"\n\n\tforeach drv_handle $all_drivers {\n if {[is_pl_ip $drv_handle] && $dt_overlay} {\n continue\n }\n if {[is_pl_ip $drv_handle] && $remove_pl} {\n continue\n }\n if {[check_ip_trustzone_state $drv_handle] == 1} {\n continue\n }\n set ip_name [get_property IP_NAME [get_cells -hier $drv_handle]]\n if {[string match -nocase $ip_name \"psv_pmc_qspi\"]} {\n set ip_type [get_property IP_TYPE [get_cells -hier $drv_handle]]\n if {[string match -nocase $ip_type \"PERIPHERAL\"]} {\n continue\n }\n }\n\n set tmp [list_property $drv_handle CONFIG.dtg.alias]\n if {[string_is_empty $tmp]} {\n continue\n } else {\n set alias_str [get_property CONFIG.dtg.alias $drv_handle]\n\t\tif {[string match -nocase $alias_str \"i2c\"]} {\n\t\t\tset upate [lappend upate $drv_handle]\n\t\t\tset i2clen [llength $upate]\n\t\t\tset i2cps [is_ps_ip $drv_handle]\n\t\t\tif {$i2cps} {\n\t\t\t\tset psi2clist [lappend psi2clist $drv_handle]\n\t\t\t}\n\t\t\tset i2cpl [is_pl_ip $drv_handle]\n\t\t\tif {$i2cpl} {\n\t\t\t\tset pli2clist [lappend pli2clist $drv_handle]\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $alias_str \"serial\"]} {\n\t\t\tset uartate [lappend uartate $drv_handle]\n\t\t\tset uartlen [llength $uartate]\n\t\t\tset uartps [is_ps_ip $drv_handle]\n\t\t\tif {$uartps} {\n\t\t\t\tset psuartlist [lappend psuartlist $drv_handle]\n\t\t\t}\n\t\t\tset uartpl [is_pl_ip $drv_handle]\n\t\t\tif {$uartpl} {\n\t\t\t\tset pluartlist [lappend pluartlist $drv_handle]\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $alias_str \"spi\"]} {\n\t\t\tset spiat [lappend spiat $drv_handle]\n\t\t\tset spilen [llength $spiat]\n\t\t\tset spips [is_ps_ip $drv_handle]\n\t\t\tif {$spips} {\n\t\t\t\tset psspilist [lappend psspilist $drv_handle]\n\t\t\t}\n\t\t\tset spipl [is_pl_ip $drv_handle]\n\t\t\tif {$spipl} {\n\t\t\t\tset plspilist [lappend plspilist $drv_handle]\n\t\t\t}\n\t\t}\n\n set alias_count [get_os_dev_count alias_${alias_str}_count]\n set conf_name ${alias_str}${alias_count}\n set value [ps_node_mapping $drv_handle label]\n # When coresight dcc is enabled then set the serial0=dcc in aliases node\n if {[regexp \".*coresight.*\" $value match]} {\n\t\tset value \"dcc\"\n\t\t}\n set ip_list \"i2c spi serial\"\n # TODO: need to check if the label already exists in the current system\n\t\t\tif {[lsearch $all_labels $conf_name] >=0} {\n\t\t\t\tset str [lsearch $ip_list $alias_str]\n\t\t\t\tif {[string match $str \"-1\"]} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t}\n set dtg_alias_only [get_property CONFIG.dtg_alias [get_os]]\n set alias_node [add_or_get_dt_node -n \"aliases\" -d ${default_dts} -p ${system_root_node}]\n if {$dtg_alias_only} {\n\t\t# if dtg_alias set to true then we are deleting the board.dtsi aliases\n\t\thsi::utils::add_new_dts_param ${system_root_node} \"/delete-node/ aliases\" \"\" boolean\n }\n hsi::utils::add_new_dts_param \"${alias_node}\" ${conf_name} ${value} aliasref\n hsi::utils::set_os_parameter_value alias_${alias_str}_count [expr $alias_count + 1]\n }\n }\n\tset i2c_pslen [llength $psi2clist]\n\tfor {set i 0} {$i < $i2c_pslen} {incr i} {\n\t\tset drv_name [lindex $psi2clist $i]\n\t\tset value [ps_node_mapping $drv_name label]\n\t\tset name \"i2c$i\"\n\t\thsi::utils::add_new_dts_param \"${alias_node}\" ${name} ${value} aliasref\n\t}\n\tset i2c_pllen [llength $pli2clist]\n\tset i2clen1 [expr {$i2c_pslen + $i2c_pllen}]\n\tfor {set i $i2c_pslen} {$i < $i2clen1} {incr i} {\n\t\tset drv_name [lindex $pli2clist [expr {$i - $i2c_pslen}]]\n\t\tset value [ps_node_mapping $drv_name label]\n\t\tset name \"i2c$i\"\n\t\thsi::utils::add_new_dts_param \"${alias_node}\" ${name} ${value} aliasref\n\t}\n\t set is_pl_console [is_pl_ip $console_ip]\n\tif {$is_pl_console} {\n\t\tfor {set i 0} {$i < $uartlen} {incr i} {\n\t\t\tset drv_name [lindex $uartate $i]\n\t\t\tset value [ps_node_mapping $drv_name label]\n\t\t\t# When coresight dcc is enabled then set the serial0=dcc in aliases node\n\t\t\tif {[regexp \".*coresight.*\" $value match]} {\n\t\t\t\tset value \"dcc\"\n\t\t\t}\n\t\t\tset name \"serial$i\"\n\t\t\thsi::utils::add_new_dts_param \"${alias_node}\" ${name} ${value} aliasref\n\t\t}\n\t} else {\n\t\tset uart_pslen [llength $psuartlist]\n\t\tfor {set i 0} {$i < $uart_pslen} {incr i} {\n\t\t\tset drv_name [lindex $psuartlist $i]\n\t\t\tset value [ps_node_mapping $drv_name label]\n\t\t\t# When coresight dcc is enabled then set the serial0=dcc in aliases node\n\t\t\tif {[regexp \".*coresight.*\" $value match]} {\n\t\t\t\tset value \"dcc\"\n\t\t\t}\n\t\t\tset name \"serial$i\"\n\t\t\thsi::utils::add_new_dts_param \"${alias_node}\" ${name} ${value} aliasref\n\t\t}\n\t\tset uart_pllen [llength $pluartlist]\n\t\tset uartlen1 [expr {$uart_pslen + $uart_pllen}]\n\t\tfor {set i $uart_pslen} {$i < $uartlen1} {incr i} {\n\t\t\tset drv_name [lindex $pluartlist [expr {$i - $uart_pslen}]]\n\t\t\tset value [ps_node_mapping $drv_name label]\n\t\t\t# When coresight dcc is enabled then set the serial0=dcc in aliases node\n\t\t\tif {[regexp \".*coresight.*\" $value match]} {\n\t\t\t\tset value \"dcc\"\n\t\t\t}\n\t\t\tset name \"serial$i\"\n\t\t\thsi::utils::add_new_dts_param \"${alias_node}\" ${name} ${value} aliasref\n\t\t}\n\t}\n\tset spi_pslen [llength $psspilist]\n\tfor {set i 0} {$i < $spi_pslen} {incr i} {\n\t\tset drv_name [lindex $psspilist $i]\n\t\tset value [ps_node_mapping $drv_name label]\n\t\tset name \"spi$i\"\n\t\thsi::utils::add_new_dts_param \"${alias_node}\" ${name} ${value} aliasref\n\t}\n\tset spi_pllen [llength $plspilist]\n\tset spilen1 [expr {$spi_pslen + $spi_pllen}]\n\tfor {set i $spi_pslen} {$i < $spilen1} {incr i} {\n\t\tset drv_name [lindex $plspilist [expr {$i - $spi_pslen}]]\n\t\tset value [ps_node_mapping $drv_name label]\n\t\tset name \"spi$i\"\n\t\thsi::utils::add_new_dts_param \"${alias_node}\" ${name} ${value} aliasref\n\t}\n}\n\n# remove main memory node\nproc remove_main_memory_node {} {\n set main_memory [get_property CONFIG.main_memory [get_os]]\n if {[string_is_empty $main_memory]} {\n return 0\n }\n\n # in theory it will not del the ps ddr as it snot been generated\n set mc_obj [get_node_object $main_memory \"\" \"\"]\n if {[string_is_empty $mc_obj]} {\n return 0\n }\n\tset all_drivers [get_drivers]\n\tforeach drv_handle $all_drivers {\n\t\tset ip [get_property IP_NAME [get_cells -hier $drv_handle]]\n\t\tif {[string match -nocase $ip \"ddr4\"]} {\n\t\t\tset slave [get_cells -hier ${drv_handle}]\n\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $slave]\n\t\t\tif {[llength $ip_mem_handles] > 1} {\n\t\t\t\treturn\n\t\t\t}\n\t\t}\n\t}\n set cur_dts [current_dt_tree]\n foreach dts_file [get_dt_tree] {\n set dts_nodes [get_all_tree_nodes $dts_file]\n foreach node ${dts_nodes} {\n if {[regexp $mc_obj $node match]} {\n current_dt_tree $dts_file\n delete_objs $mc_obj\n current_dt_tree $cur_dts\n }\n }\n }\n}\n" }, { "path": "device_tree/data/kernel_dtsi/2014.4/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2014.4/zynq/zynq-7000.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n/include/ \"skeleton.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator@0 {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-1.0\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t\txlnx,has-ecc = <0x0>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x1000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"xlnx,ps7-ethernet-1.00.a\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 13>, <&clkc 30>;\n\t\t\tclock-names = \"ref_clk\", \"aper_clk\";\n\t\t\tlocal-mac-address = [00 0a 35 00 00 00];\n\t\t\txlnx,has-mdio = <0x1>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"xlnx,ps7-ethernet-1.00.a\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 14>, <&clkc 31>;\n\t\t\tclock-names = \"ref_clk\", \"aper_clk\";\n\t\t\tlocal-mac-address = [00 0a 35 00 00 00];\n\t\t\txlnx,has-mdio = <0x1>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: sdhci@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: sdhci@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tps-clk-frequency = <33333333>;\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"xlnx,zynq-wdt-r1p2\";\n\t\t\tdevice_type = \"watchdog\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\treset = <0>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tclocks = <&clkc 28>;\n\t\t\tcompatible = \"xlnx,ps7-usb-1.00.a\", \"xlnx,zynq-usb-1.00.a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tclocks = <&clkc 29>;\n\t\t\tcompatible = \"xlnx,ps7-usb-1.00.a\", \"xlnx,zynq-usb-1.00.a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2015.1/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2015.1/zynq/zynq-7000.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n/include/ \"skeleton.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator@0 {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t\txlnx,has-ecc = <0x0>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x1000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"xlnx,ps7-ethernet-1.00.a\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 13>, <&clkc 30>;\n\t\t\tclock-names = \"ref_clk\", \"aper_clk\";\n\t\t\tlocal-mac-address = [00 0a 35 00 00 00];\n\t\t\txlnx,has-mdio = <0x1>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"xlnx,ps7-ethernet-1.00.a\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 14>, <&clkc 31>;\n\t\t\tclock-names = \"ref_clk\", \"aper_clk\";\n\t\t\tlocal-mac-address = [00 0a 35 00 00 00];\n\t\t\txlnx,has-mdio = <0x1>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: sdhci@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: sdhci@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tps-clk-frequency = <33333333>;\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tclocks = <&clkc 28>;\n\t\t\tcompatible = \"xlnx,ps7-usb-1.00.a\", \"xlnx,zynq-usb-1.00.a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tclocks = <&clkc 29>;\n\t\t\tcompatible = \"xlnx,ps7-usb-1.00.a\", \"xlnx,zynq-usb-1.00.a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2015.2/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2015.2/zynq/zynq-7000.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n/include/ \"skeleton.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator@0 {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: sdhci@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: sdhci@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2015.3/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2015.3/zynq/zynq-7000.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n/include/ \"skeleton.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator@0 {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: sdhci@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: sdhci@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-bus\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2015.4/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2015.4/zynq/zynq-7000.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n/include/ \"skeleton.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator@0 {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: sdhci@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: sdhci@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-bus\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp-clk.dtsi", "content": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n&amba {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm_clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&nand0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&qspi {\n\tclocks = <&clk300 &clk300>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&xilinx_drm {\n\tclocks = <&drm_clock>;\n};\n\n&xlnx_dp {\n\tclocks = <&dp_aclk>, <&dp_aud_clk>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&dpdma_clk>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t};\n\n\t\tcpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t};\n\n\t\tcpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tcompatible = \"xlnx,zynqmp-pm\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf01>,\n\t\t\t <1 14 0xf01>,\n\t\t\t <1 11 0xf01>,\n\t\t\t <1 10 0xf01>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x0 0x10000>,\n\t\t\t <0x0 0xf902f000 0x0 0x2000>,\n\t\t\t <0x0 0xf9040000 0x0 0x20000>,\n\t\t\t <0x0 0xf906f000 0x0 0x2000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\txlnx,id = <0>;\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\txlnx,id = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\txlnx,id = <2>;\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\txlnx,id = <3>;\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\txlnx,id = <4>;\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\txlnx,id = <5>;\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\txlnx,id = <6>;\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\txlnx,id = <7>;\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t};\n\n\t\t/* ADMA */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\txlnx,id = <0>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\txlnx,id = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\txlnx,id = <2>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\txlnx,id = <3>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\txlnx,id = <4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\txlnx,id = <5>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\txlnx,id = <6>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\txlnx,id = <7>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tjumbo-max-len = <10240>;\n\t\t\tjumbo-supported;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tjumbo-max-len = <10240>;\n\t\t\tjumbo-supported;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tjumbo-max-len = <10240>;\n\t\t\tjumbo-supported;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tjumbo-max-len = <10240>;\n\t\t\tjumbo-supported;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = < 0 118 4>,\n\t\t\t\t < 0 116 4>,\n\t\t\t\t < 0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t < 0 114 4 >;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"intx\", \"msi_1\", \"msi_0\";\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x0 0xe0000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t\t<0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t};\n\n\t\tsdhci0: sdhci@ff160000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsdhci1: sdhci@ff170000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 157 4>,\n\t\t\t\t<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,\n\t\t\t\t<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,\n\t\t\t\t<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,\n\t\t\t\t<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tusb0: usb@fe200000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tusb1: usb@fe300000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 70 4>;\n\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_drm: xilinx_drm {\n\t\t\tcompatible = \"xlnx,drm\";\n\t\t\tstatus = \"disabled\";\n\t\t\txlnx,encoder-slave = <&xlnx_dp>;\n\t\t\txlnx,connector-type = \"DisplayPort\";\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t\tplanes {\n\t\t\t\txlnx,pixel-format = \"rgb565\";\n\t\t\t\tplane0 {\n\t\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t\t\tdma-names = \"dma\";\n\t\t\t\t};\n\t\t\t\tplane1 {\n\t\t\t\t\tdmas = <&xlnx_dpdma 0>;\n\t\t\t\t\tdma-names = \"dma\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\txlnx_dp: dp@43c00000 {\n\t\t\tcompatible = \"xlnx,v-dp\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"aclk\", \"aud_clk\";\n\t\t\txlnx,dp-version = \"v1.2\";\n\t\t\txlnx,max-lanes = <2>;\n\t\t\txlnx,max-link-rate = <540000>;\n\t\t\txlnx,max-bpc = <16>;\n\t\t\txlnx,enable-ycrcb;\n\t\t\txlnx,colormetry = \"rgb\";\n\t\t\txlnx,bpc = <8>;\n\t\t\txlnx,audio-chan = <2>;\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t};\n\n\t\txlnx_dp_snd_card: dp_snd_card {\n\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\tstatus = \"disabled\";\n\t\t\txlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;\n\t\t\txlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;\n\t\t};\n\n\t\txlnx_dp_snd_codec0: dp_snd_codec0 {\n\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"aud_clk\";\n\t\t};\n\n\t\txlnx_dp_snd_pcm0: dp_snd_pcm0 {\n\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\tstatus = \"disabled\";\n\t\t\tdmas = <&xlnx_dpdma 4>;\n\t\t\tdma-names = \"tx\";\n\t\t};\n\n\t\txlnx_dp_snd_pcm1: dp_snd_pcm1 {\n\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\tstatus = \"disabled\";\n\t\t\tdmas = <&xlnx_dpdma 5>;\n\t\t\tdma-names = \"tx\";\n\t\t};\n\n\t\txlnx_dp_sub: dp_sub@43c0a000 {\n\t\t\tcompatible = \"xlnx,dp-sub\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t\t<0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t\t<0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"blend\", \"av_buf\", \"aud\";\n\t\t\txlnx,output-fmt = \"rgb\";\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel@43c10000 {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel@43c10000 {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel@43c10000 {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel@43c10000 {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel@43c10000 {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel@43c10000 {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2016.1/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2016.1/zynq/zynq-7000.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n/include/ \"skeleton.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator@0 {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: sdhci@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: sdhci@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-bus\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t\t\t<0 14 4>, <0 15 4>,\n\t\t\t\t\t<0 16 4>, <0 17 4>,\n\t\t\t\t\t<0 40 4>, <0 41 4>,\n\t\t\t\t\t<0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp-clk.dtsi", "content": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n&amba {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm_clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&nand0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&qspi {\n\tclocks = <&clk300 &clk300>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&xilinx_drm {\n\tclocks = <&drm_clock>;\n};\n\n&xlnx_dp {\n\tclocks = <&dp_aclk>, <&dp_aud_clk>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&dpdma_clk>;\n};\n\n&xlnx_dp_snd_codec0 {\n\tclocks = <&dp_aud_clk>;\n};" }, { "path": "device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t};\n\n\t\tcpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t};\n\n\t\tcpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t};\n\t};\n\n\tpower-domains {\n\t\tcompatible = \"xlnx,zynqmp-genpd\";\n\n\t\tpd_usb0: pd-usb0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x16>;\n\t\t};\n\n\t\tpd_usb1: pd-usb1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x17>;\n\t\t};\n\n\t\tpd_sata: pd-sata {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1c>;\n\t\t};\n\n\t\tpd_spi0: pd-spi0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x23>;\n\t\t};\n\n\t\tpd_spi1: pd-spi1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x24>;\n\t\t};\n\n\t\tpd_uart0: pd-uart0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x21>;\n\t\t};\n\n\t\tpd_uart1: pd-uart1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x22>;\n\t\t};\n\n\t\tpd_eth0: pd-eth0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1d>;\n\t\t};\n\n\t\tpd_eth1: pd-eth1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1e>;\n\t\t};\n\n\t\tpd_eth2: pd-eth2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1f>;\n\t\t};\n\n\t\tpd_eth3: pd-eth3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x20>;\n\t\t};\n\n\t\tpd_i2c0: pd-i2c0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x25>;\n\t\t};\n\n\t\tpd_i2c1: pd-i2c1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x26>;\n\t\t};\n\n\t\tpd_dp: pd-dp {\n\t\t\t/* fixme: what to attach to */\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x29>;\n\t\t};\n\n\t\tpd_gdma: pd-gdma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2a>;\n\t\t};\n\n\t\tpd_adma: pd-adma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2b>;\n\t\t};\n\n\t\tpd_ttc0: pd-ttc0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x18>;\n\t\t};\n\n\t\tpd_ttc1: pd-ttc1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x19>;\n\t\t};\n\n\t\tpd_ttc2: pd-ttc2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1a>;\n\t\t};\n\n\t\tpd_ttc3: pd-ttc3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1b>;\n\t\t};\n\n\t\tpd_sd0: pd-sd0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x27>;\n\t\t};\n\n\t\tpd_sd1: pd-sd1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x28>;\n\t\t};\n\n\t\tpd_nand: pd-nand {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2c>;\n\t\t};\n\n\t\tpd_qspi: pd-qspi {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2d>;\n\t\t};\n\n\t\tpd_gpio: pd-gpio {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2e>;\n\t\t};\n\n\t\tpd_can0: pd-can0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2f>;\n\t\t};\n\n\t\tpd_can1: pd-can1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x30>;\n\t\t};\n\n\t\tpd_ddr: pd-ddr {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x37>;\n\t\t};\n\n\t\tpd_apll: pd-apll {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x32>;\n\t\t};\n\n\t\tpd_vpll: pd-vpll {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x33>;\n\t\t};\n\n\t\tpd_dpll: pd-dpll {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x34>;\n\t\t};\n\n\t\tpd_rpll: pd-rpll {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x35>;\n\t\t};\n\n\t\tpd_iopll: pd-iopll {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x36>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tcompatible = \"xlnx,zynqmp-pm\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf01>,\n\t\t\t <1 14 0xf01>,\n\t\t\t <1 11 0xf01>,\n\t\t\t <1 10 0xf01>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x0 0x10000>,\n\t\t\t <0x0 0xf902f000 0x0 0x2000>,\n\t\t\t <0x0 0xf9040000 0x0 0x20000>,\n\t\t\t <0x0 0xf906f000 0x0 0x2000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <0>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <2>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <3>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <4>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <5>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <6>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <7>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t};\n\n\t\t/* ADMA */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\txlnx,id = <0>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\txlnx,id = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\txlnx,id = <2>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\txlnx,id = <3>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\txlnx,id = <4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\txlnx,id = <5>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\txlnx,id = <6>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\txlnx,id = <7>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\tpower-domains = <&pd_nand>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tpower-domains = <&pd_eth0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tpower-domains = <&pd_eth1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tpower-domains = <&pd_eth2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tpower-domains = <&pd_eth3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tpower-domains = <&pd_gpio>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"intx\", \"msi_1\", \"msi_0\";\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x0 0xe0000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t\t<0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_qspi>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&pd_sata>;\n\t\t};\n\n\t\tsdhci0: sdhci@ff160000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tbroken-tuning;\n\t\t\tpower-domains = <&pd_sd0>;\n\t\t};\n\n\t\tsdhci1: sdhci@ff170000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tbroken-tuning;\n\t\t\tpower-domains = <&pd_sd1>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t\tmmu-masters = < &gem0 0x874\n\t\t\t\t\t&gem1 0x875\n\t\t\t\t\t&gem2 0x876\n\t\t\t\t\t&gem3 0x877 >;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart1>;\n\t\t};\n\n\t\tusb0: usb@fe200000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125>, <&clk125>;\n\t\t\tpower-domains = <&pd_usb0>;\n\t\t\tranges;\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 65 4>;\n\t\t\t\t/* snps,quirk-frame-length-adjustment = <0x20>; */\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@fe300000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125>, <&clk125>;\n\t\t\tpower-domains = <&pd_usb1>;\n\t\t\tranges;\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 70 4>;\n\t\t\t\t/* snps,quirk-frame-length-adjustment = <0x20>; */\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_drm: xilinx_drm {\n\t\t\tcompatible = \"xlnx,drm\";\n\t\t\tstatus = \"disabled\";\n\t\t\txlnx,encoder-slave = <&xlnx_dp>;\n\t\t\txlnx,connector-type = \"DisplayPort\";\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t\tplanes {\n\t\t\t\txlnx,pixel-format = \"rgb565\";\n\t\t\t\tplane0 {\n\t\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t\t\tdma-names = \"dma\";\n\t\t\t\t};\n\t\t\t\tplane1 {\n\t\t\t\t\tdmas = <&xlnx_dpdma 0>;\n\t\t\t\t\tdma-names = \"dma\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\txlnx_dp: dp@fd4a0000 {\n\t\t\tcompatible = \"xlnx,v-dp\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd400000 0x0 0x20000>;\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"aclk\", \"aud_clk\";\n\t\t\txlnx,dp-version = \"v1.2\";\n\t\t\txlnx,max-lanes = <2>;\n\t\t\txlnx,max-link-rate = <540000>;\n\t\t\txlnx,max-bpc = <16>;\n\t\t\txlnx,enable-ycrcb;\n\t\t\txlnx,colormetry = \"rgb\";\n\t\t\txlnx,bpc = <8>;\n\t\t\txlnx,audio-chan = <2>;\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t\txlnx,max-pclock-frequency = <300000>;\n\t\t};\n\n\t\txlnx_dp_snd_card: dp_snd_card {\n\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\tstatus = \"disabled\";\n\t\t\txlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;\n\t\t\txlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;\n\t\t};\n\n\t\txlnx_dp_snd_codec0: dp_snd_codec0 {\n\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"aud_clk\";\n\t\t};\n\n\t\txlnx_dp_snd_pcm0: dp_snd_pcm0 {\n\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\tstatus = \"disabled\";\n\t\t\tdmas = <&xlnx_dpdma 4>;\n\t\t\tdma-names = \"tx\";\n\t\t};\n\n\t\txlnx_dp_snd_pcm1: dp_snd_pcm1 {\n\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\tstatus = \"disabled\";\n\t\t\tdmas = <&xlnx_dpdma 5>;\n\t\t\tdma-names = \"tx\";\n\t\t};\n\n\t\txlnx_dp_sub: dp_sub@fd4aa000 {\n\t\t\tcompatible = \"xlnx,dp-sub\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t\t<0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t\t<0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"blend\", \"av_buf\", \"aud\";\n\t\t\txlnx,output-fmt = \"rgb\";\n\t\t\txlnx,vid-fmt = \"yuyv\";\n\t\t\txlnx,gfx-fmt = \"rgb565\";\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2016.2/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2016.2/zynq/zynq-7000.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n/include/ \"skeleton.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator@0 {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: sdhci@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: sdhci@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-bus\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t\t\t<0 14 4>, <0 15 4>,\n\t\t\t\t\t<0 16 4>, <0 17 4>,\n\t\t\t\t\t<0 40 4>, <0 41 4>,\n\t\t\t\t\t<0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp-clk.dtsi", "content": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n&amba {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm_clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&nand0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&qspi {\n\tclocks = <&clk300 &clk300>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&xilinx_drm {\n\tclocks = <&drm_clock>;\n};\n\n&xlnx_dp {\n\tclocks = <&dp_aclk>, <&dp_aud_clk>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&dpdma_clk>;\n};\n\n&xlnx_dp_snd_codec0 {\n\tclocks = <&dp_aud_clk>;\n};" }, { "path": "device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t};\n\n\t\tcpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t};\n\n\t\tcpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t};\n\t};\n\n\tpower-domains {\n\t\tcompatible = \"xlnx,zynqmp-genpd\";\n\n\t\tpd_usb0: pd-usb0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x16>;\n\t\t};\n\n\t\tpd_usb1: pd-usb1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x17>;\n\t\t};\n\n\t\tpd_sata: pd-sata {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1c>;\n\t\t};\n\n\t\tpd_spi0: pd-spi0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x23>;\n\t\t};\n\n\t\tpd_spi1: pd-spi1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x24>;\n\t\t};\n\n\t\tpd_uart0: pd-uart0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x21>;\n\t\t};\n\n\t\tpd_uart1: pd-uart1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x22>;\n\t\t};\n\n\t\tpd_eth0: pd-eth0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1d>;\n\t\t};\n\n\t\tpd_eth1: pd-eth1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1e>;\n\t\t};\n\n\t\tpd_eth2: pd-eth2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1f>;\n\t\t};\n\n\t\tpd_eth3: pd-eth3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x20>;\n\t\t};\n\n\t\tpd_i2c0: pd-i2c0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x25>;\n\t\t};\n\n\t\tpd_i2c1: pd-i2c1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x26>;\n\t\t};\n\n\t\tpd_dp: pd-dp {\n\t\t\t/* fixme: what to attach to */\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x29>;\n\t\t};\n\n\t\tpd_gdma: pd-gdma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2a>;\n\t\t};\n\n\t\tpd_adma: pd-adma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2b>;\n\t\t};\n\n\t\tpd_ttc0: pd-ttc0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x18>;\n\t\t};\n\n\t\tpd_ttc1: pd-ttc1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x19>;\n\t\t};\n\n\t\tpd_ttc2: pd-ttc2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1a>;\n\t\t};\n\n\t\tpd_ttc3: pd-ttc3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1b>;\n\t\t};\n\n\t\tpd_sd0: pd-sd0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x27>;\n\t\t};\n\n\t\tpd_sd1: pd-sd1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x28>;\n\t\t};\n\n\t\tpd_nand: pd-nand {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2c>;\n\t\t};\n\n\t\tpd_qspi: pd-qspi {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2d>;\n\t\t};\n\n\t\tpd_gpio: pd-gpio {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2e>;\n\t\t};\n\n\t\tpd_can0: pd-can0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2f>;\n\t\t};\n\n\t\tpd_can1: pd-can1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x30>;\n\t\t};\n\n\t\tpd_ddr: pd-ddr {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x37>;\n\t\t};\n\n\t\tpd_apll: pd-apll {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x32>;\n\t\t};\n\n\t\tpd_vpll: pd-vpll {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x33>;\n\t\t};\n\n\t\tpd_dpll: pd-dpll {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x34>;\n\t\t};\n\n\t\tpd_rpll: pd-rpll {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x35>;\n\t\t};\n\n\t\tpd_iopll: pd-iopll {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x36>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tcompatible = \"xlnx,zynqmp-pm\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf01>,\n\t\t\t <1 14 0xf01>,\n\t\t\t <1 11 0xf01>,\n\t\t\t <1 10 0xf01>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <0>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <2>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <3>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <4>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <5>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <6>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,id = <7>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t};\n\n\t\t/* ADMA */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\txlnx,id = <0>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x868>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\txlnx,id = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x869>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\txlnx,id = <2>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86a>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\txlnx,id = <3>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86b>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\txlnx,id = <4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86c>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\txlnx,id = <5>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86d>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\txlnx,id = <6>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86e>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\txlnx,id = <7>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86f>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&pd_nand>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&pd_eth0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&pd_eth1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&pd_eth2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&pd_eth3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\treg = <0x0 0xff0a0000 0x1000>;\n\t\t\tpower-domains = <&pd_gpio>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"intx\", \"msi_1\", \"msi_0\";\n\t\t\treg = <0x0 0xfd0e0000 0x1000>,\n\t\t\t <0x0 0xfd480000 0x1000>,\n\t\t\t <0x0 0xe0000000 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x1000>,\n\t\t\t <0x0 0xc0000000 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&pd_qspi>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t};\n\n\t\tserdes: zynqmp_phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x40000>, <0x0 0xfd3d0000 0x1000>,\n\t\t\t\t<0x0 0xfd1a0000 0x1000>, <0x0 0xff5e0000 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\", \"fpd\", \"lpd\";\n\t\t\txlnx,tx_termination_fix;\n\t\t\tlan0: lane@0 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlan1: lane@1 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlan2: lane@2 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlan3: lane@3 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&pd_sata>;\n\t\t};\n\n\t\tsdhci0: sdhci@ff160000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tbroken-tuning;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&pd_sd0>;\n\t\t};\n\n\t\tsdhci1: sdhci@ff170000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tbroken-tuning;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&pd_sd1>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t\tmmu-masters = < &gem0 0x874\n\t\t\t\t\t&gem1 0x875\n\t\t\t\t\t&gem2 0x876\n\t\t\t\t\t&gem3 0x877\n\t\t\t\t\t&usb0 0x860\n\t\t\t\t\t&usb1 0x861\n\t\t\t\t\t&qspi 0x873\n\t\t\t\t\t&lpd_dma_chan1 0x868\n\t\t\t\t\t&lpd_dma_chan2 0x869\n\t\t\t\t\t&lpd_dma_chan3 0x86a\n\t\t\t\t\t&lpd_dma_chan4 0x86b\n\t\t\t\t\t&lpd_dma_chan5 0x86c\n\t\t\t\t\t&lpd_dma_chan6 0x86d\n\t\t\t\t\t&lpd_dma_chan7 0x86e\n\t\t\t\t\t&lpd_dma_chan8 0x86f\n\t\t\t\t\t&fpd_dma_chan1 0x14e8\n\t\t\t\t\t&fpd_dma_chan2 0x14e9\n\t\t\t\t\t&fpd_dma_chan3 0x14ea\n\t\t\t\t\t&fpd_dma_chan4 0x14eb\n\t\t\t\t\t&fpd_dma_chan5 0x14ec\n\t\t\t\t\t&fpd_dma_chan6 0x14ed\n\t\t\t\t\t&fpd_dma_chan7 0x14ee\n\t\t\t\t\t&fpd_dma_chan8 0x14ef\n\t\t\t\t\t&sdhci0 0x870\n\t\t\t\t\t&sdhci1 0x871\n\t\t\t\t\t&nand0 0x872>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart1>;\n\t\t};\n\n\t\tusb0: usb@fe200000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125>, <&clk125>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x860>;\n\t\t\tpower-domains = <&pd_usb0>;\n\t\t\tranges;\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 65 4>;\n\t\t\t\t/* snps,quirk-frame-length-adjustment = <0x20>; */\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@fe300000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125>, <&clk125>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x861>;\n\t\t\tpower-domains = <&pd_usb1>;\n\t\t\tranges;\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 70 4>;\n\t\t\t\t/* snps,quirk-frame-length-adjustment = <0x20>; */\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_drm: xilinx_drm {\n\t\t\tcompatible = \"xlnx,drm\";\n\t\t\tstatus = \"disabled\";\n\t\t\txlnx,encoder-slave = <&xlnx_dp>;\n\t\t\txlnx,connector-type = \"DisplayPort\";\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t\tplanes {\n\t\t\t\txlnx,pixel-format = \"rgb565\";\n\t\t\t\tplane0 {\n\t\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t\t\tdma-names = \"dma\";\n\t\t\t\t};\n\t\t\t\tplane1 {\n\t\t\t\t\tdmas = <&xlnx_dpdma 0>;\n\t\t\t\t\tdma-names = \"dma\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\txlnx_dp: dp@fd4a0000 {\n\t\t\tcompatible = \"xlnx,v-dp\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x1000>;\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"aclk\", \"aud_clk\";\n\t\t\txlnx,dp-version = \"v1.2\";\n\t\t\txlnx,max-lanes = <2>;\n\t\t\txlnx,max-link-rate = <540000>;\n\t\t\txlnx,max-bpc = <16>;\n\t\t\txlnx,enable-ycrcb;\n\t\t\txlnx,colormetry = \"rgb\";\n\t\t\txlnx,bpc = <8>;\n\t\t\txlnx,audio-chan = <2>;\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t\txlnx,max-pclock-frequency = <300000>;\n\t\t};\n\n\t\txlnx_dp_snd_card: dp_snd_card {\n\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\tstatus = \"disabled\";\n\t\t\txlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;\n\t\t\txlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;\n\t\t};\n\n\t\txlnx_dp_snd_codec0: dp_snd_codec0 {\n\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"aud_clk\";\n\t\t};\n\n\t\txlnx_dp_snd_pcm0: dp_snd_pcm0 {\n\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\tstatus = \"disabled\";\n\t\t\tdmas = <&xlnx_dpdma 4>;\n\t\t\tdma-names = \"tx\";\n\t\t};\n\n\t\txlnx_dp_snd_pcm1: dp_snd_pcm1 {\n\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\tstatus = \"disabled\";\n\t\t\tdmas = <&xlnx_dpdma 5>;\n\t\t\tdma-names = \"tx\";\n\t\t};\n\n\t\txlnx_dp_sub: dp_sub@fd4aa000 {\n\t\t\tcompatible = \"xlnx,dp-sub\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4aa000 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x1000>;\n\t\t\treg-names = \"blend\", \"av_buf\", \"aud\";\n\t\t\txlnx,output-fmt = \"rgb\";\n\t\t\txlnx,vid-fmt = \"yuyv\";\n\t\t\txlnx,gfx-fmt = \"rgb565\";\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2016.3/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2016.3/zynq/zynq-7000.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n/include/ \"skeleton.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator@0 {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: sdhci@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t\tbroken-adma2;\n\t\t};\n\n\t\tsdhci1: sdhci@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t\tbroken-adma2;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t\t\t<0 14 4>, <0 15 4>,\n\t\t\t\t\t<0 16 4>, <0 17 4>,\n\t\t\t\t\t<0 40 4>, <0 41 4>,\n\t\t\t\t\t<0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp-clk.dtsi", "content": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n&amba {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm_clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&nand0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&qspi {\n\tclocks = <&clk300 &clk300>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&xilinx_drm {\n\tclocks = <&drm_clock>;\n};\n\n&xlnx_dp {\n\tclocks = <&dp_aclk>, <&dp_aud_clk>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&dpdma_clk>;\n};\n\n&xlnx_dp_snd_codec0 {\n\tclocks = <&dp_aud_clk>;\n};" }, { "path": "device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t};\n\n\t\tcpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t};\n\n\t\tcpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t};\n\t};\n\n\tpower-domains {\n\t\tcompatible = \"xlnx,zynqmp-genpd\";\n\n\t\tpd_usb0: pd-usb0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x16>;\n\t\t};\n\n\t\tpd_usb1: pd-usb1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x17>;\n\t\t};\n\n\t\tpd_sata: pd-sata {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1c>;\n\t\t};\n\n\t\tpd_spi0: pd-spi0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x23>;\n\t\t};\n\n\t\tpd_spi1: pd-spi1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x24>;\n\t\t};\n\n\t\tpd_uart0: pd-uart0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x21>;\n\t\t};\n\n\t\tpd_uart1: pd-uart1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x22>;\n\t\t};\n\n\t\tpd_eth0: pd-eth0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1d>;\n\t\t};\n\n\t\tpd_eth1: pd-eth1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1e>;\n\t\t};\n\n\t\tpd_eth2: pd-eth2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1f>;\n\t\t};\n\n\t\tpd_eth3: pd-eth3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x20>;\n\t\t};\n\n\t\tpd_i2c0: pd-i2c0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x25>;\n\t\t};\n\n\t\tpd_i2c1: pd-i2c1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x26>;\n\t\t};\n\n\t\tpd_dp: pd-dp {\n\t\t\t/* fixme: what to attach to */\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x29>;\n\t\t};\n\n\t\tpd_gdma: pd-gdma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2a>;\n\t\t};\n\n\t\tpd_adma: pd-adma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2b>;\n\t\t};\n\n\t\tpd_ttc0: pd-ttc0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x18>;\n\t\t};\n\n\t\tpd_ttc1: pd-ttc1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x19>;\n\t\t};\n\n\t\tpd_ttc2: pd-ttc2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1a>;\n\t\t};\n\n\t\tpd_ttc3: pd-ttc3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1b>;\n\t\t};\n\n\t\tpd_sd0: pd-sd0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x27>;\n\t\t};\n\n\t\tpd_sd1: pd-sd1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x28>;\n\t\t};\n\n\t\tpd_nand: pd-nand {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2c>;\n\t\t};\n\n\t\tpd_qspi: pd-qspi {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2d>;\n\t\t};\n\n\t\tpd_gpio: pd-gpio {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2e>;\n\t\t};\n\n\t\tpd_can0: pd-can0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2f>;\n\t\t};\n\n\t\tpd_can1: pd-can1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x30>;\n\t\t};\n\t\tpd_pcie: pd-pcie {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3b>;\n\t\t};\n\t\tpd_gpu: pd-gpu {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3a 0x14 0x15>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tcompatible = \"xlnx,zynqmp-pm\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf01>,\n\t\t\t <1 14 0xf01>,\n\t\t\t <1 11 0xf01>,\n\t\t\t <1 10 0xf01>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tpcap {\n\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tpower-domains = <&pd_gpu>;\n\t\t};\n\n\t\t/* ADMA */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x868>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x869>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86a>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86b>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86c>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86d>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86e>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86f>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&pd_nand>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&pd_eth0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&pd_eth1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&pd_eth2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&pd_eth3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tpower-domains = <&pd_gpio>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\",\"dummy\",\"intx\", \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpower-domains = <&pd_pcie>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&pd_qspi>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t};\n\n\t\tserdes: zynqmp_phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd1a0000 0x0 0x1000>,\n\t\t\t <0x0 0xff5e0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\", \"fpd\", \"lpd\";\n\t\t\txlnx,tx_termination_fix;\n\t\t\tlane0: lane@0 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane1: lane@1 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane2: lane@2 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane3: lane@3 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&pd_sata>;\n\t\t};\n\n\t\tsdhci0: sdhci@ff160000 {\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&pd_sd0>;\n\t\t};\n\n\t\tsdhci1: sdhci@ff170000 {\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&pd_sd1>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t\tmmu-masters = < &gem0 0x874\n\t\t\t\t\t&gem1 0x875\n\t\t\t\t\t&gem2 0x876\n\t\t\t\t\t&gem3 0x877\n\t\t\t\t\t&usb0 0x860\n\t\t\t\t\t&usb1 0x861\n\t\t\t\t\t&qspi 0x873\n\t\t\t\t\t&lpd_dma_chan1 0x868\n\t\t\t\t\t&lpd_dma_chan2 0x869\n\t\t\t\t\t&lpd_dma_chan3 0x86a\n\t\t\t\t\t&lpd_dma_chan4 0x86b\n\t\t\t\t\t&lpd_dma_chan5 0x86c\n\t\t\t\t\t&lpd_dma_chan6 0x86d\n\t\t\t\t\t&lpd_dma_chan7 0x86e\n\t\t\t\t\t&lpd_dma_chan8 0x86f\n\t\t\t\t\t&fpd_dma_chan1 0x14e8\n\t\t\t\t\t&fpd_dma_chan2 0x14e9\n\t\t\t\t\t&fpd_dma_chan3 0x14ea\n\t\t\t\t\t&fpd_dma_chan4 0x14eb\n\t\t\t\t\t&fpd_dma_chan5 0x14ec\n\t\t\t\t\t&fpd_dma_chan6 0x14ed\n\t\t\t\t\t&fpd_dma_chan7 0x14ee\n\t\t\t\t\t&fpd_dma_chan8 0x14ef\n\t\t\t\t\t&sdhci0 0x870\n\t\t\t\t\t&sdhci1 0x871\n\t\t\t\t\t&nand0 0x872>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart1>;\n\t\t};\n\n\t\tusb0: usb@fe200000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125>, <&clk125>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x860>;\n\t\t\tpower-domains = <&pd_usb0>;\n\t\t\tranges;\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 65 4>;\n\t\t\t\t/* snps,quirk-frame-length-adjustment = <0x20>; */\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@fe300000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125>, <&clk125>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x861>;\n\t\t\tpower-domains = <&pd_usb1>;\n\t\t\tranges;\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 70 4>;\n\t\t\t\t/* snps,quirk-frame-length-adjustment = <0x20>; */\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_drm: xilinx_drm {\n\t\t\tcompatible = \"xlnx,drm\";\n\t\t\tstatus = \"disabled\";\n\t\t\txlnx,encoder-slave = <&xlnx_dp>;\n\t\t\txlnx,connector-type = \"DisplayPort\";\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t\tplanes {\n\t\t\t\txlnx,pixel-format = \"rgb565\";\n\t\t\t\tplane0 {\n\t\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t\t\tdma-names = \"dma0\";\n\t\t\t\t};\n\t\t\t\tplane1 {\n\t\t\t\t\tdmas = <&xlnx_dpdma 0>,\n\t\t\t\t\t <&xlnx_dpdma 1>,\n\t\t\t\t\t <&xlnx_dpdma 2>;\n\t\t\t\t\tdma-names = \"dma0\", \"dma1\", \"dma2\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\txlnx_dp: dp@fd4a0000 {\n\t\t\tcompatible = \"xlnx,v-dp\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"aclk\", \"aud_clk\";\n\t\t\txlnx,dp-version = \"v1.2\";\n\t\t\txlnx,max-lanes = <2>;\n\t\t\txlnx,max-link-rate = <540000>;\n\t\t\txlnx,max-bpc = <16>;\n\t\t\txlnx,enable-ycrcb;\n\t\t\txlnx,colormetry = \"rgb\";\n\t\t\txlnx,bpc = <8>;\n\t\t\txlnx,audio-chan = <2>;\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t\txlnx,max-pclock-frequency = <300000>;\n\t\t};\n\n\t\txlnx_dp_snd_card: dp_snd_card {\n\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\tstatus = \"disabled\";\n\t\t\txlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;\n\t\t\txlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;\n\t\t};\n\n\t\txlnx_dp_snd_codec0: dp_snd_codec0 {\n\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"aud_clk\";\n\t\t};\n\n\t\txlnx_dp_snd_pcm0: dp_snd_pcm0 {\n\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\tstatus = \"disabled\";\n\t\t\tdmas = <&xlnx_dpdma 4>;\n\t\t\tdma-names = \"tx\";\n\t\t};\n\n\t\txlnx_dp_snd_pcm1: dp_snd_pcm1 {\n\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\tstatus = \"disabled\";\n\t\t\tdmas = <&xlnx_dpdma 5>;\n\t\t\tdma-names = \"tx\";\n\t\t};\n\n\t\txlnx_dp_sub: dp_sub@fd4aa000 {\n\t\t\tcompatible = \"xlnx,dp-sub\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"blend\", \"av_buf\", \"aud\";\n\t\t\txlnx,output-fmt = \"rgb\";\n\t\t\txlnx,vid-fmt = \"yuyv\";\n\t\t\txlnx,gfx-fmt = \"rgb565\";\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2016.4/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2016.4/zynq/zynq-7000.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n/include/ \"skeleton.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator@0 {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: sdhci@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t\tbroken-adma2;\n\t\t};\n\n\t\tsdhci1: sdhci@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t\tbroken-adma2;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp-clk.dtsi", "content": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n&amba {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm_clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&nand0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&qspi {\n\tclocks = <&clk300 &clk300>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&watchdog0 {\n\tclocks = <&clk250>;\n};\n\n&xilinx_drm {\n\tclocks = <&drm_clock>;\n};\n\n&xlnx_dp {\n\tclocks = <&dp_aclk>, <&dp_aud_clk>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&dpdma_clk>;\n};\n\n&xlnx_dp_snd_codec0 {\n\tclocks = <&dp_aud_clk>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-mehod = \"arm,psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <800000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t};\n\n\tpower-domains {\n\t\tcompatible = \"xlnx,zynqmp-genpd\";\n\n\t\tpd_usb0: pd-usb0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x16>;\n\t\t};\n\n\t\tpd_usb1: pd-usb1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x17>;\n\t\t};\n\n\t\tpd_sata: pd-sata {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1c>;\n\t\t};\n\n\t\tpd_spi0: pd-spi0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x23>;\n\t\t};\n\n\t\tpd_spi1: pd-spi1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x24>;\n\t\t};\n\n\t\tpd_uart0: pd-uart0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x21>;\n\t\t};\n\n\t\tpd_uart1: pd-uart1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x22>;\n\t\t};\n\n\t\tpd_eth0: pd-eth0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1d>;\n\t\t};\n\n\t\tpd_eth1: pd-eth1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1e>;\n\t\t};\n\n\t\tpd_eth2: pd-eth2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1f>;\n\t\t};\n\n\t\tpd_eth3: pd-eth3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x20>;\n\t\t};\n\n\t\tpd_i2c0: pd-i2c0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x25>;\n\t\t};\n\n\t\tpd_i2c1: pd-i2c1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x26>;\n\t\t};\n\n\t\tpd_dp: pd-dp {\n\t\t\t/* fixme: what to attach to */\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x29>;\n\t\t};\n\n\t\tpd_gdma: pd-gdma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2a>;\n\t\t};\n\n\t\tpd_adma: pd-adma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2b>;\n\t\t};\n\n\t\tpd_ttc0: pd-ttc0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x18>;\n\t\t};\n\n\t\tpd_ttc1: pd-ttc1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x19>;\n\t\t};\n\n\t\tpd_ttc2: pd-ttc2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1a>;\n\t\t};\n\n\t\tpd_ttc3: pd-ttc3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1b>;\n\t\t};\n\n\t\tpd_sd0: pd-sd0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x27>;\n\t\t};\n\n\t\tpd_sd1: pd-sd1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x28>;\n\t\t};\n\n\t\tpd_nand: pd-nand {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2c>;\n\t\t};\n\n\t\tpd_qspi: pd-qspi {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2d>;\n\t\t};\n\n\t\tpd_gpio: pd-gpio {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2e>;\n\t\t};\n\n\t\tpd_can0: pd-can0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2f>;\n\t\t};\n\n\t\tpd_can1: pd-can1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x30>;\n\t\t};\n\n\t\tpd_pcie: pd-pcie {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3b>;\n\t\t};\n\n\t\tpd_gpu: pd-gpu {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3a 0x14 0x15>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tcompatible = \"xlnx,zynqmp-pm\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf01>,\n\t\t\t <1 14 0xf01>,\n\t\t\t <1 11 0xf01>,\n\t\t\t <1 10 0xf01>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tpcap {\n\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tpower-domains = <&pd_gpu>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x868>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x869>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86a>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86b>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86c>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86d>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86e>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86f>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&pd_nand>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&pd_eth0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&pd_eth1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&pd_eth2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&pd_eth3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tpower-domains = <&pd_gpio>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\",\"dummy\",\"intx\", \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpower-domains = <&pd_pcie>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&pd_qspi>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t};\n\n\t\tserdes: zynqmp_phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd1a0000 0x0 0x1000>,\n\t\t\t <0x0 0xff5e0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\", \"fpd\", \"lpd\";\n\t\t\txlnx,tx_termination_fix;\n\t\t\tlane0: lane@0 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane1: lane@1 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane2: lane@2 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane3: lane@3 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&pd_sata>;\n\t\t};\n\n\t\tsdhci0: sdhci@ff160000 {\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&pd_sd0>;\n\t\t};\n\n\t\tsdhci1: sdhci@ff170000 {\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&pd_sd1>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t\tmmu-masters = < &gem0 0x874\n\t\t\t\t\t&gem1 0x875\n\t\t\t\t\t&gem2 0x876\n\t\t\t\t\t&gem3 0x877\n\t\t\t\t\t&usb0 0x860\n\t\t\t\t\t&usb1 0x861\n\t\t\t\t\t&qspi 0x873\n\t\t\t\t\t&lpd_dma_chan1 0x868\n\t\t\t\t\t&lpd_dma_chan2 0x869\n\t\t\t\t\t&lpd_dma_chan3 0x86a\n\t\t\t\t\t&lpd_dma_chan4 0x86b\n\t\t\t\t\t&lpd_dma_chan5 0x86c\n\t\t\t\t\t&lpd_dma_chan6 0x86d\n\t\t\t\t\t&lpd_dma_chan7 0x86e\n\t\t\t\t\t&lpd_dma_chan8 0x86f\n\t\t\t\t\t&fpd_dma_chan1 0x14e8\n\t\t\t\t\t&fpd_dma_chan2 0x14e9\n\t\t\t\t\t&fpd_dma_chan3 0x14ea\n\t\t\t\t\t&fpd_dma_chan4 0x14eb\n\t\t\t\t\t&fpd_dma_chan5 0x14ec\n\t\t\t\t\t&fpd_dma_chan6 0x14ed\n\t\t\t\t\t&fpd_dma_chan7 0x14ee\n\t\t\t\t\t&fpd_dma_chan8 0x14ef\n\t\t\t\t\t&sdhci0 0x870\n\t\t\t\t\t&sdhci1 0x871\n\t\t\t\t\t&nand0 0x872>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart1>;\n\t\t};\n\n\t\tusb0: usb@fe200000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125>, <&clk125>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x860>;\n\t\t\tpower-domains = <&pd_usb0>;\n\t\t\tranges;\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 65 4>;\n\t\t\t\t/* snps,quirk-frame-length-adjustment = <0x20>; */\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@fe300000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125>, <&clk125>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x861>;\n\t\t\tpower-domains = <&pd_usb1>;\n\t\t\tranges;\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 70 4>;\n\t\t\t\t/* snps,quirk-frame-length-adjustment = <0x20>; */\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_drm: xilinx_drm {\n\t\t\tcompatible = \"xlnx,drm\";\n\t\t\tstatus = \"disabled\";\n\t\t\txlnx,encoder-slave = <&xlnx_dp>;\n\t\t\txlnx,connector-type = \"DisplayPort\";\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t\tplanes {\n\t\t\t\txlnx,pixel-format = \"rgb565\";\n\t\t\t\tplane0 {\n\t\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t\t\tdma-names = \"dma0\";\n\t\t\t\t};\n\t\t\t\tplane1 {\n\t\t\t\t\tdmas = <&xlnx_dpdma 0>,\n\t\t\t\t\t <&xlnx_dpdma 1>,\n\t\t\t\t\t <&xlnx_dpdma 2>;\n\t\t\t\t\tdma-names = \"dma0\", \"dma1\", \"dma2\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\txlnx_dp: dp@fd4a0000 {\n\t\t\tcompatible = \"xlnx,v-dp\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"aclk\", \"aud_clk\";\n\t\t\txlnx,dp-version = \"v1.2\";\n\t\t\txlnx,max-lanes = <2>;\n\t\t\txlnx,max-link-rate = <540000>;\n\t\t\txlnx,max-bpc = <16>;\n\t\t\txlnx,enable-ycrcb;\n\t\t\txlnx,colormetry = \"rgb\";\n\t\t\txlnx,bpc = <8>;\n\t\t\txlnx,audio-chan = <2>;\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t\txlnx,max-pclock-frequency = <300000>;\n\t\t};\n\n\t\txlnx_dp_snd_card: dp_snd_card {\n\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\tstatus = \"disabled\";\n\t\t\txlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;\n\t\t\txlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;\n\t\t};\n\n\t\txlnx_dp_snd_codec0: dp_snd_codec0 {\n\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"aud_clk\";\n\t\t};\n\n\t\txlnx_dp_snd_pcm0: dp_snd_pcm0 {\n\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\tstatus = \"disabled\";\n\t\t\tdmas = <&xlnx_dpdma 4>;\n\t\t\tdma-names = \"tx\";\n\t\t};\n\n\t\txlnx_dp_snd_pcm1: dp_snd_pcm1 {\n\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\tstatus = \"disabled\";\n\t\t\tdmas = <&xlnx_dpdma 5>;\n\t\t\tdma-names = \"tx\";\n\t\t};\n\n\t\txlnx_dp_sub: dp_sub@fd4aa000 {\n\t\t\tcompatible = \"xlnx,dp-sub\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"blend\", \"av_buf\", \"aud\";\n\t\t\txlnx,output-fmt = \"rgb\";\n\t\t\txlnx,vid-fmt = \"yuyv\";\n\t\t\txlnx,gfx-fmt = \"rgb565\";\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel@fd4c0000 {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Signed-off-by: Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\ni * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 0>;\n\tsda-gpios = <&gpio 37 0>;\n\n\teeprom@55 {\n\t\tcompatible = \"at,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 3 150000000>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v; /* for 1.0 silicon */\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n\n\n&xlnx_dp_sub {\n\txlnx,vid-clk-pl;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_0_cd_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_0_wp_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 0>;\n\tsda-gpios = <&gpio 7 0>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: spi0_flash0@0 {\n\t\tcompatible = \"m25p80\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tspi0_flash0@00000000 {\n\t\t\tlabel = \"spi0_flash0\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: spi1_flash0@0 {\n\t\tcompatible = \"mtd_dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tspi1_flash0@00000000 {\n\t\t\tlabel = \"spi1_flash0\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_0_ce_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_0_ce_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_0_rb_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_0_rb_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_0_dqs_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_0_dqs_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_0_ss0_grp\", \"spi0_0_ss1_grp\",\n\t\t\t\t\t\t\t\"spi0_0_ss2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_0_ss0_grp\", \"spi0_0_ss1_grp\",\n\t\t\t\t\t\t\t\"spi0_0_ss2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_3_ss0_grp\", \"spi1_3_ss1_grp\",\n\t\t\t\t\t\t\t\"spi1_3_ss2_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_3_ss0_grp\", \"spi1_3_ss1_grp\",\n\t\t\t\t\t\t\t\"spi1_3_ss2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t\tsw13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@52 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <52>;\n\t\t\t};\n\t\t\thwmon@53 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <53>;\n\t\t\t};\n\t\t\thwmon@54 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\t/* for 1.0 silicon */\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zcu102.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\t/* for 1.0 silicon */\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zcu106.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* i2c mw 74 0 11 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>; /* FIXME */\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/zynq/zynq-7000.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: sdhci@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t\tbroken-adma2;\n\t\t};\n\n\t\tsdhci1: sdhci@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t\tbroken-adma2;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk-ccf.dtsi", "content": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 71>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 72>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 73>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 74>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tclkc: clkc {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clkc\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\", \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t\tclock-output-names = \"iopll\", \"rpll\", \"apll\", \"dpll\",\n\t\t\t\t\"vpll\", \"iopll_to_fpd\", \"rpll_to_fpd\",\n\t\t\t\t\"apll_to_lpd\", \"dpll_to_lpd\", \"vpll_to_lpd\",\n\t\t\t\t\"acpu\", \"acpu_half\", \"dbf_fpd\", \"dbf_lpd\",\n\t\t\t\t\"dbg_trace\", \"dbg_tstmp\", \"dp_video_ref\",\n\t\t\t\t\"dp_audio_ref\", \"dp_stc_ref\", \"gdma_ref\",\n\t\t\t\t\"dpdma_ref\", \"ddr_ref\", \"sata_ref\", \"pcie_ref\",\n\t\t\t\t\"gpu_ref\", \"gpu_pp0_ref\", \"gpu_pp1_ref\",\n\t\t\t\t\"topsw_main\", \"topsw_lsbus\", \"gtgref0_ref\",\n\t\t\t\t\"lpd_switch\", \"lpd_lsbus\", \"usb0_bus_ref\",\n\t\t\t\t\"usb1_bus_ref\", \"usb3_dual_ref\", \"usb0\",\n\t\t\t\t\"usb1\", \"cpu_r5\", \"cpu_r5_core\", \"csu_spb\",\n\t\t\t\t\"csu_pll\", \"pcap\", \"iou_switch\", \"gem_tsu_ref\",\n\t\t\t\t\"gem_tsu\", \"gem0_ref\", \"gem1_ref\", \"gem2_ref\",\n\t\t\t\t\"gem3_ref\", \"gem0_tx\", \"gem1_tx\", \"gem2_tx\",\n\t\t\t\t\"gem3_tx\", \"qspi_ref\", \"sdio0_ref\", \"sdio1_ref\",\n\t\t\t\t\"uart0_ref\", \"uart1_ref\", \"spi0_ref\",\n\t\t\t\t\"spi1_ref\", \"nand_ref\", \"i2c0_ref\", \"i2c1_ref\",\n\t\t\t\t\"can0_ref\", \"can1_ref\", \"can0\", \"can1\",\n\t\t\t\t\"dll_ref\", \"adma_ref\", \"timestamp_ref\",\n\t\t\t\t\"ams_ref\", \"pl0\", \"pl1\", \"pl2\", \"pl3\", \"wdt\";\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clkc 63>, <&clkc 31>;\n};\n\n&can1 {\n\tclocks = <&clkc 64>, <&clkc 31>;\n};\n\n&cpu0 {\n\tclocks = <&clkc 10>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&gpu {\n\tclocks = <&clkc 24>, <&clkc 25>, <&clkc 26>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&nand0 {\n\tclocks = <&clkc 60>, <&clkc 31>;\n};\n\n&gem0 {\n\tclocks = <&clkc 45>, <&clkc 45>, <&clkc 49>;\n\tclock-names = \"pclk\", \"tx_clk\", \"hclk\";\n};\n\n&gem1 {\n\tclocks = <&clkc 46>, <&clkc 46>, <&clkc 50>;\n\tclock-names = \"pclk\", \"tx_clk\", \"hclk\";\n};\n\n&gem2 {\n\tclocks = <&clkc 47>, <&clkc 47>, <&clkc 51>;\n\tclock-names = \"pclk\", \"tx_clk\", \"hclk\";\n};\n\n&gem3 {\n\tclocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n};\n\n&gpio {\n\tclocks = <&clkc 31>;\n};\n\n&i2c0 {\n\tclocks = <&clkc 61>;\n};\n\n&i2c1 {\n\tclocks = <&clkc 62>;\n};\n\n&pcie {\n\tclocks = <&clkc 23>;\n};\n\n&qspi {\n\tclocks = <&clkc 53>, <&clkc 31>;\n};\n\n&sata {\n\tclocks = <&clkc 22>;\n};\n\n&sdhci0 {\n\tclocks = <&clkc 54>, <&clkc 31>;\n};\n\n&sdhci1 {\n\tclocks = <&clkc 55>, <&clkc 31>;\n};\n\n&spi0 {\n\tclocks = <&clkc 58>, <&clkc 31>;\n};\n\n&spi1 {\n\tclocks = <&clkc 59>, <&clkc 31>;\n};\n\n&uart0 {\n\tclocks = <&clkc 56>, <&clkc 31>;\n};\n\n&uart1 {\n\tclocks = <&clkc 57>, <&clkc 31>;\n};\n\n&usb0 {\n\tclocks = <&clkc 32>, <&clkc 34>;\n};\n\n&usb1 {\n\tclocks = <&clkc 33>, <&clkc 34>;\n};\n\n&watchdog0 {\n\tclocks = <&clkc 75>;\n};\n\n&xilinx_ams {\n\tclocks = <&clkc 70>;\n};\n\n&xilinx_drm {\n\tclocks = <&clkc 16>;\n};\n\n&xlnx_dp {\n\tclocks = <&dp_aclk>, <&clkc 17>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&clkc 20>;\n};\n\n&xlnx_dp_snd_codec0 {\n\tclocks = <&clkc 17>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk.dtsi", "content": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n&amba {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm_clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&nand0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&qspi {\n\tclocks = <&clk300 &clk300>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&watchdog0 {\n\tclocks = <&clk250>;\n};\n\n&xilinx_drm {\n\tclocks = <&drm_clock>;\n};\n\n&xlnx_dp {\n\tclocks = <&dp_aclk>, <&dp_aud_clk>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&dpdma_clk>;\n};\n\n&xlnx_dp_snd_codec0 {\n\tclocks = <&dp_aud_clk>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"arm,psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <100000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tpower-domains {\n\t\tcompatible = \"xlnx,zynqmp-genpd\";\n\n\t\tpd_usb0: pd-usb0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x16>;\n\t\t};\n\n\t\tpd_usb1: pd-usb1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x17>;\n\t\t};\n\n\t\tpd_sata: pd-sata {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1c>;\n\t\t};\n\n\t\tpd_spi0: pd-spi0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x23>;\n\t\t};\n\n\t\tpd_spi1: pd-spi1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x24>;\n\t\t};\n\n\t\tpd_uart0: pd-uart0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x21>;\n\t\t};\n\n\t\tpd_uart1: pd-uart1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x22>;\n\t\t};\n\n\t\tpd_eth0: pd-eth0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1d>;\n\t\t};\n\n\t\tpd_eth1: pd-eth1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1e>;\n\t\t};\n\n\t\tpd_eth2: pd-eth2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1f>;\n\t\t};\n\n\t\tpd_eth3: pd-eth3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x20>;\n\t\t};\n\n\t\tpd_i2c0: pd-i2c0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x25>;\n\t\t};\n\n\t\tpd_i2c1: pd-i2c1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x26>;\n\t\t};\n\n\t\tpd_dp: pd-dp {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x29>;\n\t\t};\n\n\t\tpd_gdma: pd-gdma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2a>;\n\t\t};\n\n\t\tpd_adma: pd-adma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2b>;\n\t\t};\n\n\t\tpd_ttc0: pd-ttc0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x18>;\n\t\t};\n\n\t\tpd_ttc1: pd-ttc1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x19>;\n\t\t};\n\n\t\tpd_ttc2: pd-ttc2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1a>;\n\t\t};\n\n\t\tpd_ttc3: pd-ttc3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1b>;\n\t\t};\n\n\t\tpd_sd0: pd-sd0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x27>;\n\t\t};\n\n\t\tpd_sd1: pd-sd1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x28>;\n\t\t};\n\n\t\tpd_nand: pd-nand {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2c>;\n\t\t};\n\n\t\tpd_qspi: pd-qspi {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2d>;\n\t\t};\n\n\t\tpd_gpio: pd-gpio {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2e>;\n\t\t};\n\n\t\tpd_can0: pd-can0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2f>;\n\t\t};\n\n\t\tpd_can1: pd-can1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x30>;\n\t\t};\n\n\t\tpd_pcie: pd-pcie {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3b>;\n\t\t};\n\n\t\tpd_gpu: pd-gpu {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3a 0x14 0x15>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tpmufw: firmware {\n\t\tcompatible = \"xlnx,zynqmp-pm\";\n\t\tmethod = \"smc\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tnvmem_firmware {\n\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsoc_revision: soc_revision@0 {\n\t\t\treg = <0x0 0x4>;\n\t\t};\n\t};\n\n\tpcap {\n\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t};\n\n\trst: reset-controller {\n\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\tamba_apu: amba_apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\", \"gpu_pp0\", \"gpu_pp1\";\n\t\t\tpower-domains = <&pd_gpu>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x868>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x869>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86a>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86b>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86c>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86d>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86e>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86f>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&pd_nand>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&pd_eth0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&pd_eth1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&pd_eth2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&pd_eth3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tpower-domains = <&pd_gpio>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\",\"dummy\",\"intx\", \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpower-domains = <&pd_pcie>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&pd_qspi>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tserdes: zynqmp_phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>,\n\t\t\t <0x0 0xff5e0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\", \"lpd\";\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\tresets = <&rst 16>, <&rst 59>, <&rst 60>,\n\t\t\t\t <&rst 61>, <&rst 62>, <&rst 63>,\n\t\t\t\t <&rst 64>, <&rst 3>, <&rst 29>,\n\t\t\t\t <&rst 30>, <&rst 31>, <&rst 32>;\n\t\t\treset-names = \"sata_rst\", \"usb0_crst\", \"usb1_crst\",\n\t\t\t\t \"usb0_hibrst\", \"usb1_hibrst\", \"usb0_apbrst\",\n\t\t\t\t \"usb1_apbrst\", \"dp_rst\", \"gem0_rst\",\n\t\t\t\t \"gem1_rst\", \"gem2_rst\", \"gem3_rst\";\n\t\t\tlane0: lane0 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane1: lane1 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane2: lane2 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane3: lane3 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&pd_sata>;\n\t\t};\n\n\t\tsdhci0: sdhci@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&pd_sd0>;\n\t\t};\n\n\t\tsdhci1: sdhci@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&pd_sd1>;\n\t\t};\n\n\t\tpinctrl0: pinctrl@ff180000 {\n\t\t\tcompatible = \"xlnx,pinctrl-zynqmp\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff180000 0x0 0x1000>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart1>;\n\t\t};\n\n\t\tusb0: usb0 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x860>;\n\t\t\tpower-domains = <&pd_usb0>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb1 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x861>;\n\t\t\tpower-domains = <&pd_usb1>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\n\t\t\tams_ps: ams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50800 0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50c00 0x0 0x400>;\n\t\t\t};\n\t\t};\n\n\t\txilinx_drm: xilinx_drm {\n\t\t\tcompatible = \"xlnx,drm\";\n\t\t\tstatus = \"disabled\";\n\t\t\txlnx,encoder-slave = <&xlnx_dp>;\n\t\t\txlnx,connector-type = \"DisplayPort\";\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t\tplanes {\n\t\t\t\txlnx,pixel-format = \"rgb565\";\n\t\t\t\tplane0 {\n\t\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t\t\tdma-names = \"dma0\";\n\t\t\t\t};\n\t\t\t\tplane1 {\n\t\t\t\t\tdmas = <&xlnx_dpdma 0>,\n\t\t\t\t\t <&xlnx_dpdma 1>,\n\t\t\t\t\t <&xlnx_dpdma 2>;\n\t\t\t\t\tdma-names = \"dma0\", \"dma1\", \"dma2\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\txlnx_dp: dp@fd4a0000 {\n\t\t\tcompatible = \"xlnx,v-dp\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"aclk\", \"aud_clk\";\n\t\t\tpower-domains = <&pd_dp>;\n\t\t\txlnx,dp-version = \"v1.2\";\n\t\t\txlnx,max-lanes = <2>;\n\t\t\txlnx,max-link-rate = <540000>;\n\t\t\txlnx,max-bpc = <16>;\n\t\t\txlnx,enable-ycrcb;\n\t\t\txlnx,colormetry = \"rgb\";\n\t\t\txlnx,bpc = <8>;\n\t\t\txlnx,audio-chan = <2>;\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t\txlnx,max-pclock-frequency = <300000>;\n\t\t};\n\n\t\txlnx_dp_snd_card: dp_snd_card {\n\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\tstatus = \"disabled\";\n\t\t\txlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;\n\t\t\txlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;\n\t\t};\n\n\t\txlnx_dp_snd_codec0: dp_snd_codec0 {\n\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"aud_clk\";\n\t\t};\n\n\t\txlnx_dp_snd_pcm0: dp_snd_pcm0 {\n\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\tstatus = \"disabled\";\n\t\t\tdmas = <&xlnx_dpdma 4>;\n\t\t\tdma-names = \"tx\";\n\t\t};\n\n\t\txlnx_dp_snd_pcm1: dp_snd_pcm1 {\n\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\tstatus = \"disabled\";\n\t\t\tdmas = <&xlnx_dpdma 5>;\n\t\t\tdma-names = \"tx\";\n\t\t};\n\n\t\txlnx_dp_sub: dp_sub@fd4aa000 {\n\t\t\tcompatible = \"xlnx,dp-sub\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"blend\", \"av_buf\", \"aud\";\n\t\t\txlnx,output-fmt = \"rgb\";\n\t\t\txlnx,vid-fmt = \"yuyv\";\n\t\t\txlnx,gfx-fmt = \"rgb565\";\n\t\t\tpower-domains = <&pd_dp>;\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&pd_dp>;\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 0>;\n\tsda-gpios = <&gpio 37 0>;\n\n\teeprom@55 {\n\t\tcompatible = \"at,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 3 150000000>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v; /* for 1.0 silicon */\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n\n\n&xlnx_dp_sub {\n\txlnx,vid-clk-pl;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_0_cd_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_0_wp_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 0>;\n\tsda-gpios = <&gpio 7 0>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: spi0_flash0@0 {\n\t\tcompatible = \"m25p80\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tspi0_flash0@00000000 {\n\t\t\tlabel = \"spi0_flash0\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: spi1_flash0@0 {\n\t\tcompatible = \"mtd_dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tspi1_flash0@00000000 {\n\t\t\tlabel = \"spi1_flash0\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_0_ce_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_0_ce_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_0_rb_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_0_rb_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_0_dqs_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_0_dqs_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_0_ss0_grp\", \"spi0_0_ss1_grp\",\n\t\t\t\t\t\t\t\"spi0_0_ss2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_0_ss0_grp\", \"spi0_0_ss1_grp\",\n\t\t\t\t\t\t\t\"spi0_0_ss2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_3_ss0_grp\", \"spi1_3_ss1_grp\",\n\t\t\t\t\t\t\t\"spi1_3_ss2_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_3_ss0_grp\", \"spi1_3_ss1_grp\",\n\t\t\t\t\t\t\t\"spi1_3_ss2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t\tsw13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@52 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <52>;\n\t\t\t};\n\t\t\thwmon@53 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <53>;\n\t\t\t};\n\t\t\thwmon@54 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zcu100-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2cswitch@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio_bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zcu100-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n\n\tkim { /* Bluetooth driver for connection */\n\t\tcompatible = \"kim\";\n\t\tstatus = \"okay\";\n\t\t/*\n\t\t * FIXME: The following is complete CRAP since\n\t\t * the vendor driver doesn't follow the gpio\n\t\t * binding. Passing in a magic Linux gpio number\n\t\t * here until we fix the vendor driver.\n\t\t */\n\t\t/* FIXME BT_EN*/\n\t\t/* nshutdown_gpio = <&gpio 8 0>; */\n\t\tnshutdown_gpio = <346>; /* 338 base + MIO8 */\n\t\tdev_name = \"/dev/ttyPS1\"; /* MIO2/3 */\n\t\tflow_cntrl = <1>;\n\t\tbaud_rate = <3000000>;\n\t};\n\t/*\n\t * CONFIG_BT_WILINK - depends on\n\t * btwilink: add minimal device tree support\n\t * commit b3ef820a9310743d62cf50341f529ca17319dd77\n\t */\n\tbtwilink { /* Bluetooth driver itself */\n\t\tstatus = \"okay\";\n\t\tcompatible = \"btwilink\";\n\t};\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2cswitch@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_4bit_0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_4bit_0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_0_cd_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_4bit_0_1_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_4bit_0_1_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_3_ss0_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_3_ss0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_0_ss0_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_0_ss0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO3\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO2\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO1\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n};\n\n&spi1 { /* High Speed connector */\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\t/* for 1.0 silicon */\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zcu102.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\t/* for 1.0 silicon */\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zcu106.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* i2c mw 74 0 11 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>; /* FIXME */\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/zynq/zynq-7000.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: sdhci@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t\tbroken-adma2;\n\t\t};\n\n\t\tsdhci1: sdhci@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t\tbroken-adma2;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk-ccf.dtsi", "content": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 71>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 72>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 73>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 74>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tclkc: clkc {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clkc\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\", \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t\tclock-output-names = \"iopll\", \"rpll\", \"apll\", \"dpll\",\n\t\t\t\t\"vpll\", \"iopll_to_fpd\", \"rpll_to_fpd\",\n\t\t\t\t\"apll_to_lpd\", \"dpll_to_lpd\", \"vpll_to_lpd\",\n\t\t\t\t\"acpu\", \"acpu_half\", \"dbf_fpd\", \"dbf_lpd\",\n\t\t\t\t\"dbg_trace\", \"dbg_tstmp\", \"dp_video_ref\",\n\t\t\t\t\"dp_audio_ref\", \"dp_stc_ref\", \"gdma_ref\",\n\t\t\t\t\"dpdma_ref\", \"ddr_ref\", \"sata_ref\", \"pcie_ref\",\n\t\t\t\t\"gpu_ref\", \"gpu_pp0_ref\", \"gpu_pp1_ref\",\n\t\t\t\t\"topsw_main\", \"topsw_lsbus\", \"gtgref0_ref\",\n\t\t\t\t\"lpd_switch\", \"lpd_lsbus\", \"usb0_bus_ref\",\n\t\t\t\t\"usb1_bus_ref\", \"usb3_dual_ref\", \"usb0\",\n\t\t\t\t\"usb1\", \"cpu_r5\", \"cpu_r5_core\", \"csu_spb\",\n\t\t\t\t\"csu_pll\", \"pcap\", \"iou_switch\", \"gem_tsu_ref\",\n\t\t\t\t\"gem_tsu\", \"gem0_ref\", \"gem1_ref\", \"gem2_ref\",\n\t\t\t\t\"gem3_ref\", \"gem0_tx\", \"gem1_tx\", \"gem2_tx\",\n\t\t\t\t\"gem3_tx\", \"qspi_ref\", \"sdio0_ref\", \"sdio1_ref\",\n\t\t\t\t\"uart0_ref\", \"uart1_ref\", \"spi0_ref\",\n\t\t\t\t\"spi1_ref\", \"nand_ref\", \"i2c0_ref\", \"i2c1_ref\",\n\t\t\t\t\"can0_ref\", \"can1_ref\", \"can0\", \"can1\",\n\t\t\t\t\"dll_ref\", \"adma_ref\", \"timestamp_ref\",\n\t\t\t\t\"ams_ref\", \"pl0\", \"pl1\", \"pl2\", \"pl3\", \"wdt\";\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clkc 63>, <&clkc 31>;\n};\n\n&can1 {\n\tclocks = <&clkc 64>, <&clkc 31>;\n};\n\n&cpu0 {\n\tclocks = <&clkc 10>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&gpu {\n\tclocks = <&clkc 24>, <&clkc 25>, <&clkc 26>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&nand0 {\n\tclocks = <&clkc 60>, <&clkc 31>;\n};\n\n&gem0 {\n\tclocks = <&clkc 45>, <&clkc 45>, <&clkc 49>;\n\tclock-names = \"pclk\", \"tx_clk\", \"hclk\";\n};\n\n&gem1 {\n\tclocks = <&clkc 46>, <&clkc 46>, <&clkc 50>;\n\tclock-names = \"pclk\", \"tx_clk\", \"hclk\";\n};\n\n&gem2 {\n\tclocks = <&clkc 47>, <&clkc 47>, <&clkc 51>;\n\tclock-names = \"pclk\", \"tx_clk\", \"hclk\";\n};\n\n&gem3 {\n\tclocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n};\n\n&gpio {\n\tclocks = <&clkc 31>;\n};\n\n&i2c0 {\n\tclocks = <&clkc 61>;\n};\n\n&i2c1 {\n\tclocks = <&clkc 62>;\n};\n\n&pcie {\n\tclocks = <&clkc 23>;\n};\n\n&qspi {\n\tclocks = <&clkc 53>, <&clkc 31>;\n};\n\n&sata {\n\tclocks = <&clkc 22>;\n};\n\n&sdhci0 {\n\tclocks = <&clkc 54>, <&clkc 31>;\n};\n\n&sdhci1 {\n\tclocks = <&clkc 55>, <&clkc 31>;\n};\n\n&spi0 {\n\tclocks = <&clkc 58>, <&clkc 31>;\n};\n\n&spi1 {\n\tclocks = <&clkc 59>, <&clkc 31>;\n};\n\n&uart0 {\n\tclocks = <&clkc 56>, <&clkc 31>;\n};\n\n&uart1 {\n\tclocks = <&clkc 57>, <&clkc 31>;\n};\n\n&usb0 {\n\tclocks = <&clkc 32>, <&clkc 34>;\n};\n\n&usb1 {\n\tclocks = <&clkc 33>, <&clkc 34>;\n};\n\n&watchdog0 {\n\tclocks = <&clkc 75>;\n};\n\n&xilinx_ams {\n\tclocks = <&clkc 70>;\n};\n\n&xilinx_drm {\n\tclocks = <&clkc 16>;\n};\n\n&xlnx_dp {\n\tclocks = <&dp_aclk>, <&clkc 17>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&clkc 20>;\n};\n\n&xlnx_dp_snd_codec0 {\n\tclocks = <&clkc 17>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk.dtsi", "content": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n&amba {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm_clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&nand0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&qspi {\n\tclocks = <&clk300 &clk300>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&watchdog0 {\n\tclocks = <&clk250>;\n};\n\n&xilinx_drm {\n\tclocks = <&drm_clock>;\n};\n\n&xlnx_dp {\n\tclocks = <&dp_aclk>, <&dp_aud_clk>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&dpdma_clk>;\n};\n\n&xlnx_dp_snd_codec0 {\n\tclocks = <&dp_aud_clk>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"arm,psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <100000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tpower-domains {\n\t\tcompatible = \"xlnx,zynqmp-genpd\";\n\n\t\tpd_usb0: pd-usb0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x16>;\n\t\t};\n\n\t\tpd_usb1: pd-usb1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x17>;\n\t\t};\n\n\t\tpd_sata: pd-sata {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1c>;\n\t\t};\n\n\t\tpd_spi0: pd-spi0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x23>;\n\t\t};\n\n\t\tpd_spi1: pd-spi1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x24>;\n\t\t};\n\n\t\tpd_uart0: pd-uart0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x21>;\n\t\t};\n\n\t\tpd_uart1: pd-uart1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x22>;\n\t\t};\n\n\t\tpd_eth0: pd-eth0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1d>;\n\t\t};\n\n\t\tpd_eth1: pd-eth1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1e>;\n\t\t};\n\n\t\tpd_eth2: pd-eth2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1f>;\n\t\t};\n\n\t\tpd_eth3: pd-eth3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x20>;\n\t\t};\n\n\t\tpd_i2c0: pd-i2c0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x25>;\n\t\t};\n\n\t\tpd_i2c1: pd-i2c1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x26>;\n\t\t};\n\n\t\tpd_dp: pd-dp {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x29>;\n\t\t};\n\n\t\tpd_gdma: pd-gdma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2a>;\n\t\t};\n\n\t\tpd_adma: pd-adma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2b>;\n\t\t};\n\n\t\tpd_ttc0: pd-ttc0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x18>;\n\t\t};\n\n\t\tpd_ttc1: pd-ttc1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x19>;\n\t\t};\n\n\t\tpd_ttc2: pd-ttc2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1a>;\n\t\t};\n\n\t\tpd_ttc3: pd-ttc3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1b>;\n\t\t};\n\n\t\tpd_sd0: pd-sd0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x27>;\n\t\t};\n\n\t\tpd_sd1: pd-sd1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x28>;\n\t\t};\n\n\t\tpd_nand: pd-nand {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2c>;\n\t\t};\n\n\t\tpd_qspi: pd-qspi {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2d>;\n\t\t};\n\n\t\tpd_gpio: pd-gpio {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2e>;\n\t\t};\n\n\t\tpd_can0: pd-can0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2f>;\n\t\t};\n\n\t\tpd_can1: pd-can1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x30>;\n\t\t};\n\n\t\tpd_pcie: pd-pcie {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3b>;\n\t\t};\n\n\t\tpd_gpu: pd-gpu {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3a 0x14 0x15>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tpmufw: firmware {\n\t\tcompatible = \"xlnx,zynqmp-pm\";\n\t\tmethod = \"smc\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tnvmem_firmware {\n\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsoc_revision: soc_revision@0 {\n\t\t\treg = <0x0 0x4>;\n\t\t};\n\t};\n\n\tpcap {\n\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t};\n\n\trst: reset-controller {\n\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\tamba_apu: amba_apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\", \"gpu_pp0\", \"gpu_pp1\";\n\t\t\tpower-domains = <&pd_gpu>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x868>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x869>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86a>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86b>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86c>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86d>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86e>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x86f>;\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&pd_nand>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&pd_eth0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&pd_eth1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&pd_eth2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&pd_eth3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tpower-domains = <&pd_gpio>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\",\"dummy\",\"intx\", \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpower-domains = <&pd_pcie>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&pd_qspi>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tserdes: zynqmp_phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>,\n\t\t\t <0x0 0xff5e0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\", \"lpd\";\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\tresets = <&rst 16>, <&rst 59>, <&rst 60>,\n\t\t\t\t <&rst 61>, <&rst 62>, <&rst 63>,\n\t\t\t\t <&rst 64>, <&rst 3>, <&rst 29>,\n\t\t\t\t <&rst 30>, <&rst 31>, <&rst 32>;\n\t\t\treset-names = \"sata_rst\", \"usb0_crst\", \"usb1_crst\",\n\t\t\t\t \"usb0_hibrst\", \"usb1_hibrst\", \"usb0_apbrst\",\n\t\t\t\t \"usb1_apbrst\", \"dp_rst\", \"gem0_rst\",\n\t\t\t\t \"gem1_rst\", \"gem2_rst\", \"gem3_rst\";\n\t\t\tlane0: lane0 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane1: lane1 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane2: lane2 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane3: lane3 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&pd_sata>;\n\t\t};\n\n\t\tsdhci0: sdhci@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&pd_sd0>;\n\t\t};\n\n\t\tsdhci1: sdhci@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&pd_sd1>;\n\t\t};\n\n\t\tpinctrl0: pinctrl@ff180000 {\n\t\t\tcompatible = \"xlnx,pinctrl-zynqmp\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff180000 0x0 0x1000>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart1>;\n\t\t};\n\n\t\tusb0: usb0 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x860>;\n\t\t\tpower-domains = <&pd_usb0>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb1 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x861>;\n\t\t\tpower-domains = <&pd_usb1>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\n\t\t\tams_ps: ams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50800 0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50c00 0x0 0x400>;\n\t\t\t};\n\t\t};\n\n\t\txilinx_drm: xilinx_drm {\n\t\t\tcompatible = \"xlnx,drm\";\n\t\t\tstatus = \"disabled\";\n\t\t\txlnx,encoder-slave = <&xlnx_dp>;\n\t\t\txlnx,connector-type = \"DisplayPort\";\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t\tplanes {\n\t\t\t\txlnx,pixel-format = \"rgb565\";\n\t\t\t\tplane0 {\n\t\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t\t\tdma-names = \"dma0\";\n\t\t\t\t};\n\t\t\t\tplane1 {\n\t\t\t\t\tdmas = <&xlnx_dpdma 0>,\n\t\t\t\t\t <&xlnx_dpdma 1>,\n\t\t\t\t\t <&xlnx_dpdma 2>;\n\t\t\t\t\tdma-names = \"dma0\", \"dma1\", \"dma2\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\txlnx_dp: dp@fd4a0000 {\n\t\t\tcompatible = \"xlnx,v-dp\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"aclk\", \"aud_clk\";\n\t\t\tpower-domains = <&pd_dp>;\n\t\t\txlnx,dp-version = \"v1.2\";\n\t\t\txlnx,max-lanes = <2>;\n\t\t\txlnx,max-link-rate = <540000>;\n\t\t\txlnx,max-bpc = <16>;\n\t\t\txlnx,enable-ycrcb;\n\t\t\txlnx,colormetry = \"rgb\";\n\t\t\txlnx,bpc = <8>;\n\t\t\txlnx,audio-chan = <2>;\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t\txlnx,max-pclock-frequency = <300000>;\n\t\t};\n\n\t\txlnx_dp_snd_card: dp_snd_card {\n\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\tstatus = \"disabled\";\n\t\t\txlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;\n\t\t\txlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;\n\t\t};\n\n\t\txlnx_dp_snd_codec0: dp_snd_codec0 {\n\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"aud_clk\";\n\t\t};\n\n\t\txlnx_dp_snd_pcm0: dp_snd_pcm0 {\n\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\tstatus = \"disabled\";\n\t\t\tdmas = <&xlnx_dpdma 4>;\n\t\t\tdma-names = \"tx\";\n\t\t};\n\n\t\txlnx_dp_snd_pcm1: dp_snd_pcm1 {\n\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\tstatus = \"disabled\";\n\t\t\tdmas = <&xlnx_dpdma 5>;\n\t\t\tdma-names = \"tx\";\n\t\t};\n\n\t\txlnx_dp_sub: dp_sub@fd4aa000 {\n\t\t\tcompatible = \"xlnx,dp-sub\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"blend\", \"av_buf\", \"aud\";\n\t\t\txlnx,output-fmt = \"rgb\";\n\t\t\txlnx,vid-fmt = \"yuyv\";\n\t\t\txlnx,gfx-fmt = \"rgb565\";\n\t\t\tpower-domains = <&pd_dp>;\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&pd_dp>;\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zc1232-reva.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane0 1 0 0 125000000>, <&lane1 1 1 1 125000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zc1254-reva.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zc1275-reva.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revA\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 0>;\n\tsda-gpios = <&gpio 37 0>;\n\n\teeprom@55 {\n\t\tcompatible = \"at,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 3 150000000>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n\n\n&xlnx_dp_sub {\n\txlnx,vid-clk-pl;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_0_cd_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_0_wp_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 0>;\n\tsda-gpios = <&gpio 7 0>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: spi0_flash0@0 {\n\t\tcompatible = \"m25p80\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tspi0_flash0@0 {\n\t\t\tlabel = \"spi0_flash0\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: spi1_flash0@0 {\n\t\tcompatible = \"mtd_dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tspi1_flash0@0 {\n\t\t\tlabel = \"spi1_flash0\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_0_ce_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_0_ce_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_0_rb_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_0_rb_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_0_dqs_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_0_dqs_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_0_ss0_grp\", \"spi0_0_ss1_grp\",\n\t\t\t\t\t\t\t\"spi0_0_ss2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_0_ss0_grp\", \"spi0_0_ss1_grp\",\n\t\t\t\t\t\t\t\"spi0_0_ss2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_3_ss0_grp\", \"spi1_3_ss1_grp\",\n\t\t\t\t\t\t\t\"spi1_3_ss2_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_3_ss0_grp\", \"spi1_3_ss1_grp\",\n\t\t\t\t\t\t\t\"spi1_3_ss2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t\tsw13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@52 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <52>;\n\t\t\t};\n\t\t\thwmon@53 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <53>;\n\t\t\t};\n\t\t\thwmon@54 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu100-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2cswitch@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio_bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu100-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2cswitch@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu100-revc.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2cswitch@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 1>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board_sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth_mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board_name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board_revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu104-reva.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: 8t49n287@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FIXME Npt detected */\n\t\t\ttca6416_u97: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 { /* i2c mw 74 0 10 */ /* FMC_LPC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 { /* i2c mw 74 0 14 */ /* DDR4_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n/* fpd_dma clk 667MHz, lpd_dma 500MHz */\n&fpd_dma_chan1 {\n\txlnx,include-sg; /* for testing purpose */\n\txlnx,overfetch; /* for testing purpose */\n\txlnx,ratectrl = <0>; /* for testing purpose */\n\txlnx,src-issue = <31>;\n};\n\n&fpd_dma_chan2 {\n\txlnx,ratectrl = <100>; /* for testing purpose */\n\txlnx,src-issue = <4>; /* for testing purpose */\n};\n\n&fpd_dma_chan4 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan6 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&fpd_dma_chan8 {\n\txlnx,include-sg; /* for testing purpose */\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* i2c mw 74 0 11 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>; /* FIXME */\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/zynq/zynq-7000.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: sdhci@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t\tbroken-adma2;\n\t\t};\n\n\t\tsdhci1: sdhci@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t\tbroken-adma2;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk-ccf.dtsi", "content": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 71>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 72>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 73>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 74>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tclkc: clkc {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clkc\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\", \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t\tclock-output-names = \"iopll\", \"rpll\", \"apll\", \"dpll\",\n\t\t\t\t\"vpll\", \"iopll_to_fpd\", \"rpll_to_fpd\",\n\t\t\t\t\"apll_to_lpd\", \"dpll_to_lpd\", \"vpll_to_lpd\",\n\t\t\t\t\"acpu\", \"acpu_half\", \"dbf_fpd\", \"dbf_lpd\",\n\t\t\t\t\"dbg_trace\", \"dbg_tstmp\", \"dp_video_ref\",\n\t\t\t\t\"dp_audio_ref\", \"dp_stc_ref\", \"gdma_ref\",\n\t\t\t\t\"dpdma_ref\", \"ddr_ref\", \"sata_ref\", \"pcie_ref\",\n\t\t\t\t\"gpu_ref\", \"gpu_pp0_ref\", \"gpu_pp1_ref\",\n\t\t\t\t\"topsw_main\", \"topsw_lsbus\", \"gtgref0_ref\",\n\t\t\t\t\"lpd_switch\", \"lpd_lsbus\", \"usb0_bus_ref\",\n\t\t\t\t\"usb1_bus_ref\", \"usb3_dual_ref\", \"usb0\",\n\t\t\t\t\"usb1\", \"cpu_r5\", \"cpu_r5_core\", \"csu_spb\",\n\t\t\t\t\"csu_pll\", \"pcap\", \"iou_switch\", \"gem_tsu_ref\",\n\t\t\t\t\"gem_tsu\", \"gem0_ref\", \"gem1_ref\", \"gem2_ref\",\n\t\t\t\t\"gem3_ref\", \"gem0_tx\", \"gem1_tx\", \"gem2_tx\",\n\t\t\t\t\"gem3_tx\", \"qspi_ref\", \"sdio0_ref\", \"sdio1_ref\",\n\t\t\t\t\"uart0_ref\", \"uart1_ref\", \"spi0_ref\",\n\t\t\t\t\"spi1_ref\", \"nand_ref\", \"i2c0_ref\", \"i2c1_ref\",\n\t\t\t\t\"can0_ref\", \"can1_ref\", \"can0\", \"can1\",\n\t\t\t\t\"dll_ref\", \"adma_ref\", \"timestamp_ref\",\n\t\t\t\t\"ams_ref\", \"pl0\", \"pl1\", \"pl2\", \"pl3\", \"wdt\";\n\t};\n\n\tdp_aclk: dp_aclk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clkc 63>, <&clkc 31>;\n};\n\n&can1 {\n\tclocks = <&clkc 64>, <&clkc 31>;\n};\n\n&cpu0 {\n\tclocks = <&clkc 10>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&gpu {\n\tclocks = <&clkc 24>, <&clkc 25>, <&clkc 26>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&nand0 {\n\tclocks = <&clkc 60>, <&clkc 31>;\n};\n\n&gem0 {\n\tclocks = <&clkc 45>, <&clkc 45>, <&clkc 49>;\n\tclock-names = \"pclk\", \"tx_clk\", \"hclk\";\n};\n\n&gem1 {\n\tclocks = <&clkc 46>, <&clkc 46>, <&clkc 50>;\n\tclock-names = \"pclk\", \"tx_clk\", \"hclk\";\n};\n\n&gem2 {\n\tclocks = <&clkc 47>, <&clkc 47>, <&clkc 51>;\n\tclock-names = \"pclk\", \"tx_clk\", \"hclk\";\n};\n\n&gem3 {\n\tclocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n};\n\n&gpio {\n\tclocks = <&clkc 31>;\n};\n\n&i2c0 {\n\tclocks = <&clkc 61>;\n};\n\n&i2c1 {\n\tclocks = <&clkc 62>;\n};\n\n&pcie {\n\tclocks = <&clkc 23>;\n};\n\n&qspi {\n\tclocks = <&clkc 53>, <&clkc 31>;\n};\n\n&sata {\n\tclocks = <&clkc 22>;\n};\n\n&sdhci0 {\n\tclocks = <&clkc 54>, <&clkc 31>;\n};\n\n&sdhci1 {\n\tclocks = <&clkc 55>, <&clkc 31>;\n};\n\n&spi0 {\n\tclocks = <&clkc 58>, <&clkc 31>;\n};\n\n&spi1 {\n\tclocks = <&clkc 59>, <&clkc 31>;\n};\n\n&uart0 {\n\tclocks = <&clkc 56>, <&clkc 31>;\n};\n\n&uart1 {\n\tclocks = <&clkc 57>, <&clkc 31>;\n};\n\n&usb0 {\n\tclocks = <&clkc 32>, <&clkc 34>;\n};\n\n&usb1 {\n\tclocks = <&clkc 33>, <&clkc 34>;\n};\n\n&watchdog0 {\n\tclocks = <&clkc 75>;\n};\n\n&xilinx_ams {\n\tclocks = <&clkc 70>;\n};\n\n&xilinx_drm {\n\tclocks = <&clkc 16>;\n};\n\n&xlnx_dp {\n\tclocks = <&dp_aclk>, <&clkc 17>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&clkc 20>;\n};\n\n&xlnx_dp_snd_codec0 {\n\tclocks = <&clkc 17>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk.dtsi", "content": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n&amba {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm_clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&nand0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&qspi {\n\tclocks = <&clk300 &clk300>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&watchdog0 {\n\tclocks = <&clk250>;\n};\n\n&xilinx_drm {\n\tclocks = <&drm_clock>;\n};\n\n&xlnx_dp {\n\tclocks = <&dp_aclk>, <&dp_aud_clk>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&dpdma_clk>;\n};\n\n&xlnx_dp_snd_codec0 {\n\tclocks = <&dp_aud_clk>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"arm,psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tpower-domains {\n\t\tcompatible = \"xlnx,zynqmp-genpd\";\n\n\t\tpd_usb0: pd-usb0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x16>;\n\t\t};\n\n\t\tpd_usb1: pd-usb1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x17>;\n\t\t};\n\n\t\tpd_sata: pd-sata {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1c>;\n\t\t};\n\n\t\tpd_spi0: pd-spi0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x23>;\n\t\t};\n\n\t\tpd_spi1: pd-spi1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x24>;\n\t\t};\n\n\t\tpd_uart0: pd-uart0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x21>;\n\t\t};\n\n\t\tpd_uart1: pd-uart1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x22>;\n\t\t};\n\n\t\tpd_eth0: pd-eth0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1d>;\n\t\t};\n\n\t\tpd_eth1: pd-eth1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1e>;\n\t\t};\n\n\t\tpd_eth2: pd-eth2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1f>;\n\t\t};\n\n\t\tpd_eth3: pd-eth3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x20>;\n\t\t};\n\n\t\tpd_i2c0: pd-i2c0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x25>;\n\t\t};\n\n\t\tpd_i2c1: pd-i2c1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x26>;\n\t\t};\n\n\t\tpd_dp: pd-dp {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x29>;\n\t\t};\n\n\t\tpd_gdma: pd-gdma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2a>;\n\t\t};\n\n\t\tpd_adma: pd-adma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2b>;\n\t\t};\n\n\t\tpd_ttc0: pd-ttc0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x18>;\n\t\t};\n\n\t\tpd_ttc1: pd-ttc1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x19>;\n\t\t};\n\n\t\tpd_ttc2: pd-ttc2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1a>;\n\t\t};\n\n\t\tpd_ttc3: pd-ttc3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1b>;\n\t\t};\n\n\t\tpd_sd0: pd-sd0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x27>;\n\t\t};\n\n\t\tpd_sd1: pd-sd1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x28>;\n\t\t};\n\n\t\tpd_nand: pd-nand {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2c>;\n\t\t};\n\n\t\tpd_qspi: pd-qspi {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2d>;\n\t\t};\n\n\t\tpd_gpio: pd-gpio {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2e>;\n\t\t};\n\n\t\tpd_can0: pd-can0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2f>;\n\t\t};\n\n\t\tpd_can1: pd-can1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x30>;\n\t\t};\n\n\t\tpd_pcie: pd-pcie {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3b>;\n\t\t};\n\n\t\tpd_gpu: pd-gpu {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3a 0x14 0x15>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tpmufw: firmware {\n\t\tcompatible = \"xlnx,zynqmp-pm\";\n\t\tmethod = \"smc\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tnvmem_firmware {\n\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsoc_revision: soc_revision@0 {\n\t\t\treg = <0x0 0x4>;\n\t\t};\n\t};\n\n\tpcap: pcap {\n\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t};\n\n\trst: reset-controller {\n\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\txlnx_rsa: zynqmp_rsa {\n\t\tcompatible = \"xlnx,zynqmp-rsa\";\n\t};\n\n\txlnx_keccak_384: sha384 {\n\t\tcompatible = \"xlnx,zynqmp-keccak-384\";\n\t};\n\n\txlnx_dp_snd_card: dp_snd_card {\n\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\tstatus = \"disabled\";\n\t\txlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;\n\t\txlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;\n\t};\n\n\txlnx_dp_snd_codec0: dp_snd_codec0 {\n\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\tstatus = \"disabled\";\n\t\tclock-names = \"aud_clk\";\n\t};\n\n\txlnx_dp_snd_pcm0: dp_snd_pcm0 {\n\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\tstatus = \"disabled\";\n\t\tdmas = <&xlnx_dpdma 4>;\n\t\tdma-names = \"tx\";\n\t};\n\n\txlnx_dp_snd_pcm1: dp_snd_pcm1 {\n\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\tstatus = \"disabled\";\n\t\tdmas = <&xlnx_dpdma 5>;\n\t\tdma-names = \"tx\";\n\t};\n\n\txilinx_drm: xilinx_drm {\n\t\tcompatible = \"xlnx,drm\";\n\t\tstatus = \"disabled\";\n\t\txlnx,encoder-slave = <&xlnx_dp>;\n\t\txlnx,connector-type = \"DisplayPort\";\n\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\tplanes {\n\t\t\txlnx,pixel-format = \"rgb565\";\n\t\t\tplane0 {\n\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t\tdma-names = \"dma0\";\n\t\t\t};\n\t\t\tplane1 {\n\t\t\t\tdmas = <&xlnx_dpdma 0>,\n\t\t\t\t <&xlnx_dpdma 1>,\n\t\t\t\t <&xlnx_dpdma 2>;\n\t\t\t\tdma-names = \"dma0\", \"dma1\", \"dma2\";\n\t\t\t};\n\t\t};\n\t};\n\n\tamba_apu: amba_apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\", \"gpu_pp0\", \"gpu_pp1\";\n\t\t\tpower-domains = <&pd_gpu>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&pd_nand>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&pd_eth0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&pd_eth1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&pd_eth2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&pd_eth3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tpower-domains = <&pd_gpio>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\",\"dummy\",\"intx\", \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpower-domains = <&pd_pcie>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&pd_qspi>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tserdes: zynqmp_phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>,\n\t\t\t <0x0 0xff5e0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\", \"lpd\";\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\tresets = <&rst 16>, <&rst 59>, <&rst 60>,\n\t\t\t\t <&rst 61>, <&rst 62>, <&rst 63>,\n\t\t\t\t <&rst 64>, <&rst 3>, <&rst 29>,\n\t\t\t\t <&rst 30>, <&rst 31>, <&rst 32>;\n\t\t\treset-names = \"sata_rst\", \"usb0_crst\", \"usb1_crst\",\n\t\t\t\t \"usb0_hibrst\", \"usb1_hibrst\", \"usb0_apbrst\",\n\t\t\t\t \"usb1_apbrst\", \"dp_rst\", \"gem0_rst\",\n\t\t\t\t \"gem1_rst\", \"gem2_rst\", \"gem3_rst\";\n\t\t\tlane0: lane0 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane1: lane1 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane2: lane2 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane3: lane3 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&pd_sata>;\n\t\t\t#stream-id-cells = <4>;\n\t\t\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;\n\t\t};\n\n\t\tsdhci0: sdhci@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&pd_sd0>;\n\t\t};\n\n\t\tsdhci1: sdhci@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&pd_sd1>;\n\t\t};\n\n\t\tpinctrl0: pinctrl@ff180000 {\n\t\t\tcompatible = \"xlnx,pinctrl-zynqmp\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff180000 0x0 0x1000>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart1>;\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&pd_usb0>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb1@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&pd_usb1>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges;\n\n\t\t\tams_ps: ams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50800 0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50c00 0x0 0x400>;\n\t\t\t};\n\t\t};\n\n\t\txlnx_dp: dp@fd4a0000 {\n\t\t\tcompatible = \"xlnx,v-dp\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"aclk\", \"aud_clk\";\n\t\t\tpower-domains = <&pd_dp>;\n\t\t\txlnx,dp-version = \"v1.2\";\n\t\t\txlnx,max-lanes = <2>;\n\t\t\txlnx,max-link-rate = <540000>;\n\t\t\txlnx,max-bpc = <16>;\n\t\t\txlnx,enable-ycrcb;\n\t\t\txlnx,colormetry = \"rgb\";\n\t\t\txlnx,bpc = <8>;\n\t\t\txlnx,audio-chan = <2>;\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t\txlnx,max-pclock-frequency = <300000>;\n\t\t};\n\n\t\txlnx_dp_sub: dp_sub@fd4aa000 {\n\t\t\tcompatible = \"xlnx,dp-sub\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"blend\", \"av_buf\", \"aud\";\n\t\t\txlnx,output-fmt = \"rgb\";\n\t\t\txlnx,vid-fmt = \"yuyv\";\n\t\t\txlnx,gfx-fmt = \"rgb565\";\n\t\t\tpower-domains = <&pd_dp>;\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&pd_dp>;\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zc1232-reva.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane0 1 0 0 125000000>, <&lane1 1 1 1 125000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zc1254-reva.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zc1275-reva.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revA\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 0>;\n\tsda-gpios = <&gpio 37 0>;\n\n\teeprom@55 {\n\t\tcompatible = \"at,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 3 150000000>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n\n\n&xlnx_dp_sub {\n\txlnx,vid-clk-pl;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_0_cd_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_0_wp_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zc1751-dc2.dtsi", "content": "/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 0>;\n\tsda-gpios = <&gpio 7 0>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: spi0_flash0@0 {\n\t\tcompatible = \"m25p80\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tspi0_flash0@0 {\n\t\t\tlabel = \"spi0_flash0\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: spi1_flash0@0 {\n\t\tcompatible = \"mtd_dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tspi1_flash0@0 {\n\t\t\tlabel = \"spi1_flash0\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_0_ce_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_0_ce_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_0_rb_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_0_rb_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_0_dqs_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_0_dqs_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_0_ss0_grp\", \"spi0_0_ss1_grp\",\n\t\t\t\t\t\t\t\"spi0_0_ss2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_0_ss0_grp\", \"spi0_0_ss1_grp\",\n\t\t\t\t\t\t\t\"spi0_0_ss2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_3_ss0_grp\", \"spi1_3_ss1_grp\",\n\t\t\t\t\t\t\t\"spi1_3_ss2_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_3_ss0_grp\", \"spi1_3_ss1_grp\",\n\t\t\t\t\t\t\t\"spi1_3_ss2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t\tsw13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@52 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <52>;\n\t\t\t};\n\t\t\thwmon@53 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <53>;\n\t\t\t};\n\t\t\thwmon@54 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zcu100-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2cswitch@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio_bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zcu100-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2cswitch@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zcu100-revc.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2cswitch@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 1>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board_sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth_mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board_name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board_revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zcu104-reva.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: 8t49n287@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FIXME Npt detected */\n\t\t\ttca6416_u97: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 { /* i2c mw 74 0 10 */ /* FMC_LPC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 { /* i2c mw 74 0 14 */ /* DDR4_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* i2c mw 74 0 11 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>; /* FIXME */\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_0_cd_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_0_wp_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/zynq/zynq-7000.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: sdhci@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: sdhci@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp-clk-ccf.dtsi", "content": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 71>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 72>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 73>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clkc 74>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tclkc: clkc {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clkc\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\", \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t\tclock-output-names = \"iopll\", \"rpll\", \"apll\", \"dpll\",\n\t\t\t\t\"vpll\", \"iopll_to_fpd\", \"rpll_to_fpd\",\n\t\t\t\t\"apll_to_lpd\", \"dpll_to_lpd\", \"vpll_to_lpd\",\n\t\t\t\t\"acpu\", \"acpu_half\", \"dbf_fpd\", \"dbf_lpd\",\n\t\t\t\t\"dbg_trace\", \"dbg_tstmp\", \"dp_video_ref\",\n\t\t\t\t\"dp_audio_ref\", \"dp_stc_ref\", \"gdma_ref\",\n\t\t\t\t\"dpdma_ref\", \"ddr_ref\", \"sata_ref\", \"pcie_ref\",\n\t\t\t\t\"gpu_ref\", \"gpu_pp0_ref\", \"gpu_pp1_ref\",\n\t\t\t\t\"topsw_main\", \"topsw_lsbus\", \"gtgref0_ref\",\n\t\t\t\t\"lpd_switch\", \"lpd_lsbus\", \"usb0_bus_ref\",\n\t\t\t\t\"usb1_bus_ref\", \"usb3_dual_ref\", \"usb0\",\n\t\t\t\t\"usb1\", \"cpu_r5\", \"cpu_r5_core\", \"csu_spb\",\n\t\t\t\t\"csu_pll\", \"pcap\", \"iou_switch\", \"gem_tsu_ref\",\n\t\t\t\t\"gem_tsu\", \"gem0_ref\", \"gem1_ref\", \"gem2_ref\",\n\t\t\t\t\"gem3_ref\", \"gem0_tx\", \"gem1_tx\", \"gem2_tx\",\n\t\t\t\t\"gem3_tx\", \"qspi_ref\", \"sdio0_ref\", \"sdio1_ref\",\n\t\t\t\t\"uart0_ref\", \"uart1_ref\", \"spi0_ref\",\n\t\t\t\t\"spi1_ref\", \"nand_ref\", \"i2c0_ref\", \"i2c1_ref\",\n\t\t\t\t\"can0_ref\", \"can1_ref\", \"can0\", \"can1\",\n\t\t\t\t\"dll_ref\", \"adma_ref\", \"timestamp_ref\",\n\t\t\t\t\"ams_ref\", \"pl0\", \"pl1\", \"pl2\", \"pl3\", \"wdt\";\n\t};\n\n\tdp_aclk: dp_aclk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clkc 63>, <&clkc 31>;\n};\n\n&can1 {\n\tclocks = <&clkc 64>, <&clkc 31>;\n};\n\n&cpu0 {\n\tclocks = <&clkc 10>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clkc 19>, <&clkc 31>;\n};\n\n&gpu {\n\tclocks = <&clkc 24>, <&clkc 25>, <&clkc 26>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clkc 68>, <&clkc 31>;\n};\n\n&nand0 {\n\tclocks = <&clkc 60>, <&clkc 31>;\n};\n\n&gem0 {\n\tclocks = <&clkc 45>, <&clkc 45>, <&clkc 49>;\n\tclock-names = \"pclk\", \"tx_clk\", \"hclk\";\n};\n\n&gem1 {\n\tclocks = <&clkc 46>, <&clkc 46>, <&clkc 50>;\n\tclock-names = \"pclk\", \"tx_clk\", \"hclk\";\n};\n\n&gem2 {\n\tclocks = <&clkc 47>, <&clkc 47>, <&clkc 51>;\n\tclock-names = \"pclk\", \"tx_clk\", \"hclk\";\n};\n\n&gem3 {\n\tclocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n};\n\n&gpio {\n\tclocks = <&clkc 31>;\n};\n\n&i2c0 {\n\tclocks = <&clkc 61>;\n};\n\n&i2c1 {\n\tclocks = <&clkc 62>;\n};\n\n&pcie {\n\tclocks = <&clkc 23>;\n};\n\n&qspi {\n\tclocks = <&clkc 53>, <&clkc 31>;\n};\n\n&sata {\n\tclocks = <&clkc 22>;\n};\n\n&sdhci0 {\n\tclocks = <&clkc 54>, <&clkc 31>;\n};\n\n&sdhci1 {\n\tclocks = <&clkc 55>, <&clkc 31>;\n};\n\n&spi0 {\n\tclocks = <&clkc 58>, <&clkc 31>;\n};\n\n&spi1 {\n\tclocks = <&clkc 59>, <&clkc 31>;\n};\n\n&uart0 {\n\tclocks = <&clkc 56>, <&clkc 31>;\n};\n\n&uart1 {\n\tclocks = <&clkc 57>, <&clkc 31>;\n};\n\n&usb0 {\n\tclocks = <&clkc 32>, <&clkc 34>;\n};\n\n&usb1 {\n\tclocks = <&clkc 33>, <&clkc 34>;\n};\n\n&watchdog0 {\n\tclocks = <&clkc 75>;\n};\n\n&xilinx_ams {\n\tclocks = <&clkc 70>;\n};\n\n&xilinx_drm {\n\tclocks = <&clkc 16>;\n};\n\n&xlnx_dp {\n\tclocks = <&dp_aclk>, <&clkc 17>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&clkc 20>;\n};\n\n&xlnx_dp_snd_codec0 {\n\tclocks = <&clkc 17>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp-clk.dtsi", "content": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n&amba {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm_clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&nand0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&qspi {\n\tclocks = <&clk300 &clk300>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&watchdog0 {\n\tclocks = <&clk250>;\n};\n\n&xilinx_drm {\n\tclocks = <&drm_clock>;\n};\n\n&xlnx_dp {\n\tclocks = <&dp_aclk>, <&dp_aud_clk>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&dpdma_clk>;\n};\n\n&xlnx_dp_snd_codec0 {\n\tclocks = <&dp_aud_clk>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"arm,psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tpower-domains {\n\t\tcompatible = \"xlnx,zynqmp-genpd\";\n\n\t\tpd_usb0: pd-usb0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x16>;\n\t\t};\n\n\t\tpd_usb1: pd-usb1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x17>;\n\t\t};\n\n\t\tpd_sata: pd-sata {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1c>;\n\t\t};\n\n\t\tpd_spi0: pd-spi0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x23>;\n\t\t};\n\n\t\tpd_spi1: pd-spi1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x24>;\n\t\t};\n\n\t\tpd_uart0: pd-uart0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x21>;\n\t\t};\n\n\t\tpd_uart1: pd-uart1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x22>;\n\t\t};\n\n\t\tpd_eth0: pd-eth0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1d>;\n\t\t};\n\n\t\tpd_eth1: pd-eth1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1e>;\n\t\t};\n\n\t\tpd_eth2: pd-eth2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1f>;\n\t\t};\n\n\t\tpd_eth3: pd-eth3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x20>;\n\t\t};\n\n\t\tpd_i2c0: pd-i2c0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x25>;\n\t\t};\n\n\t\tpd_i2c1: pd-i2c1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x26>;\n\t\t};\n\n\t\tpd_dp: pd-dp {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x29>;\n\t\t};\n\n\t\tpd_gdma: pd-gdma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2a>;\n\t\t};\n\n\t\tpd_adma: pd-adma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2b>;\n\t\t};\n\n\t\tpd_ttc0: pd-ttc0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x18>;\n\t\t};\n\n\t\tpd_ttc1: pd-ttc1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x19>;\n\t\t};\n\n\t\tpd_ttc2: pd-ttc2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1a>;\n\t\t};\n\n\t\tpd_ttc3: pd-ttc3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1b>;\n\t\t};\n\n\t\tpd_sd0: pd-sd0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x27>;\n\t\t};\n\n\t\tpd_sd1: pd-sd1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x28>;\n\t\t};\n\n\t\tpd_nand: pd-nand {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2c>;\n\t\t};\n\n\t\tpd_qspi: pd-qspi {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2d>;\n\t\t};\n\n\t\tpd_gpio: pd-gpio {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2e>;\n\t\t};\n\n\t\tpd_can0: pd-can0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2f>;\n\t\t};\n\n\t\tpd_can1: pd-can1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x30>;\n\t\t};\n\n\t\tpd_pcie: pd-pcie {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3b>;\n\t\t};\n\n\t\tpd_gpu: pd-gpu {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3a 0x14 0x15>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tpmufw: firmware {\n\t\tcompatible = \"xlnx,zynqmp-pm\";\n\t\tmethod = \"smc\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tnvmem_firmware {\n\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsoc_revision: soc_revision@0 {\n\t\t\treg = <0x0 0x4>;\n\t\t};\n\t};\n\n\tpcap: pcap {\n\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t};\n\n\trst: reset-controller {\n\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\txlnx_rsa: zynqmp_rsa {\n\t\tcompatible = \"xlnx,zynqmp-rsa\";\n\t};\n\n\txlnx_keccak_384: sha384 {\n\t\tcompatible = \"xlnx,zynqmp-keccak-384\";\n\t};\n\n\txlnx_dp_snd_card: dp_snd_card {\n\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\tstatus = \"disabled\";\n\t\txlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;\n\t\txlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;\n\t};\n\n\txlnx_dp_snd_codec0: dp_snd_codec0 {\n\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\tstatus = \"disabled\";\n\t\tclock-names = \"aud_clk\";\n\t};\n\n\txlnx_dp_snd_pcm0: dp_snd_pcm0 {\n\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\tstatus = \"disabled\";\n\t\tdmas = <&xlnx_dpdma 4>;\n\t\tdma-names = \"tx\";\n\t};\n\n\txlnx_dp_snd_pcm1: dp_snd_pcm1 {\n\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\tstatus = \"disabled\";\n\t\tdmas = <&xlnx_dpdma 5>;\n\t\tdma-names = \"tx\";\n\t};\n\n\txilinx_drm: xilinx_drm {\n\t\tcompatible = \"xlnx,drm\";\n\t\tstatus = \"disabled\";\n\t\txlnx,encoder-slave = <&xlnx_dp>;\n\t\txlnx,connector-type = \"DisplayPort\";\n\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\tplanes {\n\t\t\txlnx,pixel-format = \"rgb565\";\n\t\t\tplane0 {\n\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t\tdma-names = \"dma0\";\n\t\t\t};\n\t\t\tplane1 {\n\t\t\t\tdmas = <&xlnx_dpdma 0>,\n\t\t\t\t <&xlnx_dpdma 1>,\n\t\t\t\t <&xlnx_dpdma 2>;\n\t\t\t\tdma-names = \"dma0\", \"dma1\", \"dma2\";\n\t\t\t};\n\t\t};\n\t};\n\n\tamba_apu: amba_apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\", \"gpu_pp0\", \"gpu_pp1\";\n\t\t\tpower-domains = <&pd_gpu>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&pd_nand>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&pd_eth0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&pd_eth1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&pd_eth2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&pd_eth3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tpower-domains = <&pd_gpio>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\",\"dummy\",\"intx\", \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpower-domains = <&pd_pcie>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&pd_qspi>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tserdes: zynqmp_phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>,\n\t\t\t <0x0 0xff5e0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\", \"lpd\";\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\tresets = <&rst 16>, <&rst 59>, <&rst 60>,\n\t\t\t\t <&rst 61>, <&rst 62>, <&rst 63>,\n\t\t\t\t <&rst 64>, <&rst 3>, <&rst 29>,\n\t\t\t\t <&rst 30>, <&rst 31>, <&rst 32>;\n\t\t\treset-names = \"sata_rst\", \"usb0_crst\", \"usb1_crst\",\n\t\t\t\t \"usb0_hibrst\", \"usb1_hibrst\", \"usb0_apbrst\",\n\t\t\t\t \"usb1_apbrst\", \"dp_rst\", \"gem0_rst\",\n\t\t\t\t \"gem1_rst\", \"gem2_rst\", \"gem3_rst\";\n\t\t\tlane0: lane0 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane1: lane1 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane2: lane2 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane3: lane3 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&pd_sata>;\n\t\t\t#stream-id-cells = <4>;\n\t\t\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;\n\t\t};\n\n\t\tsdhci0: sdhci@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&pd_sd0>;\n\t\t};\n\n\t\tsdhci1: sdhci@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&pd_sd1>;\n\t\t};\n\n\t\tpinctrl0: pinctrl@ff180000 {\n\t\t\tcompatible = \"xlnx,pinctrl-zynqmp\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff180000 0x0 0x1000>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart1>;\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&pd_usb0>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb1@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&pd_usb1>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges;\n\n\t\t\tams_ps: ams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50800 0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50c00 0x0 0x400>;\n\t\t\t};\n\t\t};\n\n\t\txlnx_dp: dp@fd4a0000 {\n\t\t\tcompatible = \"xlnx,v-dp\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"aclk\", \"aud_clk\";\n\t\t\tpower-domains = <&pd_dp>;\n\t\t\txlnx,dp-version = \"v1.2\";\n\t\t\txlnx,max-lanes = <2>;\n\t\t\txlnx,max-link-rate = <540000>;\n\t\t\txlnx,max-bpc = <16>;\n\t\t\txlnx,enable-ycrcb;\n\t\t\txlnx,colormetry = \"rgb\";\n\t\t\txlnx,bpc = <8>;\n\t\t\txlnx,audio-chan = <2>;\n\t\t\txlnx,dp-sub = <&xlnx_dp_sub>;\n\t\t\txlnx,max-pclock-frequency = <300000>;\n\t\t};\n\n\t\txlnx_dp_sub: dp_sub@fd4aa000 {\n\t\t\tcompatible = \"xlnx,dp-sub\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"blend\", \"av_buf\", \"aud\";\n\t\t\txlnx,output-fmt = \"rgb\";\n\t\t\txlnx,vid-fmt = \"yuyv\";\n\t\t\txlnx,gfx-fmt = \"rgb565\";\n\t\t\tpower-domains = <&pd_dp>;\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&pd_dp>;\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zc1232-reva.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane0 1 0 0 125000000>, <&lane1 1 1 1 125000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zc1254-reva.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zc1275-reva.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revA\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zc1275-revb.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZC1275 RevB\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevB\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revB\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 0>;\n\tsda-gpios = <&gpio 37 0>;\n\n\teeprom@55 {\n\t\tcompatible = \"at,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 3 150000000>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 0>;\n\tsda-gpios = <&gpio 7 0>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: spi0_flash0@0 {\n\t\tcompatible = \"m25p80\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tspi0_flash0@0 {\n\t\t\tlabel = \"spi0_flash0\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: spi1_flash0@0 {\n\t\tcompatible = \"mtd_dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tspi1_flash0@0 {\n\t\t\tlabel = \"spi1_flash0\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t\tsw13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@52 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <52>;\n\t\t\t};\n\t\t\thwmon@53 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <53>;\n\t\t\t};\n\t\t\thwmon@54 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zcu100-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2cswitch@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio_bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zcu100-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2cswitch@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zcu100-revc.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2cswitch@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 1>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 0>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board_sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth_mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board_name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board_revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zcu104-reva.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: 8t49n287@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FIXME Npt detected */\n\t\t\ttca6416_u97: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 { /* i2c mw 74 0 10 */ /* FMC_LPC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 { /* i2c mw 74 0 14 */ /* DDR4_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zcu104-revc.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revC\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\ttca6416_u97: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - IRPS5401_ALERT_B\n\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t * 2 - MAX6643_OT_B\n\t\t * 3 - MAX6643_FANFAIL_B\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t * 4, 10 - 17 - not connected\n\t\t */\n\t};\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: 8t49n287@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\n\t\ti2c@5 { /* i2c mw 74 0 10 */ /* FMC_LPC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 { /* i2c mw 74 0 14 */ /* DDR4_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\txlnx,mio_bank = <1>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2cswitch@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* i2c mw 74 0 11 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>; /* FIXME */\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zcu111-reva.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2cswitch@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps54012@44 { /* IRPS5401 - u55 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps54012@45 { /* IRPS5401 - u57 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\ti2cswitch@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u46 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 { /* SI5328 - u48 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* i2c mw 74 0 11 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 { /* i2c mw 74 0 11 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection FIXME */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 3 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/zynq/zynq-7000.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: sdhci@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: sdhci@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/zynqmp/zynqmp-clk-ccf.dtsi", "content": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * SPDX-License-Identifier: GPL-2.0+\n */\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clk 71>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clk 72>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clk 73>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clk 74>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tclk: clk {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\", \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t};\n\n\tdp_aclk: dp_aclk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk 63>, <&clk 31>;\n};\n\n&can1 {\n\tclocks = <&clk 64>, <&clk 31>;\n};\n\n&cpu0 {\n\tclocks = <&clk 10>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&gpu {\n\tclocks = <&clk 24>, <&clk 25>, <&clk 26>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&nand0 {\n\tclocks = <&clk 60>, <&clk 31>;\n};\n\n&gem0 {\n\tclocks = <&clk 31>, <&clk 49>, <&clk 45>, <&clk 49>, <&clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem1 {\n\tclocks = <&clk 31>, <&clk 50>, <&clk 46>, <&clk 50>, <&clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem2 {\n\tclocks = <&clk 31>, <&clk 51>, <&clk 47>, <&clk 51>, <&clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem3 {\n\tclocks = <&clk 31>, <&clk 52>, <&clk 48>, <&clk 52>, <&clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gpio {\n\tclocks = <&clk 31>;\n};\n\n&i2c0 {\n\tclocks = <&clk 61>;\n};\n\n&i2c1 {\n\tclocks = <&clk 62>;\n};\n\n&perf_monitor_ocm {\n\tclocks = <&clk 31>;\n};\n\n&pcie {\n\tclocks = <&clk 23>;\n};\n\n&qspi {\n\tclocks = <&clk 53>, <&clk 31>;\n};\n\n&sata {\n\tclocks = <&clk 22>;\n};\n\n&sdhci0 {\n\tclocks = <&clk 54>, <&clk 31>;\n};\n\n&sdhci1 {\n\tclocks = <&clk 55>, <&clk 31>;\n};\n\n&spi0 {\n\tclocks = <&clk 58>, <&clk 31>;\n};\n\n&spi1 {\n\tclocks = <&clk 59>, <&clk 31>;\n};\n\n&uart0 {\n\tclocks = <&clk 56>, <&clk 31>;\n};\n\n&uart1 {\n\tclocks = <&clk 57>, <&clk 31>;\n};\n\n&usb0 {\n\tclocks = <&clk 32>, <&clk 34>;\n};\n\n&usb1 {\n\tclocks = <&clk 33>, <&clk 34>;\n};\n\n&watchdog0 {\n\tclocks = <&clk 75>;\n};\n\n&xilinx_ams {\n\tclocks = <&clk 70>;\n};\n\n&zynqmp_dpsub {\n\tclocks = <&dp_aclk>, <&clk 17>, <&clk 16>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&clk 20>;\n};\n\n&zynqmp_dp_snd_codec0 {\n\tclocks = <&clk 17>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.1/zynqmp/zynqmp.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"arm,psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tpower-domains {\n\t\tcompatible = \"xlnx,zynqmp-genpd\";\n\n\t\tpd_usb0: pd-usb0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x16>;\n\t\t};\n\n\t\tpd_usb1: pd-usb1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x17>;\n\t\t};\n\n\t\tpd_sata: pd-sata {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1c>;\n\t\t};\n\n\t\tpd_spi0: pd-spi0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x23>;\n\t\t};\n\n\t\tpd_spi1: pd-spi1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x24>;\n\t\t};\n\n\t\tpd_uart0: pd-uart0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x21>;\n\t\t};\n\n\t\tpd_uart1: pd-uart1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x22>;\n\t\t};\n\n\t\tpd_eth0: pd-eth0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1d>;\n\t\t};\n\n\t\tpd_eth1: pd-eth1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1e>;\n\t\t};\n\n\t\tpd_eth2: pd-eth2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1f>;\n\t\t};\n\n\t\tpd_eth3: pd-eth3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x20>;\n\t\t};\n\n\t\tpd_i2c0: pd-i2c0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x25>;\n\t\t};\n\n\t\tpd_i2c1: pd-i2c1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x26>;\n\t\t};\n\n\t\tpd_dp: pd-dp {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x29>;\n\t\t};\n\n\t\tpd_gdma: pd-gdma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2a>;\n\t\t};\n\n\t\tpd_adma: pd-adma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2b>;\n\t\t};\n\n\t\tpd_ttc0: pd-ttc0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x18>;\n\t\t};\n\n\t\tpd_ttc1: pd-ttc1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x19>;\n\t\t};\n\n\t\tpd_ttc2: pd-ttc2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1a>;\n\t\t};\n\n\t\tpd_ttc3: pd-ttc3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1b>;\n\t\t};\n\n\t\tpd_sd0: pd-sd0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x27>;\n\t\t};\n\n\t\tpd_sd1: pd-sd1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x28>;\n\t\t};\n\n\t\tpd_nand: pd-nand {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2c>;\n\t\t};\n\n\t\tpd_qspi: pd-qspi {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2d>;\n\t\t};\n\n\t\tpd_gpio: pd-gpio {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2e>;\n\t\t};\n\n\t\tpd_can0: pd-can0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2f>;\n\t\t};\n\n\t\tpd_can1: pd-can1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x30>;\n\t\t};\n\n\t\tpd_pcie: pd-pcie {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3b>;\n\t\t};\n\n\t\tpd_gpu: pd-gpu {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3a 0x14 0x15>;\n\t\t};\n\t};\n\n\t/* PMU1<->APU IPI mailbox controller */\n\tipi_mailbox_pmu1: mailbox@ff990400 {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\treg = <0x0 0xff9905c0 0x0 0x20>,\n\t\t <0x0 0xff9905e0 0x0 0x20>,\n\t\t <0x0 0xff990e80 0x0 0x20>,\n\t\t <0x0 0xff990ea0 0x0 0x20>;\n\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t#mbox-cells = <1>;\n\t\txlnx,ipi-ids = <0 4>;\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tzynqmp_firmware: zynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tzynqmp_power: zynqmp-power {\n\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\tmbox-names = \"tx\", \"rx\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tnvmem_firmware {\n\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsoc_revision: soc_revision@0 {\n\t\t\treg = <0x0 0x4>;\n\t\t};\n\t};\n\n\tpcap: pcap {\n\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t};\n\n\trst: reset-controller {\n\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\txlnx_rsa: zynqmp_rsa {\n\t\tcompatible = \"xlnx,zynqmp-rsa\";\n\t};\n\n\txlnx_keccak_384: sha384 {\n\t\tcompatible = \"xlnx,zynqmp-keccak-384\";\n\t};\n\n\tamba_apu: amba_apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\", \"gpu_pp0\", \"gpu_pp1\";\n\t\t\tpower-domains = <&pd_gpu>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&pd_nand>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&pd_eth0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&pd_eth1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&pd_eth2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&pd_eth3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tpower-domains = <&pd_gpio>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tperf_monitor_ocm: perf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa00000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <4>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpower-domains = <&pd_pcie>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&pd_qspi>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tserdes: zynqmp_phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\";\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\tresets = <&rst 16>, <&rst 59>, <&rst 60>,\n\t\t\t\t <&rst 61>, <&rst 62>, <&rst 63>,\n\t\t\t\t <&rst 64>, <&rst 3>, <&rst 29>,\n\t\t\t\t <&rst 30>, <&rst 31>, <&rst 32>;\n\t\t\treset-names = \"sata_rst\", \"usb0_crst\", \"usb1_crst\",\n\t\t\t\t \"usb0_hibrst\", \"usb1_hibrst\", \"usb0_apbrst\",\n\t\t\t\t \"usb1_apbrst\", \"dp_rst\", \"gem0_rst\",\n\t\t\t\t \"gem1_rst\", \"gem2_rst\", \"gem3_rst\";\n\t\t\tlane0: lane0 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane1: lane1 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane2: lane2 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane3: lane3 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&pd_sata>;\n\t\t\t#stream-id-cells = <4>;\n\t\t\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;\n\t\t};\n\n\t\tsdhci0: sdhci@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&pd_sd0>;\n\t\t};\n\n\t\tsdhci1: sdhci@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&pd_sd1>;\n\t\t};\n\n\t\tpinctrl0: pinctrl@ff180000 {\n\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff180000 0x0 0x1000>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart1>;\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&pd_usb0>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>, <0 75 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t\t/* snps,enable-hibernation; */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb1@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&pd_usb1>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>, <0 76 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges;\n\n\t\t\tams_ps: ams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50800 0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50c00 0x0 0x400>;\n\t\t\t};\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&pd_dp>;\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\n\t\tzynqmp_dpsub: zynqmp-display@fd4a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"dp\", \"blend\", \"av_buf\", \"aud\";\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"dp_apb_clk\", \"dp_aud_clk\", \"dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <&pd_dp>;\n\n\t\t\tvid-layer {\n\t\t\t\tdma-names = \"vid0\", \"vid1\", \"vid2\";\n\t\t\t\tdmas = <&xlnx_dpdma 0>,\n\t\t\t\t <&xlnx_dpdma 1>,\n\t\t\t\t <&xlnx_dpdma 2>;\n\t\t\t};\n\n\t\t\tgfx-layer {\n\t\t\t\tdma-names = \"gfx0\";\n\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t};\n\n\t\t\t/* dummy node to to indicate there's no child i2c device */\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&xlnx_dpdma 4>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&xlnx_dpdma 5>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card0: zynqmp_dp_snd_card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,\n\t\t\t\t\t\t <&zynqmp_dp_snd_pcm1>;\n\t\t\t\txlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane0 1 0 0 125000000>, <&lane1 1 1 1 125000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zc1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revA\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zc1275-revb.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZC1275 RevB\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevB\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revB\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 0>;\n\tsda-gpios = <&gpio 37 0>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 3 150000000>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 0>;\n\tsda-gpios = <&gpio 7 0>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: flash0@0 {\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: flash0@0 {\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t\tsw13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@52 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <52>;\n\t\t\t};\n\t\t\thwmon@53 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <53>;\n\t\t\t};\n\t\t\thwmon@54 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zcu100-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio_bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zcu100-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 1>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 0>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 {\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 {\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 {\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 {\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 {\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@20 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zcu104-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revC\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - IRPS5401_ALERT_B\n\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t * 2 - MAX6643_OT_B\n\t\t * 3 - MAX6643_FANFAIL_B\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t * 4, 10 - 17 - not connected\n\t\t */\n\t};\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\txlnx,mio_bank = <1>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps54012@44 { /* IRPS5401 - u55 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps54012@45 { /* IRPS5401 - u57 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 { /* SI5328 - u48 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection FIXME */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 3 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/zynq/zynq-7000.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: sdhci@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: sdhci@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/zynqmp/zynqmp-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clk 71>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clk 72>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clk 73>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clk 74>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tclk: clk {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\", \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t};\n\n\tdp_aclk: dp_aclk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk 63>, <&clk 31>;\n};\n\n&can1 {\n\tclocks = <&clk 64>, <&clk 31>;\n};\n\n&cpu0 {\n\tclocks = <&clk 10>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&gpu {\n\tclocks = <&clk 24>, <&clk 25>, <&clk 26>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&nand0 {\n\tclocks = <&clk 60>, <&clk 31>;\n};\n\n&gem0 {\n\tclocks = <&clk 31>, <&clk 49>, <&clk 45>, <&clk 49>, <&clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem1 {\n\tclocks = <&clk 31>, <&clk 50>, <&clk 46>, <&clk 50>, <&clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem2 {\n\tclocks = <&clk 31>, <&clk 51>, <&clk 47>, <&clk 51>, <&clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem3 {\n\tclocks = <&clk 31>, <&clk 52>, <&clk 48>, <&clk 52>, <&clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gpio {\n\tclocks = <&clk 31>;\n};\n\n&i2c0 {\n\tclocks = <&clk 61>;\n};\n\n&i2c1 {\n\tclocks = <&clk 62>;\n};\n\n&perf_monitor_ocm {\n\tclocks = <&clk 31>;\n};\n\n&pcie {\n\tclocks = <&clk 23>;\n};\n\n&qspi {\n\tclocks = <&clk 53>, <&clk 31>;\n};\n\n&sata {\n\tclocks = <&clk 22>;\n};\n\n&sdhci0 {\n\tclocks = <&clk 54>, <&clk 31>;\n};\n\n&sdhci1 {\n\tclocks = <&clk 55>, <&clk 31>;\n};\n\n&spi0 {\n\tclocks = <&clk 58>, <&clk 31>;\n};\n\n&spi1 {\n\tclocks = <&clk 59>, <&clk 31>;\n};\n\n&ttc0 {\n\tclocks = <&clk 31>;\n};\n\n&ttc1 {\n\tclocks = <&clk 31>;\n};\n\n&ttc2 {\n\tclocks = <&clk 31>;\n};\n\n&ttc3 {\n\tclocks = <&clk 31>;\n};\n\n&uart0 {\n\tclocks = <&clk 56>, <&clk 31>;\n};\n\n&uart1 {\n\tclocks = <&clk 57>, <&clk 31>;\n};\n\n&usb0 {\n\tclocks = <&clk 32>, <&clk 34>;\n};\n\n&usb1 {\n\tclocks = <&clk 33>, <&clk 34>;\n};\n\n&watchdog0 {\n\tclocks = <&clk 75>;\n};\n\n&xilinx_ams {\n\tclocks = <&clk 70>;\n};\n\n&zynqmp_dpsub {\n\tclocks = <&dp_aclk>, <&clk 17>, <&clk 16>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&clk 20>;\n};\n\n&zynqmp_dp_snd_codec0 {\n\tclocks = <&clk 17>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.2/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"arm,psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tpower-domains {\n\t\tcompatible = \"xlnx,zynqmp-genpd\";\n\n\t\tpd_usb0: pd-usb0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x16>;\n\t\t};\n\n\t\tpd_usb1: pd-usb1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x17>;\n\t\t};\n\n\t\tpd_sata: pd-sata {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1c>;\n\t\t};\n\n\t\tpd_spi0: pd-spi0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x23>;\n\t\t};\n\n\t\tpd_spi1: pd-spi1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x24>;\n\t\t};\n\n\t\tpd_uart0: pd-uart0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x21>;\n\t\t};\n\n\t\tpd_uart1: pd-uart1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x22>;\n\t\t};\n\n\t\tpd_eth0: pd-eth0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1d>;\n\t\t};\n\n\t\tpd_eth1: pd-eth1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1e>;\n\t\t};\n\n\t\tpd_eth2: pd-eth2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1f>;\n\t\t};\n\n\t\tpd_eth3: pd-eth3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x20>;\n\t\t};\n\n\t\tpd_i2c0: pd-i2c0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x25>;\n\t\t};\n\n\t\tpd_i2c1: pd-i2c1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x26>;\n\t\t};\n\n\t\tpd_dp: pd-dp {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x29>;\n\t\t};\n\n\t\tpd_gdma: pd-gdma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2a>;\n\t\t};\n\n\t\tpd_adma: pd-adma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2b>;\n\t\t};\n\n\t\tpd_ttc0: pd-ttc0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x18>;\n\t\t};\n\n\t\tpd_ttc1: pd-ttc1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x19>;\n\t\t};\n\n\t\tpd_ttc2: pd-ttc2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1a>;\n\t\t};\n\n\t\tpd_ttc3: pd-ttc3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1b>;\n\t\t};\n\n\t\tpd_sd0: pd-sd0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x27>;\n\t\t};\n\n\t\tpd_sd1: pd-sd1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x28>;\n\t\t};\n\n\t\tpd_nand: pd-nand {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2c>;\n\t\t};\n\n\t\tpd_qspi: pd-qspi {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2d>;\n\t\t};\n\n\t\tpd_gpio: pd-gpio {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2e>;\n\t\t};\n\n\t\tpd_can0: pd-can0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2f>;\n\t\t};\n\n\t\tpd_can1: pd-can1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x30>;\n\t\t};\n\n\t\tpd_pcie: pd-pcie {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3b>;\n\t\t};\n\n\t\tpd_gpu: pd-gpu {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3a 0x14 0x15>;\n\t\t};\n\t};\n\n\t/* PMU1<->APU IPI mailbox controller */\n\tipi_mailbox_pmu1: mailbox@ff990400 {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\treg = <0x0 0xff9905c0 0x0 0x20>,\n\t\t <0x0 0xff9905e0 0x0 0x20>,\n\t\t <0x0 0xff990e80 0x0 0x20>,\n\t\t <0x0 0xff990ea0 0x0 0x20>;\n\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t#mbox-cells = <1>;\n\t\txlnx,ipi-ids = <0 4>;\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tzynqmp_firmware: zynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tzynqmp_power: zynqmp-power {\n\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\tmbox-names = \"tx\", \"rx\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tnvmem_firmware {\n\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsoc_revision: soc_revision@0 {\n\t\t\treg = <0x0 0x4>;\n\t\t};\n\t};\n\n\tpcap: pcap {\n\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t};\n\n\trst: reset-controller {\n\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\txlnx_rsa: zynqmp_rsa {\n\t\tcompatible = \"xlnx,zynqmp-rsa\";\n\t};\n\n\txlnx_keccak_384: sha384 {\n\t\tcompatible = \"xlnx,zynqmp-keccak-384\";\n\t};\n\n\tamba_apu: amba_apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\", \"gpu_pp0\", \"gpu_pp1\";\n\t\t\tpower-domains = <&pd_gpu>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&pd_nand>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&pd_eth0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&pd_eth1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&pd_eth2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&pd_eth3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tpower-domains = <&pd_gpio>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tperf_monitor_ocm: perf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa00000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <4>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpower-domains = <&pd_pcie>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&pd_qspi>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tserdes: zynqmp_phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\";\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\tresets = <&rst 16>, <&rst 59>, <&rst 60>,\n\t\t\t\t <&rst 61>, <&rst 62>, <&rst 63>,\n\t\t\t\t <&rst 64>, <&rst 3>, <&rst 29>,\n\t\t\t\t <&rst 30>, <&rst 31>, <&rst 32>;\n\t\t\treset-names = \"sata_rst\", \"usb0_crst\", \"usb1_crst\",\n\t\t\t\t \"usb0_hibrst\", \"usb1_hibrst\", \"usb0_apbrst\",\n\t\t\t\t \"usb1_apbrst\", \"dp_rst\", \"gem0_rst\",\n\t\t\t\t \"gem1_rst\", \"gem2_rst\", \"gem3_rst\";\n\t\t\tlane0: lane0 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane1: lane1 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane2: lane2 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane3: lane3 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&pd_sata>;\n\t\t\t#stream-id-cells = <4>;\n\t\t\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;\n\t\t};\n\n\t\tsdhci0: sdhci@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&pd_sd0>;\n\t\t};\n\n\t\tsdhci1: sdhci@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&pd_sd1>;\n\t\t};\n\n\t\tpinctrl0: pinctrl@ff180000 {\n\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff180000 0x0 0x1000>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart1>;\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&pd_usb0>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>, <0 75 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t\t/* snps,enable-hibernation; */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb1@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&pd_usb1>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>, <0 76 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges;\n\n\t\t\tams_ps: ams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50800 0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50c00 0x0 0x400>;\n\t\t\t};\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&pd_dp>;\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\n\t\tzynqmp_dpsub: zynqmp-display@fd4a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"dp\", \"blend\", \"av_buf\", \"aud\";\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"dp_apb_clk\", \"dp_aud_clk\", \"dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <&pd_dp>;\n\n\t\t\tvid-layer {\n\t\t\t\tdma-names = \"vid0\", \"vid1\", \"vid2\";\n\t\t\t\tdmas = <&xlnx_dpdma 0>,\n\t\t\t\t <&xlnx_dpdma 1>,\n\t\t\t\t <&xlnx_dpdma 2>;\n\t\t\t};\n\n\t\t\tgfx-layer {\n\t\t\t\tdma-names = \"gfx0\";\n\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t};\n\n\t\t\t/* dummy node to to indicate there's no child i2c device */\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&xlnx_dpdma 4>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&xlnx_dpdma 5>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card0: zynqmp_dp_snd_card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,\n\t\t\t\t\t\t <&zynqmp_dp_snd_pcm1>;\n\t\t\t\txlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 1>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 0>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2cswitch@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane0 1 0 0 125000000>, <&lane1 1 1 1 125000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zc1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revA\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zc1275-revb.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZC1275 RevB\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevB\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revB\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 0>;\n\tsda-gpios = <&gpio 37 0>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 3 150000000>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 0>;\n\tsda-gpios = <&gpio 7 0>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: flash@0 {\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: flash@0 {\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t\tsw13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@52 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <52>;\n\t\t\t};\n\t\t\thwmon@53 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <53>;\n\t\t\t};\n\t\t\thwmon@54 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&watchdog0 {\n\treset-on-timeout;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zcu100-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio_bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zcu100-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 1>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 0>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@20 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zcu104-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revC\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - IRPS5401_ALERT_B\n\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t * 2 - MAX6643_OT_B\n\t\t * 3 - MAX6643_FANFAIL_B\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t * 4, 10 - 17 - not connected\n\t\t */\n\t};\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tina226@40 { /* u183 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 4, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\txlnx,mio_bank = <1>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 0>;\n\tsda-gpios = <&gpio 15 0>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps54012@44 { /* IRPS5401 - u55 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps54012@45 { /* IRPS5401 - u57 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 0>;\n\tsda-gpios = <&gpio 17 0>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 { /* SI5328 - u48 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection FIXME */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 1 1 3 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 2 26000000>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/zynq/zynq-7000.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"aclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: mmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: mmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/zynqmp/zynqmp-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clk 71>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clk 72>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clk 73>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"disabled\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&clk 74>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tclk: clk {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\", \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t};\n\n\tdp_aclk: dp_aclk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk 63>, <&clk 31>;\n};\n\n&can1 {\n\tclocks = <&clk 64>, <&clk 31>;\n};\n\n&cpu0 {\n\tclocks = <&clk 10>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk 19>, <&clk 31>;\n};\n\n&gpu {\n\tclocks = <&clk 24>, <&clk 25>, <&clk 26>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk 68>, <&clk 31>;\n};\n\n&nand0 {\n\tclocks = <&clk 60>, <&clk 31>;\n};\n\n&gem0 {\n\tclocks = <&clk 31>, <&clk 104>, <&clk 45>, <&clk 49>, <&clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem1 {\n\tclocks = <&clk 31>, <&clk 105>, <&clk 46>, <&clk 50>, <&clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem2 {\n\tclocks = <&clk 31>, <&clk 106>, <&clk 47>, <&clk 51>, <&clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem3 {\n\tclocks = <&clk 31>, <&clk 107>, <&clk 48>, <&clk 52>, <&clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gpio {\n\tclocks = <&clk 31>;\n};\n\n&i2c0 {\n\tclocks = <&clk 61>;\n};\n\n&i2c1 {\n\tclocks = <&clk 62>;\n};\n\n&perf_monitor_ocm {\n\tclocks = <&clk 31>;\n};\n\n&pcie {\n\tclocks = <&clk 23>;\n};\n\n&qspi {\n\tclocks = <&clk 53>, <&clk 31>;\n};\n\n&sata {\n\tclocks = <&clk 22>;\n};\n\n&sdhci0 {\n\tclocks = <&clk 54>, <&clk 31>;\n};\n\n&sdhci1 {\n\tclocks = <&clk 55>, <&clk 31>;\n};\n\n&spi0 {\n\tclocks = <&clk 58>, <&clk 31>;\n};\n\n&spi1 {\n\tclocks = <&clk 59>, <&clk 31>;\n};\n\n&ttc0 {\n\tclocks = <&clk 31>;\n};\n\n&ttc1 {\n\tclocks = <&clk 31>;\n};\n\n&ttc2 {\n\tclocks = <&clk 31>;\n};\n\n&ttc3 {\n\tclocks = <&clk 31>;\n};\n\n&uart0 {\n\tclocks = <&clk 56>, <&clk 31>;\n};\n\n&uart1 {\n\tclocks = <&clk 57>, <&clk 31>;\n};\n\n&usb0 {\n\tclocks = <&clk 32>, <&clk 34>;\n};\n\n&usb1 {\n\tclocks = <&clk 33>, <&clk 34>;\n};\n\n&watchdog0 {\n\tclocks = <&clk 75>;\n};\n\n&lpd_watchdog {\n\tclocks = <&clk 75>;\n};\n\n&xilinx_ams {\n\tclocks = <&clk 70>;\n};\n\n&zynqmp_dpsub {\n\tclocks = <&dp_aclk>, <&clk 17>, <&clk 16>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&clk 20>;\n};\n\n&zynqmp_dp_snd_codec0 {\n\tclocks = <&clk 17>;\n};\n\n&pcap {\n\tclocks = <&clk 41>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2018.3/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"arm,psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tpower-domains {\n\t\tcompatible = \"xlnx,zynqmp-genpd\";\n\n\t\tpd_usb0: pd-usb0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x16>;\n\t\t};\n\n\t\tpd_usb1: pd-usb1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x17>;\n\t\t};\n\n\t\tpd_sata: pd-sata {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1c>;\n\t\t};\n\n\t\tpd_spi0: pd-spi0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x23>;\n\t\t};\n\n\t\tpd_spi1: pd-spi1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x24>;\n\t\t};\n\n\t\tpd_uart0: pd-uart0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x21>;\n\t\t};\n\n\t\tpd_uart1: pd-uart1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x22>;\n\t\t};\n\n\t\tpd_eth0: pd-eth0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1d>;\n\t\t};\n\n\t\tpd_eth1: pd-eth1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1e>;\n\t\t};\n\n\t\tpd_eth2: pd-eth2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1f>;\n\t\t};\n\n\t\tpd_eth3: pd-eth3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x20>;\n\t\t};\n\n\t\tpd_i2c0: pd-i2c0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x25>;\n\t\t};\n\n\t\tpd_i2c1: pd-i2c1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x26>;\n\t\t};\n\n\t\tpd_dp: pd-dp {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x29>;\n\t\t};\n\n\t\tpd_gdma: pd-gdma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2a>;\n\t\t};\n\n\t\tpd_adma: pd-adma {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2b>;\n\t\t};\n\n\t\tpd_ttc0: pd-ttc0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x18>;\n\t\t};\n\n\t\tpd_ttc1: pd-ttc1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x19>;\n\t\t};\n\n\t\tpd_ttc2: pd-ttc2 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1a>;\n\t\t};\n\n\t\tpd_ttc3: pd-ttc3 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x1b>;\n\t\t};\n\n\t\tpd_sd0: pd-sd0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x27>;\n\t\t};\n\n\t\tpd_sd1: pd-sd1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x28>;\n\t\t};\n\n\t\tpd_nand: pd-nand {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2c>;\n\t\t};\n\n\t\tpd_qspi: pd-qspi {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2d>;\n\t\t};\n\n\t\tpd_gpio: pd-gpio {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2e>;\n\t\t};\n\n\t\tpd_can0: pd-can0 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x2f>;\n\t\t};\n\n\t\tpd_can1: pd-can1 {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x30>;\n\t\t};\n\n\t\tpd_pcie: pd-pcie {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3b>;\n\t\t};\n\n\t\tpd_gpu: pd-gpu {\n\t\t\t#power-domain-cells = <0x0>;\n\t\t\tpd-id = <0x3a 0x14 0x15>;\n\t\t};\n\t};\n\n\t/* PMU1<->APU IPI mailbox controller */\n\tipi_mailbox_pmu1: mailbox@ff990400 {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\treg = <0x0 0xff9905c0 0x0 0x20>,\n\t\t <0x0 0xff9905e0 0x0 0x20>,\n\t\t <0x0 0xff990e80 0x0 0x20>,\n\t\t <0x0 0xff990ea0 0x0 0x20>;\n\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t#mbox-cells = <1>;\n\t\txlnx,ipi-ids = <0 4>;\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tzynqmp_firmware: zynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tzynqmp_power: zynqmp-power {\n\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\tmbox-names = \"tx\", \"rx\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tnvmem_firmware {\n\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsoc_revision: soc_revision@0 {\n\t\t\treg = <0x0 0x4>;\n\t\t};\n\t\t/* efuse access */\n\t\tefuse_dna: efuse_dna@c {\n\t\t\treg = <0xc 0xc>;\n\t\t};\n\t\tefuse_usr0: efuse_usr0@20 {\n\t\t\treg = <0x20 0x4>;\n\t\t};\n\t\tefuse_usr1: efuse_usr1@24 {\n\t\t\treg = <0x24 0x4>;\n\t\t};\n\t\tefuse_usr2: efuse_usr2@28 {\n\t\t\treg = <0x28 0x4>;\n\t\t};\n\t\tefuse_usr3: efuse_usr3@2c {\n\t\t\treg = <0x2c 0x4>;\n\t\t};\n\t\tefuse_usr4: efuse_usr4@30 {\n\t\t\treg = <0x30 0x4>;\n\t\t};\n\t\tefuse_usr5: efuse_usr5@34 {\n\t\t\treg = <0x34 0x4>;\n\t\t};\n\t\tefuse_usr6: efuse_usr6@38 {\n\t\t\treg = <0x38 0x4>;\n\t\t};\n\t\tefuse_usr7: efuse_usr7@3c {\n\t\t\treg = <0x3c 0x4>;\n\t\t};\n\t\tefuse_miscusr: efuse_miscusr@40 {\n\t\t\treg = <0x40 0x4>;\n\t\t};\n\t\tefuse_chash: efuse_chash@50 {\n\t\t\treg = <0x50 0x4>;\n\t\t};\n\t\tefuse_pufmisc: efuse_pufmisc@54 {\n\t\t\treg = <0x54 0x4>;\n\t\t};\n\t\tefuse_sec: efuse_sec@58 {\n\t\t\treg = <0x58 0x4>;\n\t\t};\n\t\tefuse_spkid: efuse_spkid@5c {\n\t\t\treg = <0x5c 0x4>;\n\t\t};\n\t\tefuse_ppk0hash: efuse_ppk0hash@a0 {\n\t\t\treg = <0xa0 0x30>;\n\t\t};\n\t\tefuse_ppk1hash: efuse_ppk1hash@d0 {\n\t\t\treg = <0xd0 0x30>;\n\t\t};\n\t};\n\n\tpcap: pcap {\n\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t\tclock-names = \"ref_clk\";\n\t};\n\n\trst: reset-controller {\n\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\txlnx_rsa: zynqmp_rsa {\n\t\tcompatible = \"xlnx,zynqmp-rsa\";\n\t};\n\n\txlnx_keccak_384: sha384 {\n\t\tcompatible = \"xlnx,zynqmp-keccak-384\";\n\t};\n\n\txlnx_aes: zynqmp_aes {\n\t\tcompatible = \"xlnx,zynqmp-aes\";\n\t};\n\n\tamba_apu: amba_apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tsmmu: smmu@fd800000 {\n\t\tcompatible = \"arm,mmu-500\";\n\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t#iommu-cells = <1>;\n\t\tstatus = \"disabled\";\n\t\t#global-interrupts = <1>;\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&pd_can1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&pd_gdma>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\", \"gpu_pp0\", \"gpu_pp1\";\n\t\t\tpower-domains = <&pd_gpu>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&pd_adma>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&pd_nand>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&pd_eth0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&pd_eth1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&pd_eth2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&pd_eth3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tpower-domains = <&pd_gpio>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_i2c1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tperf_monitor_ocm: perf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa00000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <4>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpower-domains = <&pd_pcie>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&pd_qspi>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tserdes: zynqmp_phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\";\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\tresets = <&rst 16>, <&rst 59>, <&rst 60>,\n\t\t\t\t <&rst 61>, <&rst 62>, <&rst 63>,\n\t\t\t\t <&rst 64>, <&rst 3>, <&rst 29>,\n\t\t\t\t <&rst 30>, <&rst 31>, <&rst 32>;\n\t\t\treset-names = \"sata_rst\", \"usb0_crst\", \"usb1_crst\",\n\t\t\t\t \"usb0_hibrst\", \"usb1_hibrst\", \"usb0_apbrst\",\n\t\t\t\t \"usb1_apbrst\", \"dp_rst\", \"gem0_rst\",\n\t\t\t\t \"gem1_rst\", \"gem2_rst\", \"gem3_rst\";\n\t\t\tlane0: lane0 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane1: lane1 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane2: lane2 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane3: lane3 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&pd_sata>;\n\t\t\t#stream-id-cells = <4>;\n\t\t/*\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;*/\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&pd_sd0>;\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&pd_sd1>;\n\t\t};\n\n\t\tpinctrl0: pinctrl@ff180000 {\n\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff180000 0x0 0x1000>;\n\t\t};\n\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&pd_spi1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&pd_ttc3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&pd_uart1>;\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&pd_usb0>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>, <0 75 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t\t/* snps,enable-hibernation; */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb1@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&pd_usb1>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>, <0 76 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <60>;\n\t\t\treset-on-timeout;\n\t\t};\n\n\t\tlpd_watchdog: watchdog@ff150000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 52 1>;\n\t\t\treg = <0x0 0xff150000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges;\n\n\t\t\tams_ps: ams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50800 0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50c00 0x0 0x400>;\n\t\t\t};\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&pd_dp>;\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\n\t\tzynqmp_dpsub: zynqmp-display@fd4a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"dp\", \"blend\", \"av_buf\", \"aud\";\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"dp_apb_clk\", \"dp_aud_clk\", \"dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <&pd_dp>;\n\n\t\t\tvid-layer {\n\t\t\t\tdma-names = \"vid0\", \"vid1\", \"vid2\";\n\t\t\t\tdmas = <&xlnx_dpdma 0>,\n\t\t\t\t <&xlnx_dpdma 1>,\n\t\t\t\t <&xlnx_dpdma 2>;\n\t\t\t};\n\n\t\t\tgfx-layer {\n\t\t\t\tdma-names = \"gfx0\";\n\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t};\n\n\t\t\t/* dummy node to to indicate there's no child i2c device */\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&xlnx_dpdma 4>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&xlnx_dpdma 5>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card0: zynqmp_dp_snd_card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,\n\t\t\t\t\t\t <&zynqmp_dp_snd_pcm1>;\n\t\t\t\txlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/sp701-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze sp701.\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@1 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x3>;\n\t\t\tti,tx-internal-delay = <0x3>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/vcu118-rev2.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze vcu118\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@3 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\tti,6-wire-mode;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treg = <3>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/versal-a2197-sc-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller RevA\";\n\tcompatible = \"xlnx,versal-sc-revA\", \"xlnx,versal-sc\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\t/* SC Bank 43\n\tFIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS\n\tSYSCTLR_GPIO0 - 5 - conneced to versal */\n\t/* cpu thermal for MAX6643 fan control */\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tdc38_led {\n\t\t\tlabel = \"ds38-green\"; /* sc AB11 500_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc37_led {\n\t\t\tlabel = \"ds37-green\"; /* sc AD10 501_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc36_led {\n\t\t\tlabel = \"ds36-green\"; /* sc AD11 502_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t};\n};\n\n/* usb - type C - pl\n and micro usb 2.0, gt\n*/\n/* Feb 28/2019 version */\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n/* TODO\nUSB0 MIO52-63\nUSB1 MIO64-75\n*/\n\n/*eth MDIO 76/77\neth reset MIO42\nmarwell m88e1512 - SGMII */\n&gem0 {\n\tphy-handle = <&phy0>;\n\t/* phy-mode = \"sgmii\"; DTG generates this properly */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: phy@21 {\n\t\treg = <21>; /* FIXME */\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5- 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 0 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\"; /* FIXME no linux driver */\n\t\t\t\treg = <0xc0>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <10000000>; /* 10 ohm */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\ti2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* FIXME connection to Samtec J212D */\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t/* FIXME connection to Samtec J53C */\n\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@5d { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@5d { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@5d { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"LPDDR4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/versal-emu-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-emu-itr8\", \"xlnx,versal-emu\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal EMU ITR8 HW 4.0\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tclk0212: clk0212 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <212000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t\tclock-frequency = <440000>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */\n\t\t\t <0x0 0xf9080000 0x0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x1 0x9 4>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x2>;\n\t\tranges;\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tclocks = <&clk0212 &clk0212>;\n\t\t\tcurrent-speed = <9600>;\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk0212 &clk0212>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk0212 &clk0212>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk0212 &clk0212>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk0212 &clk0212>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk0212 &clk0212>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk0212 &clk0212>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk0212 &clk0212>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk0212 &clk0212>;\n\t\t};\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\treg = <0x0 0xf1040000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <0>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\treg = <0x0 0xf1050000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <1>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t};\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:9600\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/versal-spp-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-spp-itr8-cn13940875\", \"xlnx,versal-spp-itr8\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal SPP ITR8 HW 4.0\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333000>;\n\t};\n\n\talt_ref_clk: alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333000>;\n\t};\n\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333000>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware-wip\";\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x1>;\n\t\t\tu-boot,dm-pre-reloc;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"alt_ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n\n\tclk2: clk2 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <2670000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t\tclock-frequency = <2720000>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */\n\t\t\t <0x0 0xf9080000 0x0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x1 0x9 4>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x2>;\n\t\tranges;\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tpower-domains = <&versal_firmware 0x18224021>;\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\t/* dma-coherent; */\n\t\t\tpower-domains = <&versal_firmware 0x18224035>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\t/* dma-coherent; */\n\t\t\tpower-domains = <&versal_firmware 0x18224036>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\t/* dma-coherent; */\n\t\t\tpower-domains = <&versal_firmware 0x18224037>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&versal_clk 96>, <&versal_clk 82>;\n\t\t\treg = <0x0 0xff060000 0x0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&versal_firmware 0x1822401f>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&versal_clk 97>, <&versal_clk 82>;\n\t\t\treg = <0x0 0xff070000 0x0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&versal_firmware 0x18224020>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_clk 98>;\n\t\t\tpower-domains = <&versal_firmware 0x1822401d>;\n\t\t\teeprom1: eeprom@53 {\n\t\t\t\treg = <0x53>;\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t};\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_clk 99>;\n\t\t\tpower-domains = <&versal_firmware 0x1822401e>;\n\t\t\teeprom2: eeprom@55 {\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x55>;\n\t\t\t};\n\t\t};\n\n\t\tgpio: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tclocks = <&versal_clk 82>;\n\t\t\tpower-domains = <&versal_firmware 0x18224023>;\n\t\t};\n\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\t/* dma-coherent; */\n\t\t\tpower-domains = <&versal_firmware 0x18224038>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\t/* dma-coherent; */\n\t\t\tpower-domains = <&versal_firmware 0x18224039>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\t/* dma-coherent; */\n\t\t\tpower-domains = <&versal_firmware 0x1822403a>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\t/* dma-coherent; */\n\t\t\tpower-domains = <&versal_firmware 0x1822403b>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\t/* dma-coherent; */\n\t\t\tpower-domains = <&versal_firmware 0x1822403c>;\n\t\t};\n\n\t\tgem0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 56 4>, <0x0 56 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\t\t\t/* dma-coherent; */\n\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tpower-domains = <&versal_firmware 0x18224019>;\n\n\t\t\tphy0: phy@0 {\n\t\t\t\treg = <0x0>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\t};\n\t\t};\n\n\t\tgem1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 58 4>, <0x0 58 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\t\t\t/* dma-coherent; */\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tpower-domains = <&versal_firmware 0x1822401a>;\n\n\t\t\tphy1: phy@1 {\n\t\t\t\treg = <0x1>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\t};\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xf12a0000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t\tpower-domains = <&versal_firmware 0x18224034>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tnum-cs = <0x1>;\n\t\t\treg = <0x0 0xf1030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\t/* dma-coherent; */\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\t\t\tpower-domains = <&versal_firmware 0x1822402b>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"n25q512a\", \"micron,m25p80\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <25000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@100000 {\n\t\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@600000 {\n\t\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@620000 {\n\t\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"cadence,qspi\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xf1010000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tbus-num = <2>;\n\t\t\tnum-cs = <1>;\n\t\t\tcdns,fifo-depth = <508>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,is-stig-pgm = <1>;\n\t\t\tcdns,trigger-address = <0x00000000>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"n25q512a\", \"micron,m25p80\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <8>;\n\t\t\t\tspi-max-frequency = <108000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@100000 {\n\t\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@600000 {\n\t\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@620000 {\n\t\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\tnum-cs = <1>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpower-domains = <&versal_firmware 0x1822401b>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <25000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\tnum-cs = <3>;\n\t\t\tpower-domains = <&versal_firmware 0x1822401c>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <25000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0x0 0x84000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcci@fd000000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"arm,cci-500\";\n\t\t\treg = <0x0 0xfd000000 0x0 0x10000>;\n\t\t\tranges = <0x0 0x0 0xfd000000 0xa0000>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x1>;\n\t\t\tpmu@10000 {\n\t\t\t\tcompatible = \"arm,cci-500-pmu,r0\";\n\t\t\t\treg = <0x10000 0x90000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>;\n\t\t\t};\n\t\t};\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\treg = <0x0 0xf1040000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&versal_clk 59>,\n\t\t\t\t <&versal_clk 82>;\n\t\t\txlnx,device_id = <0>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tpower-domains = <&versal_firmware 0x1822402e>;\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\treg = <0x0 0xf1050000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&versal_clk 60>,\n\t\t\t\t <&versal_clk 82>;\n\t\t\txlnx,device_id = <1>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tpower-domains = <&versal_firmware 0x1822402f>;\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\t#address-cells = <0x2>;\n\t\t\t#size-cells = <0x2>;\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tranges;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tpower-domains = <&versal_firmware 0x18224018>;\n\n\t\t\tdwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x10000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\";\n\t\t\t\tinterrupts = <0x0 0x16 0x4>, <0x0 0x1A 0x4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\twatchdog: watchdog@fd4d0000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x10000>;\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = <&clk25>;\n\t\t};\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &ospi;\n\t\tspi2 = &spi0;\n\t\tspi3 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/versal-virt.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-virt\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal Virtual\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tclk2: clk2 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <2670000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t\tclock-frequency = <2720000>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */\n\t\t\t <0x0 0xf9080000 0x0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x1 0x9 4>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x2>;\n\t\tranges;\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff060000 0x0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff070000 0x0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom1: eeprom@53 {\n\t\t\t\treg = <0x53>;\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t};\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom2: eeprom@55 {\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x55>;\n\t\t\t};\n\t\t};\n\n\t\tgpio: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tethernet0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 56 4>, <0x0 56 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy0: phy@0 {\n\t\t\t\treg = <0x0>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tethernet1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 58 4>, <0x0 58 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy1: phy@1 {\n\t\t\t\treg = <0x1>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xf12a0000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tnum-cs = <0x1>;\n\t\t\treg = <0x0 0xf1030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tis-dual = <0>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"n25q512a\", \"micron,m25p80\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <108000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@100000 {\n\t\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@600000 {\n\t\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@620000 {\n\t\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <1>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <3>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0x0 0x84000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\treg = <0x0 0xf1040000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <0>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\treg = <0x0 0xf1050000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <1>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\t#address-cells = <0x2>;\n\t\t\t#size-cells = <0x2>;\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tranges;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125 &clk125>;\n\n\t\t\tdwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x10000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = ðernet0;\n\t\tethernet1 = ðernet1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zc1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revA\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zc1275-revb.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZC1275 RevB\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevB\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revB\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\tno-1-8-v;\n};\n\n&gem1 {\n\tpsu_ethernet_1_mdio: mdio {\n\t\tphy1: phy@1 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 3 150000000>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: flash@0 {\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: flash@0 {\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t\tsw13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@52 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <52>;\n\t\t\t};\n\t\t\thwmon@53 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <53>;\n\t\t\t};\n\t\t\thwmon@54 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&watchdog0 {\n\treset-on-timeout;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zcu100-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio_bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zcu100-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@20 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zcu104-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revC\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - IRPS5401_ALERT_B\n\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t * 2 - MAX6643_OT_B\n\t\t * 3 - MAX6643_FANFAIL_B\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t * 4, 10 - 17 - not connected\n\t\t */\n\t};\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tina226@40 { /* u183 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 4, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\txlnx,mio_bank = <1>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps54012@44 { /* IRPS5401 - u55 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps54012@45 { /* IRPS5401 - u57 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 { /* SI5328 - u48 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection FIXME */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zcu1285-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU1285 RevA\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1285 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1285-revA\", \"xlnx,zynqmp-zcu1285\", \"xlnx,zynqmp\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PMBUS */\n\t\t\tmax20751@74 { /* u23 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x74>;\n\t\t\t};\n\t\t\tmax20751@70 { /* u89 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x70>;\n\t\t\t};\n\t\t\tmax15301@a { /* u28 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u48 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@d { /* u27 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\tmax15303@e { /* u11 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\tmax15303@f { /* u96 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\tmax15303@11 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\tmax15303@12 { /* u24 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u29 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u51 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u30 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u102 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15301@17 { /* u50 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u31 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* CM_I2C */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYS_EEPROM */\n\t\t\teeprom: eeprom@54 { /* u101 */\n\t\t\t\tcompatible = \"atmel,24c32\"; /* 24LC32A */\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FMC1 */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FMC2 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* ANALOG_PMBUS */\n\t\t\tina226@40 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tina226@41 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tina226@42 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tina226@43 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tina226@44 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* ANALOG_CM_I2C */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FMC3 */\n\t\t};\n\t};\n};\n\n&gem1 {\n\tmdio {\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy2>;\n\tphy2: ethernet-phy@1 {\n\t\treg = <1>; /* KSZ9031RNXIC */\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-g-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 MGT Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-a2197-g-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 { /* eth MDIO 76/77 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: phy@0 { /* marwell m88e1512 */\n\t\treg = <0>;\n\t\treset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 5 - 9 */\n\t\t \"\", \"\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"\", \"\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\ti2c-mux@74 { /* u94 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* CM_I2C_SCL - Samtec */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* PMBUS - AFX_PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\ttps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\ttps544@10 { /* u73 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\ttps544@11 { /* u76 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\ttps544@12 { /* u77 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\ttps544@13 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\ttps544@14 { /* u81 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\ttps544@15 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\ttps544@16 { /* u63 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\ttps544@17 { /* u66 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\ttps544@18 { /* u67 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\ttps544@19 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\ttps544@1d { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\ttps544@1e { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\ttps544@1f { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t\ttps544@20 { /* u71 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\t\t\tina226@40 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tina226@41 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tina226@44 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tina226@45 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\ttps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\"; /* FIXME no linux driver */\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* fmc1 via JA2G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom_fmc1: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* fmc2 via JA3G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\teeprom_fmc2: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* fmc3 via JA4G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\teeprom_fmc3: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* ddr dimm */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&usb0 { /* USB0 MIO52-63 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"high-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-m-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-a2197-m-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n/* SC Bank 43\nFIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS\nSYSCTLR_GPIO0 - 5 - conneced to versal */\n/* cpu thermal for MAX6643 fan control */\n};\n/*\nusb - type C - pl\n and micro usb 2.0, gt\n*/\n/* Feb 28/2019 version */\n\n&qspi {\n\tstatus = \"okay\";\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n/* TODO\nUSB0 MIO52-63\nUSB1 MIO64-75\n*/\n\n/*eth MDIO 76/77\neth reset MIO42\nmarwell m88e1512 - SGMII */\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: phy@0 {\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc0v6_lp4: ina226@49 { /* u101 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\"; /* FIXME no linux driver */\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* UTIL_PMBUS - FIXME incorrect schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <1>; */\n\t\t};\n\t\ti2c@2 { /* C0_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_lp4: clock-generator@5d { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@5d { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@5d { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@5d { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-p-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-a2197-p-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n/* SC Bank 43\nFIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS\nSYSCTLR_GPIO0 - 5 - conneced to versal */\n/* cpu thermal for MAX6643 fan control */\n};\n/*\nusb - type C - pl\n and micro usb 2.0, gt\n*/\n/* Feb 28/2019 version */\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n/* TODO\nUSB0 MIO52-63\nUSB1 MIO64-75\n*/\n\n/*eth MDIO 76/77\neth reset MIO42\nmarwell m88e1512 - SGMII */\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 0 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\"; /* FIXME no linux driver */\n\t\t\t\treg = <0xc0>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <10000000>; /* 10 ohm */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* 570JAC000900DG */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\t/* 570BAB000299DG */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\t/* 570BAB000299DG */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\t/* 570BAB000299DG */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"LPDDR4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\t/* 570JAC000900DG */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"okay\";\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Versal System Controller on a2197 board RevA\";\n\tcompatible = \"xlnx,zynqmp-a2197-revA\", \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>;\n\t};\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* this cover MGT board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* This cover processor board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/gpio/gpio.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most GPIO bindings.\n *\n * Most GPIO bindings include a flags cell as part of the GPIO specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_GPIO_GPIO_H\n#define _DT_BINDINGS_GPIO_GPIO_H\n\n/* Bit 0 express polarity */\n#define GPIO_ACTIVE_HIGH 0\n#define GPIO_ACTIVE_LOW 1\n\n/* Bit 1 express single-endedness */\n#define GPIO_PUSH_PULL 0\n#define GPIO_SINGLE_ENDED 2\n\n/* Bit 2 express Open drain or open source */\n#define GPIO_LINE_OPEN_SOURCE 0\n#define GPIO_LINE_OPEN_DRAIN 4\n\n/*\n * * Open Drain/Collector is the combination of single-ended open drain interface.\n * * Open Source/Emitter is the combination of single-ended open source interface.\n * */\n#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)\n#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)\n\n/* Bit 3 express GPIO suspend/resume persistence */\n#define GPIO_SLEEP_MAINTAIN_VALUE 0\n#define GPIO_SLEEP_MAY_LOOSE_VALUE 8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/input/input.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most input bindings.\n *\n * Most input bindings include key code, matrix key code format.\n * In most cases, key code and matrix key code format uses\n * the standard values/macro defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INPUT_INPUT_H\n#define _DT_BINDINGS_INPUT_INPUT_H\n\n/*\n * Device properties and quirks\n */\n\n#define INPUT_PROP_POINTER\t\t0x00\t/* needs a pointer */\n#define INPUT_PROP_DIRECT\t\t0x01\t/* direct input devices */\n#define INPUT_PROP_BUTTONPAD\t\t0x02\t/* has button(s) under pad */\n#define INPUT_PROP_SEMI_MT\t\t0x03\t/* touch rectangle only */\n#define INPUT_PROP_TOPBUTTONPAD\t\t0x04\t/* softbuttons at top of pad */\n#define INPUT_PROP_POINTING_STICK\t0x05\t/* is a pointing stick */\n#define INPUT_PROP_ACCELEROMETER\t0x06\t/* has accelerometer */\n\n#define INPUT_PROP_MAX\t\t\t0x1f\n#define INPUT_PROP_CNT\t\t\t(INPUT_PROP_MAX + 1)\n\n\n/*\n * Event types\n */\n\n#define EV_SYN\t\t\t0x00\n#define EV_KEY\t\t\t0x01\n#define EV_REL\t\t\t0x02\n#define EV_ABS\t\t\t0x03\n#define EV_MSC\t\t\t0x04\n#define EV_SW\t\t\t0x05\n#define EV_LED\t\t\t0x11\n#define EV_SND\t\t\t0x12\n#define EV_REP\t\t\t0x14\n#define EV_FF\t\t\t0x15\n#define EV_PWR\t\t\t0x16\n#define EV_FF_STATUS\t\t0x17\n#define EV_MAX\t\t\t0x1f\n#define EV_CNT\t\t\t(EV_MAX+1)\n\n/*\n * Synchronization events.\n */\n\n#define SYN_REPORT\t\t0\n#define SYN_CONFIG\t\t1\n#define SYN_MT_REPORT\t\t2\n#define SYN_DROPPED\t\t3\n#define SYN_MAX\t\t\t0xf\n#define SYN_CNT\t\t\t(SYN_MAX+1)\n\n/*\n * Keys and buttons\n *\n * Most of the keys/buttons are modeled after USB HUT 1.12\n * (see http://www.usb.org/developers/hidpage).\n * Abbreviations in the comments:\n * AC - Application Control\n * AL - Application Launch Button\n * SC - System Control\n */\n\n#define KEY_RESERVED\t\t0\n#define KEY_ESC\t\t\t1\n#define KEY_1\t\t\t2\n#define KEY_2\t\t\t3\n#define KEY_3\t\t\t4\n#define KEY_4\t\t\t5\n#define KEY_5\t\t\t6\n#define KEY_6\t\t\t7\n#define KEY_7\t\t\t8\n#define KEY_8\t\t\t9\n#define KEY_9\t\t\t10\n#define KEY_0\t\t\t11\n#define KEY_MINUS\t\t12\n#define KEY_EQUAL\t\t13\n#define KEY_BACKSPACE\t\t14\n#define KEY_TAB\t\t\t15\n#define KEY_Q\t\t\t16\n#define KEY_W\t\t\t17\n#define KEY_E\t\t\t18\n#define KEY_R\t\t\t19\n#define KEY_T\t\t\t20\n#define KEY_Y\t\t\t21\n#define KEY_U\t\t\t22\n#define KEY_I\t\t\t23\n#define KEY_O\t\t\t24\n#define KEY_P\t\t\t25\n#define KEY_LEFTBRACE\t\t26\n#define KEY_RIGHTBRACE\t\t27\n#define KEY_ENTER\t\t28\n#define KEY_LEFTCTRL\t\t29\n#define KEY_A\t\t\t30\n#define KEY_S\t\t\t31\n#define KEY_D\t\t\t32\n#define KEY_F\t\t\t33\n#define KEY_G\t\t\t34\n#define KEY_H\t\t\t35\n#define KEY_J\t\t\t36\n#define KEY_K\t\t\t37\n#define KEY_L\t\t\t38\n#define KEY_SEMICOLON\t\t39\n#define KEY_APOSTROPHE\t\t40\n#define KEY_GRAVE\t\t41\n#define KEY_LEFTSHIFT\t\t42\n#define KEY_BACKSLASH\t\t43\n#define KEY_Z\t\t\t44\n#define KEY_X\t\t\t45\n#define KEY_C\t\t\t46\n#define KEY_V\t\t\t47\n#define KEY_B\t\t\t48\n#define KEY_N\t\t\t49\n#define KEY_M\t\t\t50\n#define KEY_COMMA\t\t51\n#define KEY_DOT\t\t\t52\n#define KEY_SLASH\t\t53\n#define KEY_RIGHTSHIFT\t\t54\n#define KEY_KPASTERISK\t\t55\n#define KEY_LEFTALT\t\t56\n#define KEY_SPACE\t\t57\n#define KEY_CAPSLOCK\t\t58\n#define KEY_F1\t\t\t59\n#define KEY_F2\t\t\t60\n#define KEY_F3\t\t\t61\n#define KEY_F4\t\t\t62\n#define KEY_F5\t\t\t63\n#define KEY_F6\t\t\t64\n#define KEY_F7\t\t\t65\n#define KEY_F8\t\t\t66\n#define KEY_F9\t\t\t67\n#define KEY_F10\t\t\t68\n#define KEY_NUMLOCK\t\t69\n#define KEY_SCROLLLOCK\t\t70\n#define KEY_KP7\t\t\t71\n#define KEY_KP8\t\t\t72\n#define KEY_KP9\t\t\t73\n#define KEY_KPMINUS\t\t74\n#define KEY_KP4\t\t\t75\n#define KEY_KP5\t\t\t76\n#define KEY_KP6\t\t\t77\n#define KEY_KPPLUS\t\t78\n#define KEY_KP1\t\t\t79\n#define KEY_KP2\t\t\t80\n#define KEY_KP3\t\t\t81\n#define KEY_KP0\t\t\t82\n#define KEY_KPDOT\t\t83\n\n#define KEY_ZENKAKUHANKAKU\t85\n#define KEY_102ND\t\t86\n#define KEY_F11\t\t\t87\n#define KEY_F12\t\t\t88\n#define KEY_RO\t\t\t89\n#define KEY_KATAKANA\t\t90\n#define KEY_HIRAGANA\t\t91\n#define KEY_HENKAN\t\t92\n#define KEY_KATAKANAHIRAGANA\t93\n#define KEY_MUHENKAN\t\t94\n#define KEY_KPJPCOMMA\t\t95\n#define KEY_KPENTER\t\t96\n#define KEY_RIGHTCTRL\t\t97\n#define KEY_KPSLASH\t\t98\n#define KEY_SYSRQ\t\t99\n#define KEY_RIGHTALT\t\t100\n#define KEY_LINEFEED\t\t101\n#define KEY_HOME\t\t102\n#define KEY_UP\t\t\t103\n#define KEY_PAGEUP\t\t104\n#define KEY_LEFT\t\t105\n#define KEY_RIGHT\t\t106\n#define KEY_END\t\t\t107\n#define KEY_DOWN\t\t108\n#define KEY_PAGEDOWN\t\t109\n#define KEY_INSERT\t\t110\n#define KEY_DELETE\t\t111\n#define KEY_MACRO\t\t112\n#define KEY_MUTE\t\t113\n#define KEY_VOLUMEDOWN\t\t114\n#define KEY_VOLUMEUP\t\t115\n#define KEY_POWER\t\t116\t/* SC System Power Down */\n#define KEY_KPEQUAL\t\t117\n#define KEY_KPPLUSMINUS\t\t118\n#define KEY_PAUSE\t\t119\n#define KEY_SCALE\t\t120\t/* AL Compiz Scale (Expose) */\n\n#define KEY_KPCOMMA\t\t121\n#define KEY_HANGEUL\t\t122\n#define KEY_HANGUEL\t\tKEY_HANGEUL\n#define KEY_HANJA\t\t123\n#define KEY_YEN\t\t\t124\n#define KEY_LEFTMETA\t\t125\n#define KEY_RIGHTMETA\t\t126\n#define KEY_COMPOSE\t\t127\n#define KEY_STOP\t\t128\t/* AC Stop */\n#define KEY_AGAIN\t\t129\n#define KEY_PROPS\t\t130\t/* AC Properties */\n#define KEY_UNDO\t\t131\t/* AC Undo */\n#define KEY_FRONT\t\t132\n#define KEY_COPY\t\t133\t/* AC Copy */\n#define KEY_OPEN\t\t134\t/* AC Open */\n#define KEY_PASTE\t\t135\t/* AC Paste */\n#define KEY_FIND\t\t136\t/* AC Search */\n#define KEY_CUT\t\t\t137\t/* AC Cut */\n#define KEY_HELP\t\t138\t/* AL Integrated Help Center */\n#define KEY_MENU\t\t139\t/* Menu (show menu) */\n#define KEY_CALC\t\t140\t/* AL Calculator */\n#define KEY_SETUP\t\t141\n#define KEY_SLEEP\t\t142\t/* SC System Sleep */\n#define KEY_WAKEUP\t\t143\t/* System Wake Up */\n#define KEY_FILE\t\t144\t/* AL Local Machine Browser */\n#define KEY_SENDFILE\t\t145\n#define KEY_DELETEFILE\t\t146\n#define KEY_XFER\t\t147\n#define KEY_PROG1\t\t148\n#define KEY_PROG2\t\t149\n#define KEY_WWW\t\t\t150\t/* AL Internet Browser */\n#define KEY_MSDOS\t\t151\n#define KEY_COFFEE\t\t152\t/* AL Terminal Lock/Screensaver */\n#define KEY_SCREENLOCK\t\tKEY_COFFEE\n#define KEY_ROTATE_DISPLAY\t153\t/* Display orientation for e.g. tablets */\n#define KEY_DIRECTION\t\tKEY_ROTATE_DISPLAY\n#define KEY_CYCLEWINDOWS\t154\n#define KEY_MAIL\t\t155\n#define KEY_BOOKMARKS\t\t156\t/* AC Bookmarks */\n#define KEY_COMPUTER\t\t157\n#define KEY_BACK\t\t158\t/* AC Back */\n#define KEY_FORWARD\t\t159\t/* AC Forward */\n#define KEY_CLOSECD\t\t160\n#define KEY_EJECTCD\t\t161\n#define KEY_EJECTCLOSECD\t162\n#define KEY_NEXTSONG\t\t163\n#define KEY_PLAYPAUSE\t\t164\n#define KEY_PREVIOUSSONG\t165\n#define KEY_STOPCD\t\t166\n#define KEY_RECORD\t\t167\n#define KEY_REWIND\t\t168\n#define KEY_PHONE\t\t169\t/* Media Select Telephone */\n#define KEY_ISO\t\t\t170\n#define KEY_CONFIG\t\t171\t/* AL Consumer Control Configuration */\n#define KEY_HOMEPAGE\t\t172\t/* AC Home */\n#define KEY_REFRESH\t\t173\t/* AC Refresh */\n#define KEY_EXIT\t\t174\t/* AC Exit */\n#define KEY_MOVE\t\t175\n#define KEY_EDIT\t\t176\n#define KEY_SCROLLUP\t\t177\n#define KEY_SCROLLDOWN\t\t178\n#define KEY_KPLEFTPAREN\t\t179\n#define KEY_KPRIGHTPAREN\t180\n#define KEY_NEW\t\t\t181\t/* AC New */\n#define KEY_REDO\t\t182\t/* AC Redo/Repeat */\n\n#define KEY_F13\t\t\t183\n#define KEY_F14\t\t\t184\n#define KEY_F15\t\t\t185\n#define KEY_F16\t\t\t186\n#define KEY_F17\t\t\t187\n#define KEY_F18\t\t\t188\n#define KEY_F19\t\t\t189\n#define KEY_F20\t\t\t190\n#define KEY_F21\t\t\t191\n#define KEY_F22\t\t\t192\n#define KEY_F23\t\t\t193\n#define KEY_F24\t\t\t194\n\n#define KEY_PLAYCD\t\t200\n#define KEY_PAUSECD\t\t201\n#define KEY_PROG3\t\t202\n#define KEY_PROG4\t\t203\n#define KEY_DASHBOARD\t\t204\t/* AL Dashboard */\n#define KEY_SUSPEND\t\t205\n#define KEY_CLOSE\t\t206\t/* AC Close */\n#define KEY_PLAY\t\t207\n#define KEY_FASTFORWARD\t\t208\n#define KEY_BASSBOOST\t\t209\n#define KEY_PRINT\t\t210\t/* AC Print */\n#define KEY_HP\t\t\t211\n#define KEY_CAMERA\t\t212\n#define KEY_SOUND\t\t213\n#define KEY_QUESTION\t\t214\n#define KEY_EMAIL\t\t215\n#define KEY_CHAT\t\t216\n#define KEY_SEARCH\t\t217\n#define KEY_CONNECT\t\t218\n#define KEY_FINANCE\t\t219\t/* AL Checkbook/Finance */\n#define KEY_SPORT\t\t220\n#define KEY_SHOP\t\t221\n#define KEY_ALTERASE\t\t222\n#define KEY_CANCEL\t\t223\t/* AC Cancel */\n#define KEY_BRIGHTNESSDOWN\t224\n#define KEY_BRIGHTNESSUP\t225\n#define KEY_MEDIA\t\t226\n\n#define KEY_SWITCHVIDEOMODE\t227\t/* Cycle between available video\n\t\t\t\t\t outputs (Monitor/LCD/TV-out/etc) */\n#define KEY_KBDILLUMTOGGLE\t228\n#define KEY_KBDILLUMDOWN\t229\n#define KEY_KBDILLUMUP\t\t230\n\n#define KEY_SEND\t\t231\t/* AC Send */\n#define KEY_REPLY\t\t232\t/* AC Reply */\n#define KEY_FORWARDMAIL\t\t233\t/* AC Forward Msg */\n#define KEY_SAVE\t\t234\t/* AC Save */\n#define KEY_DOCUMENTS\t\t235\n\n#define KEY_BATTERY\t\t236\n\n#define KEY_BLUETOOTH\t\t237\n#define KEY_WLAN\t\t238\n#define KEY_UWB\t\t\t239\n\n#define KEY_UNKNOWN\t\t240\n#define KEY_VIDEO_NEXT\t\t241\t/* drive next video source */\n#define KEY_VIDEO_PREV\t\t242\t/* drive previous video source */\n#define KEY_BRIGHTNESS_CYCLE\t243\t/* brightness up, after max is min */\n#define KEY_BRIGHTNESS_AUTO\t244\t/* Set Auto Brightness: manual\n\t\t\t\t\t brightness control is off,\n\t\t\t\t\t rely on ambient */\n#define KEY_BRIGHTNESS_ZERO\tKEY_BRIGHTNESS_AUTO\n#define KEY_DISPLAY_OFF\t\t245\t/* display device to off state */\n\n#define KEY_WWAN\t\t246\t/* Wireless WAN (LTE, UMTS, GSM, etc.) */\n#define KEY_WIMAX\t\tKEY_WWAN\n#define KEY_RFKILL\t\t247\t/* Key that controls all radios */\n\n#define KEY_MICMUTE\t\t248\t/* Mute / unmute the microphone */\n\n/* Code 255 is reserved for special needs of AT keyboard driver */\n\n#define BTN_MISC\t\t0x100\n#define BTN_0\t\t\t0x100\n#define BTN_1\t\t\t0x101\n#define BTN_2\t\t\t0x102\n#define BTN_3\t\t\t0x103\n#define BTN_4\t\t\t0x104\n#define BTN_5\t\t\t0x105\n#define BTN_6\t\t\t0x106\n#define BTN_7\t\t\t0x107\n#define BTN_8\t\t\t0x108\n#define BTN_9\t\t\t0x109\n\n#define BTN_MOUSE\t\t0x110\n#define BTN_LEFT\t\t0x110\n#define BTN_RIGHT\t\t0x111\n#define BTN_MIDDLE\t\t0x112\n#define BTN_SIDE\t\t0x113\n#define BTN_EXTRA\t\t0x114\n#define BTN_FORWARD\t\t0x115\n#define BTN_BACK\t\t0x116\n#define BTN_TASK\t\t0x117\n\n#define BTN_JOYSTICK\t\t0x120\n#define BTN_TRIGGER\t\t0x120\n#define BTN_THUMB\t\t0x121\n#define BTN_THUMB2\t\t0x122\n#define BTN_TOP\t\t\t0x123\n#define BTN_TOP2\t\t0x124\n#define BTN_PINKIE\t\t0x125\n#define BTN_BASE\t\t0x126\n#define BTN_BASE2\t\t0x127\n#define BTN_BASE3\t\t0x128\n#define BTN_BASE4\t\t0x129\n#define BTN_BASE5\t\t0x12a\n#define BTN_BASE6\t\t0x12b\n#define BTN_DEAD\t\t0x12f\n\n#define BTN_GAMEPAD\t\t0x130\n#define BTN_SOUTH\t\t0x130\n#define BTN_A\t\t\tBTN_SOUTH\n#define BTN_EAST\t\t0x131\n#define BTN_B\t\t\tBTN_EAST\n#define BTN_C\t\t\t0x132\n#define BTN_NORTH\t\t0x133\n#define BTN_X\t\t\tBTN_NORTH\n#define BTN_WEST\t\t0x134\n#define BTN_Y\t\t\tBTN_WEST\n#define BTN_Z\t\t\t0x135\n#define BTN_TL\t\t\t0x136\n#define BTN_TR\t\t\t0x137\n#define BTN_TL2\t\t\t0x138\n#define BTN_TR2\t\t\t0x139\n#define BTN_SELECT\t\t0x13a\n#define BTN_START\t\t0x13b\n#define BTN_MODE\t\t0x13c\n#define BTN_THUMBL\t\t0x13d\n#define BTN_THUMBR\t\t0x13e\n\n#define BTN_DIGI\t\t0x140\n#define BTN_TOOL_PEN\t\t0x140\n#define BTN_TOOL_RUBBER\t\t0x141\n#define BTN_TOOL_BRUSH\t\t0x142\n#define BTN_TOOL_PENCIL\t\t0x143\n#define BTN_TOOL_AIRBRUSH\t0x144\n#define BTN_TOOL_FINGER\t\t0x145\n#define BTN_TOOL_MOUSE\t\t0x146\n#define BTN_TOOL_LENS\t\t0x147\n#define BTN_TOOL_QUINTTAP\t0x148\t/* Five fingers on trackpad */\n#define BTN_TOUCH\t\t0x14a\n#define BTN_STYLUS\t\t0x14b\n#define BTN_STYLUS2\t\t0x14c\n#define BTN_TOOL_DOUBLETAP\t0x14d\n#define BTN_TOOL_TRIPLETAP\t0x14e\n#define BTN_TOOL_QUADTAP\t0x14f\t/* Four fingers on trackpad */\n\n#define BTN_WHEEL\t\t0x150\n#define BTN_GEAR_DOWN\t\t0x150\n#define BTN_GEAR_UP\t\t0x151\n\n#define KEY_OK\t\t\t0x160\n#define KEY_SELECT\t\t0x161\n#define KEY_GOTO\t\t0x162\n#define KEY_CLEAR\t\t0x163\n#define KEY_POWER2\t\t0x164\n#define KEY_OPTION\t\t0x165\n#define KEY_INFO\t\t0x166\t/* AL OEM Features/Tips/Tutorial */\n#define KEY_TIME\t\t0x167\n#define KEY_VENDOR\t\t0x168\n#define KEY_ARCHIVE\t\t0x169\n#define KEY_PROGRAM\t\t0x16a\t/* Media Select Program Guide */\n#define KEY_CHANNEL\t\t0x16b\n#define KEY_FAVORITES\t\t0x16c\n#define KEY_EPG\t\t\t0x16d\n#define KEY_PVR\t\t\t0x16e\t/* Media Select Home */\n#define KEY_MHP\t\t\t0x16f\n#define KEY_LANGUAGE\t\t0x170\n#define KEY_TITLE\t\t0x171\n#define KEY_SUBTITLE\t\t0x172\n#define KEY_ANGLE\t\t0x173\n#define KEY_ZOOM\t\t0x174\n#define KEY_MODE\t\t0x175\n#define KEY_KEYBOARD\t\t0x176\n#define KEY_SCREEN\t\t0x177\n#define KEY_PC\t\t\t0x178\t/* Media Select Computer */\n#define KEY_TV\t\t\t0x179\t/* Media Select TV */\n#define KEY_TV2\t\t\t0x17a\t/* Media Select Cable */\n#define KEY_VCR\t\t\t0x17b\t/* Media Select VCR */\n#define KEY_VCR2\t\t0x17c\t/* VCR Plus */\n#define KEY_SAT\t\t\t0x17d\t/* Media Select Satellite */\n#define KEY_SAT2\t\t0x17e\n#define KEY_CD\t\t\t0x17f\t/* Media Select CD */\n#define KEY_TAPE\t\t0x180\t/* Media Select Tape */\n#define KEY_RADIO\t\t0x181\n#define KEY_TUNER\t\t0x182\t/* Media Select Tuner */\n#define KEY_PLAYER\t\t0x183\n#define KEY_TEXT\t\t0x184\n#define KEY_DVD\t\t\t0x185\t/* Media Select DVD */\n#define KEY_AUX\t\t\t0x186\n#define KEY_MP3\t\t\t0x187\n#define KEY_AUDIO\t\t0x188\t/* AL Audio Browser */\n#define KEY_VIDEO\t\t0x189\t/* AL Movie Browser */\n#define KEY_DIRECTORY\t\t0x18a\n#define KEY_LIST\t\t0x18b\n#define KEY_MEMO\t\t0x18c\t/* Media Select Messages */\n#define KEY_CALENDAR\t\t0x18d\n#define KEY_RED\t\t\t0x18e\n#define KEY_GREEN\t\t0x18f\n#define KEY_YELLOW\t\t0x190\n#define KEY_BLUE\t\t0x191\n#define KEY_CHANNELUP\t\t0x192\t/* Channel Increment */\n#define KEY_CHANNELDOWN\t\t0x193\t/* Channel Decrement */\n#define KEY_FIRST\t\t0x194\n#define KEY_LAST\t\t0x195\t/* Recall Last */\n#define KEY_AB\t\t\t0x196\n#define KEY_NEXT\t\t0x197\n#define KEY_RESTART\t\t0x198\n#define KEY_SLOW\t\t0x199\n#define KEY_SHUFFLE\t\t0x19a\n#define KEY_BREAK\t\t0x19b\n#define KEY_PREVIOUS\t\t0x19c\n#define KEY_DIGITS\t\t0x19d\n#define KEY_TEEN\t\t0x19e\n#define KEY_TWEN\t\t0x19f\n#define KEY_VIDEOPHONE\t\t0x1a0\t/* Media Select Video Phone */\n#define KEY_GAMES\t\t0x1a1\t/* Media Select Games */\n#define KEY_ZOOMIN\t\t0x1a2\t/* AC Zoom In */\n#define KEY_ZOOMOUT\t\t0x1a3\t/* AC Zoom Out */\n#define KEY_ZOOMRESET\t\t0x1a4\t/* AC Zoom */\n#define KEY_WORDPROCESSOR\t0x1a5\t/* AL Word Processor */\n#define KEY_EDITOR\t\t0x1a6\t/* AL Text Editor */\n#define KEY_SPREADSHEET\t\t0x1a7\t/* AL Spreadsheet */\n#define KEY_GRAPHICSEDITOR\t0x1a8\t/* AL Graphics Editor */\n#define KEY_PRESENTATION\t0x1a9\t/* AL Presentation App */\n#define KEY_DATABASE\t\t0x1aa\t/* AL Database App */\n#define KEY_NEWS\t\t0x1ab\t/* AL Newsreader */\n#define KEY_VOICEMAIL\t\t0x1ac\t/* AL Voicemail */\n#define KEY_ADDRESSBOOK\t\t0x1ad\t/* AL Contacts/Address Book */\n#define KEY_MESSENGER\t\t0x1ae\t/* AL Instant Messaging */\n#define KEY_DISPLAYTOGGLE\t0x1af\t/* Turn display (LCD) on and off */\n#define KEY_BRIGHTNESS_TOGGLE\tKEY_DISPLAYTOGGLE\n#define KEY_SPELLCHECK\t\t0x1b0 /* AL Spell Check */\n#define KEY_LOGOFF\t\t0x1b1 /* AL Logoff */\n\n#define KEY_DOLLAR\t\t0x1b2\n#define KEY_EURO\t\t0x1b3\n\n#define KEY_FRAMEBACK\t\t0x1b4\t/* Consumer - transport controls */\n#define KEY_FRAMEFORWARD\t0x1b5\n#define KEY_CONTEXT_MENU\t0x1b6\t/* GenDesc - system context menu */\n#define KEY_MEDIA_REPEAT\t0x1b7\t/* Consumer - transport control */\n#define KEY_10CHANNELSUP\t0x1b8\t/* 10 channels up (10+) */\n#define KEY_10CHANNELSDOWN\t0x1b9\t/* 10 channels down (10-) */\n#define KEY_IMAGES\t\t0x1ba\t/* AL Image Browser */\n\n#define KEY_DEL_EOL\t\t0x1c0\n#define KEY_DEL_EOS\t\t0x1c1\n#define KEY_INS_LINE\t\t0x1c2\n#define KEY_DEL_LINE\t\t0x1c3\n\n#define KEY_FN\t\t\t0x1d0\n#define KEY_FN_ESC\t\t0x1d1\n#define KEY_FN_F1\t\t0x1d2\n#define KEY_FN_F2\t\t0x1d3\n#define KEY_FN_F3\t\t0x1d4\n#define KEY_FN_F4\t\t0x1d5\n#define KEY_FN_F5\t\t0x1d6\n#define KEY_FN_F6\t\t0x1d7\n#define KEY_FN_F7\t\t0x1d8\n#define KEY_FN_F8\t\t0x1d9\n#define KEY_FN_F9\t\t0x1da\n#define KEY_FN_F10\t\t0x1db\n#define KEY_FN_F11\t\t0x1dc\n#define KEY_FN_F12\t\t0x1dd\n#define KEY_FN_1\t\t0x1de\n#define KEY_FN_2\t\t0x1df\n#define KEY_FN_D\t\t0x1e0\n#define KEY_FN_E\t\t0x1e1\n#define KEY_FN_F\t\t0x1e2\n#define KEY_FN_S\t\t0x1e3\n#define KEY_FN_B\t\t0x1e4\n\n#define KEY_BRL_DOT1\t\t0x1f1\n#define KEY_BRL_DOT2\t\t0x1f2\n#define KEY_BRL_DOT3\t\t0x1f3\n#define KEY_BRL_DOT4\t\t0x1f4\n#define KEY_BRL_DOT5\t\t0x1f5\n#define KEY_BRL_DOT6\t\t0x1f6\n#define KEY_BRL_DOT7\t\t0x1f7\n#define KEY_BRL_DOT8\t\t0x1f8\n#define KEY_BRL_DOT9\t\t0x1f9\n#define KEY_BRL_DOT10\t\t0x1fa\n\n#define KEY_NUMERIC_0\t\t0x200\t/* used by phones, remote controls, */\n#define KEY_NUMERIC_1\t\t0x201\t/* and other keypads */\n#define KEY_NUMERIC_2\t\t0x202\n#define KEY_NUMERIC_3\t\t0x203\n#define KEY_NUMERIC_4\t\t0x204\n#define KEY_NUMERIC_5\t\t0x205\n#define KEY_NUMERIC_6\t\t0x206\n#define KEY_NUMERIC_7\t\t0x207\n#define KEY_NUMERIC_8\t\t0x208\n#define KEY_NUMERIC_9\t\t0x209\n#define KEY_NUMERIC_STAR\t0x20a\n#define KEY_NUMERIC_POUND\t0x20b\n#define KEY_NUMERIC_A\t\t0x20c\t/* Phone key A - HUT Telephony 0xb9 */\n#define KEY_NUMERIC_B\t\t0x20d\n#define KEY_NUMERIC_C\t\t0x20e\n#define KEY_NUMERIC_D\t\t0x20f\n\n#define KEY_CAMERA_FOCUS\t0x210\n#define KEY_WPS_BUTTON\t\t0x211\t/* WiFi Protected Setup key */\n\n#define KEY_TOUCHPAD_TOGGLE\t0x212\t/* Request switch touchpad on or off */\n#define KEY_TOUCHPAD_ON\t\t0x213\n#define KEY_TOUCHPAD_OFF\t0x214\n\n#define KEY_CAMERA_ZOOMIN\t0x215\n#define KEY_CAMERA_ZOOMOUT\t0x216\n#define KEY_CAMERA_UP\t\t0x217\n#define KEY_CAMERA_DOWN\t\t0x218\n#define KEY_CAMERA_LEFT\t\t0x219\n#define KEY_CAMERA_RIGHT\t0x21a\n\n#define KEY_ATTENDANT_ON\t0x21b\n#define KEY_ATTENDANT_OFF\t0x21c\n#define KEY_ATTENDANT_TOGGLE\t0x21d\t/* Attendant call on or off */\n#define KEY_LIGHTS_TOGGLE\t0x21e\t/* Reading light on or off */\n\n#define BTN_DPAD_UP\t\t0x220\n#define BTN_DPAD_DOWN\t\t0x221\n#define BTN_DPAD_LEFT\t\t0x222\n#define BTN_DPAD_RIGHT\t\t0x223\n\n#define KEY_ALS_TOGGLE\t\t0x230\t/* Ambient light sensor */\n\n#define KEY_BUTTONCONFIG\t\t0x240\t/* AL Button Configuration */\n#define KEY_TASKMANAGER\t\t0x241\t/* AL Task/Project Manager */\n#define KEY_JOURNAL\t\t0x242\t/* AL Log/Journal/Timecard */\n#define KEY_CONTROLPANEL\t\t0x243\t/* AL Control Panel */\n#define KEY_APPSELECT\t\t0x244\t/* AL Select Task/Application */\n#define KEY_SCREENSAVER\t\t0x245\t/* AL Screen Saver */\n#define KEY_VOICECOMMAND\t\t0x246\t/* Listening Voice Command */\n#define KEY_ASSISTANT\t\t0x247\t/* AL Context-aware desktop assistant */\n\n#define KEY_BRIGHTNESS_MIN\t\t0x250\t/* Set Brightness to Minimum */\n#define KEY_BRIGHTNESS_MAX\t\t0x251\t/* Set Brightness to Maximum */\n\n#define KEY_KBDINPUTASSIST_PREV\t\t0x260\n#define KEY_KBDINPUTASSIST_NEXT\t\t0x261\n#define KEY_KBDINPUTASSIST_PREVGROUP\t\t0x262\n#define KEY_KBDINPUTASSIST_NEXTGROUP\t\t0x263\n#define KEY_KBDINPUTASSIST_ACCEPT\t\t0x264\n#define KEY_KBDINPUTASSIST_CANCEL\t\t0x265\n\n/* Diagonal movement keys */\n#define KEY_RIGHT_UP\t\t\t0x266\n#define KEY_RIGHT_DOWN\t\t\t0x267\n#define KEY_LEFT_UP\t\t\t0x268\n#define KEY_LEFT_DOWN\t\t\t0x269\n\n#define KEY_ROOT_MENU\t\t\t0x26a /* Show Device's Root Menu */\n/* Show Top Menu of the Media (e.g. DVD) */\n#define KEY_MEDIA_TOP_MENU\t\t0x26b\n#define KEY_NUMERIC_11\t\t\t0x26c\n#define KEY_NUMERIC_12\t\t\t0x26d\n/*\n * Toggle Audio Description: refers to an audio service that helps blind and\n * visually impaired consumers understand the action in a program. Note: in\n * some countries this is referred to as \"Video Description\".\n */\n#define KEY_AUDIO_DESC\t\t\t0x26e\n#define KEY_3D_MODE\t\t\t0x26f\n#define KEY_NEXT_FAVORITE\t\t0x270\n#define KEY_STOP_RECORD\t\t\t0x271\n#define KEY_PAUSE_RECORD\t\t0x272\n#define KEY_VOD\t\t\t\t0x273 /* Video on Demand */\n#define KEY_UNMUTE\t\t\t0x274\n#define KEY_FASTREVERSE\t\t\t0x275\n#define KEY_SLOWREVERSE\t\t\t0x276\n/*\n * Control a data application associated with the currently viewed channel,\n * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)\n */\n#define KEY_DATA\t\t\t0x277\n#define KEY_ONSCREEN_KEYBOARD\t\t0x278\n\n#define BTN_TRIGGER_HAPPY\t\t0x2c0\n#define BTN_TRIGGER_HAPPY1\t\t0x2c0\n#define BTN_TRIGGER_HAPPY2\t\t0x2c1\n#define BTN_TRIGGER_HAPPY3\t\t0x2c2\n#define BTN_TRIGGER_HAPPY4\t\t0x2c3\n#define BTN_TRIGGER_HAPPY5\t\t0x2c4\n#define BTN_TRIGGER_HAPPY6\t\t0x2c5\n#define BTN_TRIGGER_HAPPY7\t\t0x2c6\n#define BTN_TRIGGER_HAPPY8\t\t0x2c7\n#define BTN_TRIGGER_HAPPY9\t\t0x2c8\n#define BTN_TRIGGER_HAPPY10\t\t0x2c9\n#define BTN_TRIGGER_HAPPY11\t\t0x2ca\n#define BTN_TRIGGER_HAPPY12\t\t0x2cb\n#define BTN_TRIGGER_HAPPY13\t\t0x2cc\n#define BTN_TRIGGER_HAPPY14\t\t0x2cd\n#define BTN_TRIGGER_HAPPY15\t\t0x2ce\n#define BTN_TRIGGER_HAPPY16\t\t0x2cf\n#define BTN_TRIGGER_HAPPY17\t\t0x2d0\n#define BTN_TRIGGER_HAPPY18\t\t0x2d1\n#define BTN_TRIGGER_HAPPY19\t\t0x2d2\n#define BTN_TRIGGER_HAPPY20\t\t0x2d3\n#define BTN_TRIGGER_HAPPY21\t\t0x2d4\n#define BTN_TRIGGER_HAPPY22\t\t0x2d5\n#define BTN_TRIGGER_HAPPY23\t\t0x2d6\n#define BTN_TRIGGER_HAPPY24\t\t0x2d7\n#define BTN_TRIGGER_HAPPY25\t\t0x2d8\n#define BTN_TRIGGER_HAPPY26\t\t0x2d9\n#define BTN_TRIGGER_HAPPY27\t\t0x2da\n#define BTN_TRIGGER_HAPPY28\t\t0x2db\n#define BTN_TRIGGER_HAPPY29\t\t0x2dc\n#define BTN_TRIGGER_HAPPY30\t\t0x2dd\n#define BTN_TRIGGER_HAPPY31\t\t0x2de\n#define BTN_TRIGGER_HAPPY32\t\t0x2df\n#define BTN_TRIGGER_HAPPY33\t\t0x2e0\n#define BTN_TRIGGER_HAPPY34\t\t0x2e1\n#define BTN_TRIGGER_HAPPY35\t\t0x2e2\n#define BTN_TRIGGER_HAPPY36\t\t0x2e3\n#define BTN_TRIGGER_HAPPY37\t\t0x2e4\n#define BTN_TRIGGER_HAPPY38\t\t0x2e5\n#define BTN_TRIGGER_HAPPY39\t\t0x2e6\n#define BTN_TRIGGER_HAPPY40\t\t0x2e7\n\n/* We avoid low common keys in module aliases so they don't get huge. */\n#define KEY_MIN_INTERESTING\tKEY_MUTE\n#define KEY_MAX\t\t\t0x2ff\n#define KEY_CNT\t\t\t(KEY_MAX+1)\n\n/*\n * Relative axes\n */\n\n#define REL_X\t\t\t0x00\n#define REL_Y\t\t\t0x01\n#define REL_Z\t\t\t0x02\n#define REL_RX\t\t\t0x03\n#define REL_RY\t\t\t0x04\n#define REL_RZ\t\t\t0x05\n#define REL_HWHEEL\t\t0x06\n#define REL_DIAL\t\t0x07\n#define REL_WHEEL\t\t0x08\n#define REL_MISC\t\t0x09\n#define REL_MAX\t\t\t0x0f\n#define REL_CNT\t\t\t(REL_MAX+1)\n\n/*\n * Absolute axes\n */\n\n#define ABS_X\t\t\t0x00\n#define ABS_Y\t\t\t0x01\n#define ABS_Z\t\t\t0x02\n#define ABS_RX\t\t\t0x03\n#define ABS_RY\t\t\t0x04\n#define ABS_RZ\t\t\t0x05\n#define ABS_THROTTLE\t\t0x06\n#define ABS_RUDDER\t\t0x07\n#define ABS_WHEEL\t\t0x08\n#define ABS_GAS\t\t\t0x09\n#define ABS_BRAKE\t\t0x0a\n#define ABS_HAT0X\t\t0x10\n#define ABS_HAT0Y\t\t0x11\n#define ABS_HAT1X\t\t0x12\n#define ABS_HAT1Y\t\t0x13\n#define ABS_HAT2X\t\t0x14\n#define ABS_HAT2Y\t\t0x15\n#define ABS_HAT3X\t\t0x16\n#define ABS_HAT3Y\t\t0x17\n#define ABS_PRESSURE\t\t0x18\n#define ABS_DISTANCE\t\t0x19\n#define ABS_TILT_X\t\t0x1a\n#define ABS_TILT_Y\t\t0x1b\n#define ABS_TOOL_WIDTH\t\t0x1c\n\n#define ABS_VOLUME\t\t0x20\n\n#define ABS_MISC\t\t0x28\n\n#define ABS_MT_SLOT\t\t0x2f\t/* MT slot being modified */\n#define ABS_MT_TOUCH_MAJOR\t0x30\t/* Major axis of touching ellipse */\n#define ABS_MT_TOUCH_MINOR\t0x31\t/* Minor axis (omit if circular) */\n#define ABS_MT_WIDTH_MAJOR\t0x32\t/* Major axis of approaching ellipse */\n#define ABS_MT_WIDTH_MINOR\t0x33\t/* Minor axis (omit if circular) */\n#define ABS_MT_ORIENTATION\t0x34\t/* Ellipse orientation */\n#define ABS_MT_POSITION_X\t0x35\t/* Center X touch position */\n#define ABS_MT_POSITION_Y\t0x36\t/* Center Y touch position */\n#define ABS_MT_TOOL_TYPE\t0x37\t/* Type of touching device */\n#define ABS_MT_BLOB_ID\t\t0x38\t/* Group a set of packets as a blob */\n#define ABS_MT_TRACKING_ID\t0x39\t/* Unique ID of initiated contact */\n#define ABS_MT_PRESSURE\t\t0x3a\t/* Pressure on contact area */\n#define ABS_MT_DISTANCE\t\t0x3b\t/* Contact hover distance */\n#define ABS_MT_TOOL_X\t\t0x3c\t/* Center X tool position */\n#define ABS_MT_TOOL_Y\t\t0x3d\t/* Center Y tool position */\n\n\n#define ABS_MAX\t\t\t0x3f\n#define ABS_CNT\t\t\t(ABS_MAX+1)\n\n/*\n * Switch events\n */\n\n#define SW_LID\t\t\t0x00 /* set = lid shut */\n#define SW_TABLET_MODE\t\t0x01 /* set = tablet mode */\n#define SW_HEADPHONE_INSERT\t0x02 /* set = inserted */\n#define SW_RFKILL_ALL\t\t0x03 /* rfkill master switch, type \"any\"\n\t\t\t\t\t set = radio enabled */\n#define SW_RADIO\t\tSW_RFKILL_ALL\t/* deprecated */\n#define SW_MICROPHONE_INSERT\t0x04 /* set = inserted */\n#define SW_DOCK\t\t\t0x05 /* set = plugged into dock */\n#define SW_LINEOUT_INSERT\t0x06 /* set = inserted */\n#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */\n#define SW_VIDEOOUT_INSERT\t0x08 /* set = inserted */\n#define SW_CAMERA_LENS_COVER\t0x09 /* set = lens covered */\n#define SW_KEYPAD_SLIDE\t\t0x0a /* set = keypad slide out */\n#define SW_FRONT_PROXIMITY\t0x0b /* set = front proximity sensor active */\n#define SW_ROTATE_LOCK\t\t0x0c /* set = rotate locked/disabled */\n#define SW_LINEIN_INSERT\t0x0d /* set = inserted */\n#define SW_MUTE_DEVICE\t\t0x0e /* set = device disabled */\n#define SW_PEN_INSERTED\t\t0x0f /* set = pen inserted */\n#define SW_MAX\t\t\t0x0f\n#define SW_CNT\t\t\t(SW_MAX+1)\n\n/*\n * Misc events\n */\n\n#define MSC_SERIAL\t\t0x00\n#define MSC_PULSELED\t\t0x01\n#define MSC_GESTURE\t\t0x02\n#define MSC_RAW\t\t\t0x03\n#define MSC_SCAN\t\t0x04\n#define MSC_TIMESTAMP\t\t0x05\n#define MSC_MAX\t\t\t0x07\n#define MSC_CNT\t\t\t(MSC_MAX+1)\n\n/*\n * LEDs\n */\n\n#define LED_NUML\t\t0x00\n#define LED_CAPSL\t\t0x01\n#define LED_SCROLLL\t\t0x02\n#define LED_COMPOSE\t\t0x03\n#define LED_KANA\t\t0x04\n#define LED_SLEEP\t\t0x05\n#define LED_SUSPEND\t\t0x06\n#define LED_MUTE\t\t0x07\n#define LED_MISC\t\t0x08\n#define LED_MAIL\t\t0x09\n#define LED_CHARGING\t\t0x0a\n#define LED_MAX\t\t\t0x0f\n#define LED_CNT\t\t\t(LED_MAX+1)\n\n/*\n * Autorepeat values\n */\n\n#define REP_DELAY\t\t0x00\n#define REP_PERIOD\t\t0x01\n#define REP_MAX\t\t\t0x01\n#define REP_CNT\t\t\t(REP_MAX+1)\n\n/*\n * Sounds\n */\n\n#define SND_CLICK\t\t0x00\n#define SND_BELL\t\t0x01\n#define SND_TONE\t\t0x02\n#define SND_MAX\t\t\t0x07\n#define SND_CNT\t\t\t(SND_MAX+1)\n\n#define MATRIX_KEY(row, col, code)\t\\\n\t((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))\n\n#endif /* _DT_BINDINGS_INPUT_INPUT_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/interrupt-controller/irq.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most IRQ bindings.\n *\n * Most IRQ bindings include a flags cell as part of the IRQ specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n\n#define IRQ_TYPE_NONE\t\t0\n#define IRQ_TYPE_EDGE_RISING\t1\n#define IRQ_TYPE_EDGE_FALLING\t2\n#define IRQ_TYPE_EDGE_BOTH\t(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)\n#define IRQ_TYPE_LEVEL_HIGH\t4\n#define IRQ_TYPE_LEVEL_LOW\t8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/phy/phy.h", "content": "/*\n *\n * This header provides constants for the phy framework\n *\n * Copyright (C) 2014 STMicroelectronics\n * Author: Gabriel Fernandez \n * License terms: GNU General Public License (GPL), version 2\n */\n\n#ifndef _DT_BINDINGS_PHY\n#define _DT_BINDINGS_PHY\n\n#define PHY_NONE\t\t0\n#define PHY_TYPE_SATA\t\t1\n#define PHY_TYPE_PCIE\t\t2\n#define PHY_TYPE_USB2\t\t3\n#define PHY_TYPE_USB3\t\t4\n#define PHY_TYPE_UFS\t\t5\n#define PHY_TYPE_DP\t\t6\n#define PHY_TYPE_SGMII\t\t7\n\n#endif /* _DT_BINDINGS_PHY */\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h", "content": "/*\n * MIO pin configuration defines for Xilinx ZynqMP\n *\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Author: Chirag Parekh \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * version 2 as published by the Free Software Foundation.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program. If not, see .\n */\n\n#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H\n#define _DT_BINDINGS_PINCTRL_ZYNQMP_H\n\n/* Bit value for IO standards */\n#define IO_STANDARD_LVCMOS33 0\n#define IO_STANDARD_LVCMOS18 1\n\n/* Bit values for Slew Rates */\n#define SLEW_RATE_FAST 0\n#define SLEW_RATE_SLOW 1\n\n/* Bit values for Pin inputs */\n#define PIN_INPUT_TYPE_CMOS 0\n#define PIN_INPUT_TYPE_SCHMITT 1\n\n/* Bit values for drive control*/\n#define DRIVE_STRENGTH_2MA 2\n#define DRIVE_STRENGTH_4MA 4\n#define DRIVE_STRENGTH_8MA 8\n#define DRIVE_STRENGTH_12MA 12\n\n#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/versal/versal.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */\n\t\t\t <0x0 0xf9080000 0x0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x1 0x9 4>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x2>;\n ranges;\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/zynq/zynq-7000.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"apb_pclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\", \"arm,primecell\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: mmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: mmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/zynqmp/zynqmp-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk 71>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk 72>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk 73>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk 74>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tdp_aclk: dp_aclk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&zynqmp_firmware {\n\tzynqmp_clk: clock-controller {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,\n\t\t\t <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\",\n\t\t\t \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t};\n};\n\n&can0 {\n\tclocks = <&zynqmp_clk 63>, <&zynqmp_clk 31>;\n};\n\n&can1 {\n\tclocks = <&zynqmp_clk 64>, <&zynqmp_clk 31>;\n};\n\n&cpu0 {\n\tclocks = <&zynqmp_clk 10>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&gpu {\n\tclocks = <&zynqmp_clk 24>, <&zynqmp_clk 25>, <&zynqmp_clk 26>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&nand0 {\n\tclocks = <&zynqmp_clk 60>, <&zynqmp_clk 31>;\n};\n\n&gem0 {\n\tclocks = <&zynqmp_clk 31>, <&zynqmp_clk 104>, <&zynqmp_clk 45>,\n\t\t <&zynqmp_clk 49>, <&zynqmp_clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem1 {\n\tclocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>, <&zynqmp_clk 46>,\n\t\t <&zynqmp_clk 50>, <&zynqmp_clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem2 {\n\tclocks = <&zynqmp_clk 31>, <&zynqmp_clk 106>, <&zynqmp_clk 47>,\n\t\t <&zynqmp_clk 51>, <&zynqmp_clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem3 {\n\tclocks = <&zynqmp_clk 31>, <&zynqmp_clk 107>, <&zynqmp_clk 48>,\n\t\t <&zynqmp_clk 52>, <&zynqmp_clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gpio {\n\tclocks = <&zynqmp_clk 31>;\n};\n\n&i2c0 {\n\tclocks = <&zynqmp_clk 61>;\n};\n\n&i2c1 {\n\tclocks = <&zynqmp_clk 62>;\n};\n\n&perf_monitor_ocm {\n\tclocks = <&zynqmp_clk 31>;\n};\n\n&perf_monitor_ddr {\n\tclocks = <&zynqmp_clk 28>;\n};\n\n&perf_monitor_cci {\n\tclocks = <&zynqmp_clk 28>;\n};\n\n&perf_monitor_lpd {\n\tclocks = <&zynqmp_clk 31>;\n};\n\n&pcie {\n\tclocks = <&zynqmp_clk 23>;\n};\n\n&qspi {\n\tclocks = <&zynqmp_clk 53>, <&zynqmp_clk 31>;\n};\n\n&sata {\n\tclocks = <&zynqmp_clk 22>;\n};\n\n&sdhci0 {\n\tclocks = <&zynqmp_clk 54>, <&zynqmp_clk 31>;\n};\n\n&sdhci1 {\n\tclocks = <&zynqmp_clk 55>, <&zynqmp_clk 31>;\n};\n\n&spi0 {\n\tclocks = <&zynqmp_clk 58>, <&zynqmp_clk 31>;\n};\n\n&spi1 {\n\tclocks = <&zynqmp_clk 59>, <&zynqmp_clk 31>;\n};\n\n&ttc0 {\n\tclocks = <&zynqmp_clk 31>;\n};\n\n&ttc1 {\n\tclocks = <&zynqmp_clk 31>;\n};\n\n&ttc2 {\n\tclocks = <&zynqmp_clk 31>;\n};\n\n&ttc3 {\n\tclocks = <&zynqmp_clk 31>;\n};\n\n&uart0 {\n\tclocks = <&zynqmp_clk 56>, <&zynqmp_clk 31>;\n};\n\n&uart1 {\n\tclocks = <&zynqmp_clk 57>, <&zynqmp_clk 31>;\n};\n\n&usb0 {\n\tclocks = <&zynqmp_clk 32>, <&zynqmp_clk 34>;\n};\n\n&usb1 {\n\tclocks = <&zynqmp_clk 33>, <&zynqmp_clk 34>;\n};\n\n&watchdog0 {\n\tclocks = <&zynqmp_clk 75>;\n};\n\n&lpd_watchdog {\n\tclocks = <&zynqmp_clk 112>;\n};\n\n&xilinx_ams {\n\tclocks = <&zynqmp_clk 70>;\n};\n\n&zynqmp_dpsub {\n\tclocks = <&dp_aclk>, <&zynqmp_clk 17>, <&zynqmp_clk 16>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&zynqmp_clk 20>;\n};\n\n&zynqmp_dp_snd_codec0 {\n\tclocks = <&zynqmp_clk 17>;\n};\n\n&pcap {\n\tclocks = <&zynqmp_clk 41>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.1/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"arm,psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t\txlnx,ipi-id = <0>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff990400 {\n\t\t\treg = <0x0 0xff9905c0 0x0 0x20>,\n\t\t\t <0x0 0xff9905e0 0x0 0x20>,\n\t\t\t <0x0 0xff990e80 0x0 0x20>,\n\t\t\t <0x0 0xff990ea0 0x0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <4>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tzynqmp_firmware: zynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x1>;\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tzynqmp_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\t\t};\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tnvmem_firmware {\n\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsoc_revision: soc_revision@0 {\n\t\t\treg = <0x0 0x4>;\n\t\t};\n\t\t/* efuse access */\n\t\tefuse_dna: efuse_dna@c {\n\t\t\treg = <0xc 0xc>;\n\t\t};\n\t\tefuse_usr0: efuse_usr0@20 {\n\t\t\treg = <0x20 0x4>;\n\t\t};\n\t\tefuse_usr1: efuse_usr1@24 {\n\t\t\treg = <0x24 0x4>;\n\t\t};\n\t\tefuse_usr2: efuse_usr2@28 {\n\t\t\treg = <0x28 0x4>;\n\t\t};\n\t\tefuse_usr3: efuse_usr3@2c {\n\t\t\treg = <0x2c 0x4>;\n\t\t};\n\t\tefuse_usr4: efuse_usr4@30 {\n\t\t\treg = <0x30 0x4>;\n\t\t};\n\t\tefuse_usr5: efuse_usr5@34 {\n\t\t\treg = <0x34 0x4>;\n\t\t};\n\t\tefuse_usr6: efuse_usr6@38 {\n\t\t\treg = <0x38 0x4>;\n\t\t};\n\t\tefuse_usr7: efuse_usr7@3c {\n\t\t\treg = <0x3c 0x4>;\n\t\t};\n\t\tefuse_miscusr: efuse_miscusr@40 {\n\t\t\treg = <0x40 0x4>;\n\t\t};\n\t\tefuse_chash: efuse_chash@50 {\n\t\t\treg = <0x50 0x4>;\n\t\t};\n\t\tefuse_pufmisc: efuse_pufmisc@54 {\n\t\t\treg = <0x54 0x4>;\n\t\t};\n\t\tefuse_sec: efuse_sec@58 {\n\t\t\treg = <0x58 0x4>;\n\t\t};\n\t\tefuse_spkid: efuse_spkid@5c {\n\t\t\treg = <0x5c 0x4>;\n\t\t};\n\t\tefuse_ppk0hash: efuse_ppk0hash@a0 {\n\t\t\treg = <0xa0 0x30>;\n\t\t};\n\t\tefuse_ppk1hash: efuse_ppk1hash@d0 {\n\t\t\treg = <0xd0 0x30>;\n\t\t};\n\t};\n\n\tpcap: pcap {\n\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t\tclock-names = \"ref_clk\";\n\t};\n\n\txlnx_rsa: zynqmp_rsa {\n\t\tcompatible = \"xlnx,zynqmp-rsa\";\n\t};\n\n\txlnx_keccak_384: sha384 {\n\t\tcompatible = \"xlnx,zynqmp-keccak-384\";\n\t};\n\n\txlnx_aes: zynqmp_aes {\n\t\tcompatible = \"xlnx,zynqmp-aes\";\n\t};\n\n\tamba_apu: amba_apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tsmmu: smmu@fd800000 {\n\t\tcompatible = \"arm,mmu-500\";\n\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t#iommu-cells = <1>;\n\t\tstatus = \"disabled\";\n\t\t#global-interrupts = <1>;\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware 47>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware 48>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\", \"gpu_pp0\", \"gpu_pp1\";\n\t\t\tpower-domains = <&zynqmp_firmware 58>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&zynqmp_firmware 44>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&zynqmp_firmware 29>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&zynqmp_firmware 30>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&zynqmp_firmware 31>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&zynqmp_firmware 32>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tpower-domains = <&zynqmp_firmware 46>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware 37>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware 38>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tperf_monitor_ocm: perf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa00000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_ddr: perf-monitor@fd0b0000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd0b0000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <6>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <10>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_cci: perf-monitor@fd490000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd490000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_lpd: perf-monitor@ffa10000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa10000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpower-domains = <&zynqmp_firmware 59>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&zynqmp_firmware 45>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tserdes: zynqmp_phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\";\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\tresets = <&zynqmp_reset 16>, <&zynqmp_reset 59>,\n\t\t\t\t <&zynqmp_reset 60>, <&zynqmp_reset 61>,\n\t\t\t\t <&zynqmp_reset 62>, <&zynqmp_reset 63>,\n\t\t\t\t <&zynqmp_reset 64>, <&zynqmp_reset 3>,\n\t\t\t\t <&zynqmp_reset 29>, <&zynqmp_reset 30>,\n\t\t\t\t <&zynqmp_reset 31>, <&zynqmp_reset 32>;\n\t\t\treset-names = \"sata_rst\", \"usb0_crst\", \"usb1_crst\",\n\t\t\t\t \"usb0_hibrst\", \"usb1_hibrst\", \"usb0_apbrst\",\n\t\t\t\t \"usb1_apbrst\", \"dp_rst\", \"gem0_rst\",\n\t\t\t\t \"gem1_rst\", \"gem2_rst\", \"gem3_rst\";\n\t\t\tlane0: lane0 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane1: lane1 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane2: lane2 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane3: lane3 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&zynqmp_firmware 28>;\n\t\t\t#stream-id-cells = <4>;\n\t\t/*\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;*/\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&zynqmp_firmware 39>;\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&zynqmp_firmware 40>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware 35>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware 36>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware 24>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware 25>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware 26>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware 27>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware 33>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware 34>;\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware 22>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>, <0 75 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t\t/* snps,enable-hibernation; */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb1@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware 23>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>, <0 76 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <60>;\n\t\t\treset-on-timeout;\n\t\t};\n\n\t\tlpd_watchdog: watchdog@ff150000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 52 1>;\n\t\t\treg = <0x0 0xff150000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges;\n\n\t\t\tams_ps: ams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50800 0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50c00 0x0 0x400>;\n\t\t\t};\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware 41>;\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\n\t\tzynqmp_dpsub: zynqmp-display@fd4a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"dp\", \"blend\", \"av_buf\", \"aud\";\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"dp_apb_clk\", \"dp_aud_clk\", \"dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <&zynqmp_firmware 41>;\n\n\t\t\tvid-layer {\n\t\t\t\tdma-names = \"vid0\", \"vid1\", \"vid2\";\n\t\t\t\tdmas = <&xlnx_dpdma 0>,\n\t\t\t\t <&xlnx_dpdma 1>,\n\t\t\t\t <&xlnx_dpdma 2>;\n\t\t\t};\n\n\t\t\tgfx-layer {\n\t\t\t\tdma-names = \"gfx0\";\n\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t};\n\n\t\t\t/* dummy node to to indicate there's no child i2c device */\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&xlnx_dpdma 4>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&xlnx_dpdma 5>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card0: zynqmp_dp_snd_card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,\n\t\t\t\t\t\t <&zynqmp_dp_snd_pcm1>;\n\t\t\t\txlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/sp701-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze sp701.\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@1 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x3>;\n\t\t\tti,tx-internal-delay = <0x3>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/vcu118-rev2.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze vcu118\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@3 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\tti,6-wire-mode;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\treg = <3>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/versal-v350-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal v350 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tcompatible = \"xlnx,versal-v350-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal v350 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&serial1 {\n\tstatus = \"disabled\"; /* communication with MSP432 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n compatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n \"xlnx,versal-vc-p-a2197-00\",\n \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n model = \"Xilinx Versal A2197 Processor board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\n};\n\n&rtc {\n status = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&watchdog {\n status = \"okay\";\n};\n\n&qspi {\n status = \"disabled\"; /* u93 and u92 */\n};\n\n&ospi {\n\tstatus = \"okay\";\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"ospi-fsbl-uboot-boot.bin\";\n\t\t\treg = <0x0 0x6400000>;\n\t\t};\n\t\tpartition@6400000 { /* for testing purpose */\n\t\t\tlabel = \"ospi-linux\";\n\t\t\treg = <0x6400000 0x500000>;\n\t\t};\n\t\tpartition@6900000 { /* for testing purpose */\n\t\t\tlabel = \"ospi-device-tree\";\n\t\t\treg = <0x6900000 0x20000>;\n\t\t};\n\t\tpartition@6920000 { /* for testing purpose */\n\t\t\tlabel = \"ospi-rootfs\";\n\t\t\treg = <0x6920000 0xa00000>;\n\t\t};\n\t\tpartition@7f40000 {\n\t\t\tlabel = \"ospi-bootenv\";\n\t\t\treg = <0x7f40000 0x40000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* U104 */\n\tstatus = \"okay\";\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 {\n status = \"okay\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n compatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n \"xlnx,versal-vc-p-a2197-00\",\n \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n model = \"Xilinx Versal A2197 Processor board revA\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tgpio0 = &gpio;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n\n};\n\n&gpio {\n\tstatus = \"okay\";\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&qspi {\n status = \"okay\"; /* u93 and u92 */\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci1 { /* U104 */\n\tstatus = \"okay\";\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 {\n status = \"okay\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n compatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n \"xlnx,versal-vc-p-a2197-00\",\n \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n model = \"Xilinx Versal A2197 Processor board revA\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&qspi {\n status = \"okay\"; /* u93 and u92 */\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot-boot.bin\";\n\t\t\treg = <0x0 0x6400000>;\n\t\t};\n\t\tpartition@6400000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x6400000 0x500000>;\n\t\t};\n\t\tpartition@6900000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x6900000 0x20000>;\n\t\t};\n\t\tpartition@6920000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x6920000 0x5E0000>;\n\t\t};\n\t\tpartition@7f40000 {\n\t\t\tlabel = \"qspi-bootenv\";\n\t\t\treg = <0x7f40000 0x40000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* U104 */\n\tstatus = \"okay\";\n\txlnx,mio_bank = <1>;\n};\n\n&serial0 {\n status = \"okay\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n compatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n \"xlnx,versal-vc-p-a2197-00\",\n \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n model = \"Xilinx Versal A2197 Processor board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>; /* u9 */\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@1 { /* Marvell 88E1512; U9 */\n\t\treg = <1>;\n\t};\n};\n\n\n&sdhci0 {\n\tstatus = \"okay\";\n\txlnx,mio_bank = <1>;\n};\n\n&sdhci1 { /* U1A */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* U4 */\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"high-speed\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\t/* U12 Catalyst EEPROM - AT24 should be equivalent */\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U13 and U15 */\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tflash@0 { /* U18 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25vf016b\", \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tnum-cs = <3>;\t/* FIXME - check SPI1_SS0-2_B */\n\n\tflash@0 { /* U19 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@1 {\n\t\t\tlabel = \"spi1-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n compatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n \"xlnx,versal-vc-p-a2197-00\",\n \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n model = \"Xilinx Versal A2197 Processor board revA\";\n\t\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\t\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tserial0 = &serial0;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t};\n};\n\n&dcc {\n status = \"okay\";\n};\n\n/* SMAP via cc108 */\n&can0 {\n\tstatus = \"okay\";\n};\n\n&can1 {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\t/* Must be enabled via J90/J91 */\n\teeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\"; /* u7 */\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <1>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 64Mb */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x800000>;\n\t\t};\n\t};\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&sdhci0 { /* J99 MIO28 - MIO33 */\n\tstatus = \"okay\";\n\txlnx,mio_bank = <1>; /* FIXME */\n};\n\n&sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>; /* FIXME */\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tflash@0 { /* U6 - IS25LQ032B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lq032b\", \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t\t\"xlnx,versal-vc-p-a2197-00\",\n\t\t\t\"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <1>; /* FIXME */\n\t};\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"disabled\"; /* u93 and u92 and u161 and u160 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n/* Mutually exclusive with qspi */\n&ospi {\n\tstatus = \"okay\"; /* U163/U97 MT35XU02G */\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tstatus = \"okay\";\n\tdisable-wp;\n\txlnx,mio_bank = <1>; /* FIXME */\n};\n\n&serial0 { /* MIO35 - MIO37 */\n\tstatus = \"okay\";\n};\n\n&serial1 { /* MIO4 - MIO7 RS232 */\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t\t\"xlnx,versal-vc-p-a2197-00\",\n\t\t\t\"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <2>;\n\t};\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\"; /* u93 and u92 and u161 and u160 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 512MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x20000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tstatus = \"okay\";\n\tdisable-wp;\n\txlnx,mio_bank = <1>; /* FIXME */\n};\n\n&serial0 { /* MIO35 - MIO37 */\n\tstatus = \"okay\";\n};\n\n&serial1 { /* MIO4 - MIO7 RS232 */\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t\t\"xlnx,versal-vc-p-a2197-00\",\n\t\t\t\"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA\";\n\t\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 { /* 88e1510 */\n\t\treg = <1>; /* FIXME */\n\t};\n\tphy2: phy@2 { /* VSC8531 */\n\t\treg = <2>; /* FIXME */\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>;\n\tphy-mode = \"rgmii-id\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <0x1>;\n\tspi-tx-bus-width = <1>;\n\tspi-rx-bus-width = <4>;\n\n\tflash@0 { /* MX25U12835 128Mbit */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 16MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <104000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x1000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc0 */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>; /* FIXME */\n};\n\n&sdhci1 { /* connector */\n\tstatus = \"okay\";\n\txlnx,mio_bank = <1>; /* FIXME */\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA\";\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA (QSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\tstatus = \"okay\";\n\txlnx,mio_bank = <1>;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&qspi {\n status = \"okay\";\n num-cs = <1>;\n spi-tx-bus-width = <1>;\n spi-rx-bus-width = <4>;\n #address-cells = <1>;\n #size-cells = <0>;\n is-dual = <1>;\n flash@0 {\n #address-cells = <1>;\n #size-cells = <1>;\n compatible = \"m25p80\", \"spi-flash\"; /* 256MB */\n reg = <0>;\n spi-tx-bus-width = <1>;\n spi-rx-bus-width = <4>;\n spi-max-frequency = <104000000>;\n partition@0 {\n label = \"spi0-flash0\";\n reg = <0x0 0x10000000>;\n };\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vck190-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\tstatus = \"okay\";\n\txlnx,mio_bank = <1>;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA (QSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\tstatus = \"okay\";\n\txlnx,mio_bank = <1>;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\tspi-tx-bus-width = <1>;\n\tspi-rx-bus-width = <4>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tis-dual = <1>;\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* 256MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <104000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x10000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vmk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\tstatus = \"okay\";\n\txlnx,mio_bank = <1>;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 3 150000000>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: ethernet-phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: flash@0 {\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: flash@0 {\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t\tsw13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@52 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <52>;\n\t\t\t};\n\t\t\thwmon@53 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <53>;\n\t\t\t};\n\t\t\thwmon@54 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&watchdog0 {\n\treset-on-timeout;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zcu100-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio_bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zcu100-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,rxctrl-strap-worka;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@20 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zcu104-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revC\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - IRPS5401_ALERT_B\n\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t * 2 - MAX6643_OT_B\n\t\t * 3 - MAX6643_FANFAIL_B\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t * 4, 10 - 17 - not connected\n\t\t */\n\t};\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tu183: ina226@40 { /* u183 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 4, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\txlnx,mio_bank = <1>;\n\tdisable-wp;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u67 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;\n\t};\n\tina226-u59 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n\tina226-u69 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;\n\t};\n\tina226-u66 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;\n\t};\n\tina226-u71 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u73 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tu67: ina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u67\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu59: ina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u59\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu61: ina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu60: ina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu64: ina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu69: ina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u69\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu66: ina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u66\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu63: ina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu3: ina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u3\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu71: ina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u71\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu73: ina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u73\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps54012@44 { /* IRPS5401 - u55 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps54012@45 { /* IRPS5401 - u57 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 { /* SI5328 - u48 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection FIXME */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revA\", \"xlnx,zynqmp-zcu1275\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1275-revb.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU1275 RevB\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revB\", \"xlnx,zynqmp-zcu1275\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t* 1.0 revision has level shifter and this property should be\n\t* removed for supporting UHS mode\n\t*/\n\tno-1-8-v;\n};\n\n&gem1 {\n\tpsu_ethernet_1_mdio: mdio {\n\t\tphy1: ethernet-phy@1 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1285-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU1285 RevA\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1285 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1285-revA\", \"xlnx,zynqmp-zcu1285\", \"xlnx,zynqmp\";\n\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PMBUS */\n\t\t\tmax20751@74 { /* u23 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x74>;\n\t\t\t};\n\t\t\tmax20751@70 { /* u89 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x70>;\n\t\t\t};\n\t\t\tmax15301@a { /* u28 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u48 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@d { /* u27 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\tmax15303@e { /* u11 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\tmax15303@f { /* u96 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\tmax15303@11 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\tmax15303@12 { /* u24 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u29 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u51 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u30 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u102 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15301@17 { /* u50 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u31 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* CM_I2C */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYS_EEPROM */\n\t\t\teeprom: eeprom@54 { /* u101 */\n\t\t\t\tcompatible = \"atmel,24c32\"; /* 24LC32A */\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FMC1 */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FMC2 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* ANALOG_PMBUS */\n\t\t\tu60: ina226@40 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu61: ina226@41 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu63: ina226@42 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu65: ina226@43 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu64: ina226@44 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* ANALOG_CM_I2C */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FMC3 */\n\t\t};\n\t};\n};\n\n&gem1 {\n\tmdio {\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy2>;\n\tphy2: ethernet-phy@1 {\n\t\treg = <1>; /* KSZ9031RNXIC */\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zcu216-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU216\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU216 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu216-revA\", \"xlnx,zynqmp-zcu216\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps54012@44 { /* IRPS5401 - u53 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps54012@45 { /* IRPS5401 - u55 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zynqmp-a2197-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Versal System Controller on a2197 board RevA\";\n\tcompatible = \"xlnx,zynqmp-a2197-revA\", \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>;\n\t};\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* this cover MGT board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* This cover processor board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/BOARD/zynqmp-e-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevA\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vcc-soc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;\n\t};\n\tina226-vcc-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc-pslp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;\n\t};\n\tina226-vcc-psfp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;\n\t};\n\tina226-vccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;\n\t};\n\tina226-vccaux-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;\n\t};\n\tina226-vcco-500 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;\n\t};\n\tina226-vcco-501 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;\n\t};\n\tina226-vcco-502 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;\n\t};\n\tina226-vcco-503 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;\n\t};\n\tina226-vcc-1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;\n\t};\n\tina226-vcc-3v3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;\n\t};\n\tina226-vcc-1v2-ddr4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;\n\t};\n\tina226-vcc-1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtyavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;\n\t};\n\tina226-mgtyavtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;\n\t};\n\tina226-mgtyvccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;\n\t};\n\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* u131 M88E1512 */\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"ZU4_TRIGGER\", \"SYSCTLR_PB\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t\n\t\t\t/* u152 IR35215 0x16/0x46 vcc_soc */ \n\t\t\t/* u160 IRPS5401 0x17/0x47 */\n\t\t\t/* u167 IRPS5401 0x1c/0x4c */\n\t\t\t/* u175 IRPS5401 0x1d/0x4d */\n\t\t\t/* u179 ir38164 0x19/0x49 vcco_500 */\n\t\t\t/* u181 ir38164 0x1a/0x4a vcco_501 */\n\t\t\t/* u183 ir38164 0x1b/0x4b vcco_502 */\n\t\t\t/* u185 ir38164 0x1e/0x4e vadj_fmc */\n\t\t\t/* u187 ir38164 0x1F/0x4f mgtyavcc */\n\t\t\t/* u189 ir38164 0x20/0x50 mgtyavtt */\n\t\t\t/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */\n\t\t\t/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* R440 */\n\t\t\t\t/* 0.78V @ 32A 1 of 6 Phases*/\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-soc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <2000>; /* R1186 */\n\t\t\t\t/* 0.78V @ 18A */\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pmc\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* R1214 */\n\t\t\t\t/* 0.78V @ 500mA */\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u162 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r1221 */\n\t\t\t\t/* 0.78V @ 4A */\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pslp\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>; /* R1216 */\n\t\t\t\t/* 0.78V @ 1A */\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-psfp\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1219 */\n\t\t\t\t/* 0.78V @ 2A */\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* R382 */\n\t\t\t\t/* 1.5V @ 3A */\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux-pmc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>; /* R1246 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u178 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-500\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>; /* R1300 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u180 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-501\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <2000>; /* R1313 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u182 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-502\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <2000>; /* R1330 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-503\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1229 */\n\t\t\t\t/* 1.8V @ 2A */\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u173 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v8\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>; /* R400 */\n\t\t\t\t/* 1.8V @ 6A */\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-3v3\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* R1232 */\n\t\t\t\t/* 3.3V @ 500mA */\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v2-ddr4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>; /* R1275 */\n\t\t\t\t/* 1.2V @ 4A */\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>; /* R1286 */\n\t\t\t\t/* 1.1V @ 4A */\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>; /* R1350 */\n\t\t\t\t/* 1.5V @ 10A */\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavcc\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <2000>; /* R1367 */\n\t\t\t\t/* 0.88V @ 6A */\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavtt\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>; /* R1384 */\n\t\t\t\t/* 1.2V @ 10A */\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyvccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>; /* r1679 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t\ti2c@5 { /* zSFP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_zsfp: clock-generator@5d { /* u192 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* USER_SI570_1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_user1_clk: clock-generator@5d { /* u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>; /* FIXME check address */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"si570_user1\";\n\t\t\t};\n\n\t\t};\n\t\ti2c@7 { /* USER_SI570_2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* 0x5c too */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t};\n\t\t\t/* and connector J212D */\n\t\t};\n\t\tfmc1: i2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t};\n\t\tfmc2: i2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LPDDR4_SI570_CLK2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* 8A34001 - U219B and J310 connector */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/gpio/gpio.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most GPIO bindings.\n *\n * Most GPIO bindings include a flags cell as part of the GPIO specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_GPIO_GPIO_H\n#define _DT_BINDINGS_GPIO_GPIO_H\n\n/* Bit 0 express polarity */\n#define GPIO_ACTIVE_HIGH 0\n#define GPIO_ACTIVE_LOW 1\n\n/* Bit 1 express single-endedness */\n#define GPIO_PUSH_PULL 0\n#define GPIO_SINGLE_ENDED 2\n\n/* Bit 2 express Open drain or open source */\n#define GPIO_LINE_OPEN_SOURCE 0\n#define GPIO_LINE_OPEN_DRAIN 4\n\n/*\n * * Open Drain/Collector is the combination of single-ended open drain interface.\n * * Open Source/Emitter is the combination of single-ended open source interface.\n * */\n#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)\n#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)\n\n/* Bit 3 express GPIO suspend/resume persistence */\n#define GPIO_SLEEP_MAINTAIN_VALUE 0\n#define GPIO_SLEEP_MAY_LOOSE_VALUE 8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/input/input.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most input bindings.\n *\n * Most input bindings include key code, matrix key code format.\n * In most cases, key code and matrix key code format uses\n * the standard values/macro defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INPUT_INPUT_H\n#define _DT_BINDINGS_INPUT_INPUT_H\n\n/*\n * Device properties and quirks\n */\n\n#define INPUT_PROP_POINTER\t\t0x00\t/* needs a pointer */\n#define INPUT_PROP_DIRECT\t\t0x01\t/* direct input devices */\n#define INPUT_PROP_BUTTONPAD\t\t0x02\t/* has button(s) under pad */\n#define INPUT_PROP_SEMI_MT\t\t0x03\t/* touch rectangle only */\n#define INPUT_PROP_TOPBUTTONPAD\t\t0x04\t/* softbuttons at top of pad */\n#define INPUT_PROP_POINTING_STICK\t0x05\t/* is a pointing stick */\n#define INPUT_PROP_ACCELEROMETER\t0x06\t/* has accelerometer */\n\n#define INPUT_PROP_MAX\t\t\t0x1f\n#define INPUT_PROP_CNT\t\t\t(INPUT_PROP_MAX + 1)\n\n\n/*\n * Event types\n */\n\n#define EV_SYN\t\t\t0x00\n#define EV_KEY\t\t\t0x01\n#define EV_REL\t\t\t0x02\n#define EV_ABS\t\t\t0x03\n#define EV_MSC\t\t\t0x04\n#define EV_SW\t\t\t0x05\n#define EV_LED\t\t\t0x11\n#define EV_SND\t\t\t0x12\n#define EV_REP\t\t\t0x14\n#define EV_FF\t\t\t0x15\n#define EV_PWR\t\t\t0x16\n#define EV_FF_STATUS\t\t0x17\n#define EV_MAX\t\t\t0x1f\n#define EV_CNT\t\t\t(EV_MAX+1)\n\n/*\n * Synchronization events.\n */\n\n#define SYN_REPORT\t\t0\n#define SYN_CONFIG\t\t1\n#define SYN_MT_REPORT\t\t2\n#define SYN_DROPPED\t\t3\n#define SYN_MAX\t\t\t0xf\n#define SYN_CNT\t\t\t(SYN_MAX+1)\n\n/*\n * Keys and buttons\n *\n * Most of the keys/buttons are modeled after USB HUT 1.12\n * (see http://www.usb.org/developers/hidpage).\n * Abbreviations in the comments:\n * AC - Application Control\n * AL - Application Launch Button\n * SC - System Control\n */\n\n#define KEY_RESERVED\t\t0\n#define KEY_ESC\t\t\t1\n#define KEY_1\t\t\t2\n#define KEY_2\t\t\t3\n#define KEY_3\t\t\t4\n#define KEY_4\t\t\t5\n#define KEY_5\t\t\t6\n#define KEY_6\t\t\t7\n#define KEY_7\t\t\t8\n#define KEY_8\t\t\t9\n#define KEY_9\t\t\t10\n#define KEY_0\t\t\t11\n#define KEY_MINUS\t\t12\n#define KEY_EQUAL\t\t13\n#define KEY_BACKSPACE\t\t14\n#define KEY_TAB\t\t\t15\n#define KEY_Q\t\t\t16\n#define KEY_W\t\t\t17\n#define KEY_E\t\t\t18\n#define KEY_R\t\t\t19\n#define KEY_T\t\t\t20\n#define KEY_Y\t\t\t21\n#define KEY_U\t\t\t22\n#define KEY_I\t\t\t23\n#define KEY_O\t\t\t24\n#define KEY_P\t\t\t25\n#define KEY_LEFTBRACE\t\t26\n#define KEY_RIGHTBRACE\t\t27\n#define KEY_ENTER\t\t28\n#define KEY_LEFTCTRL\t\t29\n#define KEY_A\t\t\t30\n#define KEY_S\t\t\t31\n#define KEY_D\t\t\t32\n#define KEY_F\t\t\t33\n#define KEY_G\t\t\t34\n#define KEY_H\t\t\t35\n#define KEY_J\t\t\t36\n#define KEY_K\t\t\t37\n#define KEY_L\t\t\t38\n#define KEY_SEMICOLON\t\t39\n#define KEY_APOSTROPHE\t\t40\n#define KEY_GRAVE\t\t41\n#define KEY_LEFTSHIFT\t\t42\n#define KEY_BACKSLASH\t\t43\n#define KEY_Z\t\t\t44\n#define KEY_X\t\t\t45\n#define KEY_C\t\t\t46\n#define KEY_V\t\t\t47\n#define KEY_B\t\t\t48\n#define KEY_N\t\t\t49\n#define KEY_M\t\t\t50\n#define KEY_COMMA\t\t51\n#define KEY_DOT\t\t\t52\n#define KEY_SLASH\t\t53\n#define KEY_RIGHTSHIFT\t\t54\n#define KEY_KPASTERISK\t\t55\n#define KEY_LEFTALT\t\t56\n#define KEY_SPACE\t\t57\n#define KEY_CAPSLOCK\t\t58\n#define KEY_F1\t\t\t59\n#define KEY_F2\t\t\t60\n#define KEY_F3\t\t\t61\n#define KEY_F4\t\t\t62\n#define KEY_F5\t\t\t63\n#define KEY_F6\t\t\t64\n#define KEY_F7\t\t\t65\n#define KEY_F8\t\t\t66\n#define KEY_F9\t\t\t67\n#define KEY_F10\t\t\t68\n#define KEY_NUMLOCK\t\t69\n#define KEY_SCROLLLOCK\t\t70\n#define KEY_KP7\t\t\t71\n#define KEY_KP8\t\t\t72\n#define KEY_KP9\t\t\t73\n#define KEY_KPMINUS\t\t74\n#define KEY_KP4\t\t\t75\n#define KEY_KP5\t\t\t76\n#define KEY_KP6\t\t\t77\n#define KEY_KPPLUS\t\t78\n#define KEY_KP1\t\t\t79\n#define KEY_KP2\t\t\t80\n#define KEY_KP3\t\t\t81\n#define KEY_KP0\t\t\t82\n#define KEY_KPDOT\t\t83\n\n#define KEY_ZENKAKUHANKAKU\t85\n#define KEY_102ND\t\t86\n#define KEY_F11\t\t\t87\n#define KEY_F12\t\t\t88\n#define KEY_RO\t\t\t89\n#define KEY_KATAKANA\t\t90\n#define KEY_HIRAGANA\t\t91\n#define KEY_HENKAN\t\t92\n#define KEY_KATAKANAHIRAGANA\t93\n#define KEY_MUHENKAN\t\t94\n#define KEY_KPJPCOMMA\t\t95\n#define KEY_KPENTER\t\t96\n#define KEY_RIGHTCTRL\t\t97\n#define KEY_KPSLASH\t\t98\n#define KEY_SYSRQ\t\t99\n#define KEY_RIGHTALT\t\t100\n#define KEY_LINEFEED\t\t101\n#define KEY_HOME\t\t102\n#define KEY_UP\t\t\t103\n#define KEY_PAGEUP\t\t104\n#define KEY_LEFT\t\t105\n#define KEY_RIGHT\t\t106\n#define KEY_END\t\t\t107\n#define KEY_DOWN\t\t108\n#define KEY_PAGEDOWN\t\t109\n#define KEY_INSERT\t\t110\n#define KEY_DELETE\t\t111\n#define KEY_MACRO\t\t112\n#define KEY_MUTE\t\t113\n#define KEY_VOLUMEDOWN\t\t114\n#define KEY_VOLUMEUP\t\t115\n#define KEY_POWER\t\t116\t/* SC System Power Down */\n#define KEY_KPEQUAL\t\t117\n#define KEY_KPPLUSMINUS\t\t118\n#define KEY_PAUSE\t\t119\n#define KEY_SCALE\t\t120\t/* AL Compiz Scale (Expose) */\n\n#define KEY_KPCOMMA\t\t121\n#define KEY_HANGEUL\t\t122\n#define KEY_HANGUEL\t\tKEY_HANGEUL\n#define KEY_HANJA\t\t123\n#define KEY_YEN\t\t\t124\n#define KEY_LEFTMETA\t\t125\n#define KEY_RIGHTMETA\t\t126\n#define KEY_COMPOSE\t\t127\n#define KEY_STOP\t\t128\t/* AC Stop */\n#define KEY_AGAIN\t\t129\n#define KEY_PROPS\t\t130\t/* AC Properties */\n#define KEY_UNDO\t\t131\t/* AC Undo */\n#define KEY_FRONT\t\t132\n#define KEY_COPY\t\t133\t/* AC Copy */\n#define KEY_OPEN\t\t134\t/* AC Open */\n#define KEY_PASTE\t\t135\t/* AC Paste */\n#define KEY_FIND\t\t136\t/* AC Search */\n#define KEY_CUT\t\t\t137\t/* AC Cut */\n#define KEY_HELP\t\t138\t/* AL Integrated Help Center */\n#define KEY_MENU\t\t139\t/* Menu (show menu) */\n#define KEY_CALC\t\t140\t/* AL Calculator */\n#define KEY_SETUP\t\t141\n#define KEY_SLEEP\t\t142\t/* SC System Sleep */\n#define KEY_WAKEUP\t\t143\t/* System Wake Up */\n#define KEY_FILE\t\t144\t/* AL Local Machine Browser */\n#define KEY_SENDFILE\t\t145\n#define KEY_DELETEFILE\t\t146\n#define KEY_XFER\t\t147\n#define KEY_PROG1\t\t148\n#define KEY_PROG2\t\t149\n#define KEY_WWW\t\t\t150\t/* AL Internet Browser */\n#define KEY_MSDOS\t\t151\n#define KEY_COFFEE\t\t152\t/* AL Terminal Lock/Screensaver */\n#define KEY_SCREENLOCK\t\tKEY_COFFEE\n#define KEY_ROTATE_DISPLAY\t153\t/* Display orientation for e.g. tablets */\n#define KEY_DIRECTION\t\tKEY_ROTATE_DISPLAY\n#define KEY_CYCLEWINDOWS\t154\n#define KEY_MAIL\t\t155\n#define KEY_BOOKMARKS\t\t156\t/* AC Bookmarks */\n#define KEY_COMPUTER\t\t157\n#define KEY_BACK\t\t158\t/* AC Back */\n#define KEY_FORWARD\t\t159\t/* AC Forward */\n#define KEY_CLOSECD\t\t160\n#define KEY_EJECTCD\t\t161\n#define KEY_EJECTCLOSECD\t162\n#define KEY_NEXTSONG\t\t163\n#define KEY_PLAYPAUSE\t\t164\n#define KEY_PREVIOUSSONG\t165\n#define KEY_STOPCD\t\t166\n#define KEY_RECORD\t\t167\n#define KEY_REWIND\t\t168\n#define KEY_PHONE\t\t169\t/* Media Select Telephone */\n#define KEY_ISO\t\t\t170\n#define KEY_CONFIG\t\t171\t/* AL Consumer Control Configuration */\n#define KEY_HOMEPAGE\t\t172\t/* AC Home */\n#define KEY_REFRESH\t\t173\t/* AC Refresh */\n#define KEY_EXIT\t\t174\t/* AC Exit */\n#define KEY_MOVE\t\t175\n#define KEY_EDIT\t\t176\n#define KEY_SCROLLUP\t\t177\n#define KEY_SCROLLDOWN\t\t178\n#define KEY_KPLEFTPAREN\t\t179\n#define KEY_KPRIGHTPAREN\t180\n#define KEY_NEW\t\t\t181\t/* AC New */\n#define KEY_REDO\t\t182\t/* AC Redo/Repeat */\n\n#define KEY_F13\t\t\t183\n#define KEY_F14\t\t\t184\n#define KEY_F15\t\t\t185\n#define KEY_F16\t\t\t186\n#define KEY_F17\t\t\t187\n#define KEY_F18\t\t\t188\n#define KEY_F19\t\t\t189\n#define KEY_F20\t\t\t190\n#define KEY_F21\t\t\t191\n#define KEY_F22\t\t\t192\n#define KEY_F23\t\t\t193\n#define KEY_F24\t\t\t194\n\n#define KEY_PLAYCD\t\t200\n#define KEY_PAUSECD\t\t201\n#define KEY_PROG3\t\t202\n#define KEY_PROG4\t\t203\n#define KEY_DASHBOARD\t\t204\t/* AL Dashboard */\n#define KEY_SUSPEND\t\t205\n#define KEY_CLOSE\t\t206\t/* AC Close */\n#define KEY_PLAY\t\t207\n#define KEY_FASTFORWARD\t\t208\n#define KEY_BASSBOOST\t\t209\n#define KEY_PRINT\t\t210\t/* AC Print */\n#define KEY_HP\t\t\t211\n#define KEY_CAMERA\t\t212\n#define KEY_SOUND\t\t213\n#define KEY_QUESTION\t\t214\n#define KEY_EMAIL\t\t215\n#define KEY_CHAT\t\t216\n#define KEY_SEARCH\t\t217\n#define KEY_CONNECT\t\t218\n#define KEY_FINANCE\t\t219\t/* AL Checkbook/Finance */\n#define KEY_SPORT\t\t220\n#define KEY_SHOP\t\t221\n#define KEY_ALTERASE\t\t222\n#define KEY_CANCEL\t\t223\t/* AC Cancel */\n#define KEY_BRIGHTNESSDOWN\t224\n#define KEY_BRIGHTNESSUP\t225\n#define KEY_MEDIA\t\t226\n\n#define KEY_SWITCHVIDEOMODE\t227\t/* Cycle between available video\n\t\t\t\t\t outputs (Monitor/LCD/TV-out/etc) */\n#define KEY_KBDILLUMTOGGLE\t228\n#define KEY_KBDILLUMDOWN\t229\n#define KEY_KBDILLUMUP\t\t230\n\n#define KEY_SEND\t\t231\t/* AC Send */\n#define KEY_REPLY\t\t232\t/* AC Reply */\n#define KEY_FORWARDMAIL\t\t233\t/* AC Forward Msg */\n#define KEY_SAVE\t\t234\t/* AC Save */\n#define KEY_DOCUMENTS\t\t235\n\n#define KEY_BATTERY\t\t236\n\n#define KEY_BLUETOOTH\t\t237\n#define KEY_WLAN\t\t238\n#define KEY_UWB\t\t\t239\n\n#define KEY_UNKNOWN\t\t240\n#define KEY_VIDEO_NEXT\t\t241\t/* drive next video source */\n#define KEY_VIDEO_PREV\t\t242\t/* drive previous video source */\n#define KEY_BRIGHTNESS_CYCLE\t243\t/* brightness up, after max is min */\n#define KEY_BRIGHTNESS_AUTO\t244\t/* Set Auto Brightness: manual\n\t\t\t\t\t brightness control is off,\n\t\t\t\t\t rely on ambient */\n#define KEY_BRIGHTNESS_ZERO\tKEY_BRIGHTNESS_AUTO\n#define KEY_DISPLAY_OFF\t\t245\t/* display device to off state */\n\n#define KEY_WWAN\t\t246\t/* Wireless WAN (LTE, UMTS, GSM, etc.) */\n#define KEY_WIMAX\t\tKEY_WWAN\n#define KEY_RFKILL\t\t247\t/* Key that controls all radios */\n\n#define KEY_MICMUTE\t\t248\t/* Mute / unmute the microphone */\n\n/* Code 255 is reserved for special needs of AT keyboard driver */\n\n#define BTN_MISC\t\t0x100\n#define BTN_0\t\t\t0x100\n#define BTN_1\t\t\t0x101\n#define BTN_2\t\t\t0x102\n#define BTN_3\t\t\t0x103\n#define BTN_4\t\t\t0x104\n#define BTN_5\t\t\t0x105\n#define BTN_6\t\t\t0x106\n#define BTN_7\t\t\t0x107\n#define BTN_8\t\t\t0x108\n#define BTN_9\t\t\t0x109\n\n#define BTN_MOUSE\t\t0x110\n#define BTN_LEFT\t\t0x110\n#define BTN_RIGHT\t\t0x111\n#define BTN_MIDDLE\t\t0x112\n#define BTN_SIDE\t\t0x113\n#define BTN_EXTRA\t\t0x114\n#define BTN_FORWARD\t\t0x115\n#define BTN_BACK\t\t0x116\n#define BTN_TASK\t\t0x117\n\n#define BTN_JOYSTICK\t\t0x120\n#define BTN_TRIGGER\t\t0x120\n#define BTN_THUMB\t\t0x121\n#define BTN_THUMB2\t\t0x122\n#define BTN_TOP\t\t\t0x123\n#define BTN_TOP2\t\t0x124\n#define BTN_PINKIE\t\t0x125\n#define BTN_BASE\t\t0x126\n#define BTN_BASE2\t\t0x127\n#define BTN_BASE3\t\t0x128\n#define BTN_BASE4\t\t0x129\n#define BTN_BASE5\t\t0x12a\n#define BTN_BASE6\t\t0x12b\n#define BTN_DEAD\t\t0x12f\n\n#define BTN_GAMEPAD\t\t0x130\n#define BTN_SOUTH\t\t0x130\n#define BTN_A\t\t\tBTN_SOUTH\n#define BTN_EAST\t\t0x131\n#define BTN_B\t\t\tBTN_EAST\n#define BTN_C\t\t\t0x132\n#define BTN_NORTH\t\t0x133\n#define BTN_X\t\t\tBTN_NORTH\n#define BTN_WEST\t\t0x134\n#define BTN_Y\t\t\tBTN_WEST\n#define BTN_Z\t\t\t0x135\n#define BTN_TL\t\t\t0x136\n#define BTN_TR\t\t\t0x137\n#define BTN_TL2\t\t\t0x138\n#define BTN_TR2\t\t\t0x139\n#define BTN_SELECT\t\t0x13a\n#define BTN_START\t\t0x13b\n#define BTN_MODE\t\t0x13c\n#define BTN_THUMBL\t\t0x13d\n#define BTN_THUMBR\t\t0x13e\n\n#define BTN_DIGI\t\t0x140\n#define BTN_TOOL_PEN\t\t0x140\n#define BTN_TOOL_RUBBER\t\t0x141\n#define BTN_TOOL_BRUSH\t\t0x142\n#define BTN_TOOL_PENCIL\t\t0x143\n#define BTN_TOOL_AIRBRUSH\t0x144\n#define BTN_TOOL_FINGER\t\t0x145\n#define BTN_TOOL_MOUSE\t\t0x146\n#define BTN_TOOL_LENS\t\t0x147\n#define BTN_TOOL_QUINTTAP\t0x148\t/* Five fingers on trackpad */\n#define BTN_TOUCH\t\t0x14a\n#define BTN_STYLUS\t\t0x14b\n#define BTN_STYLUS2\t\t0x14c\n#define BTN_TOOL_DOUBLETAP\t0x14d\n#define BTN_TOOL_TRIPLETAP\t0x14e\n#define BTN_TOOL_QUADTAP\t0x14f\t/* Four fingers on trackpad */\n\n#define BTN_WHEEL\t\t0x150\n#define BTN_GEAR_DOWN\t\t0x150\n#define BTN_GEAR_UP\t\t0x151\n\n#define KEY_OK\t\t\t0x160\n#define KEY_SELECT\t\t0x161\n#define KEY_GOTO\t\t0x162\n#define KEY_CLEAR\t\t0x163\n#define KEY_POWER2\t\t0x164\n#define KEY_OPTION\t\t0x165\n#define KEY_INFO\t\t0x166\t/* AL OEM Features/Tips/Tutorial */\n#define KEY_TIME\t\t0x167\n#define KEY_VENDOR\t\t0x168\n#define KEY_ARCHIVE\t\t0x169\n#define KEY_PROGRAM\t\t0x16a\t/* Media Select Program Guide */\n#define KEY_CHANNEL\t\t0x16b\n#define KEY_FAVORITES\t\t0x16c\n#define KEY_EPG\t\t\t0x16d\n#define KEY_PVR\t\t\t0x16e\t/* Media Select Home */\n#define KEY_MHP\t\t\t0x16f\n#define KEY_LANGUAGE\t\t0x170\n#define KEY_TITLE\t\t0x171\n#define KEY_SUBTITLE\t\t0x172\n#define KEY_ANGLE\t\t0x173\n#define KEY_ZOOM\t\t0x174\n#define KEY_MODE\t\t0x175\n#define KEY_KEYBOARD\t\t0x176\n#define KEY_SCREEN\t\t0x177\n#define KEY_PC\t\t\t0x178\t/* Media Select Computer */\n#define KEY_TV\t\t\t0x179\t/* Media Select TV */\n#define KEY_TV2\t\t\t0x17a\t/* Media Select Cable */\n#define KEY_VCR\t\t\t0x17b\t/* Media Select VCR */\n#define KEY_VCR2\t\t0x17c\t/* VCR Plus */\n#define KEY_SAT\t\t\t0x17d\t/* Media Select Satellite */\n#define KEY_SAT2\t\t0x17e\n#define KEY_CD\t\t\t0x17f\t/* Media Select CD */\n#define KEY_TAPE\t\t0x180\t/* Media Select Tape */\n#define KEY_RADIO\t\t0x181\n#define KEY_TUNER\t\t0x182\t/* Media Select Tuner */\n#define KEY_PLAYER\t\t0x183\n#define KEY_TEXT\t\t0x184\n#define KEY_DVD\t\t\t0x185\t/* Media Select DVD */\n#define KEY_AUX\t\t\t0x186\n#define KEY_MP3\t\t\t0x187\n#define KEY_AUDIO\t\t0x188\t/* AL Audio Browser */\n#define KEY_VIDEO\t\t0x189\t/* AL Movie Browser */\n#define KEY_DIRECTORY\t\t0x18a\n#define KEY_LIST\t\t0x18b\n#define KEY_MEMO\t\t0x18c\t/* Media Select Messages */\n#define KEY_CALENDAR\t\t0x18d\n#define KEY_RED\t\t\t0x18e\n#define KEY_GREEN\t\t0x18f\n#define KEY_YELLOW\t\t0x190\n#define KEY_BLUE\t\t0x191\n#define KEY_CHANNELUP\t\t0x192\t/* Channel Increment */\n#define KEY_CHANNELDOWN\t\t0x193\t/* Channel Decrement */\n#define KEY_FIRST\t\t0x194\n#define KEY_LAST\t\t0x195\t/* Recall Last */\n#define KEY_AB\t\t\t0x196\n#define KEY_NEXT\t\t0x197\n#define KEY_RESTART\t\t0x198\n#define KEY_SLOW\t\t0x199\n#define KEY_SHUFFLE\t\t0x19a\n#define KEY_BREAK\t\t0x19b\n#define KEY_PREVIOUS\t\t0x19c\n#define KEY_DIGITS\t\t0x19d\n#define KEY_TEEN\t\t0x19e\n#define KEY_TWEN\t\t0x19f\n#define KEY_VIDEOPHONE\t\t0x1a0\t/* Media Select Video Phone */\n#define KEY_GAMES\t\t0x1a1\t/* Media Select Games */\n#define KEY_ZOOMIN\t\t0x1a2\t/* AC Zoom In */\n#define KEY_ZOOMOUT\t\t0x1a3\t/* AC Zoom Out */\n#define KEY_ZOOMRESET\t\t0x1a4\t/* AC Zoom */\n#define KEY_WORDPROCESSOR\t0x1a5\t/* AL Word Processor */\n#define KEY_EDITOR\t\t0x1a6\t/* AL Text Editor */\n#define KEY_SPREADSHEET\t\t0x1a7\t/* AL Spreadsheet */\n#define KEY_GRAPHICSEDITOR\t0x1a8\t/* AL Graphics Editor */\n#define KEY_PRESENTATION\t0x1a9\t/* AL Presentation App */\n#define KEY_DATABASE\t\t0x1aa\t/* AL Database App */\n#define KEY_NEWS\t\t0x1ab\t/* AL Newsreader */\n#define KEY_VOICEMAIL\t\t0x1ac\t/* AL Voicemail */\n#define KEY_ADDRESSBOOK\t\t0x1ad\t/* AL Contacts/Address Book */\n#define KEY_MESSENGER\t\t0x1ae\t/* AL Instant Messaging */\n#define KEY_DISPLAYTOGGLE\t0x1af\t/* Turn display (LCD) on and off */\n#define KEY_BRIGHTNESS_TOGGLE\tKEY_DISPLAYTOGGLE\n#define KEY_SPELLCHECK\t\t0x1b0 /* AL Spell Check */\n#define KEY_LOGOFF\t\t0x1b1 /* AL Logoff */\n\n#define KEY_DOLLAR\t\t0x1b2\n#define KEY_EURO\t\t0x1b3\n\n#define KEY_FRAMEBACK\t\t0x1b4\t/* Consumer - transport controls */\n#define KEY_FRAMEFORWARD\t0x1b5\n#define KEY_CONTEXT_MENU\t0x1b6\t/* GenDesc - system context menu */\n#define KEY_MEDIA_REPEAT\t0x1b7\t/* Consumer - transport control */\n#define KEY_10CHANNELSUP\t0x1b8\t/* 10 channels up (10+) */\n#define KEY_10CHANNELSDOWN\t0x1b9\t/* 10 channels down (10-) */\n#define KEY_IMAGES\t\t0x1ba\t/* AL Image Browser */\n\n#define KEY_DEL_EOL\t\t0x1c0\n#define KEY_DEL_EOS\t\t0x1c1\n#define KEY_INS_LINE\t\t0x1c2\n#define KEY_DEL_LINE\t\t0x1c3\n\n#define KEY_FN\t\t\t0x1d0\n#define KEY_FN_ESC\t\t0x1d1\n#define KEY_FN_F1\t\t0x1d2\n#define KEY_FN_F2\t\t0x1d3\n#define KEY_FN_F3\t\t0x1d4\n#define KEY_FN_F4\t\t0x1d5\n#define KEY_FN_F5\t\t0x1d6\n#define KEY_FN_F6\t\t0x1d7\n#define KEY_FN_F7\t\t0x1d8\n#define KEY_FN_F8\t\t0x1d9\n#define KEY_FN_F9\t\t0x1da\n#define KEY_FN_F10\t\t0x1db\n#define KEY_FN_F11\t\t0x1dc\n#define KEY_FN_F12\t\t0x1dd\n#define KEY_FN_1\t\t0x1de\n#define KEY_FN_2\t\t0x1df\n#define KEY_FN_D\t\t0x1e0\n#define KEY_FN_E\t\t0x1e1\n#define KEY_FN_F\t\t0x1e2\n#define KEY_FN_S\t\t0x1e3\n#define KEY_FN_B\t\t0x1e4\n\n#define KEY_BRL_DOT1\t\t0x1f1\n#define KEY_BRL_DOT2\t\t0x1f2\n#define KEY_BRL_DOT3\t\t0x1f3\n#define KEY_BRL_DOT4\t\t0x1f4\n#define KEY_BRL_DOT5\t\t0x1f5\n#define KEY_BRL_DOT6\t\t0x1f6\n#define KEY_BRL_DOT7\t\t0x1f7\n#define KEY_BRL_DOT8\t\t0x1f8\n#define KEY_BRL_DOT9\t\t0x1f9\n#define KEY_BRL_DOT10\t\t0x1fa\n\n#define KEY_NUMERIC_0\t\t0x200\t/* used by phones, remote controls, */\n#define KEY_NUMERIC_1\t\t0x201\t/* and other keypads */\n#define KEY_NUMERIC_2\t\t0x202\n#define KEY_NUMERIC_3\t\t0x203\n#define KEY_NUMERIC_4\t\t0x204\n#define KEY_NUMERIC_5\t\t0x205\n#define KEY_NUMERIC_6\t\t0x206\n#define KEY_NUMERIC_7\t\t0x207\n#define KEY_NUMERIC_8\t\t0x208\n#define KEY_NUMERIC_9\t\t0x209\n#define KEY_NUMERIC_STAR\t0x20a\n#define KEY_NUMERIC_POUND\t0x20b\n#define KEY_NUMERIC_A\t\t0x20c\t/* Phone key A - HUT Telephony 0xb9 */\n#define KEY_NUMERIC_B\t\t0x20d\n#define KEY_NUMERIC_C\t\t0x20e\n#define KEY_NUMERIC_D\t\t0x20f\n\n#define KEY_CAMERA_FOCUS\t0x210\n#define KEY_WPS_BUTTON\t\t0x211\t/* WiFi Protected Setup key */\n\n#define KEY_TOUCHPAD_TOGGLE\t0x212\t/* Request switch touchpad on or off */\n#define KEY_TOUCHPAD_ON\t\t0x213\n#define KEY_TOUCHPAD_OFF\t0x214\n\n#define KEY_CAMERA_ZOOMIN\t0x215\n#define KEY_CAMERA_ZOOMOUT\t0x216\n#define KEY_CAMERA_UP\t\t0x217\n#define KEY_CAMERA_DOWN\t\t0x218\n#define KEY_CAMERA_LEFT\t\t0x219\n#define KEY_CAMERA_RIGHT\t0x21a\n\n#define KEY_ATTENDANT_ON\t0x21b\n#define KEY_ATTENDANT_OFF\t0x21c\n#define KEY_ATTENDANT_TOGGLE\t0x21d\t/* Attendant call on or off */\n#define KEY_LIGHTS_TOGGLE\t0x21e\t/* Reading light on or off */\n\n#define BTN_DPAD_UP\t\t0x220\n#define BTN_DPAD_DOWN\t\t0x221\n#define BTN_DPAD_LEFT\t\t0x222\n#define BTN_DPAD_RIGHT\t\t0x223\n\n#define KEY_ALS_TOGGLE\t\t0x230\t/* Ambient light sensor */\n\n#define KEY_BUTTONCONFIG\t\t0x240\t/* AL Button Configuration */\n#define KEY_TASKMANAGER\t\t0x241\t/* AL Task/Project Manager */\n#define KEY_JOURNAL\t\t0x242\t/* AL Log/Journal/Timecard */\n#define KEY_CONTROLPANEL\t\t0x243\t/* AL Control Panel */\n#define KEY_APPSELECT\t\t0x244\t/* AL Select Task/Application */\n#define KEY_SCREENSAVER\t\t0x245\t/* AL Screen Saver */\n#define KEY_VOICECOMMAND\t\t0x246\t/* Listening Voice Command */\n#define KEY_ASSISTANT\t\t0x247\t/* AL Context-aware desktop assistant */\n\n#define KEY_BRIGHTNESS_MIN\t\t0x250\t/* Set Brightness to Minimum */\n#define KEY_BRIGHTNESS_MAX\t\t0x251\t/* Set Brightness to Maximum */\n\n#define KEY_KBDINPUTASSIST_PREV\t\t0x260\n#define KEY_KBDINPUTASSIST_NEXT\t\t0x261\n#define KEY_KBDINPUTASSIST_PREVGROUP\t\t0x262\n#define KEY_KBDINPUTASSIST_NEXTGROUP\t\t0x263\n#define KEY_KBDINPUTASSIST_ACCEPT\t\t0x264\n#define KEY_KBDINPUTASSIST_CANCEL\t\t0x265\n\n/* Diagonal movement keys */\n#define KEY_RIGHT_UP\t\t\t0x266\n#define KEY_RIGHT_DOWN\t\t\t0x267\n#define KEY_LEFT_UP\t\t\t0x268\n#define KEY_LEFT_DOWN\t\t\t0x269\n\n#define KEY_ROOT_MENU\t\t\t0x26a /* Show Device's Root Menu */\n/* Show Top Menu of the Media (e.g. DVD) */\n#define KEY_MEDIA_TOP_MENU\t\t0x26b\n#define KEY_NUMERIC_11\t\t\t0x26c\n#define KEY_NUMERIC_12\t\t\t0x26d\n/*\n * Toggle Audio Description: refers to an audio service that helps blind and\n * visually impaired consumers understand the action in a program. Note: in\n * some countries this is referred to as \"Video Description\".\n */\n#define KEY_AUDIO_DESC\t\t\t0x26e\n#define KEY_3D_MODE\t\t\t0x26f\n#define KEY_NEXT_FAVORITE\t\t0x270\n#define KEY_STOP_RECORD\t\t\t0x271\n#define KEY_PAUSE_RECORD\t\t0x272\n#define KEY_VOD\t\t\t\t0x273 /* Video on Demand */\n#define KEY_UNMUTE\t\t\t0x274\n#define KEY_FASTREVERSE\t\t\t0x275\n#define KEY_SLOWREVERSE\t\t\t0x276\n/*\n * Control a data application associated with the currently viewed channel,\n * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)\n */\n#define KEY_DATA\t\t\t0x277\n#define KEY_ONSCREEN_KEYBOARD\t\t0x278\n\n#define BTN_TRIGGER_HAPPY\t\t0x2c0\n#define BTN_TRIGGER_HAPPY1\t\t0x2c0\n#define BTN_TRIGGER_HAPPY2\t\t0x2c1\n#define BTN_TRIGGER_HAPPY3\t\t0x2c2\n#define BTN_TRIGGER_HAPPY4\t\t0x2c3\n#define BTN_TRIGGER_HAPPY5\t\t0x2c4\n#define BTN_TRIGGER_HAPPY6\t\t0x2c5\n#define BTN_TRIGGER_HAPPY7\t\t0x2c6\n#define BTN_TRIGGER_HAPPY8\t\t0x2c7\n#define BTN_TRIGGER_HAPPY9\t\t0x2c8\n#define BTN_TRIGGER_HAPPY10\t\t0x2c9\n#define BTN_TRIGGER_HAPPY11\t\t0x2ca\n#define BTN_TRIGGER_HAPPY12\t\t0x2cb\n#define BTN_TRIGGER_HAPPY13\t\t0x2cc\n#define BTN_TRIGGER_HAPPY14\t\t0x2cd\n#define BTN_TRIGGER_HAPPY15\t\t0x2ce\n#define BTN_TRIGGER_HAPPY16\t\t0x2cf\n#define BTN_TRIGGER_HAPPY17\t\t0x2d0\n#define BTN_TRIGGER_HAPPY18\t\t0x2d1\n#define BTN_TRIGGER_HAPPY19\t\t0x2d2\n#define BTN_TRIGGER_HAPPY20\t\t0x2d3\n#define BTN_TRIGGER_HAPPY21\t\t0x2d4\n#define BTN_TRIGGER_HAPPY22\t\t0x2d5\n#define BTN_TRIGGER_HAPPY23\t\t0x2d6\n#define BTN_TRIGGER_HAPPY24\t\t0x2d7\n#define BTN_TRIGGER_HAPPY25\t\t0x2d8\n#define BTN_TRIGGER_HAPPY26\t\t0x2d9\n#define BTN_TRIGGER_HAPPY27\t\t0x2da\n#define BTN_TRIGGER_HAPPY28\t\t0x2db\n#define BTN_TRIGGER_HAPPY29\t\t0x2dc\n#define BTN_TRIGGER_HAPPY30\t\t0x2dd\n#define BTN_TRIGGER_HAPPY31\t\t0x2de\n#define BTN_TRIGGER_HAPPY32\t\t0x2df\n#define BTN_TRIGGER_HAPPY33\t\t0x2e0\n#define BTN_TRIGGER_HAPPY34\t\t0x2e1\n#define BTN_TRIGGER_HAPPY35\t\t0x2e2\n#define BTN_TRIGGER_HAPPY36\t\t0x2e3\n#define BTN_TRIGGER_HAPPY37\t\t0x2e4\n#define BTN_TRIGGER_HAPPY38\t\t0x2e5\n#define BTN_TRIGGER_HAPPY39\t\t0x2e6\n#define BTN_TRIGGER_HAPPY40\t\t0x2e7\n\n/* We avoid low common keys in module aliases so they don't get huge. */\n#define KEY_MIN_INTERESTING\tKEY_MUTE\n#define KEY_MAX\t\t\t0x2ff\n#define KEY_CNT\t\t\t(KEY_MAX+1)\n\n/*\n * Relative axes\n */\n\n#define REL_X\t\t\t0x00\n#define REL_Y\t\t\t0x01\n#define REL_Z\t\t\t0x02\n#define REL_RX\t\t\t0x03\n#define REL_RY\t\t\t0x04\n#define REL_RZ\t\t\t0x05\n#define REL_HWHEEL\t\t0x06\n#define REL_DIAL\t\t0x07\n#define REL_WHEEL\t\t0x08\n#define REL_MISC\t\t0x09\n#define REL_MAX\t\t\t0x0f\n#define REL_CNT\t\t\t(REL_MAX+1)\n\n/*\n * Absolute axes\n */\n\n#define ABS_X\t\t\t0x00\n#define ABS_Y\t\t\t0x01\n#define ABS_Z\t\t\t0x02\n#define ABS_RX\t\t\t0x03\n#define ABS_RY\t\t\t0x04\n#define ABS_RZ\t\t\t0x05\n#define ABS_THROTTLE\t\t0x06\n#define ABS_RUDDER\t\t0x07\n#define ABS_WHEEL\t\t0x08\n#define ABS_GAS\t\t\t0x09\n#define ABS_BRAKE\t\t0x0a\n#define ABS_HAT0X\t\t0x10\n#define ABS_HAT0Y\t\t0x11\n#define ABS_HAT1X\t\t0x12\n#define ABS_HAT1Y\t\t0x13\n#define ABS_HAT2X\t\t0x14\n#define ABS_HAT2Y\t\t0x15\n#define ABS_HAT3X\t\t0x16\n#define ABS_HAT3Y\t\t0x17\n#define ABS_PRESSURE\t\t0x18\n#define ABS_DISTANCE\t\t0x19\n#define ABS_TILT_X\t\t0x1a\n#define ABS_TILT_Y\t\t0x1b\n#define ABS_TOOL_WIDTH\t\t0x1c\n\n#define ABS_VOLUME\t\t0x20\n\n#define ABS_MISC\t\t0x28\n\n#define ABS_MT_SLOT\t\t0x2f\t/* MT slot being modified */\n#define ABS_MT_TOUCH_MAJOR\t0x30\t/* Major axis of touching ellipse */\n#define ABS_MT_TOUCH_MINOR\t0x31\t/* Minor axis (omit if circular) */\n#define ABS_MT_WIDTH_MAJOR\t0x32\t/* Major axis of approaching ellipse */\n#define ABS_MT_WIDTH_MINOR\t0x33\t/* Minor axis (omit if circular) */\n#define ABS_MT_ORIENTATION\t0x34\t/* Ellipse orientation */\n#define ABS_MT_POSITION_X\t0x35\t/* Center X touch position */\n#define ABS_MT_POSITION_Y\t0x36\t/* Center Y touch position */\n#define ABS_MT_TOOL_TYPE\t0x37\t/* Type of touching device */\n#define ABS_MT_BLOB_ID\t\t0x38\t/* Group a set of packets as a blob */\n#define ABS_MT_TRACKING_ID\t0x39\t/* Unique ID of initiated contact */\n#define ABS_MT_PRESSURE\t\t0x3a\t/* Pressure on contact area */\n#define ABS_MT_DISTANCE\t\t0x3b\t/* Contact hover distance */\n#define ABS_MT_TOOL_X\t\t0x3c\t/* Center X tool position */\n#define ABS_MT_TOOL_Y\t\t0x3d\t/* Center Y tool position */\n\n\n#define ABS_MAX\t\t\t0x3f\n#define ABS_CNT\t\t\t(ABS_MAX+1)\n\n/*\n * Switch events\n */\n\n#define SW_LID\t\t\t0x00 /* set = lid shut */\n#define SW_TABLET_MODE\t\t0x01 /* set = tablet mode */\n#define SW_HEADPHONE_INSERT\t0x02 /* set = inserted */\n#define SW_RFKILL_ALL\t\t0x03 /* rfkill master switch, type \"any\"\n\t\t\t\t\t set = radio enabled */\n#define SW_RADIO\t\tSW_RFKILL_ALL\t/* deprecated */\n#define SW_MICROPHONE_INSERT\t0x04 /* set = inserted */\n#define SW_DOCK\t\t\t0x05 /* set = plugged into dock */\n#define SW_LINEOUT_INSERT\t0x06 /* set = inserted */\n#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */\n#define SW_VIDEOOUT_INSERT\t0x08 /* set = inserted */\n#define SW_CAMERA_LENS_COVER\t0x09 /* set = lens covered */\n#define SW_KEYPAD_SLIDE\t\t0x0a /* set = keypad slide out */\n#define SW_FRONT_PROXIMITY\t0x0b /* set = front proximity sensor active */\n#define SW_ROTATE_LOCK\t\t0x0c /* set = rotate locked/disabled */\n#define SW_LINEIN_INSERT\t0x0d /* set = inserted */\n#define SW_MUTE_DEVICE\t\t0x0e /* set = device disabled */\n#define SW_PEN_INSERTED\t\t0x0f /* set = pen inserted */\n#define SW_MAX\t\t\t0x0f\n#define SW_CNT\t\t\t(SW_MAX+1)\n\n/*\n * Misc events\n */\n\n#define MSC_SERIAL\t\t0x00\n#define MSC_PULSELED\t\t0x01\n#define MSC_GESTURE\t\t0x02\n#define MSC_RAW\t\t\t0x03\n#define MSC_SCAN\t\t0x04\n#define MSC_TIMESTAMP\t\t0x05\n#define MSC_MAX\t\t\t0x07\n#define MSC_CNT\t\t\t(MSC_MAX+1)\n\n/*\n * LEDs\n */\n\n#define LED_NUML\t\t0x00\n#define LED_CAPSL\t\t0x01\n#define LED_SCROLLL\t\t0x02\n#define LED_COMPOSE\t\t0x03\n#define LED_KANA\t\t0x04\n#define LED_SLEEP\t\t0x05\n#define LED_SUSPEND\t\t0x06\n#define LED_MUTE\t\t0x07\n#define LED_MISC\t\t0x08\n#define LED_MAIL\t\t0x09\n#define LED_CHARGING\t\t0x0a\n#define LED_MAX\t\t\t0x0f\n#define LED_CNT\t\t\t(LED_MAX+1)\n\n/*\n * Autorepeat values\n */\n\n#define REP_DELAY\t\t0x00\n#define REP_PERIOD\t\t0x01\n#define REP_MAX\t\t\t0x01\n#define REP_CNT\t\t\t(REP_MAX+1)\n\n/*\n * Sounds\n */\n\n#define SND_CLICK\t\t0x00\n#define SND_BELL\t\t0x01\n#define SND_TONE\t\t0x02\n#define SND_MAX\t\t\t0x07\n#define SND_CNT\t\t\t(SND_MAX+1)\n\n#define MATRIX_KEY(row, col, code)\t\\\n\t((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))\n\n#endif /* _DT_BINDINGS_INPUT_INPUT_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/interrupt-controller/irq.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most IRQ bindings.\n *\n * Most IRQ bindings include a flags cell as part of the IRQ specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n\n#define IRQ_TYPE_NONE\t\t0\n#define IRQ_TYPE_EDGE_RISING\t1\n#define IRQ_TYPE_EDGE_FALLING\t2\n#define IRQ_TYPE_EDGE_BOTH\t(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)\n#define IRQ_TYPE_LEVEL_HIGH\t4\n#define IRQ_TYPE_LEVEL_LOW\t8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/phy/phy.h", "content": "/*\n *\n * This header provides constants for the phy framework\n *\n * Copyright (C) 2014 STMicroelectronics\n * Author: Gabriel Fernandez \n * License terms: GNU General Public License (GPL), version 2\n */\n\n#ifndef _DT_BINDINGS_PHY\n#define _DT_BINDINGS_PHY\n\n#define PHY_NONE\t\t0\n#define PHY_TYPE_SATA\t\t1\n#define PHY_TYPE_PCIE\t\t2\n#define PHY_TYPE_USB2\t\t3\n#define PHY_TYPE_USB3\t\t4\n#define PHY_TYPE_UFS\t\t5\n#define PHY_TYPE_DP\t\t6\n#define PHY_TYPE_SGMII\t\t7\n\n#endif /* _DT_BINDINGS_PHY */\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h", "content": "/*\n * MIO pin configuration defines for Xilinx ZynqMP\n *\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Author: Chirag Parekh \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * version 2 as published by the Free Software Foundation.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program. If not, see .\n */\n\n#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H\n#define _DT_BINDINGS_PINCTRL_ZYNQMP_H\n\n/* Bit value for IO standards */\n#define IO_STANDARD_LVCMOS33 0\n#define IO_STANDARD_LVCMOS18 1\n\n/* Bit values for Slew Rates */\n#define SLEW_RATE_FAST 0\n#define SLEW_RATE_SLOW 1\n\n/* Bit values for Pin inputs */\n#define PIN_INPUT_TYPE_CMOS 0\n#define PIN_INPUT_TYPE_SCHMITT 1\n\n/* Bit values for drive control*/\n#define DRIVE_STRENGTH_2MA 2\n#define DRIVE_STRENGTH_4MA 4\n#define DRIVE_STRENGTH_8MA 8\n#define DRIVE_STRENGTH_12MA 12\n\n#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/versal/versal-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\talt_ref_clk: alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tcan0_clk: can0_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk 96>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tcan1_clk: can1_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk 97>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware-wip\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"alt_ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk 77>;\n};\n\n&can0 {\n\tclocks = <&can0_clk>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401f>;\n};\n\n&can1 {\n\tclocks = <&can1_clk>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224020>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x18224019>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x1822401a>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk 61>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk 98>;\n\tpower-domains = <&versal_firmware 0x1822401d>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk 99>;\n\tpower-domains = <&versal_firmware 0x1822401e>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224035>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224036>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224037>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224038>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224039>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403a>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403b>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403c>;\n};\n\n&qspi {\n\tclocks = <&versal_clk 57>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402b>;\n};\n\n&ospi {\n\tclocks = <&versal_clk 58>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402a>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware 0x18224034>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk 92>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224021>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk 93>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224022>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk 59>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402e>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk 60>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402f>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk 94>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401b>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk 95>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401c>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk 91>, <&versal_clk 104>;\n\tpower-domains = <&versal_firmware 0x18224018>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224029>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/versal/versal.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal\";\n\n\tcpus: cpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <1>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tfpga: fpga {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&versal_fpga>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tpsci: psci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t};\n\n\tversal_fpga: versal_fpga {\n\t\tcompatible = \"xlnx,versal-fpga\";\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\t\t\treg = <0 0xf9000000 0 0x80000>, /* GICD */\n\t\t\t <0 0xf9080000 0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 4>;\n\n\t\t\tgic_its: gic-its@f9020000 {\n\t\t\t\tcompatible = \"arm,gic-v3-its\";\n\t\t\t\tmsi-controller;\n\t\t\t\tmsi-cells = <1>;\n\t\t\t\treg = <0 0xf9020000 0 0x20000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t\tinterrupt-parent = <&gic>;\n\t\tu-boot,dm-pre-reloc;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff060000 0 0x6000>;\n\t\t\tinterrupts = <0 20 1>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff070000 0 0x6000>;\n\t\t\tinterrupts = <0 21 1>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcci: cci@fd000000 {\n\t\t\tcompatible = \"arm,cci-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd000000 0 0x10000>;\n\t\t\tranges = <0 0 0xfd000000 0xa0000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcci_pmu: pmu@10000 {\n\t\t\t\tcompatible = \"arm,cci-500-pmu,r0\";\n\t\t\t\treg = <0x10000 0x90000>;\n\t\t\t\tinterrupts = <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>;\n\t\t\t};\n\t\t};\n\n\t\tlpd_dma_chan0: dma@ffa80000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa80000 0 0x1000>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa90000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa90000 0 0x1000>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffaa0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaa0000 0 0x1000>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\n\t\tlpd_dma_chan3: dma@ffab0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffab0000 0 0x1000>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffac0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffac0000 0 0x1000>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffad0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffad0000 0 0x1000>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffae0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffae0000 0 0x1000>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffaf0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaf0000 0 0x1000>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tgem0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,versal-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0c0000 0 0x1000>;\n\t\t\tinterrupts = <0 56 4>, <0 56 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,versal-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0d0000 0 0x1000>;\n\t\t\tinterrupts = <0 58 4>, <0 58 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tgpio0: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0b0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff020000 0 0x1000>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff030000 0 0x1000>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff000000 0 0x1000>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tserial1: serial@ff010000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff010000 0 0x1000>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd800000 0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 124 4>, <0 124 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,is-stig-pgm = <1>;\n\t\t\tcdns,trigger-address = <0xC0000000>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff040000 0 0x1000>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff050000 0 0x1000>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tusb0: usb@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff9d0000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0 0xfe200000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"usb-wakeup\";\n\t\t\t\tinterrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,mask_phy_reset;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\tcpm_pciea: pci@fca10000 {\n\t\t\t#address-cells = <3>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"xlnx,versal-cpm-host-1.00\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc_0 1>,\n\t\t\t\t\t<0 0 0 2 &pcie_intc_0 2>,\n\t\t\t\t\t<0 0 0 3 &pcie_intc_0 3>,\n\t\t\t\t\t<0 0 0 4 &pcie_intc_0 4>;\n\t\t\tinterrupt-map-mask = <0 0 0 7>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupt-names = \"misc\";\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>,\n\t\t\t\t <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>;\n\t\t\tmsi-map = <0x0 &gic_its 0x0 0x10000>;\n\t\t\treg = <0x0 0xfca10000 0x0 0x1000>,\n\t\t\t <0x6 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"cpm_slcr\", \"cfg\";\n\t\t\tpcie_intc_0: pci-interrupt-controller {\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\tinterrupt-controller ;\n\t\t\t};\n\t\t};\n\n\t\twatchdog: watchdog@fd4d0000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd4d0000 0 0x10000>;\n\t\t\ttimeout-sec = <60>;\n\t\t};\n\t};\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/zynq/zynq-7000.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"apb_pclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\", \"arm,primecell\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: mmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: mmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/zynqmp/zynqmp-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk 71>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk 72>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk 73>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk 74>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tdp_aclk: dp_aclk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&zynqmp_firmware {\n\tzynqmp_clk: clock-controller {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,\n\t\t\t <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\",\n\t\t\t \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t};\n};\n\n&can0 {\n\tclocks = <&zynqmp_clk 63>, <&zynqmp_clk 31>;\n};\n\n&can1 {\n\tclocks = <&zynqmp_clk 64>, <&zynqmp_clk 31>;\n};\n\n&cpu0 {\n\tclocks = <&zynqmp_clk 10>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;\n};\n\n&gpu {\n\tclocks = <&zynqmp_clk 24>, <&zynqmp_clk 25>, <&zynqmp_clk 26>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>;\n};\n\n&nand0 {\n\tclocks = <&zynqmp_clk 60>, <&zynqmp_clk 31>;\n};\n\n&gem0 {\n\tclocks = <&zynqmp_clk 31>, <&zynqmp_clk 104>, <&zynqmp_clk 45>,\n\t\t <&zynqmp_clk 49>, <&zynqmp_clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem1 {\n\tclocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>, <&zynqmp_clk 46>,\n\t\t <&zynqmp_clk 50>, <&zynqmp_clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem2 {\n\tclocks = <&zynqmp_clk 31>, <&zynqmp_clk 106>, <&zynqmp_clk 47>,\n\t\t <&zynqmp_clk 51>, <&zynqmp_clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem3 {\n\tclocks = <&zynqmp_clk 31>, <&zynqmp_clk 107>, <&zynqmp_clk 48>,\n\t\t <&zynqmp_clk 52>, <&zynqmp_clk 44>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gpio {\n\tclocks = <&zynqmp_clk 31>;\n};\n\n&i2c0 {\n\tclocks = <&zynqmp_clk 61>;\n};\n\n&i2c1 {\n\tclocks = <&zynqmp_clk 62>;\n};\n\n&perf_monitor_ocm {\n\tclocks = <&zynqmp_clk 31>;\n};\n\n&perf_monitor_ddr {\n\tclocks = <&zynqmp_clk 28>;\n};\n\n&perf_monitor_cci {\n\tclocks = <&zynqmp_clk 28>;\n};\n\n&perf_monitor_lpd {\n\tclocks = <&zynqmp_clk 31>;\n};\n\n&pcie {\n\tclocks = <&zynqmp_clk 23>;\n};\n\n&qspi {\n\tclocks = <&zynqmp_clk 53>, <&zynqmp_clk 31>;\n};\n\n&sata {\n\tclocks = <&zynqmp_clk 22>;\n};\n\n&sdhci0 {\n\tclocks = <&zynqmp_clk 54>, <&zynqmp_clk 31>;\n};\n\n&sdhci1 {\n\tclocks = <&zynqmp_clk 55>, <&zynqmp_clk 31>;\n};\n\n&spi0 {\n\tclocks = <&zynqmp_clk 58>, <&zynqmp_clk 31>;\n};\n\n&spi1 {\n\tclocks = <&zynqmp_clk 59>, <&zynqmp_clk 31>;\n};\n\n&ttc0 {\n\tclocks = <&zynqmp_clk 31>;\n};\n\n&ttc1 {\n\tclocks = <&zynqmp_clk 31>;\n};\n\n&ttc2 {\n\tclocks = <&zynqmp_clk 31>;\n};\n\n&ttc3 {\n\tclocks = <&zynqmp_clk 31>;\n};\n\n&uart0 {\n\tclocks = <&zynqmp_clk 56>, <&zynqmp_clk 31>;\n};\n\n&uart1 {\n\tclocks = <&zynqmp_clk 57>, <&zynqmp_clk 31>;\n};\n\n&usb0 {\n\tclocks = <&zynqmp_clk 32>, <&zynqmp_clk 34>;\n};\n\n&usb1 {\n\tclocks = <&zynqmp_clk 33>, <&zynqmp_clk 34>;\n};\n\n&watchdog0 {\n\tclocks = <&zynqmp_clk 75>;\n};\n\n&lpd_watchdog {\n\tclocks = <&zynqmp_clk 112>;\n};\n\n&xilinx_ams {\n\tclocks = <&zynqmp_clk 70>;\n};\n\n&zynqmp_dpsub {\n\tclocks = <&dp_aclk>, <&zynqmp_clk 17>, <&zynqmp_clk 16>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&zynqmp_clk 20>;\n};\n\n&zynqmp_dp_snd_codec0 {\n\tclocks = <&zynqmp_clk 17>;\n};\n\n&pcap {\n\tclocks = <&zynqmp_clk 41>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2019.2/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t\txlnx,ipi-id = <0>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff990400 {\n\t\t\treg = <0x0 0xff9905c0 0x0 0x20>,\n\t\t\t <0x0 0xff9905e0 0x0 0x20>,\n\t\t\t <0x0 0xff990e80 0x0 0x20>,\n\t\t\t <0x0 0xff990ea0 0x0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <4>;\n\t\t};\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tzynqmp_firmware: zynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x1>;\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tzynqmp_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\t\t};\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tnvmem_firmware {\n\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsoc_revision: soc_revision@0 {\n\t\t\treg = <0x0 0x4>;\n\t\t};\n\t\t/* efuse access */\n\t\tefuse_dna: efuse_dna@c {\n\t\t\treg = <0xc 0xc>;\n\t\t};\n\t\tefuse_usr0: efuse_usr0@20 {\n\t\t\treg = <0x20 0x4>;\n\t\t};\n\t\tefuse_usr1: efuse_usr1@24 {\n\t\t\treg = <0x24 0x4>;\n\t\t};\n\t\tefuse_usr2: efuse_usr2@28 {\n\t\t\treg = <0x28 0x4>;\n\t\t};\n\t\tefuse_usr3: efuse_usr3@2c {\n\t\t\treg = <0x2c 0x4>;\n\t\t};\n\t\tefuse_usr4: efuse_usr4@30 {\n\t\t\treg = <0x30 0x4>;\n\t\t};\n\t\tefuse_usr5: efuse_usr5@34 {\n\t\t\treg = <0x34 0x4>;\n\t\t};\n\t\tefuse_usr6: efuse_usr6@38 {\n\t\t\treg = <0x38 0x4>;\n\t\t};\n\t\tefuse_usr7: efuse_usr7@3c {\n\t\t\treg = <0x3c 0x4>;\n\t\t};\n\t\tefuse_miscusr: efuse_miscusr@40 {\n\t\t\treg = <0x40 0x4>;\n\t\t};\n\t\tefuse_chash: efuse_chash@50 {\n\t\t\treg = <0x50 0x4>;\n\t\t};\n\t\tefuse_pufmisc: efuse_pufmisc@54 {\n\t\t\treg = <0x54 0x4>;\n\t\t};\n\t\tefuse_sec: efuse_sec@58 {\n\t\t\treg = <0x58 0x4>;\n\t\t};\n\t\tefuse_spkid: efuse_spkid@5c {\n\t\t\treg = <0x5c 0x4>;\n\t\t};\n\t\tefuse_ppk0hash: efuse_ppk0hash@a0 {\n\t\t\treg = <0xa0 0x30>;\n\t\t};\n\t\tefuse_ppk1hash: efuse_ppk1hash@d0 {\n\t\t\treg = <0xd0 0x30>;\n\t\t};\n\t};\n\n\tpcap: pcap {\n\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t\tclock-names = \"ref_clk\";\n\t};\n\n\txlnx_rsa: zynqmp_rsa {\n\t\tcompatible = \"xlnx,zynqmp-rsa\";\n\t};\n\n\txlnx_keccak_384: sha384 {\n\t\tcompatible = \"xlnx,zynqmp-keccak-384\";\n\t};\n\n\txlnx_aes: zynqmp_aes {\n\t\tcompatible = \"xlnx,zynqmp-aes\";\n\t};\n\n\tamba_apu: amba_apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tsmmu: smmu@fd800000 {\n\t\tcompatible = \"arm,mmu-500\";\n\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t#iommu-cells = <1>;\n\t\tstatus = \"disabled\";\n\t\t#global-interrupts = <1>;\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware 47>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware 48>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&zynqmp_firmware 42>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\", \"gpu_pp0\", \"gpu_pp1\";\n\t\t\tpower-domains = <&zynqmp_firmware 58>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&zynqmp_firmware 43>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&zynqmp_firmware 44>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&zynqmp_firmware 29>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&zynqmp_firmware 30>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&zynqmp_firmware 31>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&zynqmp_firmware 32>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tpower-domains = <&zynqmp_firmware 46>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware 37>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware 38>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tperf_monitor_ocm: perf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa00000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_ddr: perf-monitor@fd0b0000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd0b0000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <6>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <10>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_cci: perf-monitor@fd490000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd490000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_lpd: perf-monitor@ffa10000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa10000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpower-domains = <&zynqmp_firmware 59>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&zynqmp_firmware 45>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tserdes: zynqmp_phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\";\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\tresets = <&zynqmp_reset 16>, <&zynqmp_reset 59>,\n\t\t\t\t <&zynqmp_reset 60>, <&zynqmp_reset 61>,\n\t\t\t\t <&zynqmp_reset 62>, <&zynqmp_reset 63>,\n\t\t\t\t <&zynqmp_reset 64>, <&zynqmp_reset 3>,\n\t\t\t\t <&zynqmp_reset 29>, <&zynqmp_reset 30>,\n\t\t\t\t <&zynqmp_reset 31>, <&zynqmp_reset 32>;\n\t\t\treset-names = \"sata_rst\", \"usb0_crst\", \"usb1_crst\",\n\t\t\t\t \"usb0_hibrst\", \"usb1_hibrst\", \"usb0_apbrst\",\n\t\t\t\t \"usb1_apbrst\", \"dp_rst\", \"gem0_rst\",\n\t\t\t\t \"gem1_rst\", \"gem2_rst\", \"gem3_rst\";\n\t\t\tlane0: lane0 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane1: lane1 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane2: lane2 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane3: lane3 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&zynqmp_firmware 28>;\n\t\t\t#stream-id-cells = <4>;\n\t\t/*\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;*/\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&zynqmp_firmware 39>;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&zynqmp_firmware 40>;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware 35>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware 36>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware 24>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware 25>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware 26>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware 27>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware 33>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware 34>;\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware 22>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>, <0 75 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t\t/* snps,enable-hibernation; */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb1@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware 23>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>, <0 76 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <60>;\n\t\t\treset-on-timeout;\n\t\t};\n\n\t\tlpd_watchdog: watchdog@ff150000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 52 1>;\n\t\t\treg = <0x0 0xff150000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges;\n\n\t\t\tams_ps: ams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50800 0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50c00 0x0 0x400>;\n\t\t\t};\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware 41>;\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\n\t\tzynqmp_dpsub: zynqmp-display@fd4a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"dp\", \"blend\", \"av_buf\", \"aud\";\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"dp_apb_clk\", \"dp_aud_clk\", \"dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <&zynqmp_firmware 41>;\n\n\t\t\tvid-layer {\n\t\t\t\tdma-names = \"vid0\", \"vid1\", \"vid2\";\n\t\t\t\tdmas = <&xlnx_dpdma 0>,\n\t\t\t\t <&xlnx_dpdma 1>,\n\t\t\t\t <&xlnx_dpdma 2>;\n\t\t\t};\n\n\t\t\tgfx-layer {\n\t\t\t\tdma-names = \"gfx0\";\n\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t};\n\n\t\t\t/* dummy node to to indicate there's no child i2c device */\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&xlnx_dpdma 4>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&xlnx_dpdma 5>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card0: zynqmp_dp_snd_card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,\n\t\t\t\t\t\t <&zynqmp_dp_snd_pcm1>;\n\t\t\t\txlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\thard-reset-gpios = <&reset_gpio 0 1>;\n};\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/sp701-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze sp701.\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@1 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x3>;\n\t\t\tti,tx-internal-delay = <0x3>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/vcu118-rev2.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze vcu118\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@3 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\tti,sgmii-ref-clock-output-enable;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\treg = <3>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-a2197-sc-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller RevA\";\n\tcompatible = \"xlnx,versal-sc-revA\", \"xlnx,versal-sc\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\t/* SC Bank 43\n\tFIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS\n\tSYSCTLR_GPIO0 - 5 - conneced to versal */\n\t/* cpu thermal for MAX6643 fan control */\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tdc38_led {\n\t\t\tlabel = \"ds38-green\"; /* sc AB11 500_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc37_led {\n\t\t\tlabel = \"ds37-green\"; /* sc AD10 501_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc36_led {\n\t\t\tlabel = \"ds36-green\"; /* sc AD11 502_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t};\n};\n\n/* usb - type C - pl\n and micro usb 2.0, gt\n*/\n/* Feb 28/2019 version */\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n/* TODO\nUSB0 MIO52-63\nUSB1 MIO64-75\n*/\n\n/*eth MDIO 76/77\neth reset MIO42\nmarwell m88e1512 - SGMII */\n&gem0 {\n\tphy-handle = <&phy0>;\n\t/* phy-mode = \"sgmii\"; DTG generates this properly */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: phy@21 {\n\t\treg = <21>; /* FIXME */\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5- 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 0 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\"; /* FIXME no linux driver */\n\t\t\t\treg = <0xc0>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <10000000>; /* 10 ohm */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\ti2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* FIXME connection to Samtec J212D */\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t/* FIXME connection to Samtec J53C */\n\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@5d { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@5d { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@5d { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"LPDDR4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-emu-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-emu-itr8\", \"xlnx,versal-emu\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal EMU ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:9600\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n\n\tclk0212: clk0212 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <212000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n};\n\n&timer {\n clock-frequency = <440000>;\n};\n\n&serial0 {\n status = \"okay\";\n clocks = <&clk0212 &clk0212>;\n\tcurrent-speed = <9600>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-spp-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-spp-itr8-cn13940875\", \"xlnx,versal-spp-itr8\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal SPP ITR8 HW 4.0\";\n\t\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &ospi;\n\t\tspi2 = &spi0;\n\t\tspi3 = &spi1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tusb0 = &usb0;\n\t};\n\t\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>;\n\t};\n\tchosen {\n\t\tbootargs = \"rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\t\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n};\n\n&timer {\n\tclock-frequency = <2720000>;\n};\n\n&serial0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tmaximum-speed = \"high-speed\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n phy0: phy@0 {\n\t\treg = <0x0>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n phy1: phy@1 {\n\t\treg = <0x1>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <0x1>;\n\treg = <0x0 0xf1030000 0x0 0x1000>;\n\tclocks = <&clk125 &clk125>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\t\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot-boot.bin\";\n\t\t\t\treg = <0x0 0x6400000>;\n\t\t\t};\n\t\t\tpartition@6400000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x6400000 0x500000>;\n\t\t\t};\n\t\t\tpartition@6900000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x6900000 0x20000>;\n\t\t\t};\n\t\t\tpartition@6920000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x6920000 0x5E0000>;\n\t\t\t};\n\t\t\tpartition@7f40000 {\n\t\t\t\tlabel = \"qspi-bootenv\";\n\t\t\t\treg = <0x7f40000 0x40000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ospi {\n\tstatus = \"disabled\";\n\tclocks = <&clk125 &clk125>;\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\tcdns,fifo-depth = <508>;\n\tcdns,fifo-width = <4>;\n\tcdns,is-dma = <1>;\n\tcdns,is-stig-pgm = <1>;\n\tcdns,trigger-address = <0x00000000>;\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t};\n\t\t\tpartition@600000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t};\n\t\t\tpartition@620000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <1>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <3>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\treg = <0x0 0x84000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-v350-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal v350 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-v350-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal v350 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tspi0 = &ospi;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&serial1 {\n\tstatus = \"disabled\"; /* communication with MSP432 */\n};\n\n&ospi {\n\tstatus = \"okay\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-01 revA OSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\n};\n\n&rtc {\n status = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&watchdog {\n status = \"okay\";\n};\n\n&qspi {\n status = \"disabled\"; /* u93 and u92 */\n};\n\n&ospi {\n\tstatus = \"okay\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 {\n status = \"okay\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n compatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n \"xlnx,versal-vc-p-a2197-00\",\n \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n model = \"Xilinx Versal A2197 Processor board revA\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tgpio0 = &gpio;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n\n};\n\n&gpio {\n\tstatus = \"okay\";\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&qspi {\n status = \"okay\"; /* u93 and u92 */\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci1 { /* U104 */\n\tstatus = \"okay\";\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 {\n status = \"okay\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-01 revA QSPI\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&qspi {\n status = \"okay\"; /* u93 and u92 */\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 {\n status = \"okay\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-02 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>; /* u9 */\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@1 { /* Marvell 88E1512; U9 */\n\t\treg = <1>;\n\t};\n};\n\n\n&sdhci0 {\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&sdhci1 { /* U1A */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n\tno-1-8-v;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* U4 */\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"high-speed\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\t/* U12 Catalyst EEPROM - AT24 should be equivalent */\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U13 and U15 */\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tflash@0 { /* U18 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tnum-cs = <3>;\t/* FIXME - check SPI1_SS0-2_B */\n\n\tflash@0 { /* U19 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst26vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-03 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\t\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tserial0 = &serial0;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t};\n};\n\n&dcc {\n status = \"okay\";\n};\n\n/* SMAP via cc108 */\n&can0 {\n\tstatus = \"okay\";\n};\n\n&can1 {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\t/* Must be enabled via J90/J91 */\n\teeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\"; /* u7 */\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <1>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 64Mb */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x800000>;\n\t\t};\n\t};\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&sdhci0 { /* J99 MIO28 - MIO33 */\n\txlnx,mio_bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>; /* FIXME */\n\tno-1-8-v;\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tflash@0 { /* U6 - IS25LQ032B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lq032b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-04 revA OSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <1>; /* FIXME */\n\t};\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"disabled\"; /* u93 and u92 and u161 and u160 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n/* Mutually exclusive with qspi */\n&ospi {\n\tstatus = \"okay\"; /* U163/U97 MT35XU02G */\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio_bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&serial0 { /* MIO35 - MIO37 */\n\tstatus = \"okay\";\n};\n\n&serial1 { /* MIO4 - MIO7 RS232 */\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-04 revA QSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <2>;\n\t};\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\"; /* u93 and u92 and u161 and u160 */\n\tnum-cs = <1>;\n\tis-dual = <0>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 512MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x20000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio_bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&serial0 { /* MIO35 - MIO37 */\n\tstatus = \"okay\";\n};\n\n&serial1 { /* MIO4 - MIO7 RS232 */\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-05 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 { /* 88e1510 */\n\t\treg = <1>; /* FIXME */\n\t};\n\tphy2: phy@2 { /* VSC8531 */\n\t\treg = <2>; /* FIXME */\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>;\n\tphy-mode = \"rgmii-id\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <0x1>;\n\tspi-tx-bus-width = <1>;\n\tspi-rx-bus-width = <4>;\n\n\tflash@0 { /* MX25U12835 128Mbit */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 16MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <104000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x1000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc0 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>; /* FIXME */\n\tno-1-8-v;\n};\n\n&sdhci1 { /* connector */\n\txlnx,mio_bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA\";\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 {\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA (QSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&qspi {\n status = \"okay\";\n num-cs = <1>;\n spi-tx-bus-width = <1>;\n spi-rx-bus-width = <4>;\n #address-cells = <1>;\n #size-cells = <0>;\n is-dual = <1>;\n flash@0 {\n #address-cells = <1>;\n #size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 256MB */\n reg = <0>;\n spi-tx-bus-width = <1>;\n spi-rx-bus-width = <4>;\n spi-max-frequency = <104000000>;\n partition@0 {\n label = \"spi0-flash0\";\n reg = <0x0 0x10000000>;\n };\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA-x-ebm-02-revA\",\n\t\t \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA (EMMC)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci0 {\n\t/* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA-x-ebm-03-revA\",\n\t\t \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA (OSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&ospi {\n\t/* U97 MT35XU02G */\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-virt.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-virt\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal Virtual\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tclk2: clk2 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <2670000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t\tclock-frequency = <2720000>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */\n\t\t\t <0x0 0xf9080000 0x0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x1 0x9 4>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x2>;\n\t\tranges;\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff060000 0x0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff070000 0x0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom1: eeprom@53 {\n\t\t\t\treg = <0x53>;\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t};\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom2: eeprom@55 {\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x55>;\n\t\t\t};\n\t\t};\n\n\t\tgpio: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tethernet0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 56 4>, <0x0 56 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy0: phy@0 {\n\t\t\t\treg = <0x0>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tethernet1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 58 4>, <0x0 58 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy1: phy@1 {\n\t\t\t\treg = <0x1>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xf12a0000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tnum-cs = <0x1>;\n\t\t\treg = <0x0 0xf1030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"n25q512a\", \"micron,m25p80\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <108000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@100000 {\n\t\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@600000 {\n\t\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@620000 {\n\t\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <1>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <3>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0x0 0x84000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\treg = <0x0 0xf1040000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <0>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\treg = <0x0 0xf1050000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <1>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\t#address-cells = <0x2>;\n\t\t\t#size-cells = <0x2>;\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tranges;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125 &clk125>;\n\n\t\t\tdwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x10000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = ðernet0;\n\t\tethernet1 = ðernet1;\n\t\tqspi = &qspi;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA (QSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\tspi-tx-bus-width = <1>;\n\tspi-rx-bus-width = <4>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tis-dual = <1>;\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 256MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <104000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x10000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA-x-ebm-02-revA\",\n\t\t \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA (EMMC)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci0 {\n\t/* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA-x-ebm-03-revA\",\n\t\t \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA (OSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&ospi {\n\t/* U97 MT35XU02G */\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 3 150000000>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: ethernet-phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: flash@0 {\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: flash@0 {\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t\tsw13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@34 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x34>;\n\t\t\t};\n\t\t\thwmon@35 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\thwmon@36 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&watchdog0 {\n\treset-on-timeout;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zcu100-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio_bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zcu100-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * 1.0 revision has level shifter and this property should be\n\t * removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\t/*\n\t * 1.0 revision has level shifter and this property should be\n\t * removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@20 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zcu104-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revC\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - IRPS5401_ALERT_B\n\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t * 2 - MAX6643_OT_B\n\t\t * 3 - MAX6643_FANFAIL_B\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t * 4, 10 - 17 - not connected\n\t\t */\n\t};\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tu183: ina226@40 { /* u183 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 4, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\txlnx,mio_bank = <1>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u67 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;\n\t};\n\tina226-u59 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n\tina226-u69 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;\n\t};\n\tina226-u66 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;\n\t};\n\tina226-u71 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u73 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tu67: ina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u67\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu59: ina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u59\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu61: ina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu60: ina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu64: ina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu69: ina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u69\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu66: ina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u66\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu63: ina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu3: ina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u3\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu71: ina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u71\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu73: ina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u73\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u57 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 { /* SI5328 - u48 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection FIXME */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revA\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1275-revb.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU1275 RevB\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revB\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t* 1.0 revision has level shifter and this property should be\n\t* removed for supporting UHS mode\n\t*/\n\tno-1-8-v;\n};\n\n&gem1 {\n\t/* U-Boot gmii-to-rgmii bridge */\n\tphy-mode = \"gmii\";\n\tphy-handle = <&gmiitorgmii>;\n\tphy: ethernet-phy@0 {\n\t\treg = <0x0>;\n\t};\n\tgmiitorgmii: gmiitorgmii@8 {\n\t\tcompatible = \"xlnx,gmii-to-rgmii-1.0\";\n\t\treg = <8>;\n\t\tphy-handle = <&phy>;\n\t};\n\n\t/* Linux gmii-to-rgmii bridge */\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1285-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU1285 RevA\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1285 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1285-revA\", \"xlnx,zynqmp-zcu1285\", \"xlnx,zynqmp\";\n\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PMBUS */\n\t\t\tmax20751@74 { /* u23 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x74>;\n\t\t\t};\n\t\t\tmax20751@70 { /* u89 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x70>;\n\t\t\t};\n\t\t\tmax15301@a { /* u28 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u48 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@d { /* u27 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\tmax15303@e { /* u11 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\tmax15303@f { /* u96 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\tmax15303@11 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\tmax15303@12 { /* u24 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u29 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u51 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u30 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u102 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15301@17 { /* u50 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u31 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* CM_I2C */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYS_EEPROM */\n\t\t\teeprom: eeprom@54 { /* u101 */\n\t\t\t\tcompatible = \"atmel,24c32\"; /* 24LC32A */\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FMC1 */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FMC2 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* ANALOG_PMBUS */\n\t\t\tu60: ina226@40 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu61: ina226@41 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu63: ina226@42 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu65: ina226@43 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu64: ina226@44 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* ANALOG_CM_I2C */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FMC3 */\n\t\t};\n\t};\n};\n\n&gem1 {\n\tmdio {\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zcu208-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU208\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU208 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu208-revA\", \"xlnx,zynqmp-zcu208\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zcu216-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU216\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU216 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu216-revA\", \"xlnx,zynqmp-zcu216\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-a2197-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Versal System Controller on a2197 board RevA\";\n\tcompatible = \"xlnx,zynqmp-a2197-revA\", \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>;\n\t};\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* this cover MGT board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* This cover processor board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-e-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevA\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tsi570_ddrdimm1_clk: si570_ddrdimm1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tsi570_lpddr4_clk2: si570_lpddr4_clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570_lpddr4_clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk1>;\n\t};\n\n\tsi570_hsdp_clk: si570_hsdp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi570_zsfp_clk: si570_zsfp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_zsfp>;\n\t};\n\n\tsi570_user1_clk: si570_user1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_user1>;\n\t};\n\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vcc-soc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;\n\t};\n\tina226-vcc-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc-pslp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;\n\t};\n\tina226-vcc-psfp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;\n\t};\n\tina226-vccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;\n\t};\n\tina226-vccaux-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;\n\t};\n\tina226-vcco-500 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;\n\t};\n\tina226-vcco-501 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;\n\t};\n\tina226-vcco-502 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;\n\t};\n\tina226-vcco-503 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;\n\t};\n\tina226-vcc-1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;\n\t};\n\tina226-vcc-3v3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;\n\t};\n\tina226-vcc-1v2-ddr4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;\n\t};\n\tina226-vcc-1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtyavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;\n\t};\n\tina226-mgtyavtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;\n\t};\n\tina226-mgtyvccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;\n\t};\n\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* u131 M88E1512 */\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"ZU4_TRIGGER\", \"SYSCTLR_PB\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t\n\t\t\t/* u152 IR35215 0x16/0x46 vcc_soc */ \n\t\t\t/* u179 ir38164 0x19/0x49 vcco_500 */\n\t\t\t/* u181 ir38164 0x1a/0x4a vcco_501 */\n\t\t\t/* u183 ir38164 0x1b/0x4b vcco_502 */\n\t\t\t/* u185 ir38164 0x1e/0x4e vadj_fmc */\n\t\t\t/* u187 ir38164 0x1F/0x4f mgtyavcc */\n\t\t\t/* u189 ir38164 0x20/0x50 mgtyavtt */\n\t\t\t/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */\n\t\t\t/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */\n\n\t\t\tirps5401_47: irps5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* pmbus / i2c 0x17 */\n\t\t\t};\n\t\t\tirps5401_4c: irps5401@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* pmbus / i2c 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: irps5401@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* pmbus / i2c 0x1d */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* R440 */\n\t\t\t\t/* 0.78V @ 32A 1 of 6 Phases*/\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-soc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <2000>; /* R1186 */\n\t\t\t\t/* 0.78V @ 18A */\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pmc\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* R1214 */\n\t\t\t\t/* 0.78V @ 500mA */\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u162 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r1221 */\n\t\t\t\t/* 0.78V @ 4A */\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pslp\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>; /* R1216 */\n\t\t\t\t/* 0.78V @ 1A */\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-psfp\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1219 */\n\t\t\t\t/* 0.78V @ 2A */\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* R382 */\n\t\t\t\t/* 1.5V @ 3A */\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux-pmc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>; /* R1246 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u178 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-500\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>; /* R1300 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u180 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-501\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <2000>; /* R1313 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u182 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-502\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <2000>; /* R1330 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-503\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1229 */\n\t\t\t\t/* 1.8V @ 2A */\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u173 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v8\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>; /* R400 */\n\t\t\t\t/* 1.8V @ 6A */\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-3v3\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* R1232 */\n\t\t\t\t/* 3.3V @ 500mA */\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v2-ddr4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>; /* R1275 */\n\t\t\t\t/* 1.2V @ 4A */\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>; /* R1286 */\n\t\t\t\t/* 1.1V @ 4A */\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>; /* R1350 */\n\t\t\t\t/* 1.5V @ 10A */\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavcc\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <2000>; /* R1367 */\n\t\t\t\t/* 0.88V @ 6A */\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavtt\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>; /* R1384 */\n\t\t\t\t/* 1.2V @ 10A */\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyvccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>; /* r1679 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t\ti2c@5 { /* zSFP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_zsfp: clock-generator@5d { /* u192 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_zsfp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* USER_SI570_1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_user1: clock-generator@5d { /* u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>; /* FIXME check address */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"si570_user1\";\n\t\t\t};\n\n\t\t};\n\t\ti2c@7 { /* USER_SI570_2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* 0x5c too */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t};\n\t\t\t/* and connector J212D */\n\t\t};\n\t\tfmc1: i2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t};\n\t\tfmc2: i2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LPDDR4_SI570_CLK2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_lpddr4clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4clk1: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* 8A34001 - U219B and J310 connector */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-g-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 MGT Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-g-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u82 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 { /* eth MDIO 76/77 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 */\n\t\treg = <0>;\n\t\treset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 5 - 9 */\n\t\t \"\", \"\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"\", \"\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\ti2c-mux@74 { /* u94 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* CM_I2C_SCL - Samtec */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* PMBUS - AFX_PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\ttps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\ttps544@10 { /* u73 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\ttps544@11 { /* u76 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\ttps544@12 { /* u77 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\ttps544@13 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\ttps544@14 { /* u81 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\ttps544@15 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\ttps544@16 { /* u63 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\ttps544@17 { /* u66 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\ttps544@18 { /* u67 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\ttps544@19 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\ttps544@1d { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\ttps544@1e { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\ttps544@1f { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t\ttps544@20 { /* u71 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\t\t\tu74: ina226@40 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu75: ina226@41 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\"\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@43 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu82: ina226@44 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u82\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu84: ina226@45 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\ttps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* fmc1 via JA2G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom_fmc1: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* fmc2 via JA3G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\teeprom_fmc2: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* fmc3 via JA4G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\teeprom_fmc3: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* ddr dimm */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&usb0 { /* USB0 MIO52-63 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"high-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-01-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\tina226-vcc0v6-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc0v6_lp4: ina226@49 { /* u101 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc0v6-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@5d { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n status = \"okay\";\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n status = \"okay\";\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n status = \"disabled\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n /delete-property/ phy-names ;\n /delete-property/ phys ;\n maximum-speed = \"high-speed\";\n snps,dis_u2_susphy_quirk ;\n snps,dis_u3_susphy_quirk ;\n status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-02-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_vpp_2v5_ddr4: tps544@1x { /* u3007 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>; /* FIXME wrong in schematics */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* C0_DDR4_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\ti2c@6 { /* C2_DDR5_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\ti2c@7 { /* C3_DDR4_UDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_RLD3 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_RLD3_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_DDR5 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_DDR5_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-03-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_vpp_2v5_ddr4: tps544@1x { /* u3007 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>; /* FIXME wrong in schematics */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* DDR4_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_SODIMM_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_QDRIV */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_QDRIV_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-01-revA\", \"xlnx,zynqmp-x-prc-01\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\",\"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n status = \"okay\";\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane1 PHY_TYPE_USB3 0 1 26000000>;\n};\n\n&usb1 {\n status = \"okay\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"okay\";\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-02-revA\", \"xlnx,zynqmp-x-prc-02\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n status = \"okay\";\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane1 PHY_TYPE_USB3 0 1 26000000>;\n};\n\n&usb1 {\n status = \"okay\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"okay\";\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-03-revA\", \"xlnx,zynqmp-x-prc-03\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tx_prc_si5338: clock-generator@70 { /* U9 */\n\t\t\t\tcompatible = \"silabs,si5338\";\n\t\t\t\treg = <0x70>; /* FIXME */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n status = \"okay\";\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane1 PHY_TYPE_USB3 0 1 26000000>;\n};\n\n&usb1 {\n status = \"okay\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"okay\";\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-04-revA\", \"xlnx,zynqmp-x-prc-04\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n status = \"okay\";\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane1 PHY_TYPE_USB3 0 1 26000000>;\n};\n\n&usb1 {\n status = \"okay\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"okay\";\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-05-revA\", \"xlnx,zynqmp-x-prc-05\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n status = \"okay\";\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane1 PHY_TYPE_USB3 0 1 26000000>;\n};\n\n&usb1 {\n status = \"okay\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"okay\";\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n status = \"okay\";\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane1 PHY_TYPE_USB3 0 1 26000000>;\n};\n\n&usb1 {\n status = \"okay\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"okay\";\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/clock/xlnx-versal-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_VERSAL_H\n#define _DT_BINDINGS_CLK_VERSAL_H\n\n#define PMC_PLL\t\t\t\t\t1\n#define APU_PLL\t\t\t\t\t2\n#define RPU_PLL\t\t\t\t\t3\n#define CPM_PLL\t\t\t\t\t4\n#define NOC_PLL\t\t\t\t\t5\n#define PLL_MAX\t\t\t\t\t6\n#define PMC_PRESRC\t\t\t\t7\n#define PMC_POSTCLK\t\t\t\t8\n#define PMC_PLL_OUT\t\t\t\t9\n#define PPLL\t\t\t\t\t10\n#define NOC_PRESRC\t\t\t\t11\n#define NOC_POSTCLK\t\t\t\t12\n#define NOC_PLL_OUT\t\t\t\t13\n#define NPLL\t\t\t\t\t14\n#define APU_PRESRC\t\t\t\t15\n#define APU_POSTCLK\t\t\t\t16\n#define APU_PLL_OUT\t\t\t\t17\n#define APLL\t\t\t\t\t18\n#define RPU_PRESRC\t\t\t\t19\n#define RPU_POSTCLK\t\t\t\t20\n#define RPU_PLL_OUT\t\t\t\t21\n#define RPLL\t\t\t\t\t22\n#define CPM_PRESRC\t\t\t\t23\n#define CPM_POSTCLK\t\t\t\t24\n#define CPM_PLL_OUT\t\t\t\t25\n#define CPLL\t\t\t\t\t26\n#define PPLL_TO_XPD\t\t\t\t27\n#define NPLL_TO_XPD\t\t\t\t28\n#define APLL_TO_XPD\t\t\t\t29\n#define RPLL_TO_XPD\t\t\t\t30\n#define EFUSE_REF\t\t\t\t31\n#define SYSMON_REF\t\t\t\t32\n#define IRO_SUSPEND_REF\t\t\t\t33\n#define USB_SUSPEND\t\t\t\t34\n#define SWITCH_TIMEOUT\t\t\t\t35\n#define RCLK_PMC\t\t\t\t36\n#define RCLK_LPD\t\t\t\t37\n#define WDT\t\t\t\t\t38\n#define TTC0\t\t\t\t\t39\n#define TTC1\t\t\t\t\t40\n#define TTC2\t\t\t\t\t41\n#define TTC3\t\t\t\t\t42\n#define GEM_TSU\t\t\t\t\t43\n#define GEM_TSU_LB\t\t\t\t44\n#define MUXED_IRO_DIV2\t\t\t\t45\n#define MUXED_IRO_DIV4\t\t\t\t46\n#define PSM_REF\t\t\t\t\t47\n#define GEM0_RX\t\t\t\t\t48\n#define GEM0_TX\t\t\t\t\t49\n#define GEM1_RX\t\t\t\t\t50\n#define GEM1_TX\t\t\t\t\t51\n#define CPM_CORE_REF\t\t\t\t52\n#define CPM_LSBUS_REF\t\t\t\t53\n#define CPM_DBG_REF\t\t\t\t54\n#define CPM_AUX0_REF\t\t\t\t55\n#define CPM_AUX1_REF\t\t\t\t56\n#define QSPI_REF\t\t\t\t57\n#define OSPI_REF\t\t\t\t58\n#define SDIO0_REF\t\t\t\t59\n#define SDIO1_REF\t\t\t\t60\n#define PMC_LSBUS_REF\t\t\t\t61\n#define I2C_REF\t\t\t\t\t62\n#define TEST_PATTERN_REF\t\t\t63\n#define DFT_OSC_REF\t\t\t\t64\n#define PMC_PL0_REF\t\t\t\t65\n#define PMC_PL1_REF\t\t\t\t66\n#define PMC_PL2_REF\t\t\t\t67\n#define PMC_PL3_REF\t\t\t\t68\n#define CFU_REF\t\t\t\t\t69\n#define SPARE_REF\t\t\t\t70\n#define NPI_REF\t\t\t\t\t71\n#define HSM0_REF\t\t\t\t72\n#define HSM1_REF\t\t\t\t73\n#define SD_DLL_REF\t\t\t\t74\n#define FPD_TOP_SWITCH\t\t\t\t75\n#define FPD_LSBUS\t\t\t\t76\n#define ACPU\t\t\t\t\t77\n#define DBG_TRACE\t\t\t\t78\n#define DBG_FPD\t\t\t\t\t79\n#define LPD_TOP_SWITCH\t\t\t\t80\n#define ADMA\t\t\t\t\t81\n#define LPD_LSBUS\t\t\t\t82\n#define CPU_R5\t\t\t\t\t83\n#define CPU_R5_CORE\t\t\t\t84\n#define CPU_R5_OCM\t\t\t\t85\n#define CPU_R5_OCM2\t\t\t\t86\n#define IOU_SWITCH\t\t\t\t87\n#define GEM0_REF\t\t\t\t88\n#define GEM1_REF\t\t\t\t89\n#define GEM_TSU_REF\t\t\t\t90\n#define USB0_BUS_REF\t\t\t\t91\n#define UART0_REF\t\t\t\t92\n#define UART1_REF\t\t\t\t93\n#define SPI0_REF\t\t\t\t94\n#define SPI1_REF\t\t\t\t95\n#define CAN0_REF\t\t\t\t96\n#define CAN1_REF\t\t\t\t97\n#define I2C0_REF\t\t\t\t98\n#define I2C1_REF\t\t\t\t99\n#define DBG_LPD\t\t\t\t\t100\n#define TIMESTAMP_REF\t\t\t\t101\n#define DBG_TSTMP\t\t\t\t102\n#define CPM_TOPSW_REF\t\t\t\t103\n#define USB3_DUAL_REF\t\t\t\t104\n#define OUTCLK_MAX\t\t\t\t105\n#define REF_CLK\t\t\t\t\t106\n#define PL_ALT_REF_CLK\t\t\t\t107\n#define MUXED_IRO\t\t\t\t108\n#define PL_EXT\t\t\t\t\t109\n#define PL_LB\t\t\t\t\t110\n#define MIO_50_OR_51\t\t\t\t111\n#define MIO_24_OR_25\t\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Xilinx Zynq MPSoC Firmware layer\n *\n * Copyright (C) 2014-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_ZYNQMP_H\n#define _DT_BINDINGS_CLK_ZYNQMP_H\n\n#define IOPLL\t\t\t0\n#define RPLL\t\t\t1\n#define APLL\t\t\t2\n#define DPLL\t\t\t3\n#define VPLL\t\t\t4\n#define IOPLL_TO_FPD\t\t5\n#define RPLL_TO_FPD\t\t6\n#define APLL_TO_LPD\t\t7\n#define DPLL_TO_LPD\t\t8\n#define VPLL_TO_LPD\t\t9\n#define ACPU\t\t\t10\n#define ACPU_HALF\t\t11\n#define DBF_FPD\t\t\t12\n#define DBF_LPD\t\t\t13\n#define DBG_TRACE\t\t14\n#define DBG_TSTMP\t\t15\n#define DP_VIDEO_REF\t\t16\n#define DP_AUDIO_REF\t\t17\n#define DP_STC_REF\t\t18\n#define GDMA_REF\t\t19\n#define DPDMA_REF\t\t20\n#define DDR_REF\t\t\t21\n#define SATA_REF\t\t22\n#define PCIE_REF\t\t23\n#define GPU_REF\t\t\t24\n#define GPU_PP0_REF\t\t25\n#define GPU_PP1_REF\t\t26\n#define TOPSW_MAIN\t\t27\n#define TOPSW_LSBUS\t\t28\n#define GTGREF0_REF\t\t29\n#define LPD_SWITCH\t\t30\n#define LPD_LSBUS\t\t31\n#define USB0_BUS_REF\t\t32\n#define USB1_BUS_REF\t\t33\n#define USB3_DUAL_REF\t\t34\n#define USB0\t\t\t35\n#define USB1\t\t\t36\n#define CPU_R5\t\t\t37\n#define CPU_R5_CORE\t\t38\n#define CSU_SPB\t\t\t39\n#define CSU_PLL\t\t\t40\n#define PCAP\t\t\t41\n#define IOU_SWITCH\t\t42\n#define GEM_TSU_REF\t\t43\n#define GEM_TSU\t\t\t44\n#define GEM0_TX\t\t\t45\n#define GEM1_TX\t\t\t46\n#define GEM2_TX\t\t\t47\n#define GEM3_TX\t\t\t48\n#define GEM0_RX\t\t\t49\n#define GEM1_RX\t\t\t50\n#define GEM2_RX\t\t\t51\n#define GEM3_RX\t\t\t52\n#define QSPI_REF\t\t53\n#define SDIO0_REF\t\t54\n#define SDIO1_REF\t\t55\n#define UART0_REF\t\t56\n#define UART1_REF\t\t57\n#define SPI0_REF\t\t58\n#define SPI1_REF\t\t59\n#define NAND_REF\t\t60\n#define I2C0_REF\t\t61\n#define I2C1_REF\t\t62\n#define CAN0_REF\t\t63\n#define CAN1_REF\t\t64\n#define CAN0\t\t\t65\n#define CAN1\t\t\t66\n#define DLL_REF\t\t\t67\n#define ADMA_REF\t\t68\n#define TIMESTAMP_REF\t\t69\n#define AMS_REF\t\t\t70\n#define PL0_REF\t\t\t71\n#define PL1_REF\t\t\t72\n#define PL2_REF\t\t\t73\n#define PL3_REF\t\t\t74\n#define WDT\t\t\t75\n#define IOPLL_INT\t\t76\n#define IOPLL_PRE_SRC\t\t77\n#define IOPLL_HALF\t\t78\n#define IOPLL_INT_MUX\t\t79\n#define IOPLL_POST_SRC\t\t80\n#define RPLL_INT\t\t81\n#define RPLL_PRE_SRC\t\t82\n#define RPLL_HALF\t\t83\n#define RPLL_INT_MUX\t\t84\n#define RPLL_POST_SRC\t\t85\n#define APLL_INT\t\t86\n#define APLL_PRE_SRC\t\t87\n#define APLL_HALF\t\t88\n#define APLL_INT_MUX\t\t89\n#define APLL_POST_SRC\t\t90\n#define DPLL_INT\t\t91\n#define DPLL_PRE_SRC\t\t92\n#define DPLL_HALF\t\t93\n#define DPLL_INT_MUX\t\t94\n#define DPLL_POST_SRC\t\t95\n#define VPLL_INT\t\t96\n#define VPLL_PRE_SRC\t\t97\n#define VPLL_HALF\t\t98\n#define VPLL_INT_MUX\t\t99\n#define VPLL_POST_SRC\t\t100\n#define CAN0_MIO\t\t101\n#define CAN1_MIO\t\t102\n#define ACPU_FULL\t\t103\n#define GEM0_REF\t\t104\n#define GEM1_REF\t\t105\n#define GEM2_REF\t\t106\n#define GEM3_REF\t\t107\n#define GEM0_REF_UNG\t\t108\n#define GEM1_REF_UNG\t\t109\n#define GEM2_REF_UNG\t\t110\n#define GEM3_REF_UNG\t\t111\n#define LPD_WDT\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/gpio/gpio.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most GPIO bindings.\n *\n * Most GPIO bindings include a flags cell as part of the GPIO specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_GPIO_GPIO_H\n#define _DT_BINDINGS_GPIO_GPIO_H\n\n/* Bit 0 express polarity */\n#define GPIO_ACTIVE_HIGH 0\n#define GPIO_ACTIVE_LOW 1\n\n/* Bit 1 express single-endedness */\n#define GPIO_PUSH_PULL 0\n#define GPIO_SINGLE_ENDED 2\n\n/* Bit 2 express Open drain or open source */\n#define GPIO_LINE_OPEN_SOURCE 0\n#define GPIO_LINE_OPEN_DRAIN 4\n\n/*\n * * Open Drain/Collector is the combination of single-ended open drain interface.\n * * Open Source/Emitter is the combination of single-ended open source interface.\n * */\n#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)\n#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)\n\n/* Bit 3 express GPIO suspend/resume persistence */\n#define GPIO_SLEEP_MAINTAIN_VALUE 0\n#define GPIO_SLEEP_MAY_LOOSE_VALUE 8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/input/input.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most input bindings.\n *\n * Most input bindings include key code, matrix key code format.\n * In most cases, key code and matrix key code format uses\n * the standard values/macro defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INPUT_INPUT_H\n#define _DT_BINDINGS_INPUT_INPUT_H\n\n/*\n * Device properties and quirks\n */\n\n#define INPUT_PROP_POINTER\t\t0x00\t/* needs a pointer */\n#define INPUT_PROP_DIRECT\t\t0x01\t/* direct input devices */\n#define INPUT_PROP_BUTTONPAD\t\t0x02\t/* has button(s) under pad */\n#define INPUT_PROP_SEMI_MT\t\t0x03\t/* touch rectangle only */\n#define INPUT_PROP_TOPBUTTONPAD\t\t0x04\t/* softbuttons at top of pad */\n#define INPUT_PROP_POINTING_STICK\t0x05\t/* is a pointing stick */\n#define INPUT_PROP_ACCELEROMETER\t0x06\t/* has accelerometer */\n\n#define INPUT_PROP_MAX\t\t\t0x1f\n#define INPUT_PROP_CNT\t\t\t(INPUT_PROP_MAX + 1)\n\n\n/*\n * Event types\n */\n\n#define EV_SYN\t\t\t0x00\n#define EV_KEY\t\t\t0x01\n#define EV_REL\t\t\t0x02\n#define EV_ABS\t\t\t0x03\n#define EV_MSC\t\t\t0x04\n#define EV_SW\t\t\t0x05\n#define EV_LED\t\t\t0x11\n#define EV_SND\t\t\t0x12\n#define EV_REP\t\t\t0x14\n#define EV_FF\t\t\t0x15\n#define EV_PWR\t\t\t0x16\n#define EV_FF_STATUS\t\t0x17\n#define EV_MAX\t\t\t0x1f\n#define EV_CNT\t\t\t(EV_MAX+1)\n\n/*\n * Synchronization events.\n */\n\n#define SYN_REPORT\t\t0\n#define SYN_CONFIG\t\t1\n#define SYN_MT_REPORT\t\t2\n#define SYN_DROPPED\t\t3\n#define SYN_MAX\t\t\t0xf\n#define SYN_CNT\t\t\t(SYN_MAX+1)\n\n/*\n * Keys and buttons\n *\n * Most of the keys/buttons are modeled after USB HUT 1.12\n * (see http://www.usb.org/developers/hidpage).\n * Abbreviations in the comments:\n * AC - Application Control\n * AL - Application Launch Button\n * SC - System Control\n */\n\n#define KEY_RESERVED\t\t0\n#define KEY_ESC\t\t\t1\n#define KEY_1\t\t\t2\n#define KEY_2\t\t\t3\n#define KEY_3\t\t\t4\n#define KEY_4\t\t\t5\n#define KEY_5\t\t\t6\n#define KEY_6\t\t\t7\n#define KEY_7\t\t\t8\n#define KEY_8\t\t\t9\n#define KEY_9\t\t\t10\n#define KEY_0\t\t\t11\n#define KEY_MINUS\t\t12\n#define KEY_EQUAL\t\t13\n#define KEY_BACKSPACE\t\t14\n#define KEY_TAB\t\t\t15\n#define KEY_Q\t\t\t16\n#define KEY_W\t\t\t17\n#define KEY_E\t\t\t18\n#define KEY_R\t\t\t19\n#define KEY_T\t\t\t20\n#define KEY_Y\t\t\t21\n#define KEY_U\t\t\t22\n#define KEY_I\t\t\t23\n#define KEY_O\t\t\t24\n#define KEY_P\t\t\t25\n#define KEY_LEFTBRACE\t\t26\n#define KEY_RIGHTBRACE\t\t27\n#define KEY_ENTER\t\t28\n#define KEY_LEFTCTRL\t\t29\n#define KEY_A\t\t\t30\n#define KEY_S\t\t\t31\n#define KEY_D\t\t\t32\n#define KEY_F\t\t\t33\n#define KEY_G\t\t\t34\n#define KEY_H\t\t\t35\n#define KEY_J\t\t\t36\n#define KEY_K\t\t\t37\n#define KEY_L\t\t\t38\n#define KEY_SEMICOLON\t\t39\n#define KEY_APOSTROPHE\t\t40\n#define KEY_GRAVE\t\t41\n#define KEY_LEFTSHIFT\t\t42\n#define KEY_BACKSLASH\t\t43\n#define KEY_Z\t\t\t44\n#define KEY_X\t\t\t45\n#define KEY_C\t\t\t46\n#define KEY_V\t\t\t47\n#define KEY_B\t\t\t48\n#define KEY_N\t\t\t49\n#define KEY_M\t\t\t50\n#define KEY_COMMA\t\t51\n#define KEY_DOT\t\t\t52\n#define KEY_SLASH\t\t53\n#define KEY_RIGHTSHIFT\t\t54\n#define KEY_KPASTERISK\t\t55\n#define KEY_LEFTALT\t\t56\n#define KEY_SPACE\t\t57\n#define KEY_CAPSLOCK\t\t58\n#define KEY_F1\t\t\t59\n#define KEY_F2\t\t\t60\n#define KEY_F3\t\t\t61\n#define KEY_F4\t\t\t62\n#define KEY_F5\t\t\t63\n#define KEY_F6\t\t\t64\n#define KEY_F7\t\t\t65\n#define KEY_F8\t\t\t66\n#define KEY_F9\t\t\t67\n#define KEY_F10\t\t\t68\n#define KEY_NUMLOCK\t\t69\n#define KEY_SCROLLLOCK\t\t70\n#define KEY_KP7\t\t\t71\n#define KEY_KP8\t\t\t72\n#define KEY_KP9\t\t\t73\n#define KEY_KPMINUS\t\t74\n#define KEY_KP4\t\t\t75\n#define KEY_KP5\t\t\t76\n#define KEY_KP6\t\t\t77\n#define KEY_KPPLUS\t\t78\n#define KEY_KP1\t\t\t79\n#define KEY_KP2\t\t\t80\n#define KEY_KP3\t\t\t81\n#define KEY_KP0\t\t\t82\n#define KEY_KPDOT\t\t83\n\n#define KEY_ZENKAKUHANKAKU\t85\n#define KEY_102ND\t\t86\n#define KEY_F11\t\t\t87\n#define KEY_F12\t\t\t88\n#define KEY_RO\t\t\t89\n#define KEY_KATAKANA\t\t90\n#define KEY_HIRAGANA\t\t91\n#define KEY_HENKAN\t\t92\n#define KEY_KATAKANAHIRAGANA\t93\n#define KEY_MUHENKAN\t\t94\n#define KEY_KPJPCOMMA\t\t95\n#define KEY_KPENTER\t\t96\n#define KEY_RIGHTCTRL\t\t97\n#define KEY_KPSLASH\t\t98\n#define KEY_SYSRQ\t\t99\n#define KEY_RIGHTALT\t\t100\n#define KEY_LINEFEED\t\t101\n#define KEY_HOME\t\t102\n#define KEY_UP\t\t\t103\n#define KEY_PAGEUP\t\t104\n#define KEY_LEFT\t\t105\n#define KEY_RIGHT\t\t106\n#define KEY_END\t\t\t107\n#define KEY_DOWN\t\t108\n#define KEY_PAGEDOWN\t\t109\n#define KEY_INSERT\t\t110\n#define KEY_DELETE\t\t111\n#define KEY_MACRO\t\t112\n#define KEY_MUTE\t\t113\n#define KEY_VOLUMEDOWN\t\t114\n#define KEY_VOLUMEUP\t\t115\n#define KEY_POWER\t\t116\t/* SC System Power Down */\n#define KEY_KPEQUAL\t\t117\n#define KEY_KPPLUSMINUS\t\t118\n#define KEY_PAUSE\t\t119\n#define KEY_SCALE\t\t120\t/* AL Compiz Scale (Expose) */\n\n#define KEY_KPCOMMA\t\t121\n#define KEY_HANGEUL\t\t122\n#define KEY_HANGUEL\t\tKEY_HANGEUL\n#define KEY_HANJA\t\t123\n#define KEY_YEN\t\t\t124\n#define KEY_LEFTMETA\t\t125\n#define KEY_RIGHTMETA\t\t126\n#define KEY_COMPOSE\t\t127\n#define KEY_STOP\t\t128\t/* AC Stop */\n#define KEY_AGAIN\t\t129\n#define KEY_PROPS\t\t130\t/* AC Properties */\n#define KEY_UNDO\t\t131\t/* AC Undo */\n#define KEY_FRONT\t\t132\n#define KEY_COPY\t\t133\t/* AC Copy */\n#define KEY_OPEN\t\t134\t/* AC Open */\n#define KEY_PASTE\t\t135\t/* AC Paste */\n#define KEY_FIND\t\t136\t/* AC Search */\n#define KEY_CUT\t\t\t137\t/* AC Cut */\n#define KEY_HELP\t\t138\t/* AL Integrated Help Center */\n#define KEY_MENU\t\t139\t/* Menu (show menu) */\n#define KEY_CALC\t\t140\t/* AL Calculator */\n#define KEY_SETUP\t\t141\n#define KEY_SLEEP\t\t142\t/* SC System Sleep */\n#define KEY_WAKEUP\t\t143\t/* System Wake Up */\n#define KEY_FILE\t\t144\t/* AL Local Machine Browser */\n#define KEY_SENDFILE\t\t145\n#define KEY_DELETEFILE\t\t146\n#define KEY_XFER\t\t147\n#define KEY_PROG1\t\t148\n#define KEY_PROG2\t\t149\n#define KEY_WWW\t\t\t150\t/* AL Internet Browser */\n#define KEY_MSDOS\t\t151\n#define KEY_COFFEE\t\t152\t/* AL Terminal Lock/Screensaver */\n#define KEY_SCREENLOCK\t\tKEY_COFFEE\n#define KEY_ROTATE_DISPLAY\t153\t/* Display orientation for e.g. tablets */\n#define KEY_DIRECTION\t\tKEY_ROTATE_DISPLAY\n#define KEY_CYCLEWINDOWS\t154\n#define KEY_MAIL\t\t155\n#define KEY_BOOKMARKS\t\t156\t/* AC Bookmarks */\n#define KEY_COMPUTER\t\t157\n#define KEY_BACK\t\t158\t/* AC Back */\n#define KEY_FORWARD\t\t159\t/* AC Forward */\n#define KEY_CLOSECD\t\t160\n#define KEY_EJECTCD\t\t161\n#define KEY_EJECTCLOSECD\t162\n#define KEY_NEXTSONG\t\t163\n#define KEY_PLAYPAUSE\t\t164\n#define KEY_PREVIOUSSONG\t165\n#define KEY_STOPCD\t\t166\n#define KEY_RECORD\t\t167\n#define KEY_REWIND\t\t168\n#define KEY_PHONE\t\t169\t/* Media Select Telephone */\n#define KEY_ISO\t\t\t170\n#define KEY_CONFIG\t\t171\t/* AL Consumer Control Configuration */\n#define KEY_HOMEPAGE\t\t172\t/* AC Home */\n#define KEY_REFRESH\t\t173\t/* AC Refresh */\n#define KEY_EXIT\t\t174\t/* AC Exit */\n#define KEY_MOVE\t\t175\n#define KEY_EDIT\t\t176\n#define KEY_SCROLLUP\t\t177\n#define KEY_SCROLLDOWN\t\t178\n#define KEY_KPLEFTPAREN\t\t179\n#define KEY_KPRIGHTPAREN\t180\n#define KEY_NEW\t\t\t181\t/* AC New */\n#define KEY_REDO\t\t182\t/* AC Redo/Repeat */\n\n#define KEY_F13\t\t\t183\n#define KEY_F14\t\t\t184\n#define KEY_F15\t\t\t185\n#define KEY_F16\t\t\t186\n#define KEY_F17\t\t\t187\n#define KEY_F18\t\t\t188\n#define KEY_F19\t\t\t189\n#define KEY_F20\t\t\t190\n#define KEY_F21\t\t\t191\n#define KEY_F22\t\t\t192\n#define KEY_F23\t\t\t193\n#define KEY_F24\t\t\t194\n\n#define KEY_PLAYCD\t\t200\n#define KEY_PAUSECD\t\t201\n#define KEY_PROG3\t\t202\n#define KEY_PROG4\t\t203\n#define KEY_DASHBOARD\t\t204\t/* AL Dashboard */\n#define KEY_SUSPEND\t\t205\n#define KEY_CLOSE\t\t206\t/* AC Close */\n#define KEY_PLAY\t\t207\n#define KEY_FASTFORWARD\t\t208\n#define KEY_BASSBOOST\t\t209\n#define KEY_PRINT\t\t210\t/* AC Print */\n#define KEY_HP\t\t\t211\n#define KEY_CAMERA\t\t212\n#define KEY_SOUND\t\t213\n#define KEY_QUESTION\t\t214\n#define KEY_EMAIL\t\t215\n#define KEY_CHAT\t\t216\n#define KEY_SEARCH\t\t217\n#define KEY_CONNECT\t\t218\n#define KEY_FINANCE\t\t219\t/* AL Checkbook/Finance */\n#define KEY_SPORT\t\t220\n#define KEY_SHOP\t\t221\n#define KEY_ALTERASE\t\t222\n#define KEY_CANCEL\t\t223\t/* AC Cancel */\n#define KEY_BRIGHTNESSDOWN\t224\n#define KEY_BRIGHTNESSUP\t225\n#define KEY_MEDIA\t\t226\n\n#define KEY_SWITCHVIDEOMODE\t227\t/* Cycle between available video\n\t\t\t\t\t outputs (Monitor/LCD/TV-out/etc) */\n#define KEY_KBDILLUMTOGGLE\t228\n#define KEY_KBDILLUMDOWN\t229\n#define KEY_KBDILLUMUP\t\t230\n\n#define KEY_SEND\t\t231\t/* AC Send */\n#define KEY_REPLY\t\t232\t/* AC Reply */\n#define KEY_FORWARDMAIL\t\t233\t/* AC Forward Msg */\n#define KEY_SAVE\t\t234\t/* AC Save */\n#define KEY_DOCUMENTS\t\t235\n\n#define KEY_BATTERY\t\t236\n\n#define KEY_BLUETOOTH\t\t237\n#define KEY_WLAN\t\t238\n#define KEY_UWB\t\t\t239\n\n#define KEY_UNKNOWN\t\t240\n#define KEY_VIDEO_NEXT\t\t241\t/* drive next video source */\n#define KEY_VIDEO_PREV\t\t242\t/* drive previous video source */\n#define KEY_BRIGHTNESS_CYCLE\t243\t/* brightness up, after max is min */\n#define KEY_BRIGHTNESS_AUTO\t244\t/* Set Auto Brightness: manual\n\t\t\t\t\t brightness control is off,\n\t\t\t\t\t rely on ambient */\n#define KEY_BRIGHTNESS_ZERO\tKEY_BRIGHTNESS_AUTO\n#define KEY_DISPLAY_OFF\t\t245\t/* display device to off state */\n\n#define KEY_WWAN\t\t246\t/* Wireless WAN (LTE, UMTS, GSM, etc.) */\n#define KEY_WIMAX\t\tKEY_WWAN\n#define KEY_RFKILL\t\t247\t/* Key that controls all radios */\n\n#define KEY_MICMUTE\t\t248\t/* Mute / unmute the microphone */\n\n/* Code 255 is reserved for special needs of AT keyboard driver */\n\n#define BTN_MISC\t\t0x100\n#define BTN_0\t\t\t0x100\n#define BTN_1\t\t\t0x101\n#define BTN_2\t\t\t0x102\n#define BTN_3\t\t\t0x103\n#define BTN_4\t\t\t0x104\n#define BTN_5\t\t\t0x105\n#define BTN_6\t\t\t0x106\n#define BTN_7\t\t\t0x107\n#define BTN_8\t\t\t0x108\n#define BTN_9\t\t\t0x109\n\n#define BTN_MOUSE\t\t0x110\n#define BTN_LEFT\t\t0x110\n#define BTN_RIGHT\t\t0x111\n#define BTN_MIDDLE\t\t0x112\n#define BTN_SIDE\t\t0x113\n#define BTN_EXTRA\t\t0x114\n#define BTN_FORWARD\t\t0x115\n#define BTN_BACK\t\t0x116\n#define BTN_TASK\t\t0x117\n\n#define BTN_JOYSTICK\t\t0x120\n#define BTN_TRIGGER\t\t0x120\n#define BTN_THUMB\t\t0x121\n#define BTN_THUMB2\t\t0x122\n#define BTN_TOP\t\t\t0x123\n#define BTN_TOP2\t\t0x124\n#define BTN_PINKIE\t\t0x125\n#define BTN_BASE\t\t0x126\n#define BTN_BASE2\t\t0x127\n#define BTN_BASE3\t\t0x128\n#define BTN_BASE4\t\t0x129\n#define BTN_BASE5\t\t0x12a\n#define BTN_BASE6\t\t0x12b\n#define BTN_DEAD\t\t0x12f\n\n#define BTN_GAMEPAD\t\t0x130\n#define BTN_SOUTH\t\t0x130\n#define BTN_A\t\t\tBTN_SOUTH\n#define BTN_EAST\t\t0x131\n#define BTN_B\t\t\tBTN_EAST\n#define BTN_C\t\t\t0x132\n#define BTN_NORTH\t\t0x133\n#define BTN_X\t\t\tBTN_NORTH\n#define BTN_WEST\t\t0x134\n#define BTN_Y\t\t\tBTN_WEST\n#define BTN_Z\t\t\t0x135\n#define BTN_TL\t\t\t0x136\n#define BTN_TR\t\t\t0x137\n#define BTN_TL2\t\t\t0x138\n#define BTN_TR2\t\t\t0x139\n#define BTN_SELECT\t\t0x13a\n#define BTN_START\t\t0x13b\n#define BTN_MODE\t\t0x13c\n#define BTN_THUMBL\t\t0x13d\n#define BTN_THUMBR\t\t0x13e\n\n#define BTN_DIGI\t\t0x140\n#define BTN_TOOL_PEN\t\t0x140\n#define BTN_TOOL_RUBBER\t\t0x141\n#define BTN_TOOL_BRUSH\t\t0x142\n#define BTN_TOOL_PENCIL\t\t0x143\n#define BTN_TOOL_AIRBRUSH\t0x144\n#define BTN_TOOL_FINGER\t\t0x145\n#define BTN_TOOL_MOUSE\t\t0x146\n#define BTN_TOOL_LENS\t\t0x147\n#define BTN_TOOL_QUINTTAP\t0x148\t/* Five fingers on trackpad */\n#define BTN_TOUCH\t\t0x14a\n#define BTN_STYLUS\t\t0x14b\n#define BTN_STYLUS2\t\t0x14c\n#define BTN_TOOL_DOUBLETAP\t0x14d\n#define BTN_TOOL_TRIPLETAP\t0x14e\n#define BTN_TOOL_QUADTAP\t0x14f\t/* Four fingers on trackpad */\n\n#define BTN_WHEEL\t\t0x150\n#define BTN_GEAR_DOWN\t\t0x150\n#define BTN_GEAR_UP\t\t0x151\n\n#define KEY_OK\t\t\t0x160\n#define KEY_SELECT\t\t0x161\n#define KEY_GOTO\t\t0x162\n#define KEY_CLEAR\t\t0x163\n#define KEY_POWER2\t\t0x164\n#define KEY_OPTION\t\t0x165\n#define KEY_INFO\t\t0x166\t/* AL OEM Features/Tips/Tutorial */\n#define KEY_TIME\t\t0x167\n#define KEY_VENDOR\t\t0x168\n#define KEY_ARCHIVE\t\t0x169\n#define KEY_PROGRAM\t\t0x16a\t/* Media Select Program Guide */\n#define KEY_CHANNEL\t\t0x16b\n#define KEY_FAVORITES\t\t0x16c\n#define KEY_EPG\t\t\t0x16d\n#define KEY_PVR\t\t\t0x16e\t/* Media Select Home */\n#define KEY_MHP\t\t\t0x16f\n#define KEY_LANGUAGE\t\t0x170\n#define KEY_TITLE\t\t0x171\n#define KEY_SUBTITLE\t\t0x172\n#define KEY_ANGLE\t\t0x173\n#define KEY_ZOOM\t\t0x174\n#define KEY_MODE\t\t0x175\n#define KEY_KEYBOARD\t\t0x176\n#define KEY_SCREEN\t\t0x177\n#define KEY_PC\t\t\t0x178\t/* Media Select Computer */\n#define KEY_TV\t\t\t0x179\t/* Media Select TV */\n#define KEY_TV2\t\t\t0x17a\t/* Media Select Cable */\n#define KEY_VCR\t\t\t0x17b\t/* Media Select VCR */\n#define KEY_VCR2\t\t0x17c\t/* VCR Plus */\n#define KEY_SAT\t\t\t0x17d\t/* Media Select Satellite */\n#define KEY_SAT2\t\t0x17e\n#define KEY_CD\t\t\t0x17f\t/* Media Select CD */\n#define KEY_TAPE\t\t0x180\t/* Media Select Tape */\n#define KEY_RADIO\t\t0x181\n#define KEY_TUNER\t\t0x182\t/* Media Select Tuner */\n#define KEY_PLAYER\t\t0x183\n#define KEY_TEXT\t\t0x184\n#define KEY_DVD\t\t\t0x185\t/* Media Select DVD */\n#define KEY_AUX\t\t\t0x186\n#define KEY_MP3\t\t\t0x187\n#define KEY_AUDIO\t\t0x188\t/* AL Audio Browser */\n#define KEY_VIDEO\t\t0x189\t/* AL Movie Browser */\n#define KEY_DIRECTORY\t\t0x18a\n#define KEY_LIST\t\t0x18b\n#define KEY_MEMO\t\t0x18c\t/* Media Select Messages */\n#define KEY_CALENDAR\t\t0x18d\n#define KEY_RED\t\t\t0x18e\n#define KEY_GREEN\t\t0x18f\n#define KEY_YELLOW\t\t0x190\n#define KEY_BLUE\t\t0x191\n#define KEY_CHANNELUP\t\t0x192\t/* Channel Increment */\n#define KEY_CHANNELDOWN\t\t0x193\t/* Channel Decrement */\n#define KEY_FIRST\t\t0x194\n#define KEY_LAST\t\t0x195\t/* Recall Last */\n#define KEY_AB\t\t\t0x196\n#define KEY_NEXT\t\t0x197\n#define KEY_RESTART\t\t0x198\n#define KEY_SLOW\t\t0x199\n#define KEY_SHUFFLE\t\t0x19a\n#define KEY_BREAK\t\t0x19b\n#define KEY_PREVIOUS\t\t0x19c\n#define KEY_DIGITS\t\t0x19d\n#define KEY_TEEN\t\t0x19e\n#define KEY_TWEN\t\t0x19f\n#define KEY_VIDEOPHONE\t\t0x1a0\t/* Media Select Video Phone */\n#define KEY_GAMES\t\t0x1a1\t/* Media Select Games */\n#define KEY_ZOOMIN\t\t0x1a2\t/* AC Zoom In */\n#define KEY_ZOOMOUT\t\t0x1a3\t/* AC Zoom Out */\n#define KEY_ZOOMRESET\t\t0x1a4\t/* AC Zoom */\n#define KEY_WORDPROCESSOR\t0x1a5\t/* AL Word Processor */\n#define KEY_EDITOR\t\t0x1a6\t/* AL Text Editor */\n#define KEY_SPREADSHEET\t\t0x1a7\t/* AL Spreadsheet */\n#define KEY_GRAPHICSEDITOR\t0x1a8\t/* AL Graphics Editor */\n#define KEY_PRESENTATION\t0x1a9\t/* AL Presentation App */\n#define KEY_DATABASE\t\t0x1aa\t/* AL Database App */\n#define KEY_NEWS\t\t0x1ab\t/* AL Newsreader */\n#define KEY_VOICEMAIL\t\t0x1ac\t/* AL Voicemail */\n#define KEY_ADDRESSBOOK\t\t0x1ad\t/* AL Contacts/Address Book */\n#define KEY_MESSENGER\t\t0x1ae\t/* AL Instant Messaging */\n#define KEY_DISPLAYTOGGLE\t0x1af\t/* Turn display (LCD) on and off */\n#define KEY_BRIGHTNESS_TOGGLE\tKEY_DISPLAYTOGGLE\n#define KEY_SPELLCHECK\t\t0x1b0 /* AL Spell Check */\n#define KEY_LOGOFF\t\t0x1b1 /* AL Logoff */\n\n#define KEY_DOLLAR\t\t0x1b2\n#define KEY_EURO\t\t0x1b3\n\n#define KEY_FRAMEBACK\t\t0x1b4\t/* Consumer - transport controls */\n#define KEY_FRAMEFORWARD\t0x1b5\n#define KEY_CONTEXT_MENU\t0x1b6\t/* GenDesc - system context menu */\n#define KEY_MEDIA_REPEAT\t0x1b7\t/* Consumer - transport control */\n#define KEY_10CHANNELSUP\t0x1b8\t/* 10 channels up (10+) */\n#define KEY_10CHANNELSDOWN\t0x1b9\t/* 10 channels down (10-) */\n#define KEY_IMAGES\t\t0x1ba\t/* AL Image Browser */\n\n#define KEY_DEL_EOL\t\t0x1c0\n#define KEY_DEL_EOS\t\t0x1c1\n#define KEY_INS_LINE\t\t0x1c2\n#define KEY_DEL_LINE\t\t0x1c3\n\n#define KEY_FN\t\t\t0x1d0\n#define KEY_FN_ESC\t\t0x1d1\n#define KEY_FN_F1\t\t0x1d2\n#define KEY_FN_F2\t\t0x1d3\n#define KEY_FN_F3\t\t0x1d4\n#define KEY_FN_F4\t\t0x1d5\n#define KEY_FN_F5\t\t0x1d6\n#define KEY_FN_F6\t\t0x1d7\n#define KEY_FN_F7\t\t0x1d8\n#define KEY_FN_F8\t\t0x1d9\n#define KEY_FN_F9\t\t0x1da\n#define KEY_FN_F10\t\t0x1db\n#define KEY_FN_F11\t\t0x1dc\n#define KEY_FN_F12\t\t0x1dd\n#define KEY_FN_1\t\t0x1de\n#define KEY_FN_2\t\t0x1df\n#define KEY_FN_D\t\t0x1e0\n#define KEY_FN_E\t\t0x1e1\n#define KEY_FN_F\t\t0x1e2\n#define KEY_FN_S\t\t0x1e3\n#define KEY_FN_B\t\t0x1e4\n\n#define KEY_BRL_DOT1\t\t0x1f1\n#define KEY_BRL_DOT2\t\t0x1f2\n#define KEY_BRL_DOT3\t\t0x1f3\n#define KEY_BRL_DOT4\t\t0x1f4\n#define KEY_BRL_DOT5\t\t0x1f5\n#define KEY_BRL_DOT6\t\t0x1f6\n#define KEY_BRL_DOT7\t\t0x1f7\n#define KEY_BRL_DOT8\t\t0x1f8\n#define KEY_BRL_DOT9\t\t0x1f9\n#define KEY_BRL_DOT10\t\t0x1fa\n\n#define KEY_NUMERIC_0\t\t0x200\t/* used by phones, remote controls, */\n#define KEY_NUMERIC_1\t\t0x201\t/* and other keypads */\n#define KEY_NUMERIC_2\t\t0x202\n#define KEY_NUMERIC_3\t\t0x203\n#define KEY_NUMERIC_4\t\t0x204\n#define KEY_NUMERIC_5\t\t0x205\n#define KEY_NUMERIC_6\t\t0x206\n#define KEY_NUMERIC_7\t\t0x207\n#define KEY_NUMERIC_8\t\t0x208\n#define KEY_NUMERIC_9\t\t0x209\n#define KEY_NUMERIC_STAR\t0x20a\n#define KEY_NUMERIC_POUND\t0x20b\n#define KEY_NUMERIC_A\t\t0x20c\t/* Phone key A - HUT Telephony 0xb9 */\n#define KEY_NUMERIC_B\t\t0x20d\n#define KEY_NUMERIC_C\t\t0x20e\n#define KEY_NUMERIC_D\t\t0x20f\n\n#define KEY_CAMERA_FOCUS\t0x210\n#define KEY_WPS_BUTTON\t\t0x211\t/* WiFi Protected Setup key */\n\n#define KEY_TOUCHPAD_TOGGLE\t0x212\t/* Request switch touchpad on or off */\n#define KEY_TOUCHPAD_ON\t\t0x213\n#define KEY_TOUCHPAD_OFF\t0x214\n\n#define KEY_CAMERA_ZOOMIN\t0x215\n#define KEY_CAMERA_ZOOMOUT\t0x216\n#define KEY_CAMERA_UP\t\t0x217\n#define KEY_CAMERA_DOWN\t\t0x218\n#define KEY_CAMERA_LEFT\t\t0x219\n#define KEY_CAMERA_RIGHT\t0x21a\n\n#define KEY_ATTENDANT_ON\t0x21b\n#define KEY_ATTENDANT_OFF\t0x21c\n#define KEY_ATTENDANT_TOGGLE\t0x21d\t/* Attendant call on or off */\n#define KEY_LIGHTS_TOGGLE\t0x21e\t/* Reading light on or off */\n\n#define BTN_DPAD_UP\t\t0x220\n#define BTN_DPAD_DOWN\t\t0x221\n#define BTN_DPAD_LEFT\t\t0x222\n#define BTN_DPAD_RIGHT\t\t0x223\n\n#define KEY_ALS_TOGGLE\t\t0x230\t/* Ambient light sensor */\n\n#define KEY_BUTTONCONFIG\t\t0x240\t/* AL Button Configuration */\n#define KEY_TASKMANAGER\t\t0x241\t/* AL Task/Project Manager */\n#define KEY_JOURNAL\t\t0x242\t/* AL Log/Journal/Timecard */\n#define KEY_CONTROLPANEL\t\t0x243\t/* AL Control Panel */\n#define KEY_APPSELECT\t\t0x244\t/* AL Select Task/Application */\n#define KEY_SCREENSAVER\t\t0x245\t/* AL Screen Saver */\n#define KEY_VOICECOMMAND\t\t0x246\t/* Listening Voice Command */\n#define KEY_ASSISTANT\t\t0x247\t/* AL Context-aware desktop assistant */\n\n#define KEY_BRIGHTNESS_MIN\t\t0x250\t/* Set Brightness to Minimum */\n#define KEY_BRIGHTNESS_MAX\t\t0x251\t/* Set Brightness to Maximum */\n\n#define KEY_KBDINPUTASSIST_PREV\t\t0x260\n#define KEY_KBDINPUTASSIST_NEXT\t\t0x261\n#define KEY_KBDINPUTASSIST_PREVGROUP\t\t0x262\n#define KEY_KBDINPUTASSIST_NEXTGROUP\t\t0x263\n#define KEY_KBDINPUTASSIST_ACCEPT\t\t0x264\n#define KEY_KBDINPUTASSIST_CANCEL\t\t0x265\n\n/* Diagonal movement keys */\n#define KEY_RIGHT_UP\t\t\t0x266\n#define KEY_RIGHT_DOWN\t\t\t0x267\n#define KEY_LEFT_UP\t\t\t0x268\n#define KEY_LEFT_DOWN\t\t\t0x269\n\n#define KEY_ROOT_MENU\t\t\t0x26a /* Show Device's Root Menu */\n/* Show Top Menu of the Media (e.g. DVD) */\n#define KEY_MEDIA_TOP_MENU\t\t0x26b\n#define KEY_NUMERIC_11\t\t\t0x26c\n#define KEY_NUMERIC_12\t\t\t0x26d\n/*\n * Toggle Audio Description: refers to an audio service that helps blind and\n * visually impaired consumers understand the action in a program. Note: in\n * some countries this is referred to as \"Video Description\".\n */\n#define KEY_AUDIO_DESC\t\t\t0x26e\n#define KEY_3D_MODE\t\t\t0x26f\n#define KEY_NEXT_FAVORITE\t\t0x270\n#define KEY_STOP_RECORD\t\t\t0x271\n#define KEY_PAUSE_RECORD\t\t0x272\n#define KEY_VOD\t\t\t\t0x273 /* Video on Demand */\n#define KEY_UNMUTE\t\t\t0x274\n#define KEY_FASTREVERSE\t\t\t0x275\n#define KEY_SLOWREVERSE\t\t\t0x276\n/*\n * Control a data application associated with the currently viewed channel,\n * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)\n */\n#define KEY_DATA\t\t\t0x277\n#define KEY_ONSCREEN_KEYBOARD\t\t0x278\n\n#define BTN_TRIGGER_HAPPY\t\t0x2c0\n#define BTN_TRIGGER_HAPPY1\t\t0x2c0\n#define BTN_TRIGGER_HAPPY2\t\t0x2c1\n#define BTN_TRIGGER_HAPPY3\t\t0x2c2\n#define BTN_TRIGGER_HAPPY4\t\t0x2c3\n#define BTN_TRIGGER_HAPPY5\t\t0x2c4\n#define BTN_TRIGGER_HAPPY6\t\t0x2c5\n#define BTN_TRIGGER_HAPPY7\t\t0x2c6\n#define BTN_TRIGGER_HAPPY8\t\t0x2c7\n#define BTN_TRIGGER_HAPPY9\t\t0x2c8\n#define BTN_TRIGGER_HAPPY10\t\t0x2c9\n#define BTN_TRIGGER_HAPPY11\t\t0x2ca\n#define BTN_TRIGGER_HAPPY12\t\t0x2cb\n#define BTN_TRIGGER_HAPPY13\t\t0x2cc\n#define BTN_TRIGGER_HAPPY14\t\t0x2cd\n#define BTN_TRIGGER_HAPPY15\t\t0x2ce\n#define BTN_TRIGGER_HAPPY16\t\t0x2cf\n#define BTN_TRIGGER_HAPPY17\t\t0x2d0\n#define BTN_TRIGGER_HAPPY18\t\t0x2d1\n#define BTN_TRIGGER_HAPPY19\t\t0x2d2\n#define BTN_TRIGGER_HAPPY20\t\t0x2d3\n#define BTN_TRIGGER_HAPPY21\t\t0x2d4\n#define BTN_TRIGGER_HAPPY22\t\t0x2d5\n#define BTN_TRIGGER_HAPPY23\t\t0x2d6\n#define BTN_TRIGGER_HAPPY24\t\t0x2d7\n#define BTN_TRIGGER_HAPPY25\t\t0x2d8\n#define BTN_TRIGGER_HAPPY26\t\t0x2d9\n#define BTN_TRIGGER_HAPPY27\t\t0x2da\n#define BTN_TRIGGER_HAPPY28\t\t0x2db\n#define BTN_TRIGGER_HAPPY29\t\t0x2dc\n#define BTN_TRIGGER_HAPPY30\t\t0x2dd\n#define BTN_TRIGGER_HAPPY31\t\t0x2de\n#define BTN_TRIGGER_HAPPY32\t\t0x2df\n#define BTN_TRIGGER_HAPPY33\t\t0x2e0\n#define BTN_TRIGGER_HAPPY34\t\t0x2e1\n#define BTN_TRIGGER_HAPPY35\t\t0x2e2\n#define BTN_TRIGGER_HAPPY36\t\t0x2e3\n#define BTN_TRIGGER_HAPPY37\t\t0x2e4\n#define BTN_TRIGGER_HAPPY38\t\t0x2e5\n#define BTN_TRIGGER_HAPPY39\t\t0x2e6\n#define BTN_TRIGGER_HAPPY40\t\t0x2e7\n\n/* We avoid low common keys in module aliases so they don't get huge. */\n#define KEY_MIN_INTERESTING\tKEY_MUTE\n#define KEY_MAX\t\t\t0x2ff\n#define KEY_CNT\t\t\t(KEY_MAX+1)\n\n/*\n * Relative axes\n */\n\n#define REL_X\t\t\t0x00\n#define REL_Y\t\t\t0x01\n#define REL_Z\t\t\t0x02\n#define REL_RX\t\t\t0x03\n#define REL_RY\t\t\t0x04\n#define REL_RZ\t\t\t0x05\n#define REL_HWHEEL\t\t0x06\n#define REL_DIAL\t\t0x07\n#define REL_WHEEL\t\t0x08\n#define REL_MISC\t\t0x09\n#define REL_MAX\t\t\t0x0f\n#define REL_CNT\t\t\t(REL_MAX+1)\n\n/*\n * Absolute axes\n */\n\n#define ABS_X\t\t\t0x00\n#define ABS_Y\t\t\t0x01\n#define ABS_Z\t\t\t0x02\n#define ABS_RX\t\t\t0x03\n#define ABS_RY\t\t\t0x04\n#define ABS_RZ\t\t\t0x05\n#define ABS_THROTTLE\t\t0x06\n#define ABS_RUDDER\t\t0x07\n#define ABS_WHEEL\t\t0x08\n#define ABS_GAS\t\t\t0x09\n#define ABS_BRAKE\t\t0x0a\n#define ABS_HAT0X\t\t0x10\n#define ABS_HAT0Y\t\t0x11\n#define ABS_HAT1X\t\t0x12\n#define ABS_HAT1Y\t\t0x13\n#define ABS_HAT2X\t\t0x14\n#define ABS_HAT2Y\t\t0x15\n#define ABS_HAT3X\t\t0x16\n#define ABS_HAT3Y\t\t0x17\n#define ABS_PRESSURE\t\t0x18\n#define ABS_DISTANCE\t\t0x19\n#define ABS_TILT_X\t\t0x1a\n#define ABS_TILT_Y\t\t0x1b\n#define ABS_TOOL_WIDTH\t\t0x1c\n\n#define ABS_VOLUME\t\t0x20\n\n#define ABS_MISC\t\t0x28\n\n#define ABS_MT_SLOT\t\t0x2f\t/* MT slot being modified */\n#define ABS_MT_TOUCH_MAJOR\t0x30\t/* Major axis of touching ellipse */\n#define ABS_MT_TOUCH_MINOR\t0x31\t/* Minor axis (omit if circular) */\n#define ABS_MT_WIDTH_MAJOR\t0x32\t/* Major axis of approaching ellipse */\n#define ABS_MT_WIDTH_MINOR\t0x33\t/* Minor axis (omit if circular) */\n#define ABS_MT_ORIENTATION\t0x34\t/* Ellipse orientation */\n#define ABS_MT_POSITION_X\t0x35\t/* Center X touch position */\n#define ABS_MT_POSITION_Y\t0x36\t/* Center Y touch position */\n#define ABS_MT_TOOL_TYPE\t0x37\t/* Type of touching device */\n#define ABS_MT_BLOB_ID\t\t0x38\t/* Group a set of packets as a blob */\n#define ABS_MT_TRACKING_ID\t0x39\t/* Unique ID of initiated contact */\n#define ABS_MT_PRESSURE\t\t0x3a\t/* Pressure on contact area */\n#define ABS_MT_DISTANCE\t\t0x3b\t/* Contact hover distance */\n#define ABS_MT_TOOL_X\t\t0x3c\t/* Center X tool position */\n#define ABS_MT_TOOL_Y\t\t0x3d\t/* Center Y tool position */\n\n\n#define ABS_MAX\t\t\t0x3f\n#define ABS_CNT\t\t\t(ABS_MAX+1)\n\n/*\n * Switch events\n */\n\n#define SW_LID\t\t\t0x00 /* set = lid shut */\n#define SW_TABLET_MODE\t\t0x01 /* set = tablet mode */\n#define SW_HEADPHONE_INSERT\t0x02 /* set = inserted */\n#define SW_RFKILL_ALL\t\t0x03 /* rfkill master switch, type \"any\"\n\t\t\t\t\t set = radio enabled */\n#define SW_RADIO\t\tSW_RFKILL_ALL\t/* deprecated */\n#define SW_MICROPHONE_INSERT\t0x04 /* set = inserted */\n#define SW_DOCK\t\t\t0x05 /* set = plugged into dock */\n#define SW_LINEOUT_INSERT\t0x06 /* set = inserted */\n#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */\n#define SW_VIDEOOUT_INSERT\t0x08 /* set = inserted */\n#define SW_CAMERA_LENS_COVER\t0x09 /* set = lens covered */\n#define SW_KEYPAD_SLIDE\t\t0x0a /* set = keypad slide out */\n#define SW_FRONT_PROXIMITY\t0x0b /* set = front proximity sensor active */\n#define SW_ROTATE_LOCK\t\t0x0c /* set = rotate locked/disabled */\n#define SW_LINEIN_INSERT\t0x0d /* set = inserted */\n#define SW_MUTE_DEVICE\t\t0x0e /* set = device disabled */\n#define SW_PEN_INSERTED\t\t0x0f /* set = pen inserted */\n#define SW_MAX\t\t\t0x0f\n#define SW_CNT\t\t\t(SW_MAX+1)\n\n/*\n * Misc events\n */\n\n#define MSC_SERIAL\t\t0x00\n#define MSC_PULSELED\t\t0x01\n#define MSC_GESTURE\t\t0x02\n#define MSC_RAW\t\t\t0x03\n#define MSC_SCAN\t\t0x04\n#define MSC_TIMESTAMP\t\t0x05\n#define MSC_MAX\t\t\t0x07\n#define MSC_CNT\t\t\t(MSC_MAX+1)\n\n/*\n * LEDs\n */\n\n#define LED_NUML\t\t0x00\n#define LED_CAPSL\t\t0x01\n#define LED_SCROLLL\t\t0x02\n#define LED_COMPOSE\t\t0x03\n#define LED_KANA\t\t0x04\n#define LED_SLEEP\t\t0x05\n#define LED_SUSPEND\t\t0x06\n#define LED_MUTE\t\t0x07\n#define LED_MISC\t\t0x08\n#define LED_MAIL\t\t0x09\n#define LED_CHARGING\t\t0x0a\n#define LED_MAX\t\t\t0x0f\n#define LED_CNT\t\t\t(LED_MAX+1)\n\n/*\n * Autorepeat values\n */\n\n#define REP_DELAY\t\t0x00\n#define REP_PERIOD\t\t0x01\n#define REP_MAX\t\t\t0x01\n#define REP_CNT\t\t\t(REP_MAX+1)\n\n/*\n * Sounds\n */\n\n#define SND_CLICK\t\t0x00\n#define SND_BELL\t\t0x01\n#define SND_TONE\t\t0x02\n#define SND_MAX\t\t\t0x07\n#define SND_CNT\t\t\t(SND_MAX+1)\n\n#define MATRIX_KEY(row, col, code)\t\\\n\t((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))\n\n#endif /* _DT_BINDINGS_INPUT_INPUT_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/interrupt-controller/irq.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most IRQ bindings.\n *\n * Most IRQ bindings include a flags cell as part of the IRQ specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n\n#define IRQ_TYPE_NONE\t\t0\n#define IRQ_TYPE_EDGE_RISING\t1\n#define IRQ_TYPE_EDGE_FALLING\t2\n#define IRQ_TYPE_EDGE_BOTH\t(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)\n#define IRQ_TYPE_LEVEL_HIGH\t4\n#define IRQ_TYPE_LEVEL_LOW\t8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/phy/phy.h", "content": "/*\n *\n * This header provides constants for the phy framework\n *\n * Copyright (C) 2014 STMicroelectronics\n * Author: Gabriel Fernandez \n * License terms: GNU General Public License (GPL), version 2\n */\n\n#ifndef _DT_BINDINGS_PHY\n#define _DT_BINDINGS_PHY\n\n#define PHY_NONE\t\t0\n#define PHY_TYPE_SATA\t\t1\n#define PHY_TYPE_PCIE\t\t2\n#define PHY_TYPE_USB2\t\t3\n#define PHY_TYPE_USB3\t\t4\n#define PHY_TYPE_UFS\t\t5\n#define PHY_TYPE_DP\t\t6\n#define PHY_TYPE_SGMII\t\t7\n\n#endif /* _DT_BINDINGS_PHY */\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h", "content": "/*\n * MIO pin configuration defines for Xilinx ZynqMP\n *\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Author: Chirag Parekh \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * version 2 as published by the Free Software Foundation.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program. If not, see .\n */\n\n#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H\n#define _DT_BINDINGS_PINCTRL_ZYNQMP_H\n\n/* Bit value for IO standards */\n#define IO_STANDARD_LVCMOS33 0\n#define IO_STANDARD_LVCMOS18 1\n\n/* Bit values for Slew Rates */\n#define SLEW_RATE_FAST 0\n#define SLEW_RATE_SLOW 1\n\n/* Bit values for Pin inputs */\n#define PIN_INPUT_TYPE_CMOS 0\n#define PIN_INPUT_TYPE_SCHMITT 1\n\n/* Bit values for drive control*/\n#define DRIVE_STRENGTH_2MA 2\n#define DRIVE_STRENGTH_4MA 4\n#define DRIVE_STRENGTH_8MA 8\n#define DRIVE_STRENGTH_12MA 12\n\n#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/power/xlnx-versal-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_POWER_H\n#define _DT_BINDINGS_VERSAL_POWER_H\n\n#define PM_DEV_USB_0\t\t\t\t(0x18224018U)\n#define PM_DEV_GEM_0\t\t\t\t(0x18224019U)\n#define PM_DEV_GEM_1\t\t\t\t(0x1822401aU)\n#define PM_DEV_SPI_0\t\t\t\t(0x1822401bU)\n#define PM_DEV_SPI_1\t\t\t\t(0x1822401cU)\n#define PM_DEV_I2C_0\t\t\t\t(0x1822401dU)\n#define PM_DEV_I2C_1\t\t\t\t(0x1822401eU)\n#define PM_DEV_CAN_FD_0\t\t\t\t(0x1822401fU)\n#define PM_DEV_CAN_FD_1\t\t\t\t(0x18224020U)\n#define PM_DEV_UART_0\t\t\t\t(0x18224021U)\n#define PM_DEV_UART_1\t\t\t\t(0x18224022U)\n#define PM_DEV_GPIO\t\t\t\t(0x18224023U)\n#define PM_DEV_TTC_0\t\t\t\t(0x18224024U)\n#define PM_DEV_TTC_1\t\t\t\t(0x18224025U)\n#define PM_DEV_TTC_2\t\t\t\t(0x18224026U)\n#define PM_DEV_TTC_3\t\t\t\t(0x18224027U)\n#define PM_DEV_SWDT_FPD\t\t\t\t(0x18224029U)\n#define PM_DEV_OSPI\t\t\t\t(0x1822402aU)\n#define PM_DEV_QSPI\t\t\t\t(0x1822402bU)\n#define PM_DEV_GPIO_PMC\t\t\t\t(0x1822402cU)\n#define PM_DEV_SDIO_0\t\t\t\t(0x1822402eU)\n#define PM_DEV_SDIO_1\t\t\t\t(0x1822402fU)\n#define PM_DEV_RTC\t\t\t\t(0x18224034U)\n#define PM_DEV_ADMA_0\t\t\t\t(0x18224035U)\n#define PM_DEV_ADMA_1\t\t\t\t(0x18224036U)\n#define PM_DEV_ADMA_2\t\t\t\t(0x18224037U)\n#define PM_DEV_ADMA_3\t\t\t\t(0x18224038U)\n#define PM_DEV_ADMA_4\t\t\t\t(0x18224039U)\n#define PM_DEV_ADMA_5\t\t\t\t(0x1822403aU)\n#define PM_DEV_ADMA_6\t\t\t\t(0x1822403bU)\n#define PM_DEV_ADMA_7\t\t\t\t(0x1822403cU)\n#define PM_DEV_AI\t\t\t\t(0x18224072U)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/power/xlnx-zynqmp-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_POWER_H\n#define _DT_BINDINGS_ZYNQMP_POWER_H\n\n#define\t\tPD_USB_0\t22\n#define\t\tPD_USB_1\t23\n#define\t\tPD_TTC_0\t24\n#define\t\tPD_TTC_1\t25\n#define\t\tPD_TTC_2\t26\n#define\t\tPD_TTC_3\t27\n#define\t\tPD_SATA\t\t28\n#define\t\tPD_ETH_0\t29\n#define\t\tPD_ETH_1\t30\n#define\t\tPD_ETH_2\t31\n#define\t\tPD_ETH_3\t32\n#define\t\tPD_UART_0\t33\n#define\t\tPD_UART_1\t34\n#define\t\tPD_SPI_0\t35\n#define\t\tPD_SPI_1\t36\n#define\t\tPD_I2C_0\t37\n#define\t\tPD_I2C_1\t38\n#define\t\tPD_SD_0\t\t39\n#define\t\tPD_SD_1\t\t40\n#define\t\tPD_DP\t\t41\n#define\t\tPD_GDMA\t\t42\n#define\t\tPD_ADMA\t\t43\n#define\t\tPD_NAND\t\t44\n#define\t\tPD_QSPI\t\t45\n#define\t\tPD_GPIO\t\t46\n#define\t\tPD_CAN_0\t47\n#define\t\tPD_CAN_1\t48\n#define\t\tPD_GPU\t\t58\n#define\t\tPD_PCIE\t\t59\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H\n#define _DT_BINDINGS_ZYNQMP_RESETS_H\n\n#define\t\tZYNQMP_RESET_PCIE_CFG\t\t0\n#define\t\tZYNQMP_RESET_PCIE_BRIDGE\t1\n#define\t\tZYNQMP_RESET_PCIE_CTRL\t\t2\n#define\t\tZYNQMP_RESET_DP\t\t\t3\n#define\t\tZYNQMP_RESET_SWDT_CRF\t\t4\n#define\t\tZYNQMP_RESET_AFI_FM5\t\t5\n#define\t\tZYNQMP_RESET_AFI_FM4\t\t6\n#define\t\tZYNQMP_RESET_AFI_FM3\t\t7\n#define\t\tZYNQMP_RESET_AFI_FM2\t\t8\n#define\t\tZYNQMP_RESET_AFI_FM1\t\t9\n#define\t\tZYNQMP_RESET_AFI_FM0\t\t10\n#define\t\tZYNQMP_RESET_GDMA\t\t11\n#define\t\tZYNQMP_RESET_GPU_PP1\t\t12\n#define\t\tZYNQMP_RESET_GPU_PP0\t\t13\n#define\t\tZYNQMP_RESET_GPU\t\t14\n#define\t\tZYNQMP_RESET_GT\t\t\t15\n#define\t\tZYNQMP_RESET_SATA\t\t16\n#define\t\tZYNQMP_RESET_ACPU3_PWRON\t17\n#define\t\tZYNQMP_RESET_ACPU2_PWRON\t18\n#define\t\tZYNQMP_RESET_ACPU1_PWRON\t19\n#define\t\tZYNQMP_RESET_ACPU0_PWRON\t20\n#define\t\tZYNQMP_RESET_APU_L2\t\t21\n#define\t\tZYNQMP_RESET_ACPU3\t\t22\n#define\t\tZYNQMP_RESET_ACPU2\t\t23\n#define\t\tZYNQMP_RESET_ACPU1\t\t24\n#define\t\tZYNQMP_RESET_ACPU0\t\t25\n#define\t\tZYNQMP_RESET_DDR\t\t26\n#define\t\tZYNQMP_RESET_APM_FPD\t\t27\n#define\t\tZYNQMP_RESET_SOFT\t\t28\n#define\t\tZYNQMP_RESET_GEM0\t\t29\n#define\t\tZYNQMP_RESET_GEM1\t\t30\n#define\t\tZYNQMP_RESET_GEM2\t\t31\n#define\t\tZYNQMP_RESET_GEM3\t\t32\n#define\t\tZYNQMP_RESET_QSPI\t\t33\n#define\t\tZYNQMP_RESET_UART0\t\t34\n#define\t\tZYNQMP_RESET_UART1\t\t35\n#define\t\tZYNQMP_RESET_SPI0\t\t36\n#define\t\tZYNQMP_RESET_SPI1\t\t37\n#define\t\tZYNQMP_RESET_SDIO0\t\t38\n#define\t\tZYNQMP_RESET_SDIO1\t\t39\n#define\t\tZYNQMP_RESET_CAN0\t\t40\n#define\t\tZYNQMP_RESET_CAN1\t\t41\n#define\t\tZYNQMP_RESET_I2C0\t\t42\n#define\t\tZYNQMP_RESET_I2C1\t\t43\n#define\t\tZYNQMP_RESET_TTC0\t\t44\n#define\t\tZYNQMP_RESET_TTC1\t\t45\n#define\t\tZYNQMP_RESET_TTC2\t\t46\n#define\t\tZYNQMP_RESET_TTC3\t\t47\n#define\t\tZYNQMP_RESET_SWDT_CRL\t\t48\n#define\t\tZYNQMP_RESET_NAND\t\t49\n#define\t\tZYNQMP_RESET_ADMA\t\t50\n#define\t\tZYNQMP_RESET_GPIO\t\t51\n#define\t\tZYNQMP_RESET_IOU_CC\t\t52\n#define\t\tZYNQMP_RESET_TIMESTAMP\t\t53\n#define\t\tZYNQMP_RESET_RPU_R50\t\t54\n#define\t\tZYNQMP_RESET_RPU_R51\t\t55\n#define\t\tZYNQMP_RESET_RPU_AMBA\t\t56\n#define\t\tZYNQMP_RESET_OCM\t\t57\n#define\t\tZYNQMP_RESET_RPU_PGE\t\t58\n#define\t\tZYNQMP_RESET_USB0_CORERESET\t59\n#define\t\tZYNQMP_RESET_USB1_CORERESET\t60\n#define\t\tZYNQMP_RESET_USB0_HIBERRESET\t61\n#define\t\tZYNQMP_RESET_USB1_HIBERRESET\t62\n#define\t\tZYNQMP_RESET_USB0_APB\t\t63\n#define\t\tZYNQMP_RESET_USB1_APB\t\t64\n#define\t\tZYNQMP_RESET_IPI\t\t65\n#define\t\tZYNQMP_RESET_APM_LPD\t\t66\n#define\t\tZYNQMP_RESET_RTC\t\t67\n#define\t\tZYNQMP_RESET_SYSMON\t\t68\n#define\t\tZYNQMP_RESET_AFI_FM6\t\t69\n#define\t\tZYNQMP_RESET_LPD_SWDT\t\t70\n#define\t\tZYNQMP_RESET_FPD\t\t71\n#define\t\tZYNQMP_RESET_RPU_DBG1\t\t72\n#define\t\tZYNQMP_RESET_RPU_DBG0\t\t73\n#define\t\tZYNQMP_RESET_DBG_LPD\t\t74\n#define\t\tZYNQMP_RESET_DBG_FPD\t\t75\n#define\t\tZYNQMP_RESET_APLL\t\t76\n#define\t\tZYNQMP_RESET_DPLL\t\t77\n#define\t\tZYNQMP_RESET_VPLL\t\t78\n#define\t\tZYNQMP_RESET_IOPLL\t\t79\n#define\t\tZYNQMP_RESET_RPLL\t\t80\n#define\t\tZYNQMP_RESET_GPO3_PL_0\t\t81\n#define\t\tZYNQMP_RESET_GPO3_PL_1\t\t82\n#define\t\tZYNQMP_RESET_GPO3_PL_2\t\t83\n#define\t\tZYNQMP_RESET_GPO3_PL_3\t\t84\n#define\t\tZYNQMP_RESET_GPO3_PL_4\t\t85\n#define\t\tZYNQMP_RESET_GPO3_PL_5\t\t86\n#define\t\tZYNQMP_RESET_GPO3_PL_6\t\t87\n#define\t\tZYNQMP_RESET_GPO3_PL_7\t\t88\n#define\t\tZYNQMP_RESET_GPO3_PL_8\t\t89\n#define\t\tZYNQMP_RESET_GPO3_PL_9\t\t90\n#define\t\tZYNQMP_RESET_GPO3_PL_10\t\t91\n#define\t\tZYNQMP_RESET_GPO3_PL_11\t\t92\n#define\t\tZYNQMP_RESET_GPO3_PL_12\t\t93\n#define\t\tZYNQMP_RESET_GPO3_PL_13\t\t94\n#define\t\tZYNQMP_RESET_GPO3_PL_14\t\t95\n#define\t\tZYNQMP_RESET_GPO3_PL_15\t\t96\n#define\t\tZYNQMP_RESET_GPO3_PL_16\t\t97\n#define\t\tZYNQMP_RESET_GPO3_PL_17\t\t98\n#define\t\tZYNQMP_RESET_GPO3_PL_18\t\t99\n#define\t\tZYNQMP_RESET_GPO3_PL_19\t\t100\n#define\t\tZYNQMP_RESET_GPO3_PL_20\t\t101\n#define\t\tZYNQMP_RESET_GPO3_PL_21\t\t102\n#define\t\tZYNQMP_RESET_GPO3_PL_22\t\t103\n#define\t\tZYNQMP_RESET_GPO3_PL_23\t\t104\n#define\t\tZYNQMP_RESET_GPO3_PL_24\t\t105\n#define\t\tZYNQMP_RESET_GPO3_PL_25\t\t106\n#define\t\tZYNQMP_RESET_GPO3_PL_26\t\t107\n#define\t\tZYNQMP_RESET_GPO3_PL_27\t\t108\n#define\t\tZYNQMP_RESET_GPO3_PL_28\t\t109\n#define\t\tZYNQMP_RESET_GPO3_PL_29\t\t110\n#define\t\tZYNQMP_RESET_GPO3_PL_30\t\t111\n#define\t\tZYNQMP_RESET_GPO3_PL_31\t\t112\n#define\t\tZYNQMP_RESET_RPU_LS\t\t113\n#define\t\tZYNQMP_RESET_PS_ONLY\t\t114\n#define\t\tZYNQMP_RESET_PL\t\t\t115\n#define\t\tZYNQMP_RESET_PS_PL0\t\t116\n#define\t\tZYNQMP_RESET_PS_PL1\t\t117\n#define\t\tZYNQMP_RESET_PS_PL2\t\t118\n#define\t\tZYNQMP_RESET_PS_PL3\t\t119\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/versal/versal-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-versal-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-power.h\"\n/ {\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tcan0_clk: can0_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN0_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tcan1_clk: can1_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN1_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk ACPU>;\n};\n\n&can0 {\n\tclocks = <&can0_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_0>;\n};\n\n&can1 {\n\tclocks = <&can1_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_1>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_0>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_1>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk PMC_LSBUS_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO_PMC>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk I2C0_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_0>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk I2C1_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_1>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_0>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_1>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_2>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_3>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_4>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_5>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_6>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_7>;\n};\n\n&qspi {\n\tclocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_QSPI>;\n};\n\n&ospi {\n\tclocks = <&versal_clk OSPI_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_OSPI>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware PM_DEV_RTC>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_0>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_1>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_0>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_1>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_0>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_1>;\n};\n\n&ttc0 {\n\tclocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_0>;\n};\n\n&ttc1 {\n\tclocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_1>;\n};\n\n&ttc2 {\n\tclocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_2>;\n};\n\n&ttc3 {\n\tclocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_3>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_USB_0>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SWDT_FPD>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/versal/versal-spp-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\talt_ref_clk: alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware-wip\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"alt_ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk 77>;\n};\n\n&can0 {\n\tclocks = <&versal_clk 96>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401f>;\n};\n\n&can1 {\n\tclocks = <&versal_clk 97>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224020>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x18224019>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x1822401a>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk 61>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk 98>;\n\tpower-domains = <&versal_firmware 0x1822401d>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk 99>;\n\tpower-domains = <&versal_firmware 0x1822401e>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224035>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224036>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224037>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224038>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224039>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403a>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403b>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403c>;\n};\n\n&qspi {\n\tclocks = <&versal_clk 57>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402b>;\n};\n\n&ospi {\n\tclocks = <&versal_clk 58>, <&versal_clk 82>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware 0x18224034>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk 92>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224021>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk 93>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224022>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk 59>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402e>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk 60>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402f>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk 94>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401b>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk 95>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401c>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk 91>, <&versal_clk 104>;\n\tpower-domains = <&versal_firmware 0x18224018>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk 82>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/versal/versal.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal\";\n\n\tcpus: cpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <1>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tfpga: fpga {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&versal_fpga>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tpsci: psci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t};\n\n\tversal_fpga: versal_fpga {\n\t\tcompatible = \"xlnx,versal-fpga\";\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\t\t\treg = <0 0xf9000000 0 0x80000>, /* GICD */\n\t\t\t <0 0xf9080000 0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 4>;\n\n\t\t\tgic_its: gic-its@f9020000 {\n\t\t\t\tcompatible = \"arm,gic-v3-its\";\n\t\t\t\tmsi-controller;\n\t\t\t\tmsi-cells = <1>;\n\t\t\t\treg = <0 0xf9020000 0 0x20000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t\tinterrupt-parent = <&gic>;\n\t\tu-boot,dm-pre-reloc;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff060000 0 0x6000>;\n\t\t\tinterrupts = <0 20 1>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff070000 0 0x6000>;\n\t\t\tinterrupts = <0 21 1>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcci: cci@fd000000 {\n\t\t\tcompatible = \"arm,cci-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd000000 0 0x10000>;\n\t\t\tranges = <0 0 0xfd000000 0xa0000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcci_pmu: pmu@10000 {\n\t\t\t\tcompatible = \"arm,cci-500-pmu,r0\";\n\t\t\t\treg = <0x10000 0x90000>;\n\t\t\t\tinterrupts = <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>;\n\t\t\t};\n\t\t};\n\n\t\tlpd_dma_chan0: dma@ffa80000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa80000 0 0x1000>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa90000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa90000 0 0x1000>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffaa0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaa0000 0 0x1000>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\n\t\tlpd_dma_chan3: dma@ffab0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffab0000 0 0x1000>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffac0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffac0000 0 0x1000>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffad0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffad0000 0 0x1000>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffae0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffae0000 0 0x1000>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffaf0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaf0000 0 0x1000>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tgem0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,versal-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0c0000 0 0x1000>;\n\t\t\tinterrupts = <0 56 4>, <0 56 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,versal-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0d0000 0 0x1000>;\n\t\t\tinterrupts = <0 58 4>, <0 58 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tgpio0: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0b0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff020000 0 0x1000>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff030000 0 0x1000>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff000000 0 0x1000>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tserial1: serial@ff010000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff010000 0 0x1000>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd800000 0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 124 4>, <0 124 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,is-stig-pgm = <1>;\n\t\t\tcdns,trigger-address = <0xC0000000>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff040000 0 0x1000>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff050000 0 0x1000>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tttc0: timer@ff0e0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff0f0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 40 4>, <0 41 4>, <0 42 4>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff100000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 46 4>, <0 47 4>, <0 48 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tusb0: usb@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff9d0000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0 0xfe200000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"usb-wakeup\";\n\t\t\t\tinterrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,mask_phy_reset;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\tcpm_pciea: pci@fca10000 {\n\t\t\t#address-cells = <3>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"xlnx,versal-cpm-host-1.00\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc_0 1>,\n\t\t\t\t\t<0 0 0 2 &pcie_intc_0 2>,\n\t\t\t\t\t<0 0 0 3 &pcie_intc_0 3>,\n\t\t\t\t\t<0 0 0 4 &pcie_intc_0 4>;\n\t\t\tinterrupt-map-mask = <0 0 0 7>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupt-names = \"misc\";\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>,\n\t\t\t\t <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>;\n\t\t\tmsi-map = <0x0 &gic_its 0x0 0x10000>;\n\t\t\treg = <0x0 0xfca10000 0x0 0x1000>,\n\t\t\t <0x6 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"cpm_slcr\", \"cfg\";\n\t\t\tpcie_intc_0: pci-interrupt-controller {\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\tinterrupt-controller ;\n\t\t\t};\n\t\t};\n\n\t\twatchdog: watchdog@fd4d0000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd4d0000 0 0x10000>;\n\t\t\ttimeout-sec = <60>;\n\t\t};\n\t};\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/zynq/zynq-7000.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\treplicator {\n\t\tcompatible = \"arm,coresight-static-replicator\";\n\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\tout-ports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\t/* replicator output ports */\n\t\t\tport@0 {\n\t\t\t\treg = <0>;\n\t\t\t\treplicator_out_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&tpiu_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tport@1 {\n\t\t\t\treg = <1>;\n\t\t\t\treplicator_out_port1: endpoint {\n\t\t\t\t\tremote-endpoint = <&etb_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tin-ports {\n\t\t\t/* replicator input port */\n\t\t\tport {\n\t\t\t\treplicator_in_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&funnel_out_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"apb_pclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\", \"arm,primecell\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: mmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: mmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\tetb@f8801000 {\n\t\t\tcompatible = \"arm,coresight-etb10\", \"arm,primecell\";\n\t\t\treg = <0xf8801000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\tetb_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ttpiu@f8803000 {\n\t\t\tcompatible = \"arm,coresight-tpiu\", \"arm,primecell\";\n\t\t\treg = <0xf8803000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\ttpiu_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tfunnel@f8804000 {\n\t\t\tcompatible = \"arm,coresight-static-funnel\", \"arm,primecell\";\n\t\t\treg = <0xf8804000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\t\t/* funnel output ports */\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tfunnel_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint =\n\t\t\t\t\t\t\t<&replicator_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tin-ports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\t/* funnel input ports */\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tfunnel0_in_port0: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm0_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tfunnel0_in_port1: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm1_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tfunnel0_in_port2: endpoint {\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t/* The other input ports are not connect to anything */\n\t\t\t};\n\t\t};\n\n\t\tptm@f889c000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889c000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu0>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm0_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889d000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889d000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu1>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm1_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/zynqmp/zynqmp-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-zynqmp-clk.h\"\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL0_REF>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL1_REF>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL2_REF>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL3_REF>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tdp_aclk: dp_aclk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&zynqmp_firmware {\n\tzynqmp_clk: clock-controller {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,\n\t\t\t <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\",\n\t\t\t \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t};\n};\n\n&can0 {\n\tclocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&can1 {\n\tclocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&cpu0 {\n\tclocks = <&zynqmp_clk ACPU>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gpu {\n\tclocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&nand0 {\n\tclocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gem0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>,\n\t\t <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>,\n\t\t <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>,\n\t\t <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>,\n\t\t <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gpio {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&i2c0 {\n\tclocks = <&zynqmp_clk I2C0_REF>;\n};\n\n&i2c1 {\n\tclocks = <&zynqmp_clk I2C1_REF>;\n};\n\n&perf_monitor_ocm {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&perf_monitor_ddr {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_cci {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_lpd {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&pcie {\n\tclocks = <&zynqmp_clk PCIE_REF>;\n};\n\n&qspi {\n\tclocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&sata {\n\tclocks = <&zynqmp_clk SATA_REF>;\n};\n\n&sdhci0 {\n\tclocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&sdhci1 {\n\tclocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&spi0 {\n\tclocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&spi1 {\n\tclocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart0 {\n\tclocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart1 {\n\tclocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&usb0 {\n\tclocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&usb1 {\n\tclocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&watchdog0 {\n\tclocks = <&zynqmp_clk WDT>;\n};\n\n&lpd_watchdog {\n\tclocks = <&zynqmp_clk LPD_WDT>;\n};\n\n&xilinx_ams {\n\tclocks = <&zynqmp_clk AMS_REF>;\n};\n\n&zynqmp_dpsub {\n\tclocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&zynqmp_clk DPDMA_REF>;\n};\n\n&zynqmp_dp_snd_codec0 {\n\tclocks = <&zynqmp_clk DP_AUDIO_REF>;\n};\n\n&zynqmp_pcap {\n\tclocks = <&zynqmp_clk PCAP>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.1/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n#include \"include/dt-bindings/power/xlnx-zynqmp-power.h\"\n#include \"include/dt-bindings/reset/xlnx-zynqmp-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu-opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t\txlnx,ipi-id = <0>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff990400 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\treg = <0x0 0xff9905c0 0x0 0x20>,\n\t\t\t <0x0 0xff9905e0 0x0 0x20>,\n\t\t\t <0x0 0xff990e80 0x0 0x20>,\n\t\t\t <0x0 0xff990ea0 0x0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <4>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tzynqmp_firmware: zynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x1>;\n\n\t\t\tzynqmp_pcap: pcap {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t\t\t\tclock-names = \"ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tzynqmp_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\t\t};\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&zynqmp_pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t};\n\n\tnvmem_firmware {\n\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsoc_revision: soc_revision@0 {\n\t\t\treg = <0x0 0x4>;\n\t\t};\n\t\t/* efuse access */\n\t\tefuse_dna: efuse_dna@c {\n\t\t\treg = <0xc 0xc>;\n\t\t};\n\t\tefuse_usr0: efuse_usr0@20 {\n\t\t\treg = <0x20 0x4>;\n\t\t};\n\t\tefuse_usr1: efuse_usr1@24 {\n\t\t\treg = <0x24 0x4>;\n\t\t};\n\t\tefuse_usr2: efuse_usr2@28 {\n\t\t\treg = <0x28 0x4>;\n\t\t};\n\t\tefuse_usr3: efuse_usr3@2c {\n\t\t\treg = <0x2c 0x4>;\n\t\t};\n\t\tefuse_usr4: efuse_usr4@30 {\n\t\t\treg = <0x30 0x4>;\n\t\t};\n\t\tefuse_usr5: efuse_usr5@34 {\n\t\t\treg = <0x34 0x4>;\n\t\t};\n\t\tefuse_usr6: efuse_usr6@38 {\n\t\t\treg = <0x38 0x4>;\n\t\t};\n\t\tefuse_usr7: efuse_usr7@3c {\n\t\t\treg = <0x3c 0x4>;\n\t\t};\n\t\tefuse_miscusr: efuse_miscusr@40 {\n\t\t\treg = <0x40 0x4>;\n\t\t};\n\t\tefuse_chash: efuse_chash@50 {\n\t\t\treg = <0x50 0x4>;\n\t\t};\n\t\tefuse_pufmisc: efuse_pufmisc@54 {\n\t\t\treg = <0x54 0x4>;\n\t\t};\n\t\tefuse_sec: efuse_sec@58 {\n\t\t\treg = <0x58 0x4>;\n\t\t};\n\t\tefuse_spkid: efuse_spkid@5c {\n\t\t\treg = <0x5c 0x4>;\n\t\t};\n\t\tefuse_ppk0hash: efuse_ppk0hash@a0 {\n\t\t\treg = <0xa0 0x30>;\n\t\t};\n\t\tefuse_ppk1hash: efuse_ppk1hash@d0 {\n\t\t\treg = <0xd0 0x30>;\n\t\t};\n\t};\n\n\txlnx_rsa: zynqmp_rsa {\n\t\tcompatible = \"xlnx,zynqmp-rsa\";\n\t};\n\n\txlnx_keccak_384: sha384 {\n\t\tcompatible = \"xlnx,zynqmp-keccak-384\";\n\t};\n\n\txlnx_aes: zynqmp_aes {\n\t\tcompatible = \"xlnx,zynqmp-aes\";\n\t};\n\n\tamba_apu: amba-apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tsmmu: smmu@fd800000 {\n\t\tcompatible = \"arm,mmu-500\";\n\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t#iommu-cells = <1>;\n\t\tstatus = \"disabled\";\n\t\t#global-interrupts = <1>;\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\", \"gpu_pp0\", \"gpu_pp1\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPU>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_NAND>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPIO>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tperf_monitor_ocm: perf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa00000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_ddr: perf-monitor@fd0b0000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd0b0000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <6>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <10>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_cci: perf-monitor@fd490000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd490000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_lpd: perf-monitor@ffa10000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa10000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_PCIE>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_QSPI>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tserdes: zynqmp_phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\";\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SATA>, <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_APB>, <&zynqmp_reset ZYNQMP_RESET_DP>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_GEM0>, <&zynqmp_reset ZYNQMP_RESET_GEM1>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_GEM2>, <&zynqmp_reset ZYNQMP_RESET_GEM3>;\n\t\t\treset-names = \"sata_rst\", \"usb0_crst\", \"usb1_crst\",\n\t\t\t\t \"usb0_hibrst\", \"usb1_hibrst\", \"usb0_apbrst\",\n\t\t\t\t \"usb1_apbrst\", \"dp_rst\", \"gem0_rst\",\n\t\t\t\t \"gem1_rst\", \"gem2_rst\", \"gem3_rst\";\n\t\t\tlane0: lane0 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane1: lane1 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane2: lane2 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane3: lane3 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SATA>;\n\t\t\t#stream-id-cells = <4>;\n\t\t/*\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;*/\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_0>;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_1>;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_1>;\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_0>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>, <0 75 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t\t/* snps,enable-hibernation; */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb1@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_1>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>, <0 76 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <60>;\n\t\t\treset-on-timeout;\n\t\t};\n\n\t\tlpd_watchdog: watchdog@ff150000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 52 1>;\n\t\t\treg = <0x0 0xff150000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges;\n\n\t\t\tams_ps: ams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50800 0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50c00 0x0 0x400>;\n\t\t\t};\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\n\t\tzynqmp_dpsub: zynqmp-display@fd4a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"dp\", \"blend\", \"av_buf\", \"aud\";\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"dp_apb_clk\", \"dp_aud_clk\", \"dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\n\t\t\tvid-layer {\n\t\t\t\tdma-names = \"vid0\", \"vid1\", \"vid2\";\n\t\t\t\tdmas = <&xlnx_dpdma 0>,\n\t\t\t\t <&xlnx_dpdma 1>,\n\t\t\t\t <&xlnx_dpdma 2>;\n\t\t\t};\n\n\t\t\tgfx-layer {\n\t\t\t\tdma-names = \"gfx0\";\n\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t};\n\n\t\t\t/* dummy node to to indicate there's no child i2c device */\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&xlnx_dpdma 4>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&xlnx_dpdma 5>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card0: zynqmp_dp_snd_card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,\n\t\t\t\t\t\t <&zynqmp_dp_snd_pcm1>;\n\t\t\t\txlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Signed-off-by: Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/sp701-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze sp701.\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@1 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x3>;\n\t\t\tti,tx-internal-delay = <0x3>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/vcu118-rev2.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze vcu118\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@3 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\tti,sgmii-ref-clock-output-enable;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\treg = <3>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-a2197-sc-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller RevA\";\n\tcompatible = \"xlnx,versal-sc-revA\", \"xlnx,versal-sc\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\t/* SC Bank 43\n\tFIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS\n\tSYSCTLR_GPIO0 - 5 - conneced to versal */\n\t/* cpu thermal for MAX6643 fan control */\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tdc38_led {\n\t\t\tlabel = \"ds38-green\"; /* sc AB11 500_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc37_led {\n\t\t\tlabel = \"ds37-green\"; /* sc AD10 501_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc36_led {\n\t\t\tlabel = \"ds36-green\"; /* sc AD11 502_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t};\n};\n\n/* usb - type C - pl\n and micro usb 2.0, gt\n*/\n/* Feb 28/2019 version */\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio_bank = <1>;\n};\n\n/* TODO\nUSB0 MIO52-63\nUSB1 MIO64-75\n*/\n\n/*eth MDIO 76/77\neth reset MIO42\nmarwell m88e1512 - SGMII */\n&gem0 {\n\tphy-handle = <&phy0>;\n\t/* phy-mode = \"sgmii\"; DTG generates this properly */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: phy@21 {\n\t\treg = <21>; /* FIXME */\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5- 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 0 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\"; /* FIXME no linux driver */\n\t\t\t\treg = <0xc0>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <10000000>; /* 10 ohm */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\ti2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* FIXME connection to Samtec J212D */\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t/* FIXME connection to Samtec J53C */\n\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@5d { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@5d { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@5d { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"LPDDR4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-emu-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-emu-itr8\", \"xlnx,versal-emu\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal EMU ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:9600\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n\n\tclk0212: clk0212 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <212000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n};\n\n&timer {\n clock-frequency = <440000>;\n};\n\n&serial0 {\n status = \"okay\";\n clocks = <&clk0212 &clk0212>;\n\tcurrent-speed = <9600>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-spp-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-spp-itr8-cn13940875\", \"xlnx,versal-spp-itr8\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal SPP ITR8 HW 4.0\";\n\t\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &ospi;\n\t\tspi2 = &spi0;\n\t\tspi3 = &spi1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tusb0 = &usb0;\n\t};\n\t\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>;\n\t};\n\tchosen {\n\t\tbootargs = \"rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\t\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n};\n\n&timer {\n\tclock-frequency = <2720000>;\n};\n\n&serial0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tmaximum-speed = \"high-speed\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n phy0: phy@0 {\n\t\treg = <0x0>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n phy1: phy@1 {\n\t\treg = <0x1>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <0x1>;\n\treg = <0x0 0xf1030000 0x0 0x1000>;\n\tclocks = <&clk125 &clk125>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\t\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot-boot.bin\";\n\t\t\t\treg = <0x0 0x6400000>;\n\t\t\t};\n\t\t\tpartition@6400000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x6400000 0x500000>;\n\t\t\t};\n\t\t\tpartition@6900000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x6900000 0x20000>;\n\t\t\t};\n\t\t\tpartition@6920000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x6920000 0x5E0000>;\n\t\t\t};\n\t\t\tpartition@7f40000 {\n\t\t\t\tlabel = \"qspi-bootenv\";\n\t\t\t\treg = <0x7f40000 0x40000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ospi {\n\tstatus = \"disabled\";\n\tclocks = <&clk125 &clk125>;\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\tcdns,fifo-depth = <508>;\n\tcdns,fifo-width = <4>;\n\tcdns,is-dma = <1>;\n\tcdns,is-stig-pgm = <1>;\n\tcdns,trigger-address = <0x00000000>;\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t};\n\t\t\tpartition@600000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t};\n\t\t\tpartition@620000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <1>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <3>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\treg = <0x0 0x84000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-v350-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal v350 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-v350-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal v350 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tspi0 = &ospi;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&serial1 {\n\tstatus = \"disabled\"; /* communication with MSP432 */\n};\n\n&ospi {\n\tstatus = \"okay\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-01 revA OSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\n};\n\n&rtc {\n status = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&watchdog {\n status = \"okay\";\n};\n\n&qspi {\n status = \"disabled\"; /* u93 and u92 */\n};\n\n&ospi {\n\tstatus = \"okay\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 {\n status = \"okay\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n compatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n \"xlnx,versal-vc-p-a2197-00\",\n \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n model = \"Xilinx Versal A2197 Processor board revA\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tgpio0 = &gpio;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n\n};\n\n&gpio {\n\tstatus = \"okay\";\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&qspi {\n status = \"okay\"; /* u93 and u92 */\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci1 { /* U104 */\n\tstatus = \"okay\";\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 {\n status = \"okay\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-01 revA QSPI\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&qspi {\n status = \"okay\"; /* u93 and u92 */\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 {\n status = \"okay\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-02 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>; /* u9 */\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@1 { /* Marvell 88E1512; U9 */\n\t\treg = <1>;\n\t};\n};\n\n\n&sdhci0 {\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&sdhci1 { /* U1A */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n\tno-1-8-v;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* U4 */\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"high-speed\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\t/* U12 Catalyst EEPROM - AT24 should be equivalent */\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U13 and U15 */\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tflash@0 { /* U18 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tnum-cs = <3>;\t/* FIXME - check SPI1_SS0-2_B */\n\n\tflash@0 { /* U19 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst26vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-03 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\t\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tserial0 = &serial0;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t};\n};\n\n&dcc {\n status = \"okay\";\n};\n\n/* SMAP via cc108 */\n&can0 {\n\tstatus = \"okay\";\n};\n\n&can1 {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\t/* Must be enabled via J90/J91 */\n\teeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\"; /* u7 */\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <1>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 64Mb */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x800000>;\n\t\t};\n\t};\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&sdhci0 { /* J99 MIO28 - MIO33 */\n\txlnx,mio_bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>; /* FIXME */\n\tno-1-8-v;\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tflash@0 { /* U6 - IS25LQ032B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lq032b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-04 revA OSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <1>; /* FIXME */\n\t};\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"disabled\"; /* u93 and u92 and u161 and u160 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n/* Mutually exclusive with qspi */\n&ospi {\n\tstatus = \"okay\"; /* U163/U97 MT35XU02G */\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio_bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&serial0 { /* MIO35 - MIO37 */\n\tstatus = \"okay\";\n};\n\n&serial1 { /* MIO4 - MIO7 RS232 */\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-04 revA QSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <2>;\n\t};\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\"; /* u93 and u92 and u161 and u160 */\n\tnum-cs = <1>;\n\tis-dual = <0>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 512MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x20000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio_bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&serial0 { /* MIO35 - MIO37 */\n\tstatus = \"okay\";\n};\n\n&serial1 { /* MIO4 - MIO7 RS232 */\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-05 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 { /* 88e1510 */\n\t\treg = <1>;\n\t};\n\tphy2: phy@2 { /* VSC8531 */\n\t\treg = <2>;\n\t\tvsc8531,rx-delay = <6>;\n\t\tvsc8531,tx-delay = <6>;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>;\n\tphy-mode = \"rgmii-id\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <0x1>;\n\tspi-tx-bus-width = <1>;\n\tspi-rx-bus-width = <4>;\n\n\tflash@0 { /* MX25U12835 128Mbit */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 16MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <104000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x1000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc0 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>; /* FIXME */\n\tno-1-8-v;\n};\n\n&sdhci1 { /* connector */\n\txlnx,mio_bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA\";\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 {\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA (QSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&qspi {\n status = \"okay\";\n num-cs = <1>;\n spi-tx-bus-width = <1>;\n spi-rx-bus-width = <4>;\n #address-cells = <1>;\n #size-cells = <0>;\n is-dual = <1>;\n flash@0 {\n #address-cells = <1>;\n #size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 256MB */\n reg = <0>;\n spi-tx-bus-width = <1>;\n spi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <150000000>;\n partition@0 {\n label = \"spi0-flash0\";\n reg = <0x0 0x10000000>;\n };\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA-x-ebm-02-revA\",\n\t\t \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA (EMMC)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n\tno-1-8-v;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci0 {\n\t/* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA-x-ebm-03-revA\",\n\t\t \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA (OSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&ospi {\n\t/* U97 MT35XU02G */\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck5000-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck5000 revA\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vck5000-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck5000 board revA\";\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tspi0 = &ospi;\n\t};\n\n};\n\n&ospi {\n\tstatus = \"okay\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x10000000>;\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&serial1 {\n\tstatus = \"disabled\"; /* communication with MSP432 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-virt.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-virt\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal Virtual\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tclk2: clk2 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <2670000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t\tclock-frequency = <2720000>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */\n\t\t\t <0x0 0xf9080000 0x0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x1 0x9 4>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x2>;\n\t\tranges;\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff060000 0x0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff070000 0x0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom1: eeprom@53 {\n\t\t\t\treg = <0x53>;\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t};\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom2: eeprom@55 {\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x55>;\n\t\t\t};\n\t\t};\n\n\t\tgpio: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tethernet0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 56 4>, <0x0 56 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy0: phy@0 {\n\t\t\t\treg = <0x0>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tethernet1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 58 4>, <0x0 58 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy1: phy@1 {\n\t\t\t\treg = <0x1>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xf12a0000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tnum-cs = <0x1>;\n\t\t\treg = <0x0 0xf1030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"n25q512a\", \"micron,m25p80\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <108000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@100000 {\n\t\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@600000 {\n\t\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@620000 {\n\t\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <1>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <3>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0x0 0x84000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\treg = <0x0 0xf1040000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <0>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\treg = <0x0 0xf1050000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <1>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\t#address-cells = <0x2>;\n\t\t\t#size-cells = <0x2>;\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tranges;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125 &clk125>;\n\n\t\t\tdwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x10000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = ðernet0;\n\t\tethernet1 = ðernet1;\n\t\tqspi = &qspi;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA (QSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\tspi-tx-bus-width = <1>;\n\tspi-rx-bus-width = <4>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tis-dual = <1>;\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 256MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <150000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x10000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA-x-ebm-02-revA\",\n\t\t \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA (EMMC)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n\tno-1-8-v;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci0 {\n\t/* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio_bank = <0>;\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA-x-ebm-03-revA\",\n\t\t \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA (OSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&ospi {\n\t/* U97 MT35XU02G */\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&can1 { /* MIO40-41 */\n\tstatus = \"okay\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio_bank = <1>;\n\tno-1-8-v;\n};\n\n&serial0 { /* PMC_MIO42/43 */\n\tstatus = \"okay\";\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 3 150000000>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: ethernet-phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: flash@0 {\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: flash@0 {\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t\tsw13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@34 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x34>;\n\t\t\t};\n\t\t\thwmon@35 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\thwmon@36 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&watchdog0 {\n\treset-on-timeout;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zcu100-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio-bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zcu100-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * 1.0 revision has level shifter and this property should be\n\t * removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\t/*\n\t * 1.0 revision has level shifter and this property should be\n\t * removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@20 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zcu104-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revC\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - IRPS5401_ALERT_B\n\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t * 2 - MAX6643_OT_B\n\t\t * 3 - MAX6643_FANFAIL_B\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t * 4, 10 - 17 - not connected\n\t\t */\n\t};\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tu183: ina226@40 { /* u183 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 4, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\txlnx,mio-bank = <1>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u67 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;\n\t};\n\tina226-u59 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n\tina226-u69 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;\n\t};\n\tina226-u66 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;\n\t};\n\tina226-u71 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u73 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tu67: ina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u67\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu59: ina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u59\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu61: ina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu60: ina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu64: ina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu69: ina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u69\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu66: ina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u66\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu63: ina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu3: ina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u3\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu71: ina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u71\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu73: ina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u73\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u57 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 { /* SI5328 - u48 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection FIXME */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revA\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1275-revb.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU1275 RevB\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revB\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t* 1.0 revision has level shifter and this property should be\n\t* removed for supporting UHS mode\n\t*/\n\tno-1-8-v;\n};\n\n&gem1 {\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1285-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU1285 RevA\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1285 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1285-revA\", \"xlnx,zynqmp-zcu1285\", \"xlnx,zynqmp\";\n\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PMBUS */\n\t\t\tmax20751@74 { /* u23 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x74>;\n\t\t\t};\n\t\t\tmax20751@70 { /* u89 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x70>;\n\t\t\t};\n\t\t\tmax15301@a { /* u28 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u48 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@d { /* u27 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\tmax15303@e { /* u11 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\tmax15303@f { /* u96 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\tmax15303@11 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\tmax15303@12 { /* u24 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u29 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u51 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u30 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u102 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15301@17 { /* u50 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u31 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* CM_I2C */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYS_EEPROM */\n\t\t\teeprom: eeprom@54 { /* u101 */\n\t\t\t\tcompatible = \"atmel,24c32\"; /* 24LC32A */\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FMC1 */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FMC2 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* ANALOG_PMBUS */\n\t\t\tu60: ina226@40 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu61: ina226@41 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu63: ina226@42 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu65: ina226@43 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu64: ina226@44 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* ANALOG_CM_I2C */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FMC3 */\n\t\t};\n\t};\n};\n\n&gem1 {\n\tmdio {\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zcu208-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU208\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU208 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu208-revA\", \"xlnx,zynqmp-zcu208\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zcu216-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU216\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU216 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu216-revA\", \"xlnx,zynqmp-zcu216\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-a2197-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Versal System Controller on a2197 board RevA\";\n\tcompatible = \"xlnx,zynqmp-a2197-revA\", \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>;\n\t};\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* this cover MGT board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* This cover processor board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-e-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevA\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tsi570_ddrdimm1_clk: si570_ddrdimm1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tsi570_lpddr4_clk2: si570_lpddr4_clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570_lpddr4_clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk1>;\n\t};\n\n\tsi570_hsdp_clk: si570_hsdp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi570_zsfp_clk: si570_zsfp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_zsfp>;\n\t};\n\n\tsi570_user1_clk: si570_user1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_user1>;\n\t};\n\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vcc-soc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;\n\t};\n\tina226-vcc-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc-pslp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;\n\t};\n\tina226-vcc-psfp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;\n\t};\n\tina226-vccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;\n\t};\n\tina226-vccaux-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;\n\t};\n\tina226-vcco-500 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;\n\t};\n\tina226-vcco-501 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;\n\t};\n\tina226-vcco-502 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;\n\t};\n\tina226-vcco-503 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;\n\t};\n\tina226-vcc-1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;\n\t};\n\tina226-vcc-3v3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;\n\t};\n\tina226-vcc-1v2-ddr4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;\n\t};\n\tina226-vcc-1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtyavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;\n\t};\n\tina226-mgtyavtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;\n\t};\n\tina226-mgtyvccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;\n\t};\n\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* u131 M88E1512 */\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"ZU4_TRIGGER\", \"SYSCTLR_PB\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t\n\t\t\t/* u152 IR35215 0x16/0x46 vcc_soc */ \n\t\t\t/* u179 ir38164 0x19/0x49 vcco_500 */\n\t\t\t/* u181 ir38164 0x1a/0x4a vcco_501 */\n\t\t\t/* u183 ir38164 0x1b/0x4b vcco_502 */\n\t\t\t/* u185 ir38164 0x1e/0x4e vadj_fmc */\n\t\t\t/* u187 ir38164 0x1F/0x4f mgtyavcc */\n\t\t\t/* u189 ir38164 0x20/0x50 mgtyavtt */\n\t\t\t/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */\n\t\t\t/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */\n\n\t\t\tirps5401_47: irps5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* pmbus / i2c 0x17 */\n\t\t\t};\n\t\t\tirps5401_4c: irps5401@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* pmbus / i2c 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: irps5401@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* pmbus / i2c 0x1d */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <500>; /* R440 */\n\t\t\t\t/* 0.80V @ 32A 1 of 6 Phases*/\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-soc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <500>; /* R1702 */\n\t\t\t\t/* 0.80V @ 18A */\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pmc\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* R1214 */\n\t\t\t\t/* 0.78V @ 500mA */\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u162 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r1221 */\n\t\t\t\t/* 0.78V @ 4A */\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pslp\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>; /* R1216 */\n\t\t\t\t/* 0.78V @ 1A */\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-psfp\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1219 */\n\t\t\t\t/* 0.78V @ 2A */\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* R382 */\n\t\t\t\t/* 1.5V @ 3A */\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux-pmc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>; /* R1246 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u178 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-500\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>; /* R1300 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u180 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-501\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <2000>; /* R1313 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u182 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-502\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <2000>; /* R1330 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-503\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1229 */\n\t\t\t\t/* 1.8V @ 2A */\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u173 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v8\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>; /* R400 */\n\t\t\t\t/* 1.8V @ 6A */\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-3v3\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* R1232 */\n\t\t\t\t/* 3.3V @ 500mA */\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v2-ddr4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>; /* R1275 */\n\t\t\t\t/* 1.2V @ 4A */\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>; /* R1286 */\n\t\t\t\t/* 1.1V @ 4A */\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>; /* R1350 */\n\t\t\t\t/* 1.5V @ 10A */\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavcc\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <2000>; /* R1367 */\n\t\t\t\t/* 0.88V @ 6A */\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavtt\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>; /* R1384 */\n\t\t\t\t/* 1.2V @ 10A */\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyvccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>; /* r1679 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t\ti2c@5 { /* zSFP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_zsfp: clock-generator@5d { /* u192 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_zsfp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* USER_SI570_1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_user1: clock-generator@5d { /* u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>; /* FIXME check address */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"si570_user1\";\n\t\t\t};\n\n\t\t};\n\t\ti2c@7 { /* USER_SI570_2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* 0x5c too */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t};\n\t\t\t/* and connector J212D */\n\t\t};\n\t\tfmc1: i2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t};\n\t\tfmc2: i2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LPDDR4_SI570_CLK2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_lpddr4clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4clk1: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* 8A34001 - U219B and J310 connector */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n\ti2c-mux@75 { /* u214 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* SFP0_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* SFP0 */\n\t\t};\n\t\ti2c@1 { /* SFP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@2 { /* QSFP1_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* QSFP1 */\n\t\t};\n\t\t/* 3 - 7 unused */\n\t};\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-g-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 MGT Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-g-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u82 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 { /* eth MDIO 76/77 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 */\n\t\treg = <0>;\n\t\treset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 5 - 9 */\n\t\t \"\", \"\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"\", \"\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\ti2c-mux@74 { /* u94 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* CM_I2C_SCL - Samtec */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* PMBUS - AFX_PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\ttps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\ttps544@10 { /* u73 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\ttps544@11 { /* u76 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\ttps544@12 { /* u77 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\ttps544@13 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\ttps544@14 { /* u81 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\ttps544@15 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\ttps544@16 { /* u63 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\ttps544@17 { /* u66 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\ttps544@18 { /* u67 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\ttps544@19 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\ttps544@1d { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\ttps544@1e { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\ttps544@1f { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t\ttps544@20 { /* u71 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\t\t\tu74: ina226@40 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu75: ina226@41 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\"\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@43 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu82: ina226@44 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u82\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu84: ina226@45 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\ttps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* fmc1 via JA2G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom_fmc1: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* fmc2 via JA3G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\teeprom_fmc2: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* fmc3 via JA4G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\teeprom_fmc3: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* ddr dimm */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&usb0 { /* USB0 MIO52-63 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"high-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-01-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\tina226-vcc0v6-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc0v6_lp4: ina226@49 { /* u101 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc0v6-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@5d { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n status = \"okay\";\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n status = \"okay\";\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n status = \"disabled\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n /delete-property/ phy-names ;\n /delete-property/ phys ;\n maximum-speed = \"high-speed\";\n snps,dis_u2_susphy_quirk ;\n snps,dis_u3_susphy_quirk ;\n status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-02-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_vpp_2v5_ddr4: tps544@1x { /* u3007 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>; /* FIXME wrong in schematics */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* C0_DDR4_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\ti2c@6 { /* C2_DDR5_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\ti2c@7 { /* C3_DDR4_UDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_RLD3 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_RLD3_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_DDR5 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_DDR5_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-03-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_vpp_2v5_ddr4: tps544@1x { /* u3007 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>; /* FIXME wrong in schematics */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* DDR4_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_SODIMM_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_QDRIV */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_QDRIV_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-01-revA\", \"xlnx,zynqmp-x-prc-01\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\",\"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n status = \"okay\";\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane1 PHY_TYPE_USB3 0 1 26000000>;\n};\n\n&usb1 {\n status = \"okay\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"okay\";\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-02-revA\", \"xlnx,zynqmp-x-prc-02\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n status = \"okay\";\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane1 PHY_TYPE_USB3 0 1 26000000>;\n};\n\n&usb1 {\n status = \"okay\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"okay\";\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-03-revA\", \"xlnx,zynqmp-x-prc-03\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tx_prc_si5338: clock-generator@70 { /* U9 */\n\t\t\t\tcompatible = \"silabs,si5338\";\n\t\t\t\treg = <0x70>; /* FIXME */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n status = \"okay\";\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane1 PHY_TYPE_USB3 0 1 26000000>;\n};\n\n&usb1 {\n status = \"okay\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"okay\";\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-04-revA\", \"xlnx,zynqmp-x-prc-04\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n status = \"okay\";\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane1 PHY_TYPE_USB3 0 1 26000000>;\n};\n\n&usb1 {\n status = \"okay\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"okay\";\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-05-revA\", \"xlnx,zynqmp-x-prc-05\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n status = \"okay\";\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane1 PHY_TYPE_USB3 0 1 26000000>;\n};\n\n&usb1 {\n status = \"okay\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"okay\";\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tstatus = \"okay\";\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n status = \"okay\";\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane1 PHY_TYPE_USB3 0 1 26000000>;\n};\n\n&usb1 {\n status = \"okay\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"okay\";\n};\n\n&xilinx_ams {\n\tstatus = \"okay\";\n};\n\n&ams_ps {\n\tstatus = \"okay\";\n};\n\n&ams_pl {\n\tstatus = \"okay\";\n};\n\n\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/clock/xlnx-versal-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_VERSAL_H\n#define _DT_BINDINGS_CLK_VERSAL_H\n\n#define PMC_PLL\t\t\t\t\t1\n#define APU_PLL\t\t\t\t\t2\n#define RPU_PLL\t\t\t\t\t3\n#define CPM_PLL\t\t\t\t\t4\n#define NOC_PLL\t\t\t\t\t5\n#define PLL_MAX\t\t\t\t\t6\n#define PMC_PRESRC\t\t\t\t7\n#define PMC_POSTCLK\t\t\t\t8\n#define PMC_PLL_OUT\t\t\t\t9\n#define PPLL\t\t\t\t\t10\n#define NOC_PRESRC\t\t\t\t11\n#define NOC_POSTCLK\t\t\t\t12\n#define NOC_PLL_OUT\t\t\t\t13\n#define NPLL\t\t\t\t\t14\n#define APU_PRESRC\t\t\t\t15\n#define APU_POSTCLK\t\t\t\t16\n#define APU_PLL_OUT\t\t\t\t17\n#define APLL\t\t\t\t\t18\n#define RPU_PRESRC\t\t\t\t19\n#define RPU_POSTCLK\t\t\t\t20\n#define RPU_PLL_OUT\t\t\t\t21\n#define RPLL\t\t\t\t\t22\n#define CPM_PRESRC\t\t\t\t23\n#define CPM_POSTCLK\t\t\t\t24\n#define CPM_PLL_OUT\t\t\t\t25\n#define CPLL\t\t\t\t\t26\n#define PPLL_TO_XPD\t\t\t\t27\n#define NPLL_TO_XPD\t\t\t\t28\n#define APLL_TO_XPD\t\t\t\t29\n#define RPLL_TO_XPD\t\t\t\t30\n#define EFUSE_REF\t\t\t\t31\n#define SYSMON_REF\t\t\t\t32\n#define IRO_SUSPEND_REF\t\t\t\t33\n#define USB_SUSPEND\t\t\t\t34\n#define SWITCH_TIMEOUT\t\t\t\t35\n#define RCLK_PMC\t\t\t\t36\n#define RCLK_LPD\t\t\t\t37\n#define WDT\t\t\t\t\t38\n#define TTC0\t\t\t\t\t39\n#define TTC1\t\t\t\t\t40\n#define TTC2\t\t\t\t\t41\n#define TTC3\t\t\t\t\t42\n#define GEM_TSU\t\t\t\t\t43\n#define GEM_TSU_LB\t\t\t\t44\n#define MUXED_IRO_DIV2\t\t\t\t45\n#define MUXED_IRO_DIV4\t\t\t\t46\n#define PSM_REF\t\t\t\t\t47\n#define GEM0_RX\t\t\t\t\t48\n#define GEM0_TX\t\t\t\t\t49\n#define GEM1_RX\t\t\t\t\t50\n#define GEM1_TX\t\t\t\t\t51\n#define CPM_CORE_REF\t\t\t\t52\n#define CPM_LSBUS_REF\t\t\t\t53\n#define CPM_DBG_REF\t\t\t\t54\n#define CPM_AUX0_REF\t\t\t\t55\n#define CPM_AUX1_REF\t\t\t\t56\n#define QSPI_REF\t\t\t\t57\n#define OSPI_REF\t\t\t\t58\n#define SDIO0_REF\t\t\t\t59\n#define SDIO1_REF\t\t\t\t60\n#define PMC_LSBUS_REF\t\t\t\t61\n#define I2C_REF\t\t\t\t\t62\n#define TEST_PATTERN_REF\t\t\t63\n#define DFT_OSC_REF\t\t\t\t64\n#define PMC_PL0_REF\t\t\t\t65\n#define PMC_PL1_REF\t\t\t\t66\n#define PMC_PL2_REF\t\t\t\t67\n#define PMC_PL3_REF\t\t\t\t68\n#define CFU_REF\t\t\t\t\t69\n#define SPARE_REF\t\t\t\t70\n#define NPI_REF\t\t\t\t\t71\n#define HSM0_REF\t\t\t\t72\n#define HSM1_REF\t\t\t\t73\n#define SD_DLL_REF\t\t\t\t74\n#define FPD_TOP_SWITCH\t\t\t\t75\n#define FPD_LSBUS\t\t\t\t76\n#define ACPU\t\t\t\t\t77\n#define DBG_TRACE\t\t\t\t78\n#define DBG_FPD\t\t\t\t\t79\n#define LPD_TOP_SWITCH\t\t\t\t80\n#define ADMA\t\t\t\t\t81\n#define LPD_LSBUS\t\t\t\t82\n#define CPU_R5\t\t\t\t\t83\n#define CPU_R5_CORE\t\t\t\t84\n#define CPU_R5_OCM\t\t\t\t85\n#define CPU_R5_OCM2\t\t\t\t86\n#define IOU_SWITCH\t\t\t\t87\n#define GEM0_REF\t\t\t\t88\n#define GEM1_REF\t\t\t\t89\n#define GEM_TSU_REF\t\t\t\t90\n#define USB0_BUS_REF\t\t\t\t91\n#define UART0_REF\t\t\t\t92\n#define UART1_REF\t\t\t\t93\n#define SPI0_REF\t\t\t\t94\n#define SPI1_REF\t\t\t\t95\n#define CAN0_REF\t\t\t\t96\n#define CAN1_REF\t\t\t\t97\n#define I2C0_REF\t\t\t\t98\n#define I2C1_REF\t\t\t\t99\n#define DBG_LPD\t\t\t\t\t100\n#define TIMESTAMP_REF\t\t\t\t101\n#define DBG_TSTMP\t\t\t\t102\n#define CPM_TOPSW_REF\t\t\t\t103\n#define USB3_DUAL_REF\t\t\t\t104\n#define OUTCLK_MAX\t\t\t\t105\n#define REF_CLK\t\t\t\t\t106\n#define PL_ALT_REF_CLK\t\t\t\t107\n#define MUXED_IRO\t\t\t\t108\n#define PL_EXT\t\t\t\t\t109\n#define PL_LB\t\t\t\t\t110\n#define MIO_50_OR_51\t\t\t\t111\n#define MIO_24_OR_25\t\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Xilinx Zynq MPSoC Firmware layer\n *\n * Copyright (C) 2014-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_ZYNQMP_H\n#define _DT_BINDINGS_CLK_ZYNQMP_H\n\n#define IOPLL\t\t\t0\n#define RPLL\t\t\t1\n#define APLL\t\t\t2\n#define DPLL\t\t\t3\n#define VPLL\t\t\t4\n#define IOPLL_TO_FPD\t\t5\n#define RPLL_TO_FPD\t\t6\n#define APLL_TO_LPD\t\t7\n#define DPLL_TO_LPD\t\t8\n#define VPLL_TO_LPD\t\t9\n#define ACPU\t\t\t10\n#define ACPU_HALF\t\t11\n#define DBF_FPD\t\t\t12\n#define DBF_LPD\t\t\t13\n#define DBG_TRACE\t\t14\n#define DBG_TSTMP\t\t15\n#define DP_VIDEO_REF\t\t16\n#define DP_AUDIO_REF\t\t17\n#define DP_STC_REF\t\t18\n#define GDMA_REF\t\t19\n#define DPDMA_REF\t\t20\n#define DDR_REF\t\t\t21\n#define SATA_REF\t\t22\n#define PCIE_REF\t\t23\n#define GPU_REF\t\t\t24\n#define GPU_PP0_REF\t\t25\n#define GPU_PP1_REF\t\t26\n#define TOPSW_MAIN\t\t27\n#define TOPSW_LSBUS\t\t28\n#define GTGREF0_REF\t\t29\n#define LPD_SWITCH\t\t30\n#define LPD_LSBUS\t\t31\n#define USB0_BUS_REF\t\t32\n#define USB1_BUS_REF\t\t33\n#define USB3_DUAL_REF\t\t34\n#define USB0\t\t\t35\n#define USB1\t\t\t36\n#define CPU_R5\t\t\t37\n#define CPU_R5_CORE\t\t38\n#define CSU_SPB\t\t\t39\n#define CSU_PLL\t\t\t40\n#define PCAP\t\t\t41\n#define IOU_SWITCH\t\t42\n#define GEM_TSU_REF\t\t43\n#define GEM_TSU\t\t\t44\n#define GEM0_TX\t\t\t45\n#define GEM1_TX\t\t\t46\n#define GEM2_TX\t\t\t47\n#define GEM3_TX\t\t\t48\n#define GEM0_RX\t\t\t49\n#define GEM1_RX\t\t\t50\n#define GEM2_RX\t\t\t51\n#define GEM3_RX\t\t\t52\n#define QSPI_REF\t\t53\n#define SDIO0_REF\t\t54\n#define SDIO1_REF\t\t55\n#define UART0_REF\t\t56\n#define UART1_REF\t\t57\n#define SPI0_REF\t\t58\n#define SPI1_REF\t\t59\n#define NAND_REF\t\t60\n#define I2C0_REF\t\t61\n#define I2C1_REF\t\t62\n#define CAN0_REF\t\t63\n#define CAN1_REF\t\t64\n#define CAN0\t\t\t65\n#define CAN1\t\t\t66\n#define DLL_REF\t\t\t67\n#define ADMA_REF\t\t68\n#define TIMESTAMP_REF\t\t69\n#define AMS_REF\t\t\t70\n#define PL0_REF\t\t\t71\n#define PL1_REF\t\t\t72\n#define PL2_REF\t\t\t73\n#define PL3_REF\t\t\t74\n#define WDT\t\t\t75\n#define IOPLL_INT\t\t76\n#define IOPLL_PRE_SRC\t\t77\n#define IOPLL_HALF\t\t78\n#define IOPLL_INT_MUX\t\t79\n#define IOPLL_POST_SRC\t\t80\n#define RPLL_INT\t\t81\n#define RPLL_PRE_SRC\t\t82\n#define RPLL_HALF\t\t83\n#define RPLL_INT_MUX\t\t84\n#define RPLL_POST_SRC\t\t85\n#define APLL_INT\t\t86\n#define APLL_PRE_SRC\t\t87\n#define APLL_HALF\t\t88\n#define APLL_INT_MUX\t\t89\n#define APLL_POST_SRC\t\t90\n#define DPLL_INT\t\t91\n#define DPLL_PRE_SRC\t\t92\n#define DPLL_HALF\t\t93\n#define DPLL_INT_MUX\t\t94\n#define DPLL_POST_SRC\t\t95\n#define VPLL_INT\t\t96\n#define VPLL_PRE_SRC\t\t97\n#define VPLL_HALF\t\t98\n#define VPLL_INT_MUX\t\t99\n#define VPLL_POST_SRC\t\t100\n#define CAN0_MIO\t\t101\n#define CAN1_MIO\t\t102\n#define ACPU_FULL\t\t103\n#define GEM0_REF\t\t104\n#define GEM1_REF\t\t105\n#define GEM2_REF\t\t106\n#define GEM3_REF\t\t107\n#define GEM0_REF_UNG\t\t108\n#define GEM1_REF_UNG\t\t109\n#define GEM2_REF_UNG\t\t110\n#define GEM3_REF_UNG\t\t111\n#define LPD_WDT\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/gpio/gpio.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most GPIO bindings.\n *\n * Most GPIO bindings include a flags cell as part of the GPIO specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_GPIO_GPIO_H\n#define _DT_BINDINGS_GPIO_GPIO_H\n\n/* Bit 0 express polarity */\n#define GPIO_ACTIVE_HIGH 0\n#define GPIO_ACTIVE_LOW 1\n\n/* Bit 1 express single-endedness */\n#define GPIO_PUSH_PULL 0\n#define GPIO_SINGLE_ENDED 2\n\n/* Bit 2 express Open drain or open source */\n#define GPIO_LINE_OPEN_SOURCE 0\n#define GPIO_LINE_OPEN_DRAIN 4\n\n/*\n * * Open Drain/Collector is the combination of single-ended open drain interface.\n * * Open Source/Emitter is the combination of single-ended open source interface.\n * */\n#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)\n#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)\n\n/* Bit 3 express GPIO suspend/resume persistence */\n#define GPIO_SLEEP_MAINTAIN_VALUE 0\n#define GPIO_SLEEP_MAY_LOOSE_VALUE 8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/input/input.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most input bindings.\n *\n * Most input bindings include key code, matrix key code format.\n * In most cases, key code and matrix key code format uses\n * the standard values/macro defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INPUT_INPUT_H\n#define _DT_BINDINGS_INPUT_INPUT_H\n\n/*\n * Device properties and quirks\n */\n\n#define INPUT_PROP_POINTER\t\t0x00\t/* needs a pointer */\n#define INPUT_PROP_DIRECT\t\t0x01\t/* direct input devices */\n#define INPUT_PROP_BUTTONPAD\t\t0x02\t/* has button(s) under pad */\n#define INPUT_PROP_SEMI_MT\t\t0x03\t/* touch rectangle only */\n#define INPUT_PROP_TOPBUTTONPAD\t\t0x04\t/* softbuttons at top of pad */\n#define INPUT_PROP_POINTING_STICK\t0x05\t/* is a pointing stick */\n#define INPUT_PROP_ACCELEROMETER\t0x06\t/* has accelerometer */\n\n#define INPUT_PROP_MAX\t\t\t0x1f\n#define INPUT_PROP_CNT\t\t\t(INPUT_PROP_MAX + 1)\n\n\n/*\n * Event types\n */\n\n#define EV_SYN\t\t\t0x00\n#define EV_KEY\t\t\t0x01\n#define EV_REL\t\t\t0x02\n#define EV_ABS\t\t\t0x03\n#define EV_MSC\t\t\t0x04\n#define EV_SW\t\t\t0x05\n#define EV_LED\t\t\t0x11\n#define EV_SND\t\t\t0x12\n#define EV_REP\t\t\t0x14\n#define EV_FF\t\t\t0x15\n#define EV_PWR\t\t\t0x16\n#define EV_FF_STATUS\t\t0x17\n#define EV_MAX\t\t\t0x1f\n#define EV_CNT\t\t\t(EV_MAX+1)\n\n/*\n * Synchronization events.\n */\n\n#define SYN_REPORT\t\t0\n#define SYN_CONFIG\t\t1\n#define SYN_MT_REPORT\t\t2\n#define SYN_DROPPED\t\t3\n#define SYN_MAX\t\t\t0xf\n#define SYN_CNT\t\t\t(SYN_MAX+1)\n\n/*\n * Keys and buttons\n *\n * Most of the keys/buttons are modeled after USB HUT 1.12\n * (see http://www.usb.org/developers/hidpage).\n * Abbreviations in the comments:\n * AC - Application Control\n * AL - Application Launch Button\n * SC - System Control\n */\n\n#define KEY_RESERVED\t\t0\n#define KEY_ESC\t\t\t1\n#define KEY_1\t\t\t2\n#define KEY_2\t\t\t3\n#define KEY_3\t\t\t4\n#define KEY_4\t\t\t5\n#define KEY_5\t\t\t6\n#define KEY_6\t\t\t7\n#define KEY_7\t\t\t8\n#define KEY_8\t\t\t9\n#define KEY_9\t\t\t10\n#define KEY_0\t\t\t11\n#define KEY_MINUS\t\t12\n#define KEY_EQUAL\t\t13\n#define KEY_BACKSPACE\t\t14\n#define KEY_TAB\t\t\t15\n#define KEY_Q\t\t\t16\n#define KEY_W\t\t\t17\n#define KEY_E\t\t\t18\n#define KEY_R\t\t\t19\n#define KEY_T\t\t\t20\n#define KEY_Y\t\t\t21\n#define KEY_U\t\t\t22\n#define KEY_I\t\t\t23\n#define KEY_O\t\t\t24\n#define KEY_P\t\t\t25\n#define KEY_LEFTBRACE\t\t26\n#define KEY_RIGHTBRACE\t\t27\n#define KEY_ENTER\t\t28\n#define KEY_LEFTCTRL\t\t29\n#define KEY_A\t\t\t30\n#define KEY_S\t\t\t31\n#define KEY_D\t\t\t32\n#define KEY_F\t\t\t33\n#define KEY_G\t\t\t34\n#define KEY_H\t\t\t35\n#define KEY_J\t\t\t36\n#define KEY_K\t\t\t37\n#define KEY_L\t\t\t38\n#define KEY_SEMICOLON\t\t39\n#define KEY_APOSTROPHE\t\t40\n#define KEY_GRAVE\t\t41\n#define KEY_LEFTSHIFT\t\t42\n#define KEY_BACKSLASH\t\t43\n#define KEY_Z\t\t\t44\n#define KEY_X\t\t\t45\n#define KEY_C\t\t\t46\n#define KEY_V\t\t\t47\n#define KEY_B\t\t\t48\n#define KEY_N\t\t\t49\n#define KEY_M\t\t\t50\n#define KEY_COMMA\t\t51\n#define KEY_DOT\t\t\t52\n#define KEY_SLASH\t\t53\n#define KEY_RIGHTSHIFT\t\t54\n#define KEY_KPASTERISK\t\t55\n#define KEY_LEFTALT\t\t56\n#define KEY_SPACE\t\t57\n#define KEY_CAPSLOCK\t\t58\n#define KEY_F1\t\t\t59\n#define KEY_F2\t\t\t60\n#define KEY_F3\t\t\t61\n#define KEY_F4\t\t\t62\n#define KEY_F5\t\t\t63\n#define KEY_F6\t\t\t64\n#define KEY_F7\t\t\t65\n#define KEY_F8\t\t\t66\n#define KEY_F9\t\t\t67\n#define KEY_F10\t\t\t68\n#define KEY_NUMLOCK\t\t69\n#define KEY_SCROLLLOCK\t\t70\n#define KEY_KP7\t\t\t71\n#define KEY_KP8\t\t\t72\n#define KEY_KP9\t\t\t73\n#define KEY_KPMINUS\t\t74\n#define KEY_KP4\t\t\t75\n#define KEY_KP5\t\t\t76\n#define KEY_KP6\t\t\t77\n#define KEY_KPPLUS\t\t78\n#define KEY_KP1\t\t\t79\n#define KEY_KP2\t\t\t80\n#define KEY_KP3\t\t\t81\n#define KEY_KP0\t\t\t82\n#define KEY_KPDOT\t\t83\n\n#define KEY_ZENKAKUHANKAKU\t85\n#define KEY_102ND\t\t86\n#define KEY_F11\t\t\t87\n#define KEY_F12\t\t\t88\n#define KEY_RO\t\t\t89\n#define KEY_KATAKANA\t\t90\n#define KEY_HIRAGANA\t\t91\n#define KEY_HENKAN\t\t92\n#define KEY_KATAKANAHIRAGANA\t93\n#define KEY_MUHENKAN\t\t94\n#define KEY_KPJPCOMMA\t\t95\n#define KEY_KPENTER\t\t96\n#define KEY_RIGHTCTRL\t\t97\n#define KEY_KPSLASH\t\t98\n#define KEY_SYSRQ\t\t99\n#define KEY_RIGHTALT\t\t100\n#define KEY_LINEFEED\t\t101\n#define KEY_HOME\t\t102\n#define KEY_UP\t\t\t103\n#define KEY_PAGEUP\t\t104\n#define KEY_LEFT\t\t105\n#define KEY_RIGHT\t\t106\n#define KEY_END\t\t\t107\n#define KEY_DOWN\t\t108\n#define KEY_PAGEDOWN\t\t109\n#define KEY_INSERT\t\t110\n#define KEY_DELETE\t\t111\n#define KEY_MACRO\t\t112\n#define KEY_MUTE\t\t113\n#define KEY_VOLUMEDOWN\t\t114\n#define KEY_VOLUMEUP\t\t115\n#define KEY_POWER\t\t116\t/* SC System Power Down */\n#define KEY_KPEQUAL\t\t117\n#define KEY_KPPLUSMINUS\t\t118\n#define KEY_PAUSE\t\t119\n#define KEY_SCALE\t\t120\t/* AL Compiz Scale (Expose) */\n\n#define KEY_KPCOMMA\t\t121\n#define KEY_HANGEUL\t\t122\n#define KEY_HANGUEL\t\tKEY_HANGEUL\n#define KEY_HANJA\t\t123\n#define KEY_YEN\t\t\t124\n#define KEY_LEFTMETA\t\t125\n#define KEY_RIGHTMETA\t\t126\n#define KEY_COMPOSE\t\t127\n#define KEY_STOP\t\t128\t/* AC Stop */\n#define KEY_AGAIN\t\t129\n#define KEY_PROPS\t\t130\t/* AC Properties */\n#define KEY_UNDO\t\t131\t/* AC Undo */\n#define KEY_FRONT\t\t132\n#define KEY_COPY\t\t133\t/* AC Copy */\n#define KEY_OPEN\t\t134\t/* AC Open */\n#define KEY_PASTE\t\t135\t/* AC Paste */\n#define KEY_FIND\t\t136\t/* AC Search */\n#define KEY_CUT\t\t\t137\t/* AC Cut */\n#define KEY_HELP\t\t138\t/* AL Integrated Help Center */\n#define KEY_MENU\t\t139\t/* Menu (show menu) */\n#define KEY_CALC\t\t140\t/* AL Calculator */\n#define KEY_SETUP\t\t141\n#define KEY_SLEEP\t\t142\t/* SC System Sleep */\n#define KEY_WAKEUP\t\t143\t/* System Wake Up */\n#define KEY_FILE\t\t144\t/* AL Local Machine Browser */\n#define KEY_SENDFILE\t\t145\n#define KEY_DELETEFILE\t\t146\n#define KEY_XFER\t\t147\n#define KEY_PROG1\t\t148\n#define KEY_PROG2\t\t149\n#define KEY_WWW\t\t\t150\t/* AL Internet Browser */\n#define KEY_MSDOS\t\t151\n#define KEY_COFFEE\t\t152\t/* AL Terminal Lock/Screensaver */\n#define KEY_SCREENLOCK\t\tKEY_COFFEE\n#define KEY_ROTATE_DISPLAY\t153\t/* Display orientation for e.g. tablets */\n#define KEY_DIRECTION\t\tKEY_ROTATE_DISPLAY\n#define KEY_CYCLEWINDOWS\t154\n#define KEY_MAIL\t\t155\n#define KEY_BOOKMARKS\t\t156\t/* AC Bookmarks */\n#define KEY_COMPUTER\t\t157\n#define KEY_BACK\t\t158\t/* AC Back */\n#define KEY_FORWARD\t\t159\t/* AC Forward */\n#define KEY_CLOSECD\t\t160\n#define KEY_EJECTCD\t\t161\n#define KEY_EJECTCLOSECD\t162\n#define KEY_NEXTSONG\t\t163\n#define KEY_PLAYPAUSE\t\t164\n#define KEY_PREVIOUSSONG\t165\n#define KEY_STOPCD\t\t166\n#define KEY_RECORD\t\t167\n#define KEY_REWIND\t\t168\n#define KEY_PHONE\t\t169\t/* Media Select Telephone */\n#define KEY_ISO\t\t\t170\n#define KEY_CONFIG\t\t171\t/* AL Consumer Control Configuration */\n#define KEY_HOMEPAGE\t\t172\t/* AC Home */\n#define KEY_REFRESH\t\t173\t/* AC Refresh */\n#define KEY_EXIT\t\t174\t/* AC Exit */\n#define KEY_MOVE\t\t175\n#define KEY_EDIT\t\t176\n#define KEY_SCROLLUP\t\t177\n#define KEY_SCROLLDOWN\t\t178\n#define KEY_KPLEFTPAREN\t\t179\n#define KEY_KPRIGHTPAREN\t180\n#define KEY_NEW\t\t\t181\t/* AC New */\n#define KEY_REDO\t\t182\t/* AC Redo/Repeat */\n\n#define KEY_F13\t\t\t183\n#define KEY_F14\t\t\t184\n#define KEY_F15\t\t\t185\n#define KEY_F16\t\t\t186\n#define KEY_F17\t\t\t187\n#define KEY_F18\t\t\t188\n#define KEY_F19\t\t\t189\n#define KEY_F20\t\t\t190\n#define KEY_F21\t\t\t191\n#define KEY_F22\t\t\t192\n#define KEY_F23\t\t\t193\n#define KEY_F24\t\t\t194\n\n#define KEY_PLAYCD\t\t200\n#define KEY_PAUSECD\t\t201\n#define KEY_PROG3\t\t202\n#define KEY_PROG4\t\t203\n#define KEY_DASHBOARD\t\t204\t/* AL Dashboard */\n#define KEY_SUSPEND\t\t205\n#define KEY_CLOSE\t\t206\t/* AC Close */\n#define KEY_PLAY\t\t207\n#define KEY_FASTFORWARD\t\t208\n#define KEY_BASSBOOST\t\t209\n#define KEY_PRINT\t\t210\t/* AC Print */\n#define KEY_HP\t\t\t211\n#define KEY_CAMERA\t\t212\n#define KEY_SOUND\t\t213\n#define KEY_QUESTION\t\t214\n#define KEY_EMAIL\t\t215\n#define KEY_CHAT\t\t216\n#define KEY_SEARCH\t\t217\n#define KEY_CONNECT\t\t218\n#define KEY_FINANCE\t\t219\t/* AL Checkbook/Finance */\n#define KEY_SPORT\t\t220\n#define KEY_SHOP\t\t221\n#define KEY_ALTERASE\t\t222\n#define KEY_CANCEL\t\t223\t/* AC Cancel */\n#define KEY_BRIGHTNESSDOWN\t224\n#define KEY_BRIGHTNESSUP\t225\n#define KEY_MEDIA\t\t226\n\n#define KEY_SWITCHVIDEOMODE\t227\t/* Cycle between available video\n\t\t\t\t\t outputs (Monitor/LCD/TV-out/etc) */\n#define KEY_KBDILLUMTOGGLE\t228\n#define KEY_KBDILLUMDOWN\t229\n#define KEY_KBDILLUMUP\t\t230\n\n#define KEY_SEND\t\t231\t/* AC Send */\n#define KEY_REPLY\t\t232\t/* AC Reply */\n#define KEY_FORWARDMAIL\t\t233\t/* AC Forward Msg */\n#define KEY_SAVE\t\t234\t/* AC Save */\n#define KEY_DOCUMENTS\t\t235\n\n#define KEY_BATTERY\t\t236\n\n#define KEY_BLUETOOTH\t\t237\n#define KEY_WLAN\t\t238\n#define KEY_UWB\t\t\t239\n\n#define KEY_UNKNOWN\t\t240\n#define KEY_VIDEO_NEXT\t\t241\t/* drive next video source */\n#define KEY_VIDEO_PREV\t\t242\t/* drive previous video source */\n#define KEY_BRIGHTNESS_CYCLE\t243\t/* brightness up, after max is min */\n#define KEY_BRIGHTNESS_AUTO\t244\t/* Set Auto Brightness: manual\n\t\t\t\t\t brightness control is off,\n\t\t\t\t\t rely on ambient */\n#define KEY_BRIGHTNESS_ZERO\tKEY_BRIGHTNESS_AUTO\n#define KEY_DISPLAY_OFF\t\t245\t/* display device to off state */\n\n#define KEY_WWAN\t\t246\t/* Wireless WAN (LTE, UMTS, GSM, etc.) */\n#define KEY_WIMAX\t\tKEY_WWAN\n#define KEY_RFKILL\t\t247\t/* Key that controls all radios */\n\n#define KEY_MICMUTE\t\t248\t/* Mute / unmute the microphone */\n\n/* Code 255 is reserved for special needs of AT keyboard driver */\n\n#define BTN_MISC\t\t0x100\n#define BTN_0\t\t\t0x100\n#define BTN_1\t\t\t0x101\n#define BTN_2\t\t\t0x102\n#define BTN_3\t\t\t0x103\n#define BTN_4\t\t\t0x104\n#define BTN_5\t\t\t0x105\n#define BTN_6\t\t\t0x106\n#define BTN_7\t\t\t0x107\n#define BTN_8\t\t\t0x108\n#define BTN_9\t\t\t0x109\n\n#define BTN_MOUSE\t\t0x110\n#define BTN_LEFT\t\t0x110\n#define BTN_RIGHT\t\t0x111\n#define BTN_MIDDLE\t\t0x112\n#define BTN_SIDE\t\t0x113\n#define BTN_EXTRA\t\t0x114\n#define BTN_FORWARD\t\t0x115\n#define BTN_BACK\t\t0x116\n#define BTN_TASK\t\t0x117\n\n#define BTN_JOYSTICK\t\t0x120\n#define BTN_TRIGGER\t\t0x120\n#define BTN_THUMB\t\t0x121\n#define BTN_THUMB2\t\t0x122\n#define BTN_TOP\t\t\t0x123\n#define BTN_TOP2\t\t0x124\n#define BTN_PINKIE\t\t0x125\n#define BTN_BASE\t\t0x126\n#define BTN_BASE2\t\t0x127\n#define BTN_BASE3\t\t0x128\n#define BTN_BASE4\t\t0x129\n#define BTN_BASE5\t\t0x12a\n#define BTN_BASE6\t\t0x12b\n#define BTN_DEAD\t\t0x12f\n\n#define BTN_GAMEPAD\t\t0x130\n#define BTN_SOUTH\t\t0x130\n#define BTN_A\t\t\tBTN_SOUTH\n#define BTN_EAST\t\t0x131\n#define BTN_B\t\t\tBTN_EAST\n#define BTN_C\t\t\t0x132\n#define BTN_NORTH\t\t0x133\n#define BTN_X\t\t\tBTN_NORTH\n#define BTN_WEST\t\t0x134\n#define BTN_Y\t\t\tBTN_WEST\n#define BTN_Z\t\t\t0x135\n#define BTN_TL\t\t\t0x136\n#define BTN_TR\t\t\t0x137\n#define BTN_TL2\t\t\t0x138\n#define BTN_TR2\t\t\t0x139\n#define BTN_SELECT\t\t0x13a\n#define BTN_START\t\t0x13b\n#define BTN_MODE\t\t0x13c\n#define BTN_THUMBL\t\t0x13d\n#define BTN_THUMBR\t\t0x13e\n\n#define BTN_DIGI\t\t0x140\n#define BTN_TOOL_PEN\t\t0x140\n#define BTN_TOOL_RUBBER\t\t0x141\n#define BTN_TOOL_BRUSH\t\t0x142\n#define BTN_TOOL_PENCIL\t\t0x143\n#define BTN_TOOL_AIRBRUSH\t0x144\n#define BTN_TOOL_FINGER\t\t0x145\n#define BTN_TOOL_MOUSE\t\t0x146\n#define BTN_TOOL_LENS\t\t0x147\n#define BTN_TOOL_QUINTTAP\t0x148\t/* Five fingers on trackpad */\n#define BTN_TOUCH\t\t0x14a\n#define BTN_STYLUS\t\t0x14b\n#define BTN_STYLUS2\t\t0x14c\n#define BTN_TOOL_DOUBLETAP\t0x14d\n#define BTN_TOOL_TRIPLETAP\t0x14e\n#define BTN_TOOL_QUADTAP\t0x14f\t/* Four fingers on trackpad */\n\n#define BTN_WHEEL\t\t0x150\n#define BTN_GEAR_DOWN\t\t0x150\n#define BTN_GEAR_UP\t\t0x151\n\n#define KEY_OK\t\t\t0x160\n#define KEY_SELECT\t\t0x161\n#define KEY_GOTO\t\t0x162\n#define KEY_CLEAR\t\t0x163\n#define KEY_POWER2\t\t0x164\n#define KEY_OPTION\t\t0x165\n#define KEY_INFO\t\t0x166\t/* AL OEM Features/Tips/Tutorial */\n#define KEY_TIME\t\t0x167\n#define KEY_VENDOR\t\t0x168\n#define KEY_ARCHIVE\t\t0x169\n#define KEY_PROGRAM\t\t0x16a\t/* Media Select Program Guide */\n#define KEY_CHANNEL\t\t0x16b\n#define KEY_FAVORITES\t\t0x16c\n#define KEY_EPG\t\t\t0x16d\n#define KEY_PVR\t\t\t0x16e\t/* Media Select Home */\n#define KEY_MHP\t\t\t0x16f\n#define KEY_LANGUAGE\t\t0x170\n#define KEY_TITLE\t\t0x171\n#define KEY_SUBTITLE\t\t0x172\n#define KEY_ANGLE\t\t0x173\n#define KEY_ZOOM\t\t0x174\n#define KEY_MODE\t\t0x175\n#define KEY_KEYBOARD\t\t0x176\n#define KEY_SCREEN\t\t0x177\n#define KEY_PC\t\t\t0x178\t/* Media Select Computer */\n#define KEY_TV\t\t\t0x179\t/* Media Select TV */\n#define KEY_TV2\t\t\t0x17a\t/* Media Select Cable */\n#define KEY_VCR\t\t\t0x17b\t/* Media Select VCR */\n#define KEY_VCR2\t\t0x17c\t/* VCR Plus */\n#define KEY_SAT\t\t\t0x17d\t/* Media Select Satellite */\n#define KEY_SAT2\t\t0x17e\n#define KEY_CD\t\t\t0x17f\t/* Media Select CD */\n#define KEY_TAPE\t\t0x180\t/* Media Select Tape */\n#define KEY_RADIO\t\t0x181\n#define KEY_TUNER\t\t0x182\t/* Media Select Tuner */\n#define KEY_PLAYER\t\t0x183\n#define KEY_TEXT\t\t0x184\n#define KEY_DVD\t\t\t0x185\t/* Media Select DVD */\n#define KEY_AUX\t\t\t0x186\n#define KEY_MP3\t\t\t0x187\n#define KEY_AUDIO\t\t0x188\t/* AL Audio Browser */\n#define KEY_VIDEO\t\t0x189\t/* AL Movie Browser */\n#define KEY_DIRECTORY\t\t0x18a\n#define KEY_LIST\t\t0x18b\n#define KEY_MEMO\t\t0x18c\t/* Media Select Messages */\n#define KEY_CALENDAR\t\t0x18d\n#define KEY_RED\t\t\t0x18e\n#define KEY_GREEN\t\t0x18f\n#define KEY_YELLOW\t\t0x190\n#define KEY_BLUE\t\t0x191\n#define KEY_CHANNELUP\t\t0x192\t/* Channel Increment */\n#define KEY_CHANNELDOWN\t\t0x193\t/* Channel Decrement */\n#define KEY_FIRST\t\t0x194\n#define KEY_LAST\t\t0x195\t/* Recall Last */\n#define KEY_AB\t\t\t0x196\n#define KEY_NEXT\t\t0x197\n#define KEY_RESTART\t\t0x198\n#define KEY_SLOW\t\t0x199\n#define KEY_SHUFFLE\t\t0x19a\n#define KEY_BREAK\t\t0x19b\n#define KEY_PREVIOUS\t\t0x19c\n#define KEY_DIGITS\t\t0x19d\n#define KEY_TEEN\t\t0x19e\n#define KEY_TWEN\t\t0x19f\n#define KEY_VIDEOPHONE\t\t0x1a0\t/* Media Select Video Phone */\n#define KEY_GAMES\t\t0x1a1\t/* Media Select Games */\n#define KEY_ZOOMIN\t\t0x1a2\t/* AC Zoom In */\n#define KEY_ZOOMOUT\t\t0x1a3\t/* AC Zoom Out */\n#define KEY_ZOOMRESET\t\t0x1a4\t/* AC Zoom */\n#define KEY_WORDPROCESSOR\t0x1a5\t/* AL Word Processor */\n#define KEY_EDITOR\t\t0x1a6\t/* AL Text Editor */\n#define KEY_SPREADSHEET\t\t0x1a7\t/* AL Spreadsheet */\n#define KEY_GRAPHICSEDITOR\t0x1a8\t/* AL Graphics Editor */\n#define KEY_PRESENTATION\t0x1a9\t/* AL Presentation App */\n#define KEY_DATABASE\t\t0x1aa\t/* AL Database App */\n#define KEY_NEWS\t\t0x1ab\t/* AL Newsreader */\n#define KEY_VOICEMAIL\t\t0x1ac\t/* AL Voicemail */\n#define KEY_ADDRESSBOOK\t\t0x1ad\t/* AL Contacts/Address Book */\n#define KEY_MESSENGER\t\t0x1ae\t/* AL Instant Messaging */\n#define KEY_DISPLAYTOGGLE\t0x1af\t/* Turn display (LCD) on and off */\n#define KEY_BRIGHTNESS_TOGGLE\tKEY_DISPLAYTOGGLE\n#define KEY_SPELLCHECK\t\t0x1b0 /* AL Spell Check */\n#define KEY_LOGOFF\t\t0x1b1 /* AL Logoff */\n\n#define KEY_DOLLAR\t\t0x1b2\n#define KEY_EURO\t\t0x1b3\n\n#define KEY_FRAMEBACK\t\t0x1b4\t/* Consumer - transport controls */\n#define KEY_FRAMEFORWARD\t0x1b5\n#define KEY_CONTEXT_MENU\t0x1b6\t/* GenDesc - system context menu */\n#define KEY_MEDIA_REPEAT\t0x1b7\t/* Consumer - transport control */\n#define KEY_10CHANNELSUP\t0x1b8\t/* 10 channels up (10+) */\n#define KEY_10CHANNELSDOWN\t0x1b9\t/* 10 channels down (10-) */\n#define KEY_IMAGES\t\t0x1ba\t/* AL Image Browser */\n\n#define KEY_DEL_EOL\t\t0x1c0\n#define KEY_DEL_EOS\t\t0x1c1\n#define KEY_INS_LINE\t\t0x1c2\n#define KEY_DEL_LINE\t\t0x1c3\n\n#define KEY_FN\t\t\t0x1d0\n#define KEY_FN_ESC\t\t0x1d1\n#define KEY_FN_F1\t\t0x1d2\n#define KEY_FN_F2\t\t0x1d3\n#define KEY_FN_F3\t\t0x1d4\n#define KEY_FN_F4\t\t0x1d5\n#define KEY_FN_F5\t\t0x1d6\n#define KEY_FN_F6\t\t0x1d7\n#define KEY_FN_F7\t\t0x1d8\n#define KEY_FN_F8\t\t0x1d9\n#define KEY_FN_F9\t\t0x1da\n#define KEY_FN_F10\t\t0x1db\n#define KEY_FN_F11\t\t0x1dc\n#define KEY_FN_F12\t\t0x1dd\n#define KEY_FN_1\t\t0x1de\n#define KEY_FN_2\t\t0x1df\n#define KEY_FN_D\t\t0x1e0\n#define KEY_FN_E\t\t0x1e1\n#define KEY_FN_F\t\t0x1e2\n#define KEY_FN_S\t\t0x1e3\n#define KEY_FN_B\t\t0x1e4\n\n#define KEY_BRL_DOT1\t\t0x1f1\n#define KEY_BRL_DOT2\t\t0x1f2\n#define KEY_BRL_DOT3\t\t0x1f3\n#define KEY_BRL_DOT4\t\t0x1f4\n#define KEY_BRL_DOT5\t\t0x1f5\n#define KEY_BRL_DOT6\t\t0x1f6\n#define KEY_BRL_DOT7\t\t0x1f7\n#define KEY_BRL_DOT8\t\t0x1f8\n#define KEY_BRL_DOT9\t\t0x1f9\n#define KEY_BRL_DOT10\t\t0x1fa\n\n#define KEY_NUMERIC_0\t\t0x200\t/* used by phones, remote controls, */\n#define KEY_NUMERIC_1\t\t0x201\t/* and other keypads */\n#define KEY_NUMERIC_2\t\t0x202\n#define KEY_NUMERIC_3\t\t0x203\n#define KEY_NUMERIC_4\t\t0x204\n#define KEY_NUMERIC_5\t\t0x205\n#define KEY_NUMERIC_6\t\t0x206\n#define KEY_NUMERIC_7\t\t0x207\n#define KEY_NUMERIC_8\t\t0x208\n#define KEY_NUMERIC_9\t\t0x209\n#define KEY_NUMERIC_STAR\t0x20a\n#define KEY_NUMERIC_POUND\t0x20b\n#define KEY_NUMERIC_A\t\t0x20c\t/* Phone key A - HUT Telephony 0xb9 */\n#define KEY_NUMERIC_B\t\t0x20d\n#define KEY_NUMERIC_C\t\t0x20e\n#define KEY_NUMERIC_D\t\t0x20f\n\n#define KEY_CAMERA_FOCUS\t0x210\n#define KEY_WPS_BUTTON\t\t0x211\t/* WiFi Protected Setup key */\n\n#define KEY_TOUCHPAD_TOGGLE\t0x212\t/* Request switch touchpad on or off */\n#define KEY_TOUCHPAD_ON\t\t0x213\n#define KEY_TOUCHPAD_OFF\t0x214\n\n#define KEY_CAMERA_ZOOMIN\t0x215\n#define KEY_CAMERA_ZOOMOUT\t0x216\n#define KEY_CAMERA_UP\t\t0x217\n#define KEY_CAMERA_DOWN\t\t0x218\n#define KEY_CAMERA_LEFT\t\t0x219\n#define KEY_CAMERA_RIGHT\t0x21a\n\n#define KEY_ATTENDANT_ON\t0x21b\n#define KEY_ATTENDANT_OFF\t0x21c\n#define KEY_ATTENDANT_TOGGLE\t0x21d\t/* Attendant call on or off */\n#define KEY_LIGHTS_TOGGLE\t0x21e\t/* Reading light on or off */\n\n#define BTN_DPAD_UP\t\t0x220\n#define BTN_DPAD_DOWN\t\t0x221\n#define BTN_DPAD_LEFT\t\t0x222\n#define BTN_DPAD_RIGHT\t\t0x223\n\n#define KEY_ALS_TOGGLE\t\t0x230\t/* Ambient light sensor */\n\n#define KEY_BUTTONCONFIG\t\t0x240\t/* AL Button Configuration */\n#define KEY_TASKMANAGER\t\t0x241\t/* AL Task/Project Manager */\n#define KEY_JOURNAL\t\t0x242\t/* AL Log/Journal/Timecard */\n#define KEY_CONTROLPANEL\t\t0x243\t/* AL Control Panel */\n#define KEY_APPSELECT\t\t0x244\t/* AL Select Task/Application */\n#define KEY_SCREENSAVER\t\t0x245\t/* AL Screen Saver */\n#define KEY_VOICECOMMAND\t\t0x246\t/* Listening Voice Command */\n#define KEY_ASSISTANT\t\t0x247\t/* AL Context-aware desktop assistant */\n\n#define KEY_BRIGHTNESS_MIN\t\t0x250\t/* Set Brightness to Minimum */\n#define KEY_BRIGHTNESS_MAX\t\t0x251\t/* Set Brightness to Maximum */\n\n#define KEY_KBDINPUTASSIST_PREV\t\t0x260\n#define KEY_KBDINPUTASSIST_NEXT\t\t0x261\n#define KEY_KBDINPUTASSIST_PREVGROUP\t\t0x262\n#define KEY_KBDINPUTASSIST_NEXTGROUP\t\t0x263\n#define KEY_KBDINPUTASSIST_ACCEPT\t\t0x264\n#define KEY_KBDINPUTASSIST_CANCEL\t\t0x265\n\n/* Diagonal movement keys */\n#define KEY_RIGHT_UP\t\t\t0x266\n#define KEY_RIGHT_DOWN\t\t\t0x267\n#define KEY_LEFT_UP\t\t\t0x268\n#define KEY_LEFT_DOWN\t\t\t0x269\n\n#define KEY_ROOT_MENU\t\t\t0x26a /* Show Device's Root Menu */\n/* Show Top Menu of the Media (e.g. DVD) */\n#define KEY_MEDIA_TOP_MENU\t\t0x26b\n#define KEY_NUMERIC_11\t\t\t0x26c\n#define KEY_NUMERIC_12\t\t\t0x26d\n/*\n * Toggle Audio Description: refers to an audio service that helps blind and\n * visually impaired consumers understand the action in a program. Note: in\n * some countries this is referred to as \"Video Description\".\n */\n#define KEY_AUDIO_DESC\t\t\t0x26e\n#define KEY_3D_MODE\t\t\t0x26f\n#define KEY_NEXT_FAVORITE\t\t0x270\n#define KEY_STOP_RECORD\t\t\t0x271\n#define KEY_PAUSE_RECORD\t\t0x272\n#define KEY_VOD\t\t\t\t0x273 /* Video on Demand */\n#define KEY_UNMUTE\t\t\t0x274\n#define KEY_FASTREVERSE\t\t\t0x275\n#define KEY_SLOWREVERSE\t\t\t0x276\n/*\n * Control a data application associated with the currently viewed channel,\n * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)\n */\n#define KEY_DATA\t\t\t0x277\n#define KEY_ONSCREEN_KEYBOARD\t\t0x278\n\n#define BTN_TRIGGER_HAPPY\t\t0x2c0\n#define BTN_TRIGGER_HAPPY1\t\t0x2c0\n#define BTN_TRIGGER_HAPPY2\t\t0x2c1\n#define BTN_TRIGGER_HAPPY3\t\t0x2c2\n#define BTN_TRIGGER_HAPPY4\t\t0x2c3\n#define BTN_TRIGGER_HAPPY5\t\t0x2c4\n#define BTN_TRIGGER_HAPPY6\t\t0x2c5\n#define BTN_TRIGGER_HAPPY7\t\t0x2c6\n#define BTN_TRIGGER_HAPPY8\t\t0x2c7\n#define BTN_TRIGGER_HAPPY9\t\t0x2c8\n#define BTN_TRIGGER_HAPPY10\t\t0x2c9\n#define BTN_TRIGGER_HAPPY11\t\t0x2ca\n#define BTN_TRIGGER_HAPPY12\t\t0x2cb\n#define BTN_TRIGGER_HAPPY13\t\t0x2cc\n#define BTN_TRIGGER_HAPPY14\t\t0x2cd\n#define BTN_TRIGGER_HAPPY15\t\t0x2ce\n#define BTN_TRIGGER_HAPPY16\t\t0x2cf\n#define BTN_TRIGGER_HAPPY17\t\t0x2d0\n#define BTN_TRIGGER_HAPPY18\t\t0x2d1\n#define BTN_TRIGGER_HAPPY19\t\t0x2d2\n#define BTN_TRIGGER_HAPPY20\t\t0x2d3\n#define BTN_TRIGGER_HAPPY21\t\t0x2d4\n#define BTN_TRIGGER_HAPPY22\t\t0x2d5\n#define BTN_TRIGGER_HAPPY23\t\t0x2d6\n#define BTN_TRIGGER_HAPPY24\t\t0x2d7\n#define BTN_TRIGGER_HAPPY25\t\t0x2d8\n#define BTN_TRIGGER_HAPPY26\t\t0x2d9\n#define BTN_TRIGGER_HAPPY27\t\t0x2da\n#define BTN_TRIGGER_HAPPY28\t\t0x2db\n#define BTN_TRIGGER_HAPPY29\t\t0x2dc\n#define BTN_TRIGGER_HAPPY30\t\t0x2dd\n#define BTN_TRIGGER_HAPPY31\t\t0x2de\n#define BTN_TRIGGER_HAPPY32\t\t0x2df\n#define BTN_TRIGGER_HAPPY33\t\t0x2e0\n#define BTN_TRIGGER_HAPPY34\t\t0x2e1\n#define BTN_TRIGGER_HAPPY35\t\t0x2e2\n#define BTN_TRIGGER_HAPPY36\t\t0x2e3\n#define BTN_TRIGGER_HAPPY37\t\t0x2e4\n#define BTN_TRIGGER_HAPPY38\t\t0x2e5\n#define BTN_TRIGGER_HAPPY39\t\t0x2e6\n#define BTN_TRIGGER_HAPPY40\t\t0x2e7\n\n/* We avoid low common keys in module aliases so they don't get huge. */\n#define KEY_MIN_INTERESTING\tKEY_MUTE\n#define KEY_MAX\t\t\t0x2ff\n#define KEY_CNT\t\t\t(KEY_MAX+1)\n\n/*\n * Relative axes\n */\n\n#define REL_X\t\t\t0x00\n#define REL_Y\t\t\t0x01\n#define REL_Z\t\t\t0x02\n#define REL_RX\t\t\t0x03\n#define REL_RY\t\t\t0x04\n#define REL_RZ\t\t\t0x05\n#define REL_HWHEEL\t\t0x06\n#define REL_DIAL\t\t0x07\n#define REL_WHEEL\t\t0x08\n#define REL_MISC\t\t0x09\n#define REL_MAX\t\t\t0x0f\n#define REL_CNT\t\t\t(REL_MAX+1)\n\n/*\n * Absolute axes\n */\n\n#define ABS_X\t\t\t0x00\n#define ABS_Y\t\t\t0x01\n#define ABS_Z\t\t\t0x02\n#define ABS_RX\t\t\t0x03\n#define ABS_RY\t\t\t0x04\n#define ABS_RZ\t\t\t0x05\n#define ABS_THROTTLE\t\t0x06\n#define ABS_RUDDER\t\t0x07\n#define ABS_WHEEL\t\t0x08\n#define ABS_GAS\t\t\t0x09\n#define ABS_BRAKE\t\t0x0a\n#define ABS_HAT0X\t\t0x10\n#define ABS_HAT0Y\t\t0x11\n#define ABS_HAT1X\t\t0x12\n#define ABS_HAT1Y\t\t0x13\n#define ABS_HAT2X\t\t0x14\n#define ABS_HAT2Y\t\t0x15\n#define ABS_HAT3X\t\t0x16\n#define ABS_HAT3Y\t\t0x17\n#define ABS_PRESSURE\t\t0x18\n#define ABS_DISTANCE\t\t0x19\n#define ABS_TILT_X\t\t0x1a\n#define ABS_TILT_Y\t\t0x1b\n#define ABS_TOOL_WIDTH\t\t0x1c\n\n#define ABS_VOLUME\t\t0x20\n\n#define ABS_MISC\t\t0x28\n\n#define ABS_MT_SLOT\t\t0x2f\t/* MT slot being modified */\n#define ABS_MT_TOUCH_MAJOR\t0x30\t/* Major axis of touching ellipse */\n#define ABS_MT_TOUCH_MINOR\t0x31\t/* Minor axis (omit if circular) */\n#define ABS_MT_WIDTH_MAJOR\t0x32\t/* Major axis of approaching ellipse */\n#define ABS_MT_WIDTH_MINOR\t0x33\t/* Minor axis (omit if circular) */\n#define ABS_MT_ORIENTATION\t0x34\t/* Ellipse orientation */\n#define ABS_MT_POSITION_X\t0x35\t/* Center X touch position */\n#define ABS_MT_POSITION_Y\t0x36\t/* Center Y touch position */\n#define ABS_MT_TOOL_TYPE\t0x37\t/* Type of touching device */\n#define ABS_MT_BLOB_ID\t\t0x38\t/* Group a set of packets as a blob */\n#define ABS_MT_TRACKING_ID\t0x39\t/* Unique ID of initiated contact */\n#define ABS_MT_PRESSURE\t\t0x3a\t/* Pressure on contact area */\n#define ABS_MT_DISTANCE\t\t0x3b\t/* Contact hover distance */\n#define ABS_MT_TOOL_X\t\t0x3c\t/* Center X tool position */\n#define ABS_MT_TOOL_Y\t\t0x3d\t/* Center Y tool position */\n\n\n#define ABS_MAX\t\t\t0x3f\n#define ABS_CNT\t\t\t(ABS_MAX+1)\n\n/*\n * Switch events\n */\n\n#define SW_LID\t\t\t0x00 /* set = lid shut */\n#define SW_TABLET_MODE\t\t0x01 /* set = tablet mode */\n#define SW_HEADPHONE_INSERT\t0x02 /* set = inserted */\n#define SW_RFKILL_ALL\t\t0x03 /* rfkill master switch, type \"any\"\n\t\t\t\t\t set = radio enabled */\n#define SW_RADIO\t\tSW_RFKILL_ALL\t/* deprecated */\n#define SW_MICROPHONE_INSERT\t0x04 /* set = inserted */\n#define SW_DOCK\t\t\t0x05 /* set = plugged into dock */\n#define SW_LINEOUT_INSERT\t0x06 /* set = inserted */\n#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */\n#define SW_VIDEOOUT_INSERT\t0x08 /* set = inserted */\n#define SW_CAMERA_LENS_COVER\t0x09 /* set = lens covered */\n#define SW_KEYPAD_SLIDE\t\t0x0a /* set = keypad slide out */\n#define SW_FRONT_PROXIMITY\t0x0b /* set = front proximity sensor active */\n#define SW_ROTATE_LOCK\t\t0x0c /* set = rotate locked/disabled */\n#define SW_LINEIN_INSERT\t0x0d /* set = inserted */\n#define SW_MUTE_DEVICE\t\t0x0e /* set = device disabled */\n#define SW_PEN_INSERTED\t\t0x0f /* set = pen inserted */\n#define SW_MAX\t\t\t0x0f\n#define SW_CNT\t\t\t(SW_MAX+1)\n\n/*\n * Misc events\n */\n\n#define MSC_SERIAL\t\t0x00\n#define MSC_PULSELED\t\t0x01\n#define MSC_GESTURE\t\t0x02\n#define MSC_RAW\t\t\t0x03\n#define MSC_SCAN\t\t0x04\n#define MSC_TIMESTAMP\t\t0x05\n#define MSC_MAX\t\t\t0x07\n#define MSC_CNT\t\t\t(MSC_MAX+1)\n\n/*\n * LEDs\n */\n\n#define LED_NUML\t\t0x00\n#define LED_CAPSL\t\t0x01\n#define LED_SCROLLL\t\t0x02\n#define LED_COMPOSE\t\t0x03\n#define LED_KANA\t\t0x04\n#define LED_SLEEP\t\t0x05\n#define LED_SUSPEND\t\t0x06\n#define LED_MUTE\t\t0x07\n#define LED_MISC\t\t0x08\n#define LED_MAIL\t\t0x09\n#define LED_CHARGING\t\t0x0a\n#define LED_MAX\t\t\t0x0f\n#define LED_CNT\t\t\t(LED_MAX+1)\n\n/*\n * Autorepeat values\n */\n\n#define REP_DELAY\t\t0x00\n#define REP_PERIOD\t\t0x01\n#define REP_MAX\t\t\t0x01\n#define REP_CNT\t\t\t(REP_MAX+1)\n\n/*\n * Sounds\n */\n\n#define SND_CLICK\t\t0x00\n#define SND_BELL\t\t0x01\n#define SND_TONE\t\t0x02\n#define SND_MAX\t\t\t0x07\n#define SND_CNT\t\t\t(SND_MAX+1)\n\n#define MATRIX_KEY(row, col, code)\t\\\n\t((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))\n\n#endif /* _DT_BINDINGS_INPUT_INPUT_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/interrupt-controller/irq.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most IRQ bindings.\n *\n * Most IRQ bindings include a flags cell as part of the IRQ specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n\n#define IRQ_TYPE_NONE\t\t0\n#define IRQ_TYPE_EDGE_RISING\t1\n#define IRQ_TYPE_EDGE_FALLING\t2\n#define IRQ_TYPE_EDGE_BOTH\t(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)\n#define IRQ_TYPE_LEVEL_HIGH\t4\n#define IRQ_TYPE_LEVEL_LOW\t8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/phy/phy.h", "content": "/*\n *\n * This header provides constants for the phy framework\n *\n * Copyright (C) 2014 STMicroelectronics\n * Author: Gabriel Fernandez \n * License terms: GNU General Public License (GPL), version 2\n */\n\n#ifndef _DT_BINDINGS_PHY\n#define _DT_BINDINGS_PHY\n\n#define PHY_NONE\t\t0\n#define PHY_TYPE_SATA\t\t1\n#define PHY_TYPE_PCIE\t\t2\n#define PHY_TYPE_USB2\t\t3\n#define PHY_TYPE_USB3\t\t4\n#define PHY_TYPE_UFS\t\t5\n#define PHY_TYPE_DP\t\t6\n#define PHY_TYPE_SGMII\t\t7\n\n#endif /* _DT_BINDINGS_PHY */\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h", "content": "/*\n * MIO pin configuration defines for Xilinx ZynqMP\n *\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Author: Chirag Parekh \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * version 2 as published by the Free Software Foundation.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program. If not, see .\n */\n\n#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H\n#define _DT_BINDINGS_PINCTRL_ZYNQMP_H\n\n/* Bit value for IO standards */\n#define IO_STANDARD_LVCMOS33 0\n#define IO_STANDARD_LVCMOS18 1\n\n/* Bit values for Slew Rates */\n#define SLEW_RATE_FAST 0\n#define SLEW_RATE_SLOW 1\n\n/* Bit values for Pin inputs */\n#define PIN_INPUT_TYPE_CMOS 0\n#define PIN_INPUT_TYPE_SCHMITT 1\n\n/* Bit values for drive control*/\n#define DRIVE_STRENGTH_2MA 2\n#define DRIVE_STRENGTH_4MA 4\n#define DRIVE_STRENGTH_8MA 8\n#define DRIVE_STRENGTH_12MA 12\n\n#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/power/xlnx-versal-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_POWER_H\n#define _DT_BINDINGS_VERSAL_POWER_H\n\n#define PM_DEV_USB_0\t\t\t\t(0x18224018U)\n#define PM_DEV_GEM_0\t\t\t\t(0x18224019U)\n#define PM_DEV_GEM_1\t\t\t\t(0x1822401aU)\n#define PM_DEV_SPI_0\t\t\t\t(0x1822401bU)\n#define PM_DEV_SPI_1\t\t\t\t(0x1822401cU)\n#define PM_DEV_I2C_0\t\t\t\t(0x1822401dU)\n#define PM_DEV_I2C_1\t\t\t\t(0x1822401eU)\n#define PM_DEV_CAN_FD_0\t\t\t\t(0x1822401fU)\n#define PM_DEV_CAN_FD_1\t\t\t\t(0x18224020U)\n#define PM_DEV_UART_0\t\t\t\t(0x18224021U)\n#define PM_DEV_UART_1\t\t\t\t(0x18224022U)\n#define PM_DEV_GPIO\t\t\t\t(0x18224023U)\n#define PM_DEV_TTC_0\t\t\t\t(0x18224024U)\n#define PM_DEV_TTC_1\t\t\t\t(0x18224025U)\n#define PM_DEV_TTC_2\t\t\t\t(0x18224026U)\n#define PM_DEV_TTC_3\t\t\t\t(0x18224027U)\n#define PM_DEV_SWDT_FPD\t\t\t\t(0x18224029U)\n#define PM_DEV_OSPI\t\t\t\t(0x1822402aU)\n#define PM_DEV_QSPI\t\t\t\t(0x1822402bU)\n#define PM_DEV_GPIO_PMC\t\t\t\t(0x1822402cU)\n#define PM_DEV_SDIO_0\t\t\t\t(0x1822402eU)\n#define PM_DEV_SDIO_1\t\t\t\t(0x1822402fU)\n#define PM_DEV_RTC\t\t\t\t(0x18224034U)\n#define PM_DEV_ADMA_0\t\t\t\t(0x18224035U)\n#define PM_DEV_ADMA_1\t\t\t\t(0x18224036U)\n#define PM_DEV_ADMA_2\t\t\t\t(0x18224037U)\n#define PM_DEV_ADMA_3\t\t\t\t(0x18224038U)\n#define PM_DEV_ADMA_4\t\t\t\t(0x18224039U)\n#define PM_DEV_ADMA_5\t\t\t\t(0x1822403aU)\n#define PM_DEV_ADMA_6\t\t\t\t(0x1822403bU)\n#define PM_DEV_ADMA_7\t\t\t\t(0x1822403cU)\n#define PM_DEV_AI\t\t\t\t(0x18224072U)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/power/xlnx-zynqmp-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_POWER_H\n#define _DT_BINDINGS_ZYNQMP_POWER_H\n\n#define\t\tPD_USB_0\t22\n#define\t\tPD_USB_1\t23\n#define\t\tPD_TTC_0\t24\n#define\t\tPD_TTC_1\t25\n#define\t\tPD_TTC_2\t26\n#define\t\tPD_TTC_3\t27\n#define\t\tPD_SATA\t\t28\n#define\t\tPD_ETH_0\t29\n#define\t\tPD_ETH_1\t30\n#define\t\tPD_ETH_2\t31\n#define\t\tPD_ETH_3\t32\n#define\t\tPD_UART_0\t33\n#define\t\tPD_UART_1\t34\n#define\t\tPD_SPI_0\t35\n#define\t\tPD_SPI_1\t36\n#define\t\tPD_I2C_0\t37\n#define\t\tPD_I2C_1\t38\n#define\t\tPD_SD_0\t\t39\n#define\t\tPD_SD_1\t\t40\n#define\t\tPD_DP\t\t41\n#define\t\tPD_GDMA\t\t42\n#define\t\tPD_ADMA\t\t43\n#define\t\tPD_NAND\t\t44\n#define\t\tPD_QSPI\t\t45\n#define\t\tPD_GPIO\t\t46\n#define\t\tPD_CAN_0\t47\n#define\t\tPD_CAN_1\t48\n#define\t\tPD_GPU\t\t58\n#define\t\tPD_PCIE\t\t59\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H\n#define _DT_BINDINGS_ZYNQMP_RESETS_H\n\n#define\t\tZYNQMP_RESET_PCIE_CFG\t\t0\n#define\t\tZYNQMP_RESET_PCIE_BRIDGE\t1\n#define\t\tZYNQMP_RESET_PCIE_CTRL\t\t2\n#define\t\tZYNQMP_RESET_DP\t\t\t3\n#define\t\tZYNQMP_RESET_SWDT_CRF\t\t4\n#define\t\tZYNQMP_RESET_AFI_FM5\t\t5\n#define\t\tZYNQMP_RESET_AFI_FM4\t\t6\n#define\t\tZYNQMP_RESET_AFI_FM3\t\t7\n#define\t\tZYNQMP_RESET_AFI_FM2\t\t8\n#define\t\tZYNQMP_RESET_AFI_FM1\t\t9\n#define\t\tZYNQMP_RESET_AFI_FM0\t\t10\n#define\t\tZYNQMP_RESET_GDMA\t\t11\n#define\t\tZYNQMP_RESET_GPU_PP1\t\t12\n#define\t\tZYNQMP_RESET_GPU_PP0\t\t13\n#define\t\tZYNQMP_RESET_GPU\t\t14\n#define\t\tZYNQMP_RESET_GT\t\t\t15\n#define\t\tZYNQMP_RESET_SATA\t\t16\n#define\t\tZYNQMP_RESET_ACPU3_PWRON\t17\n#define\t\tZYNQMP_RESET_ACPU2_PWRON\t18\n#define\t\tZYNQMP_RESET_ACPU1_PWRON\t19\n#define\t\tZYNQMP_RESET_ACPU0_PWRON\t20\n#define\t\tZYNQMP_RESET_APU_L2\t\t21\n#define\t\tZYNQMP_RESET_ACPU3\t\t22\n#define\t\tZYNQMP_RESET_ACPU2\t\t23\n#define\t\tZYNQMP_RESET_ACPU1\t\t24\n#define\t\tZYNQMP_RESET_ACPU0\t\t25\n#define\t\tZYNQMP_RESET_DDR\t\t26\n#define\t\tZYNQMP_RESET_APM_FPD\t\t27\n#define\t\tZYNQMP_RESET_SOFT\t\t28\n#define\t\tZYNQMP_RESET_GEM0\t\t29\n#define\t\tZYNQMP_RESET_GEM1\t\t30\n#define\t\tZYNQMP_RESET_GEM2\t\t31\n#define\t\tZYNQMP_RESET_GEM3\t\t32\n#define\t\tZYNQMP_RESET_QSPI\t\t33\n#define\t\tZYNQMP_RESET_UART0\t\t34\n#define\t\tZYNQMP_RESET_UART1\t\t35\n#define\t\tZYNQMP_RESET_SPI0\t\t36\n#define\t\tZYNQMP_RESET_SPI1\t\t37\n#define\t\tZYNQMP_RESET_SDIO0\t\t38\n#define\t\tZYNQMP_RESET_SDIO1\t\t39\n#define\t\tZYNQMP_RESET_CAN0\t\t40\n#define\t\tZYNQMP_RESET_CAN1\t\t41\n#define\t\tZYNQMP_RESET_I2C0\t\t42\n#define\t\tZYNQMP_RESET_I2C1\t\t43\n#define\t\tZYNQMP_RESET_TTC0\t\t44\n#define\t\tZYNQMP_RESET_TTC1\t\t45\n#define\t\tZYNQMP_RESET_TTC2\t\t46\n#define\t\tZYNQMP_RESET_TTC3\t\t47\n#define\t\tZYNQMP_RESET_SWDT_CRL\t\t48\n#define\t\tZYNQMP_RESET_NAND\t\t49\n#define\t\tZYNQMP_RESET_ADMA\t\t50\n#define\t\tZYNQMP_RESET_GPIO\t\t51\n#define\t\tZYNQMP_RESET_IOU_CC\t\t52\n#define\t\tZYNQMP_RESET_TIMESTAMP\t\t53\n#define\t\tZYNQMP_RESET_RPU_R50\t\t54\n#define\t\tZYNQMP_RESET_RPU_R51\t\t55\n#define\t\tZYNQMP_RESET_RPU_AMBA\t\t56\n#define\t\tZYNQMP_RESET_OCM\t\t57\n#define\t\tZYNQMP_RESET_RPU_PGE\t\t58\n#define\t\tZYNQMP_RESET_USB0_CORERESET\t59\n#define\t\tZYNQMP_RESET_USB1_CORERESET\t60\n#define\t\tZYNQMP_RESET_USB0_HIBERRESET\t61\n#define\t\tZYNQMP_RESET_USB1_HIBERRESET\t62\n#define\t\tZYNQMP_RESET_USB0_APB\t\t63\n#define\t\tZYNQMP_RESET_USB1_APB\t\t64\n#define\t\tZYNQMP_RESET_IPI\t\t65\n#define\t\tZYNQMP_RESET_APM_LPD\t\t66\n#define\t\tZYNQMP_RESET_RTC\t\t67\n#define\t\tZYNQMP_RESET_SYSMON\t\t68\n#define\t\tZYNQMP_RESET_AFI_FM6\t\t69\n#define\t\tZYNQMP_RESET_LPD_SWDT\t\t70\n#define\t\tZYNQMP_RESET_FPD\t\t71\n#define\t\tZYNQMP_RESET_RPU_DBG1\t\t72\n#define\t\tZYNQMP_RESET_RPU_DBG0\t\t73\n#define\t\tZYNQMP_RESET_DBG_LPD\t\t74\n#define\t\tZYNQMP_RESET_DBG_FPD\t\t75\n#define\t\tZYNQMP_RESET_APLL\t\t76\n#define\t\tZYNQMP_RESET_DPLL\t\t77\n#define\t\tZYNQMP_RESET_VPLL\t\t78\n#define\t\tZYNQMP_RESET_IOPLL\t\t79\n#define\t\tZYNQMP_RESET_RPLL\t\t80\n#define\t\tZYNQMP_RESET_GPO3_PL_0\t\t81\n#define\t\tZYNQMP_RESET_GPO3_PL_1\t\t82\n#define\t\tZYNQMP_RESET_GPO3_PL_2\t\t83\n#define\t\tZYNQMP_RESET_GPO3_PL_3\t\t84\n#define\t\tZYNQMP_RESET_GPO3_PL_4\t\t85\n#define\t\tZYNQMP_RESET_GPO3_PL_5\t\t86\n#define\t\tZYNQMP_RESET_GPO3_PL_6\t\t87\n#define\t\tZYNQMP_RESET_GPO3_PL_7\t\t88\n#define\t\tZYNQMP_RESET_GPO3_PL_8\t\t89\n#define\t\tZYNQMP_RESET_GPO3_PL_9\t\t90\n#define\t\tZYNQMP_RESET_GPO3_PL_10\t\t91\n#define\t\tZYNQMP_RESET_GPO3_PL_11\t\t92\n#define\t\tZYNQMP_RESET_GPO3_PL_12\t\t93\n#define\t\tZYNQMP_RESET_GPO3_PL_13\t\t94\n#define\t\tZYNQMP_RESET_GPO3_PL_14\t\t95\n#define\t\tZYNQMP_RESET_GPO3_PL_15\t\t96\n#define\t\tZYNQMP_RESET_GPO3_PL_16\t\t97\n#define\t\tZYNQMP_RESET_GPO3_PL_17\t\t98\n#define\t\tZYNQMP_RESET_GPO3_PL_18\t\t99\n#define\t\tZYNQMP_RESET_GPO3_PL_19\t\t100\n#define\t\tZYNQMP_RESET_GPO3_PL_20\t\t101\n#define\t\tZYNQMP_RESET_GPO3_PL_21\t\t102\n#define\t\tZYNQMP_RESET_GPO3_PL_22\t\t103\n#define\t\tZYNQMP_RESET_GPO3_PL_23\t\t104\n#define\t\tZYNQMP_RESET_GPO3_PL_24\t\t105\n#define\t\tZYNQMP_RESET_GPO3_PL_25\t\t106\n#define\t\tZYNQMP_RESET_GPO3_PL_26\t\t107\n#define\t\tZYNQMP_RESET_GPO3_PL_27\t\t108\n#define\t\tZYNQMP_RESET_GPO3_PL_28\t\t109\n#define\t\tZYNQMP_RESET_GPO3_PL_29\t\t110\n#define\t\tZYNQMP_RESET_GPO3_PL_30\t\t111\n#define\t\tZYNQMP_RESET_GPO3_PL_31\t\t112\n#define\t\tZYNQMP_RESET_RPU_LS\t\t113\n#define\t\tZYNQMP_RESET_PS_ONLY\t\t114\n#define\t\tZYNQMP_RESET_PL\t\t\t115\n#define\t\tZYNQMP_RESET_PS_PL0\t\t116\n#define\t\tZYNQMP_RESET_PS_PL1\t\t117\n#define\t\tZYNQMP_RESET_PS_PL2\t\t118\n#define\t\tZYNQMP_RESET_PS_PL3\t\t119\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/versal/versal-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-versal-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-power.h\"\n/ {\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tcan0_clk: can0_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN0_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tcan1_clk: can1_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN1_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk ACPU>;\n};\n\n&can0 {\n\tclocks = <&can0_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_0>;\n};\n\n&can1 {\n\tclocks = <&can1_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_1>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_0>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_1>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk PMC_LSBUS_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO_PMC>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk I2C0_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_0>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk I2C1_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_1>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_0>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_1>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_2>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_3>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_4>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_5>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_6>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_7>;\n};\n\n&qspi {\n\tclocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_QSPI>;\n};\n\n&ospi {\n\tclocks = <&versal_clk OSPI_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_OSPI>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware PM_DEV_RTC>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_0>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_1>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_0>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_1>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_0>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_1>;\n};\n\n&ttc0 {\n\tclocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_0>;\n};\n\n&ttc1 {\n\tclocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_1>;\n};\n\n&ttc2 {\n\tclocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_2>;\n};\n\n&ttc3 {\n\tclocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_3>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_USB_0>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SWDT_FPD>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/versal/versal-spp-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\talt_ref_clk: alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware-wip\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"alt_ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk 77>;\n};\n\n&can0 {\n\tclocks = <&versal_clk 96>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401f>;\n};\n\n&can1 {\n\tclocks = <&versal_clk 97>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224020>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x18224019>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x1822401a>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk 61>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk 98>;\n\tpower-domains = <&versal_firmware 0x1822401d>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk 99>;\n\tpower-domains = <&versal_firmware 0x1822401e>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224035>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224036>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224037>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224038>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224039>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403a>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403b>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403c>;\n};\n\n&qspi {\n\tclocks = <&versal_clk 57>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402b>;\n};\n\n&ospi {\n\tclocks = <&versal_clk 58>, <&versal_clk 82>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware 0x18224034>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk 92>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224021>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk 93>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224022>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk 59>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402e>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk 60>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402f>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk 94>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401b>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk 95>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401c>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk 91>, <&versal_clk 104>;\n\tpower-domains = <&versal_firmware 0x18224018>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk 82>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/versal/versal.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal\";\n\n\tcpus: cpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <1>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tfpga: fpga {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&versal_fpga>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tpsci: psci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t};\n\n\tversal_fpga: versal_fpga {\n\t\tcompatible = \"xlnx,versal-fpga\";\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\t\t\treg = <0 0xf9000000 0 0x80000>, /* GICD */\n\t\t\t <0 0xf9080000 0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 4>;\n\n\t\t\tgic_its: gic-its@f9020000 {\n\t\t\t\tcompatible = \"arm,gic-v3-its\";\n\t\t\t\tmsi-controller;\n\t\t\t\tmsi-cells = <1>;\n\t\t\t\treg = <0 0xf9020000 0 0x20000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t\tinterrupt-parent = <&gic>;\n\t\tu-boot,dm-pre-reloc;\n\n\t\tapm: performance-monitor@f0920000 {\n\t\t\tcompatible = \"xlnx,flexnoc-pm-2.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg-names = \"funnel\", \"baselpd\", \"basefpd\";\n\t\t\treg = <0x0 0xf0920000 0x0 0x1000>,\n\t\t\t <0x0 0xf0980000 0x0 0x9000>,\n\t\t\t <0x0 0xf0b80000 0x0 0x9000>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff060000 0 0x6000>;\n\t\t\tinterrupts = <0 20 1>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff070000 0 0x6000>;\n\t\t\tinterrupts = <0 21 1>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcci: cci@fd000000 {\n\t\t\tcompatible = \"arm,cci-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd000000 0 0x10000>;\n\t\t\tranges = <0 0 0xfd000000 0xa0000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcci_pmu: pmu@10000 {\n\t\t\t\tcompatible = \"arm,cci-500-pmu,r0\";\n\t\t\t\treg = <0x10000 0x90000>;\n\t\t\t\tinterrupts = <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>;\n\t\t\t};\n\t\t};\n\n\t\tlpd_dma_chan0: dma@ffa80000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa80000 0 0x1000>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa90000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa90000 0 0x1000>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffaa0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaa0000 0 0x1000>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\n\t\tlpd_dma_chan3: dma@ffab0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffab0000 0 0x1000>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffac0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffac0000 0 0x1000>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffad0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffad0000 0 0x1000>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffae0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffae0000 0 0x1000>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffaf0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaf0000 0 0x1000>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tgem0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,versal-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0c0000 0 0x1000>;\n\t\t\tinterrupts = <0 56 4>, <0 56 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,versal-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0d0000 0 0x1000>;\n\t\t\tinterrupts = <0 58 4>, <0 58 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tgpio0: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0b0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff020000 0 0x1000>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff030000 0 0x1000>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tmc0: memory-controller@f6150000\t{\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <0>;\n\t\t};\n\n\t\tmc1: memory-controller@f62c0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <1>;\n\t\t};\n\n\t\tmc2: memory-controller@f6430000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <2>;\n\t\t};\n\n\t\tmc3: memory-controller@f65a0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <3>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff000000 0 0x1000>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tserial1: serial@ff010000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff010000 0 0x1000>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd800000 0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 124 4>, <0 124 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,is-stig-pgm = <1>;\n\t\t\tcdns,trigger-address = <0xC0000000>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff040000 0 0x1000>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff050000 0 0x1000>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsysmon: sysmon@f1270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\treg = <0x0 0xf1270000 0x0 0x4000>;\n\t\t\tinterrupts = <0 144 4>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tttc0: timer@ff0e0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff0f0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 40 4>, <0 41 4>, <0 42 4>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff100000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 46 4>, <0 47 4>, <0 48 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tusb0: usb@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff9d0000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0 0xfe200000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"usb-wakeup\";\n\t\t\t\tinterrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,mask_phy_reset;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\tcpm_pciea: pci@fca10000 {\n\t\t\t#address-cells = <3>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"xlnx,versal-cpm-host-1.00\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc_0 1>,\n\t\t\t\t\t<0 0 0 2 &pcie_intc_0 2>,\n\t\t\t\t\t<0 0 0 3 &pcie_intc_0 3>,\n\t\t\t\t\t<0 0 0 4 &pcie_intc_0 4>;\n\t\t\tinterrupt-map-mask = <0 0 0 7>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupt-names = \"misc\";\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>,\n\t\t\t\t <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>;\n\t\t\tmsi-map = <0x0 &gic_its 0x0 0x10000>;\n\t\t\treg = <0x0 0xfca10000 0x0 0x1000>,\n\t\t\t <0x6 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"cpm_slcr\", \"cfg\";\n\t\t\tpcie_intc_0: pci-interrupt-controller {\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\tinterrupt-controller ;\n\t\t\t};\n\t\t};\n\n\t\twatchdog: watchdog@fd4d0000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd4d0000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 0x64 1>, <0 0x6D 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t};\n\t};\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/zynq/zynq-7000.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\treplicator {\n\t\tcompatible = \"arm,coresight-static-replicator\";\n\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\tout-ports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\t/* replicator output ports */\n\t\t\tport@0 {\n\t\t\t\treg = <0>;\n\t\t\t\treplicator_out_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&tpiu_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tport@1 {\n\t\t\t\treg = <1>;\n\t\t\t\treplicator_out_port1: endpoint {\n\t\t\t\t\tremote-endpoint = <&etb_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tin-ports {\n\t\t\t/* replicator input port */\n\t\t\tport {\n\t\t\t\treplicator_in_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&funnel_out_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"apb_pclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\", \"arm,primecell\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: mmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: mmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\tetb@f8801000 {\n\t\t\tcompatible = \"arm,coresight-etb10\", \"arm,primecell\";\n\t\t\treg = <0xf8801000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\tetb_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ttpiu@f8803000 {\n\t\t\tcompatible = \"arm,coresight-tpiu\", \"arm,primecell\";\n\t\t\treg = <0xf8803000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\ttpiu_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tfunnel@f8804000 {\n\t\t\tcompatible = \"arm,coresight-static-funnel\", \"arm,primecell\";\n\t\t\treg = <0xf8804000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\t\t/* funnel output ports */\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tfunnel_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint =\n\t\t\t\t\t\t\t<&replicator_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tin-ports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\t/* funnel input ports */\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tfunnel0_in_port0: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm0_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tfunnel0_in_port1: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm1_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tfunnel0_in_port2: endpoint {\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t/* The other input ports are not connect to anything */\n\t\t\t};\n\t\t};\n\n\t\tptm@f889c000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889c000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu0>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm0_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889d000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889d000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu1>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm1_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/zynqmp/zynqmp-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-zynqmp-clk.h\"\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL0_REF>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL1_REF>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL2_REF>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL3_REF>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tdp_aclk: dp_aclk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&zynqmp_firmware {\n\tzynqmp_clk: clock-controller {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,\n\t\t\t <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\",\n\t\t\t \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t};\n};\n\n&can0 {\n\tclocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&can1 {\n\tclocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&cpu0 {\n\tclocks = <&zynqmp_clk ACPU>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gpu {\n\tclocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&nand0 {\n\tclocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gem0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>,\n\t\t <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>,\n\t\t <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>,\n\t\t <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>,\n\t\t <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gpio {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&i2c0 {\n\tclocks = <&zynqmp_clk I2C0_REF>;\n};\n\n&i2c1 {\n\tclocks = <&zynqmp_clk I2C1_REF>;\n};\n\n&perf_monitor_ocm {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&perf_monitor_ddr {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_cci {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_lpd {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&pcie {\n\tclocks = <&zynqmp_clk PCIE_REF>;\n};\n\n&qspi {\n\tclocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&sata {\n\tclocks = <&zynqmp_clk SATA_REF>;\n};\n\n&sdhci0 {\n\tclocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&sdhci1 {\n\tclocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&spi0 {\n\tclocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&spi1 {\n\tclocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart0 {\n\tclocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart1 {\n\tclocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&usb0 {\n\tclocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&usb1 {\n\tclocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&watchdog0 {\n\tclocks = <&zynqmp_clk WDT>;\n};\n\n&lpd_watchdog {\n\tclocks = <&zynqmp_clk LPD_WDT>;\n};\n\n&xilinx_ams {\n\tclocks = <&zynqmp_clk AMS_REF>;\n};\n\n&zynqmp_dpsub {\n\tclocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>;\n};\n\n&xlnx_dpdma {\n\tclocks = <&zynqmp_clk DPDMA_REF>;\n};\n\n&zynqmp_dp_snd_codec0 {\n\tclocks = <&zynqmp_clk DP_AUDIO_REF>;\n};\n\n&zynqmp_pcap {\n\tclocks = <&zynqmp_clk PCAP>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2020.2/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n#include \"include/dt-bindings/power/xlnx-zynqmp-power.h\"\n#include \"include/dt-bindings/reset/xlnx-zynqmp-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu-opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t\txlnx,ipi-id = <0>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff990400 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\treg = <0x0 0xff9905c0 0x0 0x20>,\n\t\t\t <0x0 0xff9905e0 0x0 0x20>,\n\t\t\t <0x0 0xff990e80 0x0 0x20>,\n\t\t\t <0x0 0xff990ea0 0x0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <4>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tzynqmp_firmware: zynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x1>;\n\n\t\t\tzynqmp_pcap: pcap {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t\t\t\tclock-names = \"ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tzynqmp_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\t\t};\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&zynqmp_pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t};\n\n\tnvmem_firmware {\n\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsoc_revision: soc_revision@0 {\n\t\t\treg = <0x0 0x4>;\n\t\t};\n\t\t/* efuse access */\n\t\tefuse_dna: efuse_dna@c {\n\t\t\treg = <0xc 0xc>;\n\t\t};\n\t\tefuse_usr0: efuse_usr0@20 {\n\t\t\treg = <0x20 0x4>;\n\t\t};\n\t\tefuse_usr1: efuse_usr1@24 {\n\t\t\treg = <0x24 0x4>;\n\t\t};\n\t\tefuse_usr2: efuse_usr2@28 {\n\t\t\treg = <0x28 0x4>;\n\t\t};\n\t\tefuse_usr3: efuse_usr3@2c {\n\t\t\treg = <0x2c 0x4>;\n\t\t};\n\t\tefuse_usr4: efuse_usr4@30 {\n\t\t\treg = <0x30 0x4>;\n\t\t};\n\t\tefuse_usr5: efuse_usr5@34 {\n\t\t\treg = <0x34 0x4>;\n\t\t};\n\t\tefuse_usr6: efuse_usr6@38 {\n\t\t\treg = <0x38 0x4>;\n\t\t};\n\t\tefuse_usr7: efuse_usr7@3c {\n\t\t\treg = <0x3c 0x4>;\n\t\t};\n\t\tefuse_miscusr: efuse_miscusr@40 {\n\t\t\treg = <0x40 0x4>;\n\t\t};\n\t\tefuse_chash: efuse_chash@50 {\n\t\t\treg = <0x50 0x4>;\n\t\t};\n\t\tefuse_pufmisc: efuse_pufmisc@54 {\n\t\t\treg = <0x54 0x4>;\n\t\t};\n\t\tefuse_sec: efuse_sec@58 {\n\t\t\treg = <0x58 0x4>;\n\t\t};\n\t\tefuse_spkid: efuse_spkid@5c {\n\t\t\treg = <0x5c 0x4>;\n\t\t};\n\t\tefuse_ppk0hash: efuse_ppk0hash@a0 {\n\t\t\treg = <0xa0 0x30>;\n\t\t};\n\t\tefuse_ppk1hash: efuse_ppk1hash@d0 {\n\t\t\treg = <0xd0 0x30>;\n\t\t};\n\t};\n\n\txlnx_rsa: zynqmp_rsa {\n\t\tcompatible = \"xlnx,zynqmp-rsa\";\n\t};\n\n\txlnx_keccak_384: sha384 {\n\t\tcompatible = \"xlnx,zynqmp-keccak-384\";\n\t};\n\n\txlnx_aes: zynqmp_aes {\n\t\tcompatible = \"xlnx,zynqmp-aes\";\n\t};\n\n\tamba_apu: amba-apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tsmmu: smmu@fd800000 {\n\t\tcompatible = \"arm,mmu-500\";\n\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t#iommu-cells = <1>;\n\t\tstatus = \"disabled\";\n\t\t#global-interrupts = <1>;\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\", \"gpu_pp0\", \"gpu_pp1\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPU>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand@ff100000 {\n\t\t\tcompatible = \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_sys\", \"clk_flash\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_NAND>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPIO>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tperf_monitor_ocm: perf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa00000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_ddr: perf-monitor@fd0b0000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd0b0000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <6>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <10>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_cci: perf-monitor@fd490000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd490000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_lpd: perf-monitor@ffa10000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa10000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_PCIE>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_QSPI>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tserdes: zynqmp_phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\";\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SATA>, <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_APB>, <&zynqmp_reset ZYNQMP_RESET_DP>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_GEM0>, <&zynqmp_reset ZYNQMP_RESET_GEM1>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_GEM2>, <&zynqmp_reset ZYNQMP_RESET_GEM3>;\n\t\t\treset-names = \"sata_rst\", \"usb0_crst\", \"usb1_crst\",\n\t\t\t\t \"usb0_hibrst\", \"usb1_hibrst\", \"usb0_apbrst\",\n\t\t\t\t \"usb1_apbrst\", \"dp_rst\", \"gem0_rst\",\n\t\t\t\t \"gem1_rst\", \"gem2_rst\", \"gem3_rst\";\n\t\t\tlane0: lane0 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane1: lane1 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane2: lane2 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t\tlane3: lane3 {\n\t\t\t\t#phy-cells = <4>;\n\t\t\t};\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SATA>;\n\t\t\t#stream-id-cells = <4>;\n\t\t/*\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;*/\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_0>;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_1>;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_1>;\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_0>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>, <0 75 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t\t/* snps,enable-hibernation; */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb1@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_1>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>, <0 76 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <60>;\n\t\t\treset-on-timeout;\n\t\t};\n\n\t\tlpd_watchdog: watchdog@ff150000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 52 1>;\n\t\t\treg = <0x0 0xff150000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges;\n\n\t\t\tams_ps: ams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50800 0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50c00 0x0 0x400>;\n\t\t\t};\n\t\t};\n\n\t\txlnx_dpdma: dma@fd4c0000 {\n\t\t\tcompatible = \"xlnx,dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tdma-channels = <6>;\n\t\t\t#dma-cells = <1>;\n\t\t\tdma-video0channel {\n\t\t\t\tcompatible = \"xlnx,video0\";\n\t\t\t};\n\t\t\tdma-video1channel {\n\t\t\t\tcompatible = \"xlnx,video1\";\n\t\t\t};\n\t\t\tdma-video2channel {\n\t\t\t\tcompatible = \"xlnx,video2\";\n\t\t\t};\n\t\t\tdma-graphicschannel {\n\t\t\t\tcompatible = \"xlnx,graphics\";\n\t\t\t};\n\t\t\tdma-audio0channel {\n\t\t\t\tcompatible = \"xlnx,audio0\";\n\t\t\t};\n\t\t\tdma-audio1channel {\n\t\t\t\tcompatible = \"xlnx,audio1\";\n\t\t\t};\n\t\t};\n\n\t\tzynqmp_dpsub: zynqmp-display@fd4a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"dp\", \"blend\", \"av_buf\", \"aud\";\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"dp_apb_clk\", \"dp_aud_clk\", \"dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\n\t\t\tvid-layer {\n\t\t\t\tdma-names = \"vid0\", \"vid1\", \"vid2\";\n\t\t\t\tdmas = <&xlnx_dpdma 0>,\n\t\t\t\t <&xlnx_dpdma 1>,\n\t\t\t\t <&xlnx_dpdma 2>;\n\t\t\t};\n\n\t\t\tgfx-layer {\n\t\t\t\tdma-names = \"gfx0\";\n\t\t\t\tdmas = <&xlnx_dpdma 3>;\n\t\t\t};\n\n\t\t\t/* dummy node to to indicate there's no child i2c device */\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&xlnx_dpdma 4>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&xlnx_dpdma 5>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card0: zynqmp_dp_snd_card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,\n\t\t\t\t\t\t <&zynqmp_dp_snd_pcm1>;\n\t\t\t\txlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/sp701-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze sp701.\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@1 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x3>;\n\t\t\tti,tx-internal-delay = <0x3>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/vcu118-rev2.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze vcu118\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@3 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\tti,sgmii-ref-clock-output-enable;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\treg = <3>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-a2197-sc-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller RevA\";\n\tcompatible = \"xlnx,versal-sc-revA\", \"xlnx,versal-sc\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\t/* SC Bank 43\n\tFIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS\n\tSYSCTLR_GPIO0 - 5 - conneced to versal */\n\t/* cpu thermal for MAX6643 fan control */\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tdc38_led {\n\t\t\tlabel = \"ds38-green\"; /* sc AB11 500_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc37_led {\n\t\t\tlabel = \"ds37-green\"; /* sc AD10 501_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc36_led {\n\t\t\tlabel = \"ds36-green\"; /* sc AD11 502_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t};\n};\n\n/* usb - type C - pl\n and micro usb 2.0, gt\n*/\n/* Feb 28/2019 version */\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n/* TODO\nUSB0 MIO52-63\nUSB1 MIO64-75\n*/\n\n/*eth MDIO 76/77\neth reset MIO42\nmarwell m88e1512 - SGMII */\n&gem0 {\n\tphy-handle = <&phy0>;\n\t/* phy-mode = \"sgmii\"; DTG generates this properly */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: phy@21 {\n\t\treg = <21>; /* FIXME */\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5- 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 0 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\"; /* FIXME no linux driver */\n\t\t\t\treg = <0xc0>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <10000000>; /* 10 ohm */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\ti2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* FIXME connection to Samtec J212D */\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t/* FIXME connection to Samtec J53C */\n\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@5d { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@5d { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@5d { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"LPDDR4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-emu-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-emu-itr8\", \"xlnx,versal-emu\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal EMU ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:9600\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n\n\tclk0212: clk0212 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <212000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n};\n\n&timer {\n clock-frequency = <440000>;\n};\n\n&serial0 {\n status = \"okay\";\n clocks = <&clk0212 &clk0212>;\n\tcurrent-speed = <9600>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-spp-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-spp-itr8-cn13940875\", \"xlnx,versal-spp-itr8\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal SPP ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &ospi;\n\t\tspi2 = &spi0;\n\t\tspi3 = &spi1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tusb0 = &usb0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>;\n\t};\n\tchosen {\n\t\tbootargs = \"rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n};\n\n&timer {\n\tclock-frequency = <2720000>;\n};\n\n&serial0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tmaximum-speed = \"high-speed\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n phy0: phy@0 {\n\t\treg = <0x0>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n phy1: phy@1 {\n\t\treg = <0x1>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <0x1>;\n\treg = <0x0 0xf1030000 0x0 0x1000>;\n\tclocks = <&clk125 &clk125>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot-boot.bin\";\n\t\t\t\treg = <0x0 0x6400000>;\n\t\t\t};\n\t\t\tpartition@6400000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x6400000 0x500000>;\n\t\t\t};\n\t\t\tpartition@6900000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x6900000 0x20000>;\n\t\t\t};\n\t\t\tpartition@6920000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x6920000 0x5E0000>;\n\t\t\t};\n\t\t\tpartition@7f40000 {\n\t\t\t\tlabel = \"qspi-bootenv\";\n\t\t\t\treg = <0x7f40000 0x40000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ospi {\n\tstatus = \"disabled\";\n\tclocks = <&clk125 &clk125>;\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\tcdns,fifo-depth = <508>;\n\tcdns,fifo-width = <4>;\n\tcdns,is-dma = <1>;\n\tcdns,is-stig-pgm = <1>;\n\tcdns,trigger-address = <0x00000000>;\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t};\n\t\t\tpartition@600000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t};\n\t\t\tpartition@620000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <1>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <3>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\treg = <0x0 0x84000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-v350-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal v350 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-v350-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal v350 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tspi0 = &ospi;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-01 revA OSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n compatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n \"xlnx,versal-vc-p-a2197-00\",\n \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n model = \"Xilinx Versal A2197 Processor board revA\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tgpio0 = &gpio;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-01 revA QSPI\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-02 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>; /* u9 */\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@1 { /* Marvell 88E1512; U9 */\n\t\treg = <1>;\n\t};\n};\n\n\n&sdhci0 {\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&sdhci1 { /* U1A */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tno-1-8-v;\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* U4 */\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"high-speed\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* U12 Catalyst EEPROM - AT24 should be equivalent */\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U13 and U15 */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U18 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <3>;\t/* FIXME - check SPI1_SS0-2_B */\n\n\tflash@0 { /* U19 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst26vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-03 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tserial0 = &serial0;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t};\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* Must be enabled via J90/J91 */\n\teeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <1>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 64Mb */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x800000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* J99 MIO28 - MIO33 */\n\txlnx,mio-bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n\tno-1-8-v;\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U6 - IS25LQ032B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lq032b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-04 revA OSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem1 {\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <1>; /* FIXME */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"disabled\"; /* u93 and u92 and u161 and u160 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio-bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-04 revA QSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem1 {\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <2>;\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <1>;\n\tis-dual = <0>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 512MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x20000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio-bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-05 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem0 {\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 { /* 88e1510 */\n\t\treg = <1>;\n\t};\n\tphy2: phy@2 { /* VSC8531 */\n\t\treg = <2>;\n\t\tvsc8531,rx-delay = <6>;\n\t\tvsc8531,tx-delay = <6>;\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>;\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tspi-tx-bus-width = <1>;\n\tspi-rx-bus-width = <4>;\n\n\tflash@0 { /* MX25U12835 128Mbit */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 16MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <104000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x1000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc0 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n\tno-1-8-v;\n};\n\n&sdhci1 { /* connector */\n\txlnx,mio-bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA\";\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 {\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA (QSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&qspi {\n num-cs = <1>;\n spi-tx-bus-width = <1>;\n spi-rx-bus-width = <4>;\n #address-cells = <1>;\n #size-cells = <0>;\n is-dual = <1>;\n flash@0 {\n #address-cells = <1>;\n #size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 256MB */\n reg = <0>;\n spi-tx-bus-width = <1>;\n spi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <150000000>;\n partition@0 {\n label = \"spi0-flash0\";\n reg = <0x0 0x10000000>;\n };\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA-x-ebm-02-revA\",\n\t\t \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA (EMMC)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci0 {\n\t/* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA-x-ebm-03-revA\",\n\t\t \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA (OSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&ospi {\n\t/* U97 MT35XU02G */\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck5000-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck5000 revA\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vck5000-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck5000 board revA\";\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tspi0 = &ospi;\n\t};\n\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x10000000>;\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-virt.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-virt\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal Virtual\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tclk2: clk2 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <2670000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t\tclock-frequency = <2720000>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */\n\t\t\t <0x0 0xf9080000 0x0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x1 0x9 4>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x2>;\n\t\tranges;\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff060000 0x0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff070000 0x0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom1: eeprom@53 {\n\t\t\t\treg = <0x53>;\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t};\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom2: eeprom@55 {\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x55>;\n\t\t\t};\n\t\t};\n\n\t\tgpio: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tethernet0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 56 4>, <0x0 56 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy0: phy@0 {\n\t\t\t\treg = <0x0>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tethernet1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 58 4>, <0x0 58 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy1: phy@1 {\n\t\t\t\treg = <0x1>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xf12a0000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tnum-cs = <0x1>;\n\t\t\treg = <0x0 0xf1030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"n25q512a\", \"micron,m25p80\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <108000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@100000 {\n\t\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@600000 {\n\t\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@620000 {\n\t\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <1>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <3>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0x0 0x84000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\treg = <0x0 0xf1040000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <0>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\treg = <0x0 0xf1050000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <1>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\t#address-cells = <0x2>;\n\t\t\t#size-cells = <0x2>;\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tranges;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125 &clk125>;\n\n\t\t\tdwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x10000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = ðernet0;\n\t\tethernet1 = ðernet1;\n\t\tqspi = &qspi;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA (QSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&qspi {\n\tnum-cs = <1>;\n\tspi-tx-bus-width = <1>;\n\tspi-rx-bus-width = <4>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tis-dual = <1>;\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 256MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <150000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x10000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA-x-ebm-02-revA\",\n\t\t \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA (EMMC)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci0 {\n\t/* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA-x-ebm-03-revA\",\n\t\t \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA (OSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&ospi {\n\t/* U97 MT35XU02G */\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vp-x-a2785-00 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vp-x-a2785-00 Eval board revA\";\n\tcompatible = \"xlnx,versal-vp-x-a2785-00-revA\",\n\t\t \"xlnx,versal-vp-x-a2785-00\", \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tstatus = \"okay\"; /* u93 and u92 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\tstatus = \"okay\";\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n/* PWM via MIO 41/FAN TACH MIO 49 - FIXME */\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk120 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk120 Eval board revA\";\n\tcompatible = \"xlnx,versal-vpk120-revA\", \"xlnx,versal-vpk120\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\tclock_si5338_0: clk27 {\t/* u55 SI5338-GM */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tclock_si5338_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_si5338_3: clk150 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <150000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&psgtr {\n\tstatus = \"okay\";\n\t/* dp, usb3, sata */\n\tclocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: ethernet-phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"soft\";\n\t\tnand-ecc-algo = \"bch\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-0\";\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"soft\";\n\t\tnand-ecc-algo = \"bch\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-1\";\n\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: flash@0 {\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: flash@0 {\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t\tsw13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&amba {\n\tocm: sram@fffc0000 {\n\t\tcompatible = \"mmio-sram\";\n\t\treg = <0xfffc0000 0x10000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0xfffc0000 0x10000>;\n\t\tocm-sram@0 {\n\t\t\treg = <0x0 0x10000>;\n\t\t};\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@34 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x34>;\n\t\t\t};\n\t\t\thwmon@35 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\thwmon@36 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tio-standard = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&watchdog0 {\n\treset-on-timeout;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu100-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio-bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu100-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n\n\tsi5335_0: si5335_0 { /* clk0_usb - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5335_1: si5335_1 { /* clk1_dp - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 IRQ_TYPE_LEVEL_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* usb3, dp */\n\tclocks = <&si5335_0>, <&si5335_1>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_4: out@4 {\n\t\t\t\t\t/* refclk4 for PS-GT, used for PCIE slot */\n\t\t\t\t\treg = <4>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 for PS-GT, used for PCIE */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* pcie, sata, usb3, dp */\n\tclocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * 1.0 revision has level shifter and this property should be\n\t * removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_4: out@4 {\n\t\t\t\t\t/* refclk4 for PS-GT, used for PCIE slot */\n\t\t\t\t\treg = <4>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 for PS-GT, used for PCIE */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* pcie, sata, usb3, dp */\n\tclocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\t/*\n\t * 1.0 revision has level shifter and this property should be\n\t * removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_4: out@4 {\n\t\t\t\t\t/* refclk4 for PS-GT, used for PCIE slot */\n\t\t\t\t\treg = <4>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 for PS-GT, used for PCIE */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* pcie, sata, usb3, dp */\n\tclocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@20 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu104-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revC\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;\n\t};\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - IRPS5401_ALERT_B\n\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t * 2 - MAX6643_OT_B\n\t\t * 3 - MAX6643_FANFAIL_B\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t * 4, 10 - 17 - not connected\n\t\t */\n\t};\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\tcompatible = \"idt,8t49n287\";\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tu183: ina226@40 { /* u183 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 4, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\txlnx,mio-bank = <1>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n\tmaximum-speed = \"super-speed\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u67 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;\n\t};\n\tina226-u59 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n\tina226-u69 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;\n\t};\n\tina226-u66 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;\n\t};\n\tina226-u71 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u73 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tu67: ina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u67\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu59: ina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u59\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu61: ina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu60: ina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu64: ina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu69: ina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u69\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu66: ina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u66\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu63: ina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu3: ina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u3\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu71: ina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u71\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu73: ina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u73\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u57 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5382: clock-generator@69 { /* SI5382 - u48 */\n\t\t\t\tcompatible = \"silabs,si5382\";\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection FIXME */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, dp, usb3, sata */\n\tclocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revA\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1275-revb.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU1275 RevB\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revB\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t* 1.0 revision has level shifter and this property should be\n\t* removed for supporting UHS mode\n\t*/\n\tno-1-8-v;\n};\n\n&gem1 {\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1285-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU1285 RevA\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1285 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1285-revA\", \"xlnx,zynqmp-zcu1285\", \"xlnx,zynqmp\";\n\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PMBUS */\n\t\t\tmax20751@74 { /* u23 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x74>;\n\t\t\t};\n\t\t\tmax20751@70 { /* u89 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x70>;\n\t\t\t};\n\t\t\tmax15301@a { /* u28 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u48 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@d { /* u27 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\tmax15303@e { /* u11 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\tmax15303@f { /* u96 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\tmax15303@11 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\tmax15303@12 { /* u24 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u29 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u51 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u30 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u102 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15301@17 { /* u50 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u31 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* CM_I2C */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYS_EEPROM */\n\t\t\teeprom: eeprom@54 { /* u101 */\n\t\t\t\tcompatible = \"atmel,24c32\"; /* 24LC32A */\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FMC1 */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FMC2 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* ANALOG_PMBUS */\n\t\t\tu60: ina226@40 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu61: ina226@41 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu63: ina226@42 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu65: ina226@43 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu64: ina226@44 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* ANALOG_CM_I2C */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FMC3 */\n\t\t};\n\t};\n};\n\n&gem1 {\n\tmdio {\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu208-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU208\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU208 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu208-revA\", \"xlnx,zynqmp-zcu208\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu216-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU216\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU216 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu216-revA\", \"xlnx,zynqmp-zcu216\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zcu670-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR)\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU670 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu670-revA\", \"xlnx,zynqmp-zcu670\",\n\t\t \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\"; /* DS1 */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5381_6: si5381_6 { /* refclk_usb3 - u43 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"SFP3_TX_DISABLE\", \"SFP2_TX_DISABLE\", \"SFP1_TX_DISABLE\", /* 25 - 29 */\n\t\t \"SFP0_TX_DISABLE\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"SD_PWR_RST\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"SI5381_INT_ALM\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* Not in schematics */\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5381: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SI5381 - u43 */\n\t\t\t/*si5381: clock-generator@68 {\n\t\t\t\treg = <0x68>;\n\t\t\t};*/\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_psrefclk: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"si570_ps_ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 2Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&psgtr {\n\t/* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */\n\tclocks = <&si5381_6>;\n\tclock-names = \"ref2\";\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-a2197-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Versal System Controller on a2197 board RevA\";\n\tcompatible = \"xlnx,zynqmp-a2197-revA\", \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>;\n\t};\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&i2c0 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* this cover MGT board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* This cover processor board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-e-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevA\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tsi570_ddrdimm1_clk: si570_ddrdimm1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tsi570_lpddr4_clk2: si570_lpddr4_clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570_lpddr4_clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk1>;\n\t};\n\n\tsi570_hsdp_clk: si570_hsdp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi570_zsfp_clk: si570_zsfp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_zsfp>;\n\t};\n\n\tsi570_user1_clk: si570_user1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_user1>;\n\t};\n\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vcc-soc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;\n\t};\n\tina226-vcc-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc-pslp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;\n\t};\n\tina226-vcc-psfp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;\n\t};\n\tina226-vccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;\n\t};\n\tina226-vccaux-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;\n\t};\n\tina226-vcco-500 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;\n\t};\n\tina226-vcco-501 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;\n\t};\n\tina226-vcco-502 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;\n\t};\n\tina226-vcco-503 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;\n\t};\n\tina226-vcc-1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;\n\t};\n\tina226-vcc-3v3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;\n\t};\n\tina226-vcc-1v2-ddr4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;\n\t};\n\tina226-vcc-1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtyavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;\n\t};\n\tina226-mgtyavtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;\n\t};\n\tina226-mgtyvccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;\n\t};\n\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* u131 M88E1512 */\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"ZU4_TRIGGER\", \"SYSCTLR_PB\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"\", /* 85 - 89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"PMBUS_ALERT\", \"\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* u152 IR35215 0x16/0x46 vcc_soc */\n\t\t\t/* u179 ir38164 0x19/0x49 vcco_500 */\n\t\t\t/* u181 ir38164 0x1a/0x4a vcco_501 */\n\t\t\t/* u183 ir38164 0x1b/0x4b vcco_502 */\n\t\t\t/* u185 ir38164 0x1e/0x4e vadj_fmc */\n\t\t\t/* u187 ir38164 0x1F/0x4f mgtyavcc */\n\t\t\t/* u189 ir38164 0x20/0x50 mgtyavtt */\n\t\t\t/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */\n\t\t\t/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */\n\n\t\t\tirps5401_47: irps5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* pmbus / i2c 0x17 */\n\t\t\t};\n\t\t\tirps5401_4c: irps5401@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* pmbus / i2c 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: irps5401@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* pmbus / i2c 0x1d */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <500>; /* R440 */\n\t\t\t\t/* 0.80V @ 32A 1 of 6 Phases*/\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-soc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <500>; /* R1702 */\n\t\t\t\t/* 0.80V @ 18A */\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pmc\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* R1214 */\n\t\t\t\t/* 0.78V @ 500mA */\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u162 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r1221 */\n\t\t\t\t/* 0.78V @ 4A */\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pslp\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>; /* R1216 */\n\t\t\t\t/* 0.78V @ 1A */\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-psfp\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1219 */\n\t\t\t\t/* 0.78V @ 2A */\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* R382 */\n\t\t\t\t/* 1.5V @ 3A */\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux-pmc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>; /* R1246 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u178 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-500\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>; /* R1300 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u180 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-501\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <2000>; /* R1313 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u182 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-502\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <2000>; /* R1330 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-503\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1229 */\n\t\t\t\t/* 1.8V @ 2A */\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u173 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v8\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>; /* R400 */\n\t\t\t\t/* 1.8V @ 6A */\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-3v3\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* R1232 */\n\t\t\t\t/* 3.3V @ 500mA */\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v2-ddr4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>; /* R1275 */\n\t\t\t\t/* 1.2V @ 4A */\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>; /* R1286 */\n\t\t\t\t/* 1.1V @ 4A */\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>; /* R1350 */\n\t\t\t\t/* 1.5V @ 10A */\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavcc\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <2000>; /* R1367 */\n\t\t\t\t/* 0.88V @ 6A */\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavtt\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>; /* R1384 */\n\t\t\t\t/* 1.2V @ 10A */\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyvccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>; /* r1679 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t\ti2c@5 { /* zSFP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_zsfp: clock-generator@5d { /* u192 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_zsfp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* USER_SI570_1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_user1: clock-generator@5d { /* u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>; /* FIXME check address */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"si570_user1\";\n\t\t\t};\n\n\t\t};\n\t\ti2c@7 { /* USER_SI570_2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* 0x5c too */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* and connector J212D */\n\t\t};\n\t\tfmc1: i2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t};\n\t\tfmc2: i2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LPDDR4_SI570_CLK2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_lpddr4clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4clk1: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* 8A34001 - U219B and J310 connector */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n\ti2c-mux@75 { /* u214 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\ti2c@0 { /* SFP0_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* SFP0 */\n\t\t};\n\t\ti2c@1 { /* SFP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@2 { /* QSFP1_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* QSFP1 */\n\t\t};\n\t\t/* 3 - 7 unused */\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-g-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 MGT Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-g-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u82 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 { /* eth MDIO 76/77 */\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 */\n\t\treg = <0>;\n\t\treset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 5 - 9 */\n\t\t \"\", \"\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"\", \"\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\ti2c-mux@74 { /* u94 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* CM_I2C_SCL - Samtec */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* PMBUS - AFX_PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\ttps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\ttps544@10 { /* u73 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\ttps544@11 { /* u76 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\ttps544@12 { /* u77 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\ttps544@13 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\ttps544@14 { /* u81 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\ttps544@15 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\ttps544@16 { /* u63 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\ttps544@17 { /* u66 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\ttps544@18 { /* u67 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\ttps544@19 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\ttps544@1d { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\ttps544@1e { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\ttps544@1f { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t\ttps544@20 { /* u71 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\t\t\tu74: ina226@40 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu75: ina226@41 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\"\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@43 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu82: ina226@44 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u82\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu84: ina226@45 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\ttps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* fmc1 via JA2G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom_fmc1: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* fmc2 via JA3G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\teeprom_fmc2: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* fmc3 via JA4G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\teeprom_fmc3: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* ddr dimm */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&usb0 { /* USB0 MIO52-63 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"high-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-01-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\tina226-vcc0v6-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc0v6_lp4: ina226@49 { /* u101 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc0v6-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@5d { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n status = \"disabled\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n /delete-property/ phy-names ;\n /delete-property/ phys ;\n maximum-speed = \"high-speed\";\n snps,dis_u2_susphy_quirk ;\n snps,dis_u3_susphy_quirk ;\n status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-02-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_vpp_2v5_ddr4: tps544@1x { /* u3007 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>; /* FIXME wrong in schematics */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* C0_DDR4_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\ti2c@6 { /* C2_DDR5_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\ti2c@7 { /* C3_DDR4_UDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_RLD3 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_RLD3_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_DDR5 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_DDR5_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-03-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>;\n\t};\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_vpp_2v5_ddr4: tps544@1x { /* u3007 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>; /* FIXME wrong in schematics */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* DDR4_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_SODIMM_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_QDRIV */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_QDRIV_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-01-revA\", \"xlnx,zynqmp-x-prc-01\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\",\"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-02-revA\", \"xlnx,zynqmp-x-prc-02\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-03-revA\", \"xlnx,zynqmp-x-prc-03\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tx_prc_si5338: clock-generator@70 { /* U9 */\n\t\t\t\tcompatible = \"silabs,si5338\";\n\t\t\t\treg = <0x70>; /* FIXME */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-04-revA\", \"xlnx,zynqmp-x-prc-04\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-05-revA\", \"xlnx,zynqmp-x-prc-05\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\txlnx,eeprom = <&eeprom>; /* FIXME */\n\t\t/* xlnx,fmc-eeprom = FIXME */\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva-mlcc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP K26 revA\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP K26 RevA\";\n\tcompatible = \"xlnx,zynqmp-sm-k26-revA\", \"xlnx,zynqmp-sm-k26\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35 {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36 {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n\n\tsi5332_0: si5332_0 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tsi5332_1: si5332_1 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tsi5332_2: si5332_2 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5332_3: si5332_3 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24000000>;\n\t};\n\n\tsi5332_4: si5332_4 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5332_5: si5332_5 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\tstatus = \"okay\";\n\t/* pcie, usb3, sata */\n\tclocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\";\n};\n\n&uart1 { /* MIO36/MIO37 */\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tstatus = \"okay\";\n\tflash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\n\t\t};\n\t};\n};\n\n&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tstatus = \"okay\";\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\n\tu14: ina260@40 { /* u14 */\n\t\tcompatible = \"ti,ina260\";\n\t\t#io-channel-cells = <1>;\n\t\tlabel = \"ina260-u14\";\n\t\treg = <0x40>;\n\t};\n\t/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 2>;\n};\n\n&zynqmp_dpsub {\n\tstatus = \"okay\";\n\tphy-names = \"dp-phy0\", \"dp-phy1\";\n\tphys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 1>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\n\t/*\n\t * SD 3.0 requires level shifter and this property\n\t * should be removed if the board has level shifter and\n\t * need to work in UHS mode\n\t */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO37\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO36\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO72\", \"MIO74\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-bootstrap {\n\t\t\tpins = \"MIO71\", \"MIO73\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\",\n\t\t\t \"MIO67\", \"MIO68\", \"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t\t\"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\treset-delay-us = <2>;\n\n\t\tphy0: ethernet-phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0x8>;\n\t\t\tti,fifo-depth = <0x01>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tusbhub: usb5744 {\n\t\tcompatible = \"microchip,usb5744\";\n\t\treset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SM-K26 rev1/B/A\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP SM-K26 Rev1/B/A\";\n\tcompatible = \"xlnx,zynqmp-sm-k26-rev1\", \"xlnx,zynqmp-sm-k26-revB\",\n\t\t \"xlnx,zynqmp-sm-k26-revA\", \"xlnx,zynqmp-sm-k26\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35 {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36 {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tflash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\n\t\t};\n\t};\n};\n\n&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues to be fixed in next board revision.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva01-mlcc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP K26 revA\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP K26 RevA\";\n\tcompatible = \"xlnx,zynqmp-sm-k26-revA\", \"xlnx,zynqmp-sm-k26\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35 {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36 {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n\n\tsi5332_0: si5332_0 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tsi5332_1: si5332_1 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tsi5332_2: si5332_2 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5332_3: si5332_3 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24000000>;\n\t};\n\n\tsi5332_4: si5332_4 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5332_5: si5332_5 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\tstatus = \"okay\";\n\t/* pcie, usb3, sata */\n\tclocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\";\n};\n\n&uart1 { /* MIO36/MIO37 */\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tstatus = \"okay\";\n\tflash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\n\t\t};\n\t};\n};\n\n&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tstatus = \"okay\";\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\n\tu14: ina260@40 { /* u14 */\n\t\tcompatible = \"ti,ina260\";\n\t\t#io-channel-cells = <1>;\n\t\tlabel = \"ina260-u14\";\n\t\treg = <0x40>;\n\t};\n\t/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 2>;\n};\n\n&zynqmp_dpsub {\n\tstatus = \"okay\";\n\tphy-names = \"dp-phy0\", \"dp-phy1\";\n\tphys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 1>;\n\tmaximum-speed = \"super-speed\";\t\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\n\t/*\n\t * SD 3.0 requires level shifter and this property\n\t * should be removed if the board has level shifter and\n\t * need to work in UHS mode\n\t */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO37\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO36\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO72\", \"MIO74\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-bootstrap {\n\t\t\tpins = \"MIO71\", \"MIO73\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\",\n\t\t\t \"MIO67\", \"MIO68\", \"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t\t\"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\treset-delay-us = <2>;\n\n\t\tphy0: ethernet-phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0x8>;\n\t\t\tti,fifo-depth = <0x01>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tusbhub: usb5744 {\n\t\tcompatible = \"microchip,usb5744\";\n\t\treset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva01.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP K26 revA\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP K26 RevA\";\n\tcompatible = \"xlnx,zynqmp-sm-k26-revA\", \"xlnx,zynqmp-sm-k26\", \"xlnx,zynqmp\";\n\n\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35 {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36 {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n};\n\n&uart1 { /* MIO36/MIO37 */\n\tstatus = \"okay\";\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tstatus = \"okay\";\n\tflash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\n\t\t};\n\t};\n};\n\n&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tstatus = \"okay\";\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb-mlcc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP K26 revB\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP K26 Rev1.0/B\";\n\tcompatible = \"xlnx,zynqmp-sm-k26-rev1.0\",\n\t\t\t\"xlnx,zynqmp-sm-k26-revB\", \"xlnx,zynqmp-sm-k26-revA\",\n\t\t\t\"xlnx,zynqmp-sm-k26\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35 {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36 {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n\n\tsi5332_0: si5332_0 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tsi5332_1: si5332_1 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tsi5332_2: si5332_2 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5332_3: si5332_3 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24000000>;\n\t};\n\n\tsi5332_4: si5332_4 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5332_5: si5332_5 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n};\n\n&uart1 { /* MIO37/MIO38 */\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tstatus = \"okay\";\n\tflash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\t\t};\n\t};\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tstatus = \"okay\";\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\t\n\tu14: ina260@40 { /* u14 */\n\t\tcompatible = \"ti,ina260\";\n\t\t#io-channel-cells = <1>;\n\t\tlabel = \"ina260-u14\";\n\t\treg = <0x40>;\n\t};\n\n\tusbhub: usb5744@2d { /* u43 */\n\t\tcompatible = \"microchip,usb5744\";\n\t\treg = <0x2d>;\n\t\treset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;\n\t};\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues to be fixed in next board revision.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&psgtr {\n\tstatus = \"okay\";\n\t/* pcie, usb3, sata */\n\tclocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\";\n};\n\n&zynqmp_dpsub {\n\tstatus = \"okay\";\n\tphy-names = \"dp-phy0\", \"dp-phy1\";\n\tphys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 1>;\n\tmaximum-speed = \"super-speed\";\t\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\n\t/*\n\t * SD 3.0 requires level shifter and this property\n\t * should be removed if the board has level shifter and\n\t * need to work in UHS mode\n\t */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\tclk-phase-sd-hs = <126>, <60>;\n\tclk-phase-uhs-sdr25 = <120>, <60>;\n\tclk-phase-uhs-ddr50 = <126>, <48>;\n\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO37\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO36\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO72\", \"MIO74\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-bootstrap {\n\t\t\tpins = \"MIO71\", \"MIO73\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\",\n\t\t\t \"MIO67\", \"MIO68\", \"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t\t\"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\treset-delay-us = <2>;\n\n\t\tphy0: ethernet-phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0x8>;\n\t\t\tti,fifo-depth = <0x01>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP K26 revB\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP K26 Rev1/B\";\n\tcompatible = \"xlnx,zynqmp-sm-k26-rev1\",\n\t\t\t\"xlnx,zynqmp-sm-k26-revB\", \"xlnx,zynqmp-sm-k26-revA\",\n\t\t\t\"xlnx,zynqmp-sm-k26\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35 {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36 {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tstatus = \"okay\";\n\tflash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\t\t};\n\t};\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tstatus = \"okay\";\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t};\n\t};\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues to be fixed in next board revision.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb01-mlcc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP K26 revB\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP K26 Rev1.0/B\";\n\tcompatible = \"xlnx,zynqmp-sm-k26-rev1.0\",\n\t\t\t\"xlnx,zynqmp-sm-k26-revB\", \"xlnx,zynqmp-sm-k26-revA\",\n\t\t\t\"xlnx,zynqmp-sm-k26\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35 {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36 {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n\n\tsi5332_0: si5332_0 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tsi5332_1: si5332_1 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tsi5332_2: si5332_2 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5332_3: si5332_3 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24000000>;\n\t};\n\n\tsi5332_4: si5332_4 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5332_5: si5332_5 { /* u17 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n};\n\n&uart1 { /* MIO37/MIO38 */\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tstatus = \"okay\";\n\tflash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\t\t};\n\t};\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tstatus = \"okay\";\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\t\n\tu14: ina260@40 { /* u14 */\n\t\tcompatible = \"ti,ina260\";\n\t\t#io-channel-cells = <1>;\n\t\tlabel = \"ina260-u14\";\n\t\treg = <0x40>;\n\t};\n\n\tusbhub: usb5744@2d { /* u43 */\n\t\tcompatible = \"microchip,usb5744\";\n\t\treg = <0x2d>;\n\t\treset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;\n\t};\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues to be fixed in next board revision.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&psgtr {\n\tstatus = \"okay\";\n\t/* pcie, usb3, sata */\n\tclocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\";\n};\n\n&zynqmp_dpsub {\n\tstatus = \"okay\";\n\tphy-names = \"dp-phy0\", \"dp-phy1\";\n\tphys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 1>;\n\tmaximum-speed = \"super-speed\";\t\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\n\t/*\n\t * SD 3.0 requires level shifter and this property\n\t * should be removed if the board has level shifter and\n\t * need to work in UHS mode\n\t */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\tclk-phase-sd-hs = <126>, <60>;\n\tclk-phase-uhs-sdr25 = <120>, <60>;\n\tclk-phase-uhs-ddr50 = <126>, <48>;\n\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO37\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO36\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO72\", \"MIO74\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-bootstrap {\n\t\t\tpins = \"MIO71\", \"MIO73\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\",\n\t\t\t \"MIO67\", \"MIO68\", \"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t\t\"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\treset-delay-us = <2>;\n\n\t\tphy0: ethernet-phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0x8>;\n\t\t\tti,fifo-depth = <0x01>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb01.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP K26 revB\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP K26 Rev1.0/B\";\n\tcompatible = \"xlnx,zynqmp-sm-k26-rev1.0\",\n\t\t\t\"xlnx,zynqmp-sm-k26-revB\", \"xlnx,zynqmp-sm-k26-revA\",\n\t\t\t\"xlnx,zynqmp-sm-k26\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35 {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36 {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tstatus = \"okay\";\n\tflash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\t\t};\n\t};\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tstatus = \"okay\";\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t};\n\t\t};\n\t};\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues to be fixed in next board revision.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-smk-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP SMK-K26 Rev1/B/A\";\n\tcompatible = \"xlnx,zynqmp-smk-k26-rev1\", \"xlnx,zynqmp-smk-k26-revB\",\n\t\t \"xlnx,zynqmp-smk-k26-revA\", \"xlnx,zynqmp-smk-k26\",\n\t\t \"xlnx,zynqmp\";\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35 {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36 {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tflash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\n\t\t};\n\t};\n};\n\n&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues to be fixed in next board revision.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on vp-x-a2785-00 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vp-x-a2785-00-revA\",\n\t\t \"xlnx,zynqmp-vp-x-a2785-00\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tj383 {\n\t\t\tlabel = \"j383\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds52 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* u285 - mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>; /* maybe 4 here */\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* sd MIO 45-51 */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 { /* u131 - M88e1512 */\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"\", \"\", \"\", \"VCCINT_FAULT_B\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\treg_vccint: tps53681@c0 { /* u266 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@10 { /* u274 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@11 { /* u275 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@12 { /* u276 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc_cpm: tps544@14 { /* u272 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_util_3v3: tps544@1d { /* u278 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvcc_cpm: ina226@44 { /* u273 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpcie_smbus: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tpcie2_smbus: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tlpddr4_si570_clk3_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\t/* 6-7 unused */\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VPK120 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on VPK120 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vpk120-revA\",\n\t\t \"xlnx,zynqmp-vpk120\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw16 {\n\t\t\tlabel = \"sw16\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds40 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"QSFPDD1_MODSELL\", \"QSFPDD1_MODSELL\", /* 0 - 3 */\n\t\t\t\t \"PMBUS2_INA226_ALERT\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP1_FMC_PRSNT_M2C_B\", \"\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\tir38060_41: regulator@41 { /* IR38060 - u259 */\n\t\t\t\tcompatible = \"infineon,ir38060\", \"infineon,ir38064\";\n\t\t\t\treg = <0x41>; /* i2c addr 0x11 */\n\t\t\t};\n\t\t\tir38164_43: regulator@43 { /* IR38164 - u13 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x43>; /* i2c addr 0x13 */\n\t\t\t};\n\t\t\tir35221_45: pmic@46 { /* IR35221 - u152 */\n\t\t\t\tcompatible = \"infineon,ir35221\";\n\t\t\t\treg = <0x46>; /* PMBUS - 0x16 */\n\t\t\t};\n\t\t\tirps5401_47: pmic5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* i2c addr 0x17 */\n\t\t\t};\n\t\t\tir38164_49: regulator@49 { /* IR38164 - u189 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x49>; /* i2c addr 0x19 */\n\t\t\t};\n\t\t\tirps5401_4c: pmic@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: pmic@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tir38164_4e: regulator@4e { /* IR38164 - u184 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4e>; /* i2c addr 0x1e */\n\t\t\t};\n\t\t\tir38164_4f: regulator@4f { /* IR38164 - u187 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4f>; /* i2c addr 0x1f */\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u5 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpmbus2_ina226_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@42 { /* u265 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v5: ina226@43 { /* u264 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_mio: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavtt: ina226@46 { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtvccaux: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyavcc: ina226@4b { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tlpdmgtyavtt: ina226@4c { /* u260 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; // FIXME not in schematics\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"fmc_si570\";\n\t\t\t};\n\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tref_clk_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\tfmcp1_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tlpddr4_si570_clk3_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlpddr4_clk3: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk3\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\tqsfpdd_i2c: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* J1/J2 connectors */\n\t\t};\n\t\tidt8a34001_i2c: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* Via J310 connector */\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u219B */\n\t\t\t\treg = <0x5b>; /* FIXME not in schematics */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/clock/xlnx-versal-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_VERSAL_H\n#define _DT_BINDINGS_CLK_VERSAL_H\n\n#define PMC_PLL\t\t\t\t\t1\n#define APU_PLL\t\t\t\t\t2\n#define RPU_PLL\t\t\t\t\t3\n#define CPM_PLL\t\t\t\t\t4\n#define NOC_PLL\t\t\t\t\t5\n#define PLL_MAX\t\t\t\t\t6\n#define PMC_PRESRC\t\t\t\t7\n#define PMC_POSTCLK\t\t\t\t8\n#define PMC_PLL_OUT\t\t\t\t9\n#define PPLL\t\t\t\t\t10\n#define NOC_PRESRC\t\t\t\t11\n#define NOC_POSTCLK\t\t\t\t12\n#define NOC_PLL_OUT\t\t\t\t13\n#define NPLL\t\t\t\t\t14\n#define APU_PRESRC\t\t\t\t15\n#define APU_POSTCLK\t\t\t\t16\n#define APU_PLL_OUT\t\t\t\t17\n#define APLL\t\t\t\t\t18\n#define RPU_PRESRC\t\t\t\t19\n#define RPU_POSTCLK\t\t\t\t20\n#define RPU_PLL_OUT\t\t\t\t21\n#define RPLL\t\t\t\t\t22\n#define CPM_PRESRC\t\t\t\t23\n#define CPM_POSTCLK\t\t\t\t24\n#define CPM_PLL_OUT\t\t\t\t25\n#define CPLL\t\t\t\t\t26\n#define PPLL_TO_XPD\t\t\t\t27\n#define NPLL_TO_XPD\t\t\t\t28\n#define APLL_TO_XPD\t\t\t\t29\n#define RPLL_TO_XPD\t\t\t\t30\n#define EFUSE_REF\t\t\t\t31\n#define SYSMON_REF\t\t\t\t32\n#define IRO_SUSPEND_REF\t\t\t\t33\n#define USB_SUSPEND\t\t\t\t34\n#define SWITCH_TIMEOUT\t\t\t\t35\n#define RCLK_PMC\t\t\t\t36\n#define RCLK_LPD\t\t\t\t37\n#define WDT\t\t\t\t\t38\n#define TTC0\t\t\t\t\t39\n#define TTC1\t\t\t\t\t40\n#define TTC2\t\t\t\t\t41\n#define TTC3\t\t\t\t\t42\n#define GEM_TSU\t\t\t\t\t43\n#define GEM_TSU_LB\t\t\t\t44\n#define MUXED_IRO_DIV2\t\t\t\t45\n#define MUXED_IRO_DIV4\t\t\t\t46\n#define PSM_REF\t\t\t\t\t47\n#define GEM0_RX\t\t\t\t\t48\n#define GEM0_TX\t\t\t\t\t49\n#define GEM1_RX\t\t\t\t\t50\n#define GEM1_TX\t\t\t\t\t51\n#define CPM_CORE_REF\t\t\t\t52\n#define CPM_LSBUS_REF\t\t\t\t53\n#define CPM_DBG_REF\t\t\t\t54\n#define CPM_AUX0_REF\t\t\t\t55\n#define CPM_AUX1_REF\t\t\t\t56\n#define QSPI_REF\t\t\t\t57\n#define OSPI_REF\t\t\t\t58\n#define SDIO0_REF\t\t\t\t59\n#define SDIO1_REF\t\t\t\t60\n#define PMC_LSBUS_REF\t\t\t\t61\n#define I2C_REF\t\t\t\t\t62\n#define TEST_PATTERN_REF\t\t\t63\n#define DFT_OSC_REF\t\t\t\t64\n#define PMC_PL0_REF\t\t\t\t65\n#define PMC_PL1_REF\t\t\t\t66\n#define PMC_PL2_REF\t\t\t\t67\n#define PMC_PL3_REF\t\t\t\t68\n#define CFU_REF\t\t\t\t\t69\n#define SPARE_REF\t\t\t\t70\n#define NPI_REF\t\t\t\t\t71\n#define HSM0_REF\t\t\t\t72\n#define HSM1_REF\t\t\t\t73\n#define SD_DLL_REF\t\t\t\t74\n#define FPD_TOP_SWITCH\t\t\t\t75\n#define FPD_LSBUS\t\t\t\t76\n#define ACPU\t\t\t\t\t77\n#define DBG_TRACE\t\t\t\t78\n#define DBG_FPD\t\t\t\t\t79\n#define LPD_TOP_SWITCH\t\t\t\t80\n#define ADMA\t\t\t\t\t81\n#define LPD_LSBUS\t\t\t\t82\n#define CPU_R5\t\t\t\t\t83\n#define CPU_R5_CORE\t\t\t\t84\n#define CPU_R5_OCM\t\t\t\t85\n#define CPU_R5_OCM2\t\t\t\t86\n#define IOU_SWITCH\t\t\t\t87\n#define GEM0_REF\t\t\t\t88\n#define GEM1_REF\t\t\t\t89\n#define GEM_TSU_REF\t\t\t\t90\n#define USB0_BUS_REF\t\t\t\t91\n#define UART0_REF\t\t\t\t92\n#define UART1_REF\t\t\t\t93\n#define SPI0_REF\t\t\t\t94\n#define SPI1_REF\t\t\t\t95\n#define CAN0_REF\t\t\t\t96\n#define CAN1_REF\t\t\t\t97\n#define I2C0_REF\t\t\t\t98\n#define I2C1_REF\t\t\t\t99\n#define DBG_LPD\t\t\t\t\t100\n#define TIMESTAMP_REF\t\t\t\t101\n#define DBG_TSTMP\t\t\t\t102\n#define CPM_TOPSW_REF\t\t\t\t103\n#define USB3_DUAL_REF\t\t\t\t104\n#define OUTCLK_MAX\t\t\t\t105\n#define REF_CLK\t\t\t\t\t106\n#define PL_ALT_REF_CLK\t\t\t\t107\n#define MUXED_IRO\t\t\t\t108\n#define PL_EXT\t\t\t\t\t109\n#define PL_LB\t\t\t\t\t110\n#define MIO_50_OR_51\t\t\t\t111\n#define MIO_24_OR_25\t\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Xilinx Zynq MPSoC Firmware layer\n *\n * Copyright (C) 2014-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_ZYNQMP_H\n#define _DT_BINDINGS_CLK_ZYNQMP_H\n\n#define IOPLL\t\t\t0\n#define RPLL\t\t\t1\n#define APLL\t\t\t2\n#define DPLL\t\t\t3\n#define VPLL\t\t\t4\n#define IOPLL_TO_FPD\t\t5\n#define RPLL_TO_FPD\t\t6\n#define APLL_TO_LPD\t\t7\n#define DPLL_TO_LPD\t\t8\n#define VPLL_TO_LPD\t\t9\n#define ACPU\t\t\t10\n#define ACPU_HALF\t\t11\n#define DBF_FPD\t\t\t12\n#define DBF_LPD\t\t\t13\n#define DBG_TRACE\t\t14\n#define DBG_TSTMP\t\t15\n#define DP_VIDEO_REF\t\t16\n#define DP_AUDIO_REF\t\t17\n#define DP_STC_REF\t\t18\n#define GDMA_REF\t\t19\n#define DPDMA_REF\t\t20\n#define DDR_REF\t\t\t21\n#define SATA_REF\t\t22\n#define PCIE_REF\t\t23\n#define GPU_REF\t\t\t24\n#define GPU_PP0_REF\t\t25\n#define GPU_PP1_REF\t\t26\n#define TOPSW_MAIN\t\t27\n#define TOPSW_LSBUS\t\t28\n#define GTGREF0_REF\t\t29\n#define LPD_SWITCH\t\t30\n#define LPD_LSBUS\t\t31\n#define USB0_BUS_REF\t\t32\n#define USB1_BUS_REF\t\t33\n#define USB3_DUAL_REF\t\t34\n#define USB0\t\t\t35\n#define USB1\t\t\t36\n#define CPU_R5\t\t\t37\n#define CPU_R5_CORE\t\t38\n#define CSU_SPB\t\t\t39\n#define CSU_PLL\t\t\t40\n#define PCAP\t\t\t41\n#define IOU_SWITCH\t\t42\n#define GEM_TSU_REF\t\t43\n#define GEM_TSU\t\t\t44\n#define GEM0_TX\t\t\t45\n#define GEM1_TX\t\t\t46\n#define GEM2_TX\t\t\t47\n#define GEM3_TX\t\t\t48\n#define GEM0_RX\t\t\t49\n#define GEM1_RX\t\t\t50\n#define GEM2_RX\t\t\t51\n#define GEM3_RX\t\t\t52\n#define QSPI_REF\t\t53\n#define SDIO0_REF\t\t54\n#define SDIO1_REF\t\t55\n#define UART0_REF\t\t56\n#define UART1_REF\t\t57\n#define SPI0_REF\t\t58\n#define SPI1_REF\t\t59\n#define NAND_REF\t\t60\n#define I2C0_REF\t\t61\n#define I2C1_REF\t\t62\n#define CAN0_REF\t\t63\n#define CAN1_REF\t\t64\n#define CAN0\t\t\t65\n#define CAN1\t\t\t66\n#define DLL_REF\t\t\t67\n#define ADMA_REF\t\t68\n#define TIMESTAMP_REF\t\t69\n#define AMS_REF\t\t\t70\n#define PL0_REF\t\t\t71\n#define PL1_REF\t\t\t72\n#define PL2_REF\t\t\t73\n#define PL3_REF\t\t\t74\n#define WDT\t\t\t75\n#define IOPLL_INT\t\t76\n#define IOPLL_PRE_SRC\t\t77\n#define IOPLL_HALF\t\t78\n#define IOPLL_INT_MUX\t\t79\n#define IOPLL_POST_SRC\t\t80\n#define RPLL_INT\t\t81\n#define RPLL_PRE_SRC\t\t82\n#define RPLL_HALF\t\t83\n#define RPLL_INT_MUX\t\t84\n#define RPLL_POST_SRC\t\t85\n#define APLL_INT\t\t86\n#define APLL_PRE_SRC\t\t87\n#define APLL_HALF\t\t88\n#define APLL_INT_MUX\t\t89\n#define APLL_POST_SRC\t\t90\n#define DPLL_INT\t\t91\n#define DPLL_PRE_SRC\t\t92\n#define DPLL_HALF\t\t93\n#define DPLL_INT_MUX\t\t94\n#define DPLL_POST_SRC\t\t95\n#define VPLL_INT\t\t96\n#define VPLL_PRE_SRC\t\t97\n#define VPLL_HALF\t\t98\n#define VPLL_INT_MUX\t\t99\n#define VPLL_POST_SRC\t\t100\n#define CAN0_MIO\t\t101\n#define CAN1_MIO\t\t102\n#define ACPU_FULL\t\t103\n#define GEM0_REF\t\t104\n#define GEM1_REF\t\t105\n#define GEM2_REF\t\t106\n#define GEM3_REF\t\t107\n#define GEM0_REF_UNG\t\t108\n#define GEM1_REF_UNG\t\t109\n#define GEM2_REF_UNG\t\t110\n#define GEM3_REF_UNG\t\t111\n#define LPD_WDT\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h", "content": "/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */\n/*\n * Copyright 2019 Laurent Pinchart \n */\n\n#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n\n#define ZYNQMP_DPDMA_VIDEO0\t\t0\n#define ZYNQMP_DPDMA_VIDEO1\t\t1\n#define ZYNQMP_DPDMA_VIDEO2\t\t2\n#define ZYNQMP_DPDMA_GRAPHICS\t\t3\n#define ZYNQMP_DPDMA_AUDIO0\t\t4\n#define ZYNQMP_DPDMA_AUDIO1\t\t5\n\n#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/gpio/gpio.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most GPIO bindings.\n *\n * Most GPIO bindings include a flags cell as part of the GPIO specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_GPIO_GPIO_H\n#define _DT_BINDINGS_GPIO_GPIO_H\n\n/* Bit 0 express polarity */\n#define GPIO_ACTIVE_HIGH 0\n#define GPIO_ACTIVE_LOW 1\n\n/* Bit 1 express single-endedness */\n#define GPIO_PUSH_PULL 0\n#define GPIO_SINGLE_ENDED 2\n\n/* Bit 2 express Open drain or open source */\n#define GPIO_LINE_OPEN_SOURCE 0\n#define GPIO_LINE_OPEN_DRAIN 4\n\n/*\n * * Open Drain/Collector is the combination of single-ended open drain interface.\n * * Open Source/Emitter is the combination of single-ended open source interface.\n * */\n#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)\n#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)\n\n/* Bit 3 express GPIO suspend/resume persistence */\n#define GPIO_SLEEP_MAINTAIN_VALUE 0\n#define GPIO_SLEEP_MAY_LOOSE_VALUE 8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/input/input.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most input bindings.\n *\n * Most input bindings include key code, matrix key code format.\n * In most cases, key code and matrix key code format uses\n * the standard values/macro defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INPUT_INPUT_H\n#define _DT_BINDINGS_INPUT_INPUT_H\n\n/*\n * Device properties and quirks\n */\n\n#define INPUT_PROP_POINTER\t\t0x00\t/* needs a pointer */\n#define INPUT_PROP_DIRECT\t\t0x01\t/* direct input devices */\n#define INPUT_PROP_BUTTONPAD\t\t0x02\t/* has button(s) under pad */\n#define INPUT_PROP_SEMI_MT\t\t0x03\t/* touch rectangle only */\n#define INPUT_PROP_TOPBUTTONPAD\t\t0x04\t/* softbuttons at top of pad */\n#define INPUT_PROP_POINTING_STICK\t0x05\t/* is a pointing stick */\n#define INPUT_PROP_ACCELEROMETER\t0x06\t/* has accelerometer */\n\n#define INPUT_PROP_MAX\t\t\t0x1f\n#define INPUT_PROP_CNT\t\t\t(INPUT_PROP_MAX + 1)\n\n\n/*\n * Event types\n */\n\n#define EV_SYN\t\t\t0x00\n#define EV_KEY\t\t\t0x01\n#define EV_REL\t\t\t0x02\n#define EV_ABS\t\t\t0x03\n#define EV_MSC\t\t\t0x04\n#define EV_SW\t\t\t0x05\n#define EV_LED\t\t\t0x11\n#define EV_SND\t\t\t0x12\n#define EV_REP\t\t\t0x14\n#define EV_FF\t\t\t0x15\n#define EV_PWR\t\t\t0x16\n#define EV_FF_STATUS\t\t0x17\n#define EV_MAX\t\t\t0x1f\n#define EV_CNT\t\t\t(EV_MAX+1)\n\n/*\n * Synchronization events.\n */\n\n#define SYN_REPORT\t\t0\n#define SYN_CONFIG\t\t1\n#define SYN_MT_REPORT\t\t2\n#define SYN_DROPPED\t\t3\n#define SYN_MAX\t\t\t0xf\n#define SYN_CNT\t\t\t(SYN_MAX+1)\n\n/*\n * Keys and buttons\n *\n * Most of the keys/buttons are modeled after USB HUT 1.12\n * (see http://www.usb.org/developers/hidpage).\n * Abbreviations in the comments:\n * AC - Application Control\n * AL - Application Launch Button\n * SC - System Control\n */\n\n#define KEY_RESERVED\t\t0\n#define KEY_ESC\t\t\t1\n#define KEY_1\t\t\t2\n#define KEY_2\t\t\t3\n#define KEY_3\t\t\t4\n#define KEY_4\t\t\t5\n#define KEY_5\t\t\t6\n#define KEY_6\t\t\t7\n#define KEY_7\t\t\t8\n#define KEY_8\t\t\t9\n#define KEY_9\t\t\t10\n#define KEY_0\t\t\t11\n#define KEY_MINUS\t\t12\n#define KEY_EQUAL\t\t13\n#define KEY_BACKSPACE\t\t14\n#define KEY_TAB\t\t\t15\n#define KEY_Q\t\t\t16\n#define KEY_W\t\t\t17\n#define KEY_E\t\t\t18\n#define KEY_R\t\t\t19\n#define KEY_T\t\t\t20\n#define KEY_Y\t\t\t21\n#define KEY_U\t\t\t22\n#define KEY_I\t\t\t23\n#define KEY_O\t\t\t24\n#define KEY_P\t\t\t25\n#define KEY_LEFTBRACE\t\t26\n#define KEY_RIGHTBRACE\t\t27\n#define KEY_ENTER\t\t28\n#define KEY_LEFTCTRL\t\t29\n#define KEY_A\t\t\t30\n#define KEY_S\t\t\t31\n#define KEY_D\t\t\t32\n#define KEY_F\t\t\t33\n#define KEY_G\t\t\t34\n#define KEY_H\t\t\t35\n#define KEY_J\t\t\t36\n#define KEY_K\t\t\t37\n#define KEY_L\t\t\t38\n#define KEY_SEMICOLON\t\t39\n#define KEY_APOSTROPHE\t\t40\n#define KEY_GRAVE\t\t41\n#define KEY_LEFTSHIFT\t\t42\n#define KEY_BACKSLASH\t\t43\n#define KEY_Z\t\t\t44\n#define KEY_X\t\t\t45\n#define KEY_C\t\t\t46\n#define KEY_V\t\t\t47\n#define KEY_B\t\t\t48\n#define KEY_N\t\t\t49\n#define KEY_M\t\t\t50\n#define KEY_COMMA\t\t51\n#define KEY_DOT\t\t\t52\n#define KEY_SLASH\t\t53\n#define KEY_RIGHTSHIFT\t\t54\n#define KEY_KPASTERISK\t\t55\n#define KEY_LEFTALT\t\t56\n#define KEY_SPACE\t\t57\n#define KEY_CAPSLOCK\t\t58\n#define KEY_F1\t\t\t59\n#define KEY_F2\t\t\t60\n#define KEY_F3\t\t\t61\n#define KEY_F4\t\t\t62\n#define KEY_F5\t\t\t63\n#define KEY_F6\t\t\t64\n#define KEY_F7\t\t\t65\n#define KEY_F8\t\t\t66\n#define KEY_F9\t\t\t67\n#define KEY_F10\t\t\t68\n#define KEY_NUMLOCK\t\t69\n#define KEY_SCROLLLOCK\t\t70\n#define KEY_KP7\t\t\t71\n#define KEY_KP8\t\t\t72\n#define KEY_KP9\t\t\t73\n#define KEY_KPMINUS\t\t74\n#define KEY_KP4\t\t\t75\n#define KEY_KP5\t\t\t76\n#define KEY_KP6\t\t\t77\n#define KEY_KPPLUS\t\t78\n#define KEY_KP1\t\t\t79\n#define KEY_KP2\t\t\t80\n#define KEY_KP3\t\t\t81\n#define KEY_KP0\t\t\t82\n#define KEY_KPDOT\t\t83\n\n#define KEY_ZENKAKUHANKAKU\t85\n#define KEY_102ND\t\t86\n#define KEY_F11\t\t\t87\n#define KEY_F12\t\t\t88\n#define KEY_RO\t\t\t89\n#define KEY_KATAKANA\t\t90\n#define KEY_HIRAGANA\t\t91\n#define KEY_HENKAN\t\t92\n#define KEY_KATAKANAHIRAGANA\t93\n#define KEY_MUHENKAN\t\t94\n#define KEY_KPJPCOMMA\t\t95\n#define KEY_KPENTER\t\t96\n#define KEY_RIGHTCTRL\t\t97\n#define KEY_KPSLASH\t\t98\n#define KEY_SYSRQ\t\t99\n#define KEY_RIGHTALT\t\t100\n#define KEY_LINEFEED\t\t101\n#define KEY_HOME\t\t102\n#define KEY_UP\t\t\t103\n#define KEY_PAGEUP\t\t104\n#define KEY_LEFT\t\t105\n#define KEY_RIGHT\t\t106\n#define KEY_END\t\t\t107\n#define KEY_DOWN\t\t108\n#define KEY_PAGEDOWN\t\t109\n#define KEY_INSERT\t\t110\n#define KEY_DELETE\t\t111\n#define KEY_MACRO\t\t112\n#define KEY_MUTE\t\t113\n#define KEY_VOLUMEDOWN\t\t114\n#define KEY_VOLUMEUP\t\t115\n#define KEY_POWER\t\t116\t/* SC System Power Down */\n#define KEY_KPEQUAL\t\t117\n#define KEY_KPPLUSMINUS\t\t118\n#define KEY_PAUSE\t\t119\n#define KEY_SCALE\t\t120\t/* AL Compiz Scale (Expose) */\n\n#define KEY_KPCOMMA\t\t121\n#define KEY_HANGEUL\t\t122\n#define KEY_HANGUEL\t\tKEY_HANGEUL\n#define KEY_HANJA\t\t123\n#define KEY_YEN\t\t\t124\n#define KEY_LEFTMETA\t\t125\n#define KEY_RIGHTMETA\t\t126\n#define KEY_COMPOSE\t\t127\n#define KEY_STOP\t\t128\t/* AC Stop */\n#define KEY_AGAIN\t\t129\n#define KEY_PROPS\t\t130\t/* AC Properties */\n#define KEY_UNDO\t\t131\t/* AC Undo */\n#define KEY_FRONT\t\t132\n#define KEY_COPY\t\t133\t/* AC Copy */\n#define KEY_OPEN\t\t134\t/* AC Open */\n#define KEY_PASTE\t\t135\t/* AC Paste */\n#define KEY_FIND\t\t136\t/* AC Search */\n#define KEY_CUT\t\t\t137\t/* AC Cut */\n#define KEY_HELP\t\t138\t/* AL Integrated Help Center */\n#define KEY_MENU\t\t139\t/* Menu (show menu) */\n#define KEY_CALC\t\t140\t/* AL Calculator */\n#define KEY_SETUP\t\t141\n#define KEY_SLEEP\t\t142\t/* SC System Sleep */\n#define KEY_WAKEUP\t\t143\t/* System Wake Up */\n#define KEY_FILE\t\t144\t/* AL Local Machine Browser */\n#define KEY_SENDFILE\t\t145\n#define KEY_DELETEFILE\t\t146\n#define KEY_XFER\t\t147\n#define KEY_PROG1\t\t148\n#define KEY_PROG2\t\t149\n#define KEY_WWW\t\t\t150\t/* AL Internet Browser */\n#define KEY_MSDOS\t\t151\n#define KEY_COFFEE\t\t152\t/* AL Terminal Lock/Screensaver */\n#define KEY_SCREENLOCK\t\tKEY_COFFEE\n#define KEY_ROTATE_DISPLAY\t153\t/* Display orientation for e.g. tablets */\n#define KEY_DIRECTION\t\tKEY_ROTATE_DISPLAY\n#define KEY_CYCLEWINDOWS\t154\n#define KEY_MAIL\t\t155\n#define KEY_BOOKMARKS\t\t156\t/* AC Bookmarks */\n#define KEY_COMPUTER\t\t157\n#define KEY_BACK\t\t158\t/* AC Back */\n#define KEY_FORWARD\t\t159\t/* AC Forward */\n#define KEY_CLOSECD\t\t160\n#define KEY_EJECTCD\t\t161\n#define KEY_EJECTCLOSECD\t162\n#define KEY_NEXTSONG\t\t163\n#define KEY_PLAYPAUSE\t\t164\n#define KEY_PREVIOUSSONG\t165\n#define KEY_STOPCD\t\t166\n#define KEY_RECORD\t\t167\n#define KEY_REWIND\t\t168\n#define KEY_PHONE\t\t169\t/* Media Select Telephone */\n#define KEY_ISO\t\t\t170\n#define KEY_CONFIG\t\t171\t/* AL Consumer Control Configuration */\n#define KEY_HOMEPAGE\t\t172\t/* AC Home */\n#define KEY_REFRESH\t\t173\t/* AC Refresh */\n#define KEY_EXIT\t\t174\t/* AC Exit */\n#define KEY_MOVE\t\t175\n#define KEY_EDIT\t\t176\n#define KEY_SCROLLUP\t\t177\n#define KEY_SCROLLDOWN\t\t178\n#define KEY_KPLEFTPAREN\t\t179\n#define KEY_KPRIGHTPAREN\t180\n#define KEY_NEW\t\t\t181\t/* AC New */\n#define KEY_REDO\t\t182\t/* AC Redo/Repeat */\n\n#define KEY_F13\t\t\t183\n#define KEY_F14\t\t\t184\n#define KEY_F15\t\t\t185\n#define KEY_F16\t\t\t186\n#define KEY_F17\t\t\t187\n#define KEY_F18\t\t\t188\n#define KEY_F19\t\t\t189\n#define KEY_F20\t\t\t190\n#define KEY_F21\t\t\t191\n#define KEY_F22\t\t\t192\n#define KEY_F23\t\t\t193\n#define KEY_F24\t\t\t194\n\n#define KEY_PLAYCD\t\t200\n#define KEY_PAUSECD\t\t201\n#define KEY_PROG3\t\t202\n#define KEY_PROG4\t\t203\n#define KEY_DASHBOARD\t\t204\t/* AL Dashboard */\n#define KEY_SUSPEND\t\t205\n#define KEY_CLOSE\t\t206\t/* AC Close */\n#define KEY_PLAY\t\t207\n#define KEY_FASTFORWARD\t\t208\n#define KEY_BASSBOOST\t\t209\n#define KEY_PRINT\t\t210\t/* AC Print */\n#define KEY_HP\t\t\t211\n#define KEY_CAMERA\t\t212\n#define KEY_SOUND\t\t213\n#define KEY_QUESTION\t\t214\n#define KEY_EMAIL\t\t215\n#define KEY_CHAT\t\t216\n#define KEY_SEARCH\t\t217\n#define KEY_CONNECT\t\t218\n#define KEY_FINANCE\t\t219\t/* AL Checkbook/Finance */\n#define KEY_SPORT\t\t220\n#define KEY_SHOP\t\t221\n#define KEY_ALTERASE\t\t222\n#define KEY_CANCEL\t\t223\t/* AC Cancel */\n#define KEY_BRIGHTNESSDOWN\t224\n#define KEY_BRIGHTNESSUP\t225\n#define KEY_MEDIA\t\t226\n\n#define KEY_SWITCHVIDEOMODE\t227\t/* Cycle between available video\n\t\t\t\t\t outputs (Monitor/LCD/TV-out/etc) */\n#define KEY_KBDILLUMTOGGLE\t228\n#define KEY_KBDILLUMDOWN\t229\n#define KEY_KBDILLUMUP\t\t230\n\n#define KEY_SEND\t\t231\t/* AC Send */\n#define KEY_REPLY\t\t232\t/* AC Reply */\n#define KEY_FORWARDMAIL\t\t233\t/* AC Forward Msg */\n#define KEY_SAVE\t\t234\t/* AC Save */\n#define KEY_DOCUMENTS\t\t235\n\n#define KEY_BATTERY\t\t236\n\n#define KEY_BLUETOOTH\t\t237\n#define KEY_WLAN\t\t238\n#define KEY_UWB\t\t\t239\n\n#define KEY_UNKNOWN\t\t240\n#define KEY_VIDEO_NEXT\t\t241\t/* drive next video source */\n#define KEY_VIDEO_PREV\t\t242\t/* drive previous video source */\n#define KEY_BRIGHTNESS_CYCLE\t243\t/* brightness up, after max is min */\n#define KEY_BRIGHTNESS_AUTO\t244\t/* Set Auto Brightness: manual\n\t\t\t\t\t brightness control is off,\n\t\t\t\t\t rely on ambient */\n#define KEY_BRIGHTNESS_ZERO\tKEY_BRIGHTNESS_AUTO\n#define KEY_DISPLAY_OFF\t\t245\t/* display device to off state */\n\n#define KEY_WWAN\t\t246\t/* Wireless WAN (LTE, UMTS, GSM, etc.) */\n#define KEY_WIMAX\t\tKEY_WWAN\n#define KEY_RFKILL\t\t247\t/* Key that controls all radios */\n\n#define KEY_MICMUTE\t\t248\t/* Mute / unmute the microphone */\n\n/* Code 255 is reserved for special needs of AT keyboard driver */\n\n#define BTN_MISC\t\t0x100\n#define BTN_0\t\t\t0x100\n#define BTN_1\t\t\t0x101\n#define BTN_2\t\t\t0x102\n#define BTN_3\t\t\t0x103\n#define BTN_4\t\t\t0x104\n#define BTN_5\t\t\t0x105\n#define BTN_6\t\t\t0x106\n#define BTN_7\t\t\t0x107\n#define BTN_8\t\t\t0x108\n#define BTN_9\t\t\t0x109\n\n#define BTN_MOUSE\t\t0x110\n#define BTN_LEFT\t\t0x110\n#define BTN_RIGHT\t\t0x111\n#define BTN_MIDDLE\t\t0x112\n#define BTN_SIDE\t\t0x113\n#define BTN_EXTRA\t\t0x114\n#define BTN_FORWARD\t\t0x115\n#define BTN_BACK\t\t0x116\n#define BTN_TASK\t\t0x117\n\n#define BTN_JOYSTICK\t\t0x120\n#define BTN_TRIGGER\t\t0x120\n#define BTN_THUMB\t\t0x121\n#define BTN_THUMB2\t\t0x122\n#define BTN_TOP\t\t\t0x123\n#define BTN_TOP2\t\t0x124\n#define BTN_PINKIE\t\t0x125\n#define BTN_BASE\t\t0x126\n#define BTN_BASE2\t\t0x127\n#define BTN_BASE3\t\t0x128\n#define BTN_BASE4\t\t0x129\n#define BTN_BASE5\t\t0x12a\n#define BTN_BASE6\t\t0x12b\n#define BTN_DEAD\t\t0x12f\n\n#define BTN_GAMEPAD\t\t0x130\n#define BTN_SOUTH\t\t0x130\n#define BTN_A\t\t\tBTN_SOUTH\n#define BTN_EAST\t\t0x131\n#define BTN_B\t\t\tBTN_EAST\n#define BTN_C\t\t\t0x132\n#define BTN_NORTH\t\t0x133\n#define BTN_X\t\t\tBTN_NORTH\n#define BTN_WEST\t\t0x134\n#define BTN_Y\t\t\tBTN_WEST\n#define BTN_Z\t\t\t0x135\n#define BTN_TL\t\t\t0x136\n#define BTN_TR\t\t\t0x137\n#define BTN_TL2\t\t\t0x138\n#define BTN_TR2\t\t\t0x139\n#define BTN_SELECT\t\t0x13a\n#define BTN_START\t\t0x13b\n#define BTN_MODE\t\t0x13c\n#define BTN_THUMBL\t\t0x13d\n#define BTN_THUMBR\t\t0x13e\n\n#define BTN_DIGI\t\t0x140\n#define BTN_TOOL_PEN\t\t0x140\n#define BTN_TOOL_RUBBER\t\t0x141\n#define BTN_TOOL_BRUSH\t\t0x142\n#define BTN_TOOL_PENCIL\t\t0x143\n#define BTN_TOOL_AIRBRUSH\t0x144\n#define BTN_TOOL_FINGER\t\t0x145\n#define BTN_TOOL_MOUSE\t\t0x146\n#define BTN_TOOL_LENS\t\t0x147\n#define BTN_TOOL_QUINTTAP\t0x148\t/* Five fingers on trackpad */\n#define BTN_TOUCH\t\t0x14a\n#define BTN_STYLUS\t\t0x14b\n#define BTN_STYLUS2\t\t0x14c\n#define BTN_TOOL_DOUBLETAP\t0x14d\n#define BTN_TOOL_TRIPLETAP\t0x14e\n#define BTN_TOOL_QUADTAP\t0x14f\t/* Four fingers on trackpad */\n\n#define BTN_WHEEL\t\t0x150\n#define BTN_GEAR_DOWN\t\t0x150\n#define BTN_GEAR_UP\t\t0x151\n\n#define KEY_OK\t\t\t0x160\n#define KEY_SELECT\t\t0x161\n#define KEY_GOTO\t\t0x162\n#define KEY_CLEAR\t\t0x163\n#define KEY_POWER2\t\t0x164\n#define KEY_OPTION\t\t0x165\n#define KEY_INFO\t\t0x166\t/* AL OEM Features/Tips/Tutorial */\n#define KEY_TIME\t\t0x167\n#define KEY_VENDOR\t\t0x168\n#define KEY_ARCHIVE\t\t0x169\n#define KEY_PROGRAM\t\t0x16a\t/* Media Select Program Guide */\n#define KEY_CHANNEL\t\t0x16b\n#define KEY_FAVORITES\t\t0x16c\n#define KEY_EPG\t\t\t0x16d\n#define KEY_PVR\t\t\t0x16e\t/* Media Select Home */\n#define KEY_MHP\t\t\t0x16f\n#define KEY_LANGUAGE\t\t0x170\n#define KEY_TITLE\t\t0x171\n#define KEY_SUBTITLE\t\t0x172\n#define KEY_ANGLE\t\t0x173\n#define KEY_ZOOM\t\t0x174\n#define KEY_MODE\t\t0x175\n#define KEY_KEYBOARD\t\t0x176\n#define KEY_SCREEN\t\t0x177\n#define KEY_PC\t\t\t0x178\t/* Media Select Computer */\n#define KEY_TV\t\t\t0x179\t/* Media Select TV */\n#define KEY_TV2\t\t\t0x17a\t/* Media Select Cable */\n#define KEY_VCR\t\t\t0x17b\t/* Media Select VCR */\n#define KEY_VCR2\t\t0x17c\t/* VCR Plus */\n#define KEY_SAT\t\t\t0x17d\t/* Media Select Satellite */\n#define KEY_SAT2\t\t0x17e\n#define KEY_CD\t\t\t0x17f\t/* Media Select CD */\n#define KEY_TAPE\t\t0x180\t/* Media Select Tape */\n#define KEY_RADIO\t\t0x181\n#define KEY_TUNER\t\t0x182\t/* Media Select Tuner */\n#define KEY_PLAYER\t\t0x183\n#define KEY_TEXT\t\t0x184\n#define KEY_DVD\t\t\t0x185\t/* Media Select DVD */\n#define KEY_AUX\t\t\t0x186\n#define KEY_MP3\t\t\t0x187\n#define KEY_AUDIO\t\t0x188\t/* AL Audio Browser */\n#define KEY_VIDEO\t\t0x189\t/* AL Movie Browser */\n#define KEY_DIRECTORY\t\t0x18a\n#define KEY_LIST\t\t0x18b\n#define KEY_MEMO\t\t0x18c\t/* Media Select Messages */\n#define KEY_CALENDAR\t\t0x18d\n#define KEY_RED\t\t\t0x18e\n#define KEY_GREEN\t\t0x18f\n#define KEY_YELLOW\t\t0x190\n#define KEY_BLUE\t\t0x191\n#define KEY_CHANNELUP\t\t0x192\t/* Channel Increment */\n#define KEY_CHANNELDOWN\t\t0x193\t/* Channel Decrement */\n#define KEY_FIRST\t\t0x194\n#define KEY_LAST\t\t0x195\t/* Recall Last */\n#define KEY_AB\t\t\t0x196\n#define KEY_NEXT\t\t0x197\n#define KEY_RESTART\t\t0x198\n#define KEY_SLOW\t\t0x199\n#define KEY_SHUFFLE\t\t0x19a\n#define KEY_BREAK\t\t0x19b\n#define KEY_PREVIOUS\t\t0x19c\n#define KEY_DIGITS\t\t0x19d\n#define KEY_TEEN\t\t0x19e\n#define KEY_TWEN\t\t0x19f\n#define KEY_VIDEOPHONE\t\t0x1a0\t/* Media Select Video Phone */\n#define KEY_GAMES\t\t0x1a1\t/* Media Select Games */\n#define KEY_ZOOMIN\t\t0x1a2\t/* AC Zoom In */\n#define KEY_ZOOMOUT\t\t0x1a3\t/* AC Zoom Out */\n#define KEY_ZOOMRESET\t\t0x1a4\t/* AC Zoom */\n#define KEY_WORDPROCESSOR\t0x1a5\t/* AL Word Processor */\n#define KEY_EDITOR\t\t0x1a6\t/* AL Text Editor */\n#define KEY_SPREADSHEET\t\t0x1a7\t/* AL Spreadsheet */\n#define KEY_GRAPHICSEDITOR\t0x1a8\t/* AL Graphics Editor */\n#define KEY_PRESENTATION\t0x1a9\t/* AL Presentation App */\n#define KEY_DATABASE\t\t0x1aa\t/* AL Database App */\n#define KEY_NEWS\t\t0x1ab\t/* AL Newsreader */\n#define KEY_VOICEMAIL\t\t0x1ac\t/* AL Voicemail */\n#define KEY_ADDRESSBOOK\t\t0x1ad\t/* AL Contacts/Address Book */\n#define KEY_MESSENGER\t\t0x1ae\t/* AL Instant Messaging */\n#define KEY_DISPLAYTOGGLE\t0x1af\t/* Turn display (LCD) on and off */\n#define KEY_BRIGHTNESS_TOGGLE\tKEY_DISPLAYTOGGLE\n#define KEY_SPELLCHECK\t\t0x1b0 /* AL Spell Check */\n#define KEY_LOGOFF\t\t0x1b1 /* AL Logoff */\n\n#define KEY_DOLLAR\t\t0x1b2\n#define KEY_EURO\t\t0x1b3\n\n#define KEY_FRAMEBACK\t\t0x1b4\t/* Consumer - transport controls */\n#define KEY_FRAMEFORWARD\t0x1b5\n#define KEY_CONTEXT_MENU\t0x1b6\t/* GenDesc - system context menu */\n#define KEY_MEDIA_REPEAT\t0x1b7\t/* Consumer - transport control */\n#define KEY_10CHANNELSUP\t0x1b8\t/* 10 channels up (10+) */\n#define KEY_10CHANNELSDOWN\t0x1b9\t/* 10 channels down (10-) */\n#define KEY_IMAGES\t\t0x1ba\t/* AL Image Browser */\n\n#define KEY_DEL_EOL\t\t0x1c0\n#define KEY_DEL_EOS\t\t0x1c1\n#define KEY_INS_LINE\t\t0x1c2\n#define KEY_DEL_LINE\t\t0x1c3\n\n#define KEY_FN\t\t\t0x1d0\n#define KEY_FN_ESC\t\t0x1d1\n#define KEY_FN_F1\t\t0x1d2\n#define KEY_FN_F2\t\t0x1d3\n#define KEY_FN_F3\t\t0x1d4\n#define KEY_FN_F4\t\t0x1d5\n#define KEY_FN_F5\t\t0x1d6\n#define KEY_FN_F6\t\t0x1d7\n#define KEY_FN_F7\t\t0x1d8\n#define KEY_FN_F8\t\t0x1d9\n#define KEY_FN_F9\t\t0x1da\n#define KEY_FN_F10\t\t0x1db\n#define KEY_FN_F11\t\t0x1dc\n#define KEY_FN_F12\t\t0x1dd\n#define KEY_FN_1\t\t0x1de\n#define KEY_FN_2\t\t0x1df\n#define KEY_FN_D\t\t0x1e0\n#define KEY_FN_E\t\t0x1e1\n#define KEY_FN_F\t\t0x1e2\n#define KEY_FN_S\t\t0x1e3\n#define KEY_FN_B\t\t0x1e4\n\n#define KEY_BRL_DOT1\t\t0x1f1\n#define KEY_BRL_DOT2\t\t0x1f2\n#define KEY_BRL_DOT3\t\t0x1f3\n#define KEY_BRL_DOT4\t\t0x1f4\n#define KEY_BRL_DOT5\t\t0x1f5\n#define KEY_BRL_DOT6\t\t0x1f6\n#define KEY_BRL_DOT7\t\t0x1f7\n#define KEY_BRL_DOT8\t\t0x1f8\n#define KEY_BRL_DOT9\t\t0x1f9\n#define KEY_BRL_DOT10\t\t0x1fa\n\n#define KEY_NUMERIC_0\t\t0x200\t/* used by phones, remote controls, */\n#define KEY_NUMERIC_1\t\t0x201\t/* and other keypads */\n#define KEY_NUMERIC_2\t\t0x202\n#define KEY_NUMERIC_3\t\t0x203\n#define KEY_NUMERIC_4\t\t0x204\n#define KEY_NUMERIC_5\t\t0x205\n#define KEY_NUMERIC_6\t\t0x206\n#define KEY_NUMERIC_7\t\t0x207\n#define KEY_NUMERIC_8\t\t0x208\n#define KEY_NUMERIC_9\t\t0x209\n#define KEY_NUMERIC_STAR\t0x20a\n#define KEY_NUMERIC_POUND\t0x20b\n#define KEY_NUMERIC_A\t\t0x20c\t/* Phone key A - HUT Telephony 0xb9 */\n#define KEY_NUMERIC_B\t\t0x20d\n#define KEY_NUMERIC_C\t\t0x20e\n#define KEY_NUMERIC_D\t\t0x20f\n\n#define KEY_CAMERA_FOCUS\t0x210\n#define KEY_WPS_BUTTON\t\t0x211\t/* WiFi Protected Setup key */\n\n#define KEY_TOUCHPAD_TOGGLE\t0x212\t/* Request switch touchpad on or off */\n#define KEY_TOUCHPAD_ON\t\t0x213\n#define KEY_TOUCHPAD_OFF\t0x214\n\n#define KEY_CAMERA_ZOOMIN\t0x215\n#define KEY_CAMERA_ZOOMOUT\t0x216\n#define KEY_CAMERA_UP\t\t0x217\n#define KEY_CAMERA_DOWN\t\t0x218\n#define KEY_CAMERA_LEFT\t\t0x219\n#define KEY_CAMERA_RIGHT\t0x21a\n\n#define KEY_ATTENDANT_ON\t0x21b\n#define KEY_ATTENDANT_OFF\t0x21c\n#define KEY_ATTENDANT_TOGGLE\t0x21d\t/* Attendant call on or off */\n#define KEY_LIGHTS_TOGGLE\t0x21e\t/* Reading light on or off */\n\n#define BTN_DPAD_UP\t\t0x220\n#define BTN_DPAD_DOWN\t\t0x221\n#define BTN_DPAD_LEFT\t\t0x222\n#define BTN_DPAD_RIGHT\t\t0x223\n\n#define KEY_ALS_TOGGLE\t\t0x230\t/* Ambient light sensor */\n\n#define KEY_BUTTONCONFIG\t\t0x240\t/* AL Button Configuration */\n#define KEY_TASKMANAGER\t\t0x241\t/* AL Task/Project Manager */\n#define KEY_JOURNAL\t\t0x242\t/* AL Log/Journal/Timecard */\n#define KEY_CONTROLPANEL\t\t0x243\t/* AL Control Panel */\n#define KEY_APPSELECT\t\t0x244\t/* AL Select Task/Application */\n#define KEY_SCREENSAVER\t\t0x245\t/* AL Screen Saver */\n#define KEY_VOICECOMMAND\t\t0x246\t/* Listening Voice Command */\n#define KEY_ASSISTANT\t\t0x247\t/* AL Context-aware desktop assistant */\n\n#define KEY_BRIGHTNESS_MIN\t\t0x250\t/* Set Brightness to Minimum */\n#define KEY_BRIGHTNESS_MAX\t\t0x251\t/* Set Brightness to Maximum */\n\n#define KEY_KBDINPUTASSIST_PREV\t\t0x260\n#define KEY_KBDINPUTASSIST_NEXT\t\t0x261\n#define KEY_KBDINPUTASSIST_PREVGROUP\t\t0x262\n#define KEY_KBDINPUTASSIST_NEXTGROUP\t\t0x263\n#define KEY_KBDINPUTASSIST_ACCEPT\t\t0x264\n#define KEY_KBDINPUTASSIST_CANCEL\t\t0x265\n\n/* Diagonal movement keys */\n#define KEY_RIGHT_UP\t\t\t0x266\n#define KEY_RIGHT_DOWN\t\t\t0x267\n#define KEY_LEFT_UP\t\t\t0x268\n#define KEY_LEFT_DOWN\t\t\t0x269\n\n#define KEY_ROOT_MENU\t\t\t0x26a /* Show Device's Root Menu */\n/* Show Top Menu of the Media (e.g. DVD) */\n#define KEY_MEDIA_TOP_MENU\t\t0x26b\n#define KEY_NUMERIC_11\t\t\t0x26c\n#define KEY_NUMERIC_12\t\t\t0x26d\n/*\n * Toggle Audio Description: refers to an audio service that helps blind and\n * visually impaired consumers understand the action in a program. Note: in\n * some countries this is referred to as \"Video Description\".\n */\n#define KEY_AUDIO_DESC\t\t\t0x26e\n#define KEY_3D_MODE\t\t\t0x26f\n#define KEY_NEXT_FAVORITE\t\t0x270\n#define KEY_STOP_RECORD\t\t\t0x271\n#define KEY_PAUSE_RECORD\t\t0x272\n#define KEY_VOD\t\t\t\t0x273 /* Video on Demand */\n#define KEY_UNMUTE\t\t\t0x274\n#define KEY_FASTREVERSE\t\t\t0x275\n#define KEY_SLOWREVERSE\t\t\t0x276\n/*\n * Control a data application associated with the currently viewed channel,\n * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)\n */\n#define KEY_DATA\t\t\t0x277\n#define KEY_ONSCREEN_KEYBOARD\t\t0x278\n\n#define BTN_TRIGGER_HAPPY\t\t0x2c0\n#define BTN_TRIGGER_HAPPY1\t\t0x2c0\n#define BTN_TRIGGER_HAPPY2\t\t0x2c1\n#define BTN_TRIGGER_HAPPY3\t\t0x2c2\n#define BTN_TRIGGER_HAPPY4\t\t0x2c3\n#define BTN_TRIGGER_HAPPY5\t\t0x2c4\n#define BTN_TRIGGER_HAPPY6\t\t0x2c5\n#define BTN_TRIGGER_HAPPY7\t\t0x2c6\n#define BTN_TRIGGER_HAPPY8\t\t0x2c7\n#define BTN_TRIGGER_HAPPY9\t\t0x2c8\n#define BTN_TRIGGER_HAPPY10\t\t0x2c9\n#define BTN_TRIGGER_HAPPY11\t\t0x2ca\n#define BTN_TRIGGER_HAPPY12\t\t0x2cb\n#define BTN_TRIGGER_HAPPY13\t\t0x2cc\n#define BTN_TRIGGER_HAPPY14\t\t0x2cd\n#define BTN_TRIGGER_HAPPY15\t\t0x2ce\n#define BTN_TRIGGER_HAPPY16\t\t0x2cf\n#define BTN_TRIGGER_HAPPY17\t\t0x2d0\n#define BTN_TRIGGER_HAPPY18\t\t0x2d1\n#define BTN_TRIGGER_HAPPY19\t\t0x2d2\n#define BTN_TRIGGER_HAPPY20\t\t0x2d3\n#define BTN_TRIGGER_HAPPY21\t\t0x2d4\n#define BTN_TRIGGER_HAPPY22\t\t0x2d5\n#define BTN_TRIGGER_HAPPY23\t\t0x2d6\n#define BTN_TRIGGER_HAPPY24\t\t0x2d7\n#define BTN_TRIGGER_HAPPY25\t\t0x2d8\n#define BTN_TRIGGER_HAPPY26\t\t0x2d9\n#define BTN_TRIGGER_HAPPY27\t\t0x2da\n#define BTN_TRIGGER_HAPPY28\t\t0x2db\n#define BTN_TRIGGER_HAPPY29\t\t0x2dc\n#define BTN_TRIGGER_HAPPY30\t\t0x2dd\n#define BTN_TRIGGER_HAPPY31\t\t0x2de\n#define BTN_TRIGGER_HAPPY32\t\t0x2df\n#define BTN_TRIGGER_HAPPY33\t\t0x2e0\n#define BTN_TRIGGER_HAPPY34\t\t0x2e1\n#define BTN_TRIGGER_HAPPY35\t\t0x2e2\n#define BTN_TRIGGER_HAPPY36\t\t0x2e3\n#define BTN_TRIGGER_HAPPY37\t\t0x2e4\n#define BTN_TRIGGER_HAPPY38\t\t0x2e5\n#define BTN_TRIGGER_HAPPY39\t\t0x2e6\n#define BTN_TRIGGER_HAPPY40\t\t0x2e7\n\n/* We avoid low common keys in module aliases so they don't get huge. */\n#define KEY_MIN_INTERESTING\tKEY_MUTE\n#define KEY_MAX\t\t\t0x2ff\n#define KEY_CNT\t\t\t(KEY_MAX+1)\n\n/*\n * Relative axes\n */\n\n#define REL_X\t\t\t0x00\n#define REL_Y\t\t\t0x01\n#define REL_Z\t\t\t0x02\n#define REL_RX\t\t\t0x03\n#define REL_RY\t\t\t0x04\n#define REL_RZ\t\t\t0x05\n#define REL_HWHEEL\t\t0x06\n#define REL_DIAL\t\t0x07\n#define REL_WHEEL\t\t0x08\n#define REL_MISC\t\t0x09\n#define REL_MAX\t\t\t0x0f\n#define REL_CNT\t\t\t(REL_MAX+1)\n\n/*\n * Absolute axes\n */\n\n#define ABS_X\t\t\t0x00\n#define ABS_Y\t\t\t0x01\n#define ABS_Z\t\t\t0x02\n#define ABS_RX\t\t\t0x03\n#define ABS_RY\t\t\t0x04\n#define ABS_RZ\t\t\t0x05\n#define ABS_THROTTLE\t\t0x06\n#define ABS_RUDDER\t\t0x07\n#define ABS_WHEEL\t\t0x08\n#define ABS_GAS\t\t\t0x09\n#define ABS_BRAKE\t\t0x0a\n#define ABS_HAT0X\t\t0x10\n#define ABS_HAT0Y\t\t0x11\n#define ABS_HAT1X\t\t0x12\n#define ABS_HAT1Y\t\t0x13\n#define ABS_HAT2X\t\t0x14\n#define ABS_HAT2Y\t\t0x15\n#define ABS_HAT3X\t\t0x16\n#define ABS_HAT3Y\t\t0x17\n#define ABS_PRESSURE\t\t0x18\n#define ABS_DISTANCE\t\t0x19\n#define ABS_TILT_X\t\t0x1a\n#define ABS_TILT_Y\t\t0x1b\n#define ABS_TOOL_WIDTH\t\t0x1c\n\n#define ABS_VOLUME\t\t0x20\n\n#define ABS_MISC\t\t0x28\n\n#define ABS_MT_SLOT\t\t0x2f\t/* MT slot being modified */\n#define ABS_MT_TOUCH_MAJOR\t0x30\t/* Major axis of touching ellipse */\n#define ABS_MT_TOUCH_MINOR\t0x31\t/* Minor axis (omit if circular) */\n#define ABS_MT_WIDTH_MAJOR\t0x32\t/* Major axis of approaching ellipse */\n#define ABS_MT_WIDTH_MINOR\t0x33\t/* Minor axis (omit if circular) */\n#define ABS_MT_ORIENTATION\t0x34\t/* Ellipse orientation */\n#define ABS_MT_POSITION_X\t0x35\t/* Center X touch position */\n#define ABS_MT_POSITION_Y\t0x36\t/* Center Y touch position */\n#define ABS_MT_TOOL_TYPE\t0x37\t/* Type of touching device */\n#define ABS_MT_BLOB_ID\t\t0x38\t/* Group a set of packets as a blob */\n#define ABS_MT_TRACKING_ID\t0x39\t/* Unique ID of initiated contact */\n#define ABS_MT_PRESSURE\t\t0x3a\t/* Pressure on contact area */\n#define ABS_MT_DISTANCE\t\t0x3b\t/* Contact hover distance */\n#define ABS_MT_TOOL_X\t\t0x3c\t/* Center X tool position */\n#define ABS_MT_TOOL_Y\t\t0x3d\t/* Center Y tool position */\n\n\n#define ABS_MAX\t\t\t0x3f\n#define ABS_CNT\t\t\t(ABS_MAX+1)\n\n/*\n * Switch events\n */\n\n#define SW_LID\t\t\t0x00 /* set = lid shut */\n#define SW_TABLET_MODE\t\t0x01 /* set = tablet mode */\n#define SW_HEADPHONE_INSERT\t0x02 /* set = inserted */\n#define SW_RFKILL_ALL\t\t0x03 /* rfkill master switch, type \"any\"\n\t\t\t\t\t set = radio enabled */\n#define SW_RADIO\t\tSW_RFKILL_ALL\t/* deprecated */\n#define SW_MICROPHONE_INSERT\t0x04 /* set = inserted */\n#define SW_DOCK\t\t\t0x05 /* set = plugged into dock */\n#define SW_LINEOUT_INSERT\t0x06 /* set = inserted */\n#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */\n#define SW_VIDEOOUT_INSERT\t0x08 /* set = inserted */\n#define SW_CAMERA_LENS_COVER\t0x09 /* set = lens covered */\n#define SW_KEYPAD_SLIDE\t\t0x0a /* set = keypad slide out */\n#define SW_FRONT_PROXIMITY\t0x0b /* set = front proximity sensor active */\n#define SW_ROTATE_LOCK\t\t0x0c /* set = rotate locked/disabled */\n#define SW_LINEIN_INSERT\t0x0d /* set = inserted */\n#define SW_MUTE_DEVICE\t\t0x0e /* set = device disabled */\n#define SW_PEN_INSERTED\t\t0x0f /* set = pen inserted */\n#define SW_MAX\t\t\t0x0f\n#define SW_CNT\t\t\t(SW_MAX+1)\n\n/*\n * Misc events\n */\n\n#define MSC_SERIAL\t\t0x00\n#define MSC_PULSELED\t\t0x01\n#define MSC_GESTURE\t\t0x02\n#define MSC_RAW\t\t\t0x03\n#define MSC_SCAN\t\t0x04\n#define MSC_TIMESTAMP\t\t0x05\n#define MSC_MAX\t\t\t0x07\n#define MSC_CNT\t\t\t(MSC_MAX+1)\n\n/*\n * LEDs\n */\n\n#define LED_NUML\t\t0x00\n#define LED_CAPSL\t\t0x01\n#define LED_SCROLLL\t\t0x02\n#define LED_COMPOSE\t\t0x03\n#define LED_KANA\t\t0x04\n#define LED_SLEEP\t\t0x05\n#define LED_SUSPEND\t\t0x06\n#define LED_MUTE\t\t0x07\n#define LED_MISC\t\t0x08\n#define LED_MAIL\t\t0x09\n#define LED_CHARGING\t\t0x0a\n#define LED_MAX\t\t\t0x0f\n#define LED_CNT\t\t\t(LED_MAX+1)\n\n/*\n * Autorepeat values\n */\n\n#define REP_DELAY\t\t0x00\n#define REP_PERIOD\t\t0x01\n#define REP_MAX\t\t\t0x01\n#define REP_CNT\t\t\t(REP_MAX+1)\n\n/*\n * Sounds\n */\n\n#define SND_CLICK\t\t0x00\n#define SND_BELL\t\t0x01\n#define SND_TONE\t\t0x02\n#define SND_MAX\t\t\t0x07\n#define SND_CNT\t\t\t(SND_MAX+1)\n\n#define MATRIX_KEY(row, col, code)\t\\\n\t((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))\n\n#endif /* _DT_BINDINGS_INPUT_INPUT_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/interrupt-controller/irq.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most IRQ bindings.\n *\n * Most IRQ bindings include a flags cell as part of the IRQ specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n\n#define IRQ_TYPE_NONE\t\t0\n#define IRQ_TYPE_EDGE_RISING\t1\n#define IRQ_TYPE_EDGE_FALLING\t2\n#define IRQ_TYPE_EDGE_BOTH\t(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)\n#define IRQ_TYPE_LEVEL_HIGH\t4\n#define IRQ_TYPE_LEVEL_LOW\t8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/phy/phy.h", "content": "/*\n *\n * This header provides constants for the phy framework\n *\n * Copyright (C) 2014 STMicroelectronics\n * Author: Gabriel Fernandez \n * License terms: GNU General Public License (GPL), version 2\n */\n\n#ifndef _DT_BINDINGS_PHY\n#define _DT_BINDINGS_PHY\n\n#define PHY_NONE\t\t0\n#define PHY_TYPE_SATA\t\t1\n#define PHY_TYPE_PCIE\t\t2\n#define PHY_TYPE_USB2\t\t3\n#define PHY_TYPE_USB3\t\t4\n#define PHY_TYPE_UFS\t\t5\n#define PHY_TYPE_DP\t\t6\n#define PHY_TYPE_SGMII\t\t7\n\n#endif /* _DT_BINDINGS_PHY */\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h", "content": "/*\n * MIO pin configuration defines for Xilinx ZynqMP\n *\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Author: Chirag Parekh \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * version 2 as published by the Free Software Foundation.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program. If not, see .\n */\n\n#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H\n#define _DT_BINDINGS_PINCTRL_ZYNQMP_H\n\n/* Bit value for IO standards */\n#define IO_STANDARD_LVCMOS33 0\n#define IO_STANDARD_LVCMOS18 1\n\n/* Bit values for Slew Rates */\n#define SLEW_RATE_FAST 0\n#define SLEW_RATE_SLOW 1\n\n/* Bit values for Pin inputs */\n#define PIN_INPUT_TYPE_CMOS 0\n#define PIN_INPUT_TYPE_SCHMITT 1\n\n/* Bit values for drive control*/\n#define DRIVE_STRENGTH_2MA 2\n#define DRIVE_STRENGTH_4MA 4\n#define DRIVE_STRENGTH_8MA 8\n#define DRIVE_STRENGTH_12MA 12\n\n#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/power/xlnx-versal-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_POWER_H\n#define _DT_BINDINGS_VERSAL_POWER_H\n\n#define PM_DEV_USB_0\t\t\t\t(0x18224018U)\n#define PM_DEV_GEM_0\t\t\t\t(0x18224019U)\n#define PM_DEV_GEM_1\t\t\t\t(0x1822401aU)\n#define PM_DEV_SPI_0\t\t\t\t(0x1822401bU)\n#define PM_DEV_SPI_1\t\t\t\t(0x1822401cU)\n#define PM_DEV_I2C_0\t\t\t\t(0x1822401dU)\n#define PM_DEV_I2C_1\t\t\t\t(0x1822401eU)\n#define PM_DEV_CAN_FD_0\t\t\t\t(0x1822401fU)\n#define PM_DEV_CAN_FD_1\t\t\t\t(0x18224020U)\n#define PM_DEV_UART_0\t\t\t\t(0x18224021U)\n#define PM_DEV_UART_1\t\t\t\t(0x18224022U)\n#define PM_DEV_GPIO\t\t\t\t(0x18224023U)\n#define PM_DEV_TTC_0\t\t\t\t(0x18224024U)\n#define PM_DEV_TTC_1\t\t\t\t(0x18224025U)\n#define PM_DEV_TTC_2\t\t\t\t(0x18224026U)\n#define PM_DEV_TTC_3\t\t\t\t(0x18224027U)\n#define PM_DEV_SWDT_FPD\t\t\t\t(0x18224029U)\n#define PM_DEV_OSPI\t\t\t\t(0x1822402aU)\n#define PM_DEV_QSPI\t\t\t\t(0x1822402bU)\n#define PM_DEV_GPIO_PMC\t\t\t\t(0x1822402cU)\n#define PM_DEV_SDIO_0\t\t\t\t(0x1822402eU)\n#define PM_DEV_SDIO_1\t\t\t\t(0x1822402fU)\n#define PM_DEV_RTC\t\t\t\t(0x18224034U)\n#define PM_DEV_ADMA_0\t\t\t\t(0x18224035U)\n#define PM_DEV_ADMA_1\t\t\t\t(0x18224036U)\n#define PM_DEV_ADMA_2\t\t\t\t(0x18224037U)\n#define PM_DEV_ADMA_3\t\t\t\t(0x18224038U)\n#define PM_DEV_ADMA_4\t\t\t\t(0x18224039U)\n#define PM_DEV_ADMA_5\t\t\t\t(0x1822403aU)\n#define PM_DEV_ADMA_6\t\t\t\t(0x1822403bU)\n#define PM_DEV_ADMA_7\t\t\t\t(0x1822403cU)\n#define PM_DEV_AI\t\t\t\t(0x18224072U)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/power/xlnx-zynqmp-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_POWER_H\n#define _DT_BINDINGS_ZYNQMP_POWER_H\n\n#define\t\tPD_USB_0\t22\n#define\t\tPD_USB_1\t23\n#define\t\tPD_TTC_0\t24\n#define\t\tPD_TTC_1\t25\n#define\t\tPD_TTC_2\t26\n#define\t\tPD_TTC_3\t27\n#define\t\tPD_SATA\t\t28\n#define\t\tPD_ETH_0\t29\n#define\t\tPD_ETH_1\t30\n#define\t\tPD_ETH_2\t31\n#define\t\tPD_ETH_3\t32\n#define\t\tPD_UART_0\t33\n#define\t\tPD_UART_1\t34\n#define\t\tPD_SPI_0\t35\n#define\t\tPD_SPI_1\t36\n#define\t\tPD_I2C_0\t37\n#define\t\tPD_I2C_1\t38\n#define\t\tPD_SD_0\t\t39\n#define\t\tPD_SD_1\t\t40\n#define\t\tPD_DP\t\t41\n#define\t\tPD_GDMA\t\t42\n#define\t\tPD_ADMA\t\t43\n#define\t\tPD_NAND\t\t44\n#define\t\tPD_QSPI\t\t45\n#define\t\tPD_GPIO\t\t46\n#define\t\tPD_CAN_0\t47\n#define\t\tPD_CAN_1\t48\n#define\t\tPD_GPU\t\t58\n#define\t\tPD_PCIE\t\t59\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H\n#define _DT_BINDINGS_ZYNQMP_RESETS_H\n\n#define\t\tZYNQMP_RESET_PCIE_CFG\t\t0\n#define\t\tZYNQMP_RESET_PCIE_BRIDGE\t1\n#define\t\tZYNQMP_RESET_PCIE_CTRL\t\t2\n#define\t\tZYNQMP_RESET_DP\t\t\t3\n#define\t\tZYNQMP_RESET_SWDT_CRF\t\t4\n#define\t\tZYNQMP_RESET_AFI_FM5\t\t5\n#define\t\tZYNQMP_RESET_AFI_FM4\t\t6\n#define\t\tZYNQMP_RESET_AFI_FM3\t\t7\n#define\t\tZYNQMP_RESET_AFI_FM2\t\t8\n#define\t\tZYNQMP_RESET_AFI_FM1\t\t9\n#define\t\tZYNQMP_RESET_AFI_FM0\t\t10\n#define\t\tZYNQMP_RESET_GDMA\t\t11\n#define\t\tZYNQMP_RESET_GPU_PP1\t\t12\n#define\t\tZYNQMP_RESET_GPU_PP0\t\t13\n#define\t\tZYNQMP_RESET_GPU\t\t14\n#define\t\tZYNQMP_RESET_GT\t\t\t15\n#define\t\tZYNQMP_RESET_SATA\t\t16\n#define\t\tZYNQMP_RESET_ACPU3_PWRON\t17\n#define\t\tZYNQMP_RESET_ACPU2_PWRON\t18\n#define\t\tZYNQMP_RESET_ACPU1_PWRON\t19\n#define\t\tZYNQMP_RESET_ACPU0_PWRON\t20\n#define\t\tZYNQMP_RESET_APU_L2\t\t21\n#define\t\tZYNQMP_RESET_ACPU3\t\t22\n#define\t\tZYNQMP_RESET_ACPU2\t\t23\n#define\t\tZYNQMP_RESET_ACPU1\t\t24\n#define\t\tZYNQMP_RESET_ACPU0\t\t25\n#define\t\tZYNQMP_RESET_DDR\t\t26\n#define\t\tZYNQMP_RESET_APM_FPD\t\t27\n#define\t\tZYNQMP_RESET_SOFT\t\t28\n#define\t\tZYNQMP_RESET_GEM0\t\t29\n#define\t\tZYNQMP_RESET_GEM1\t\t30\n#define\t\tZYNQMP_RESET_GEM2\t\t31\n#define\t\tZYNQMP_RESET_GEM3\t\t32\n#define\t\tZYNQMP_RESET_QSPI\t\t33\n#define\t\tZYNQMP_RESET_UART0\t\t34\n#define\t\tZYNQMP_RESET_UART1\t\t35\n#define\t\tZYNQMP_RESET_SPI0\t\t36\n#define\t\tZYNQMP_RESET_SPI1\t\t37\n#define\t\tZYNQMP_RESET_SDIO0\t\t38\n#define\t\tZYNQMP_RESET_SDIO1\t\t39\n#define\t\tZYNQMP_RESET_CAN0\t\t40\n#define\t\tZYNQMP_RESET_CAN1\t\t41\n#define\t\tZYNQMP_RESET_I2C0\t\t42\n#define\t\tZYNQMP_RESET_I2C1\t\t43\n#define\t\tZYNQMP_RESET_TTC0\t\t44\n#define\t\tZYNQMP_RESET_TTC1\t\t45\n#define\t\tZYNQMP_RESET_TTC2\t\t46\n#define\t\tZYNQMP_RESET_TTC3\t\t47\n#define\t\tZYNQMP_RESET_SWDT_CRL\t\t48\n#define\t\tZYNQMP_RESET_NAND\t\t49\n#define\t\tZYNQMP_RESET_ADMA\t\t50\n#define\t\tZYNQMP_RESET_GPIO\t\t51\n#define\t\tZYNQMP_RESET_IOU_CC\t\t52\n#define\t\tZYNQMP_RESET_TIMESTAMP\t\t53\n#define\t\tZYNQMP_RESET_RPU_R50\t\t54\n#define\t\tZYNQMP_RESET_RPU_R51\t\t55\n#define\t\tZYNQMP_RESET_RPU_AMBA\t\t56\n#define\t\tZYNQMP_RESET_OCM\t\t57\n#define\t\tZYNQMP_RESET_RPU_PGE\t\t58\n#define\t\tZYNQMP_RESET_USB0_CORERESET\t59\n#define\t\tZYNQMP_RESET_USB1_CORERESET\t60\n#define\t\tZYNQMP_RESET_USB0_HIBERRESET\t61\n#define\t\tZYNQMP_RESET_USB1_HIBERRESET\t62\n#define\t\tZYNQMP_RESET_USB0_APB\t\t63\n#define\t\tZYNQMP_RESET_USB1_APB\t\t64\n#define\t\tZYNQMP_RESET_IPI\t\t65\n#define\t\tZYNQMP_RESET_APM_LPD\t\t66\n#define\t\tZYNQMP_RESET_RTC\t\t67\n#define\t\tZYNQMP_RESET_SYSMON\t\t68\n#define\t\tZYNQMP_RESET_AFI_FM6\t\t69\n#define\t\tZYNQMP_RESET_LPD_SWDT\t\t70\n#define\t\tZYNQMP_RESET_FPD\t\t71\n#define\t\tZYNQMP_RESET_RPU_DBG1\t\t72\n#define\t\tZYNQMP_RESET_RPU_DBG0\t\t73\n#define\t\tZYNQMP_RESET_DBG_LPD\t\t74\n#define\t\tZYNQMP_RESET_DBG_FPD\t\t75\n#define\t\tZYNQMP_RESET_APLL\t\t76\n#define\t\tZYNQMP_RESET_DPLL\t\t77\n#define\t\tZYNQMP_RESET_VPLL\t\t78\n#define\t\tZYNQMP_RESET_IOPLL\t\t79\n#define\t\tZYNQMP_RESET_RPLL\t\t80\n#define\t\tZYNQMP_RESET_GPO3_PL_0\t\t81\n#define\t\tZYNQMP_RESET_GPO3_PL_1\t\t82\n#define\t\tZYNQMP_RESET_GPO3_PL_2\t\t83\n#define\t\tZYNQMP_RESET_GPO3_PL_3\t\t84\n#define\t\tZYNQMP_RESET_GPO3_PL_4\t\t85\n#define\t\tZYNQMP_RESET_GPO3_PL_5\t\t86\n#define\t\tZYNQMP_RESET_GPO3_PL_6\t\t87\n#define\t\tZYNQMP_RESET_GPO3_PL_7\t\t88\n#define\t\tZYNQMP_RESET_GPO3_PL_8\t\t89\n#define\t\tZYNQMP_RESET_GPO3_PL_9\t\t90\n#define\t\tZYNQMP_RESET_GPO3_PL_10\t\t91\n#define\t\tZYNQMP_RESET_GPO3_PL_11\t\t92\n#define\t\tZYNQMP_RESET_GPO3_PL_12\t\t93\n#define\t\tZYNQMP_RESET_GPO3_PL_13\t\t94\n#define\t\tZYNQMP_RESET_GPO3_PL_14\t\t95\n#define\t\tZYNQMP_RESET_GPO3_PL_15\t\t96\n#define\t\tZYNQMP_RESET_GPO3_PL_16\t\t97\n#define\t\tZYNQMP_RESET_GPO3_PL_17\t\t98\n#define\t\tZYNQMP_RESET_GPO3_PL_18\t\t99\n#define\t\tZYNQMP_RESET_GPO3_PL_19\t\t100\n#define\t\tZYNQMP_RESET_GPO3_PL_20\t\t101\n#define\t\tZYNQMP_RESET_GPO3_PL_21\t\t102\n#define\t\tZYNQMP_RESET_GPO3_PL_22\t\t103\n#define\t\tZYNQMP_RESET_GPO3_PL_23\t\t104\n#define\t\tZYNQMP_RESET_GPO3_PL_24\t\t105\n#define\t\tZYNQMP_RESET_GPO3_PL_25\t\t106\n#define\t\tZYNQMP_RESET_GPO3_PL_26\t\t107\n#define\t\tZYNQMP_RESET_GPO3_PL_27\t\t108\n#define\t\tZYNQMP_RESET_GPO3_PL_28\t\t109\n#define\t\tZYNQMP_RESET_GPO3_PL_29\t\t110\n#define\t\tZYNQMP_RESET_GPO3_PL_30\t\t111\n#define\t\tZYNQMP_RESET_GPO3_PL_31\t\t112\n#define\t\tZYNQMP_RESET_RPU_LS\t\t113\n#define\t\tZYNQMP_RESET_PS_ONLY\t\t114\n#define\t\tZYNQMP_RESET_PL\t\t\t115\n#define\t\tZYNQMP_RESET_PS_PL0\t\t116\n#define\t\tZYNQMP_RESET_PS_PL1\t\t117\n#define\t\tZYNQMP_RESET_PS_PL2\t\t118\n#define\t\tZYNQMP_RESET_PS_PL3\t\t119\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/versal/versal-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-versal-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-power.h\"\n/ {\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tcan0_clk: can0_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN0_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tcan1_clk: can1_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN1_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk ACPU>;\n};\n\n&can0 {\n\tclocks = <&can0_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_0>;\n};\n\n&can1 {\n\tclocks = <&can1_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_1>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_0>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_1>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk PMC_LSBUS_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO_PMC>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk I2C0_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_0>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk I2C1_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_1>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_0>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_1>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_2>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_3>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_4>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_5>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_6>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_7>;\n};\n\n&qspi {\n\tclocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_QSPI>;\n};\n\n&ospi {\n\tclocks = <&versal_clk OSPI_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_OSPI>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware PM_DEV_RTC>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_0>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_1>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_0>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_1>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_0>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_1>;\n};\n\n&ttc0 {\n\tclocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_0>;\n};\n\n&ttc1 {\n\tclocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_1>;\n};\n\n&ttc2 {\n\tclocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_2>;\n};\n\n&ttc3 {\n\tclocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_3>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_USB_0>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SWDT_FPD>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/versal/versal-spp-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\talt_ref_clk: alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware-wip\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"alt_ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk 77>;\n};\n\n&can0 {\n\tclocks = <&versal_clk 96>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401f>;\n};\n\n&can1 {\n\tclocks = <&versal_clk 97>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224020>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x18224019>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x1822401a>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk 61>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk 98>;\n\tpower-domains = <&versal_firmware 0x1822401d>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk 99>;\n\tpower-domains = <&versal_firmware 0x1822401e>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224035>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224036>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224037>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224038>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224039>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403a>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403b>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403c>;\n};\n\n&qspi {\n\tclocks = <&versal_clk 57>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402b>;\n};\n\n&ospi {\n\tclocks = <&versal_clk 58>, <&versal_clk 82>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware 0x18224034>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk 92>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224021>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk 93>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224022>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk 59>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402e>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk 60>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402f>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk 94>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401b>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk 95>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401c>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk 91>, <&versal_clk 104>;\n\tpower-domains = <&versal_firmware 0x18224018>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk 82>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/versal/versal.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal\";\n\n\tcpus: cpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <1>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tfpga: fpga {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&versal_fpga>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tpsci: psci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t};\n\n\tversal_fpga: versal_fpga {\n\t\tcompatible = \"xlnx,versal-fpga\";\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t\tinterrupt-parent = <&gic>;\n\t\tu-boot,dm-pre-reloc;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\t\t\treg = <0 0xf9000000 0 0x80000>, /* GICD */\n\t\t\t <0 0xf9080000 0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\n\t\t\tgic_its: gic-its@f9020000 {\n\t\t\t\tcompatible = \"arm,gic-v3-its\";\n\t\t\t\tmsi-controller;\n\t\t\t\tmsi-cells = <1>;\n\t\t\t\treg = <0 0xf9020000 0 0x20000>;\n\t\t\t};\n\t\t};\n\n\t\tapm: performance-monitor@f0920000 {\n\t\t\tcompatible = \"xlnx,flexnoc-pm-2.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg-names = \"funnel\", \"baselpd\", \"basefpd\";\n\t\t\treg = <0x0 0xf0920000 0x0 0x1000>,\n\t\t\t <0x0 0xf0980000 0x0 0x9000>,\n\t\t\t <0x0 0xf0b80000 0x0 0x9000>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff060000 0 0x6000>;\n\t\t\tinterrupts = <0 20 1>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff070000 0 0x6000>;\n\t\t\tinterrupts = <0 21 1>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcci: cci@fd000000 {\n\t\t\tcompatible = \"arm,cci-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd000000 0 0x10000>;\n\t\t\tranges = <0 0 0xfd000000 0xa0000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcci_pmu: pmu@10000 {\n\t\t\t\tcompatible = \"arm,cci-500-pmu,r0\";\n\t\t\t\treg = <0x10000 0x90000>;\n\t\t\t\tinterrupts = <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>;\n\t\t\t};\n\t\t};\n\n\t\tlpd_dma_chan0: dma@ffa80000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa80000 0 0x1000>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa90000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa90000 0 0x1000>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffaa0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaa0000 0 0x1000>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\n\t\tlpd_dma_chan3: dma@ffab0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffab0000 0 0x1000>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffac0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffac0000 0 0x1000>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffad0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffad0000 0 0x1000>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffae0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffae0000 0 0x1000>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffaf0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaf0000 0 0x1000>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tgem0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,versal-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0c0000 0 0x1000>;\n\t\t\tinterrupts = <0 56 4>, <0 56 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,versal-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0d0000 0 0x1000>;\n\t\t\tinterrupts = <0 58 4>, <0 58 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tgpio0: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0b0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff020000 0 0x1000>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff030000 0 0x1000>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tmc0: memory-controller@f6150000\t{\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <0>;\n\t\t};\n\n\t\tmc1: memory-controller@f62c0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <1>;\n\t\t};\n\n\t\tmc2: memory-controller@f6430000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <2>;\n\t\t};\n\n\t\tmc3: memory-controller@f65a0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <3>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tcalibration = <0x7FFF>;\n\t\t};\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff000000 0 0x1000>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tserial1: serial@ff010000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff010000 0 0x1000>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd800000 0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 124 4>, <0 124 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,is-stig-pgm = <1>;\n\t\t\tcdns,trigger-address = <0xC0000000>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff040000 0 0x1000>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff050000 0 0x1000>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsysmon: sysmon@f1270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\treg = <0x0 0xf1270000 0x0 0x4000>;\n\t\t\tinterrupts = <0 144 4>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tttc0: timer@ff0e0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff0f0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 40 4>, <0 41 4>, <0 42 4>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff100000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 46 4>, <0 47 4>, <0 48 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tusb0: usb@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff9d0000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0 0xfe200000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"usb-wakeup\";\n\t\t\t\tinterrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,mask_phy_reset;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\tcpm_pciea: pci@fca10000 {\n\t\t\t#address-cells = <3>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"xlnx,versal-cpm-host-1.00\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc_0 1>,\n\t\t\t\t\t<0 0 0 2 &pcie_intc_0 2>,\n\t\t\t\t\t<0 0 0 3 &pcie_intc_0 3>,\n\t\t\t\t\t<0 0 0 4 &pcie_intc_0 4>;\n\t\t\tinterrupt-map-mask = <0 0 0 7>;\n\t\t\tinterrupt-names = \"misc\";\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>,\n\t\t\t\t <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>;\n\t\t\tmsi-map = <0x0 &gic_its 0x0 0x10000>;\n\t\t\treg = <0x0 0xfca10000 0x0 0x1000>,\n\t\t\t <0x6 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"cpm_slcr\", \"cfg\";\n\t\t\tpcie_intc_0: pci-interrupt-controller {\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\tinterrupt-controller ;\n\t\t\t};\n\t\t};\n\n\t\twatchdog: watchdog@fd4d0000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd4d0000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 0x64 1>, <0 0x6D 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t};\n\t};\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/zynq/zynq-7000.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\treplicator {\n\t\tcompatible = \"arm,coresight-static-replicator\";\n\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\tout-ports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\t/* replicator output ports */\n\t\t\tport@0 {\n\t\t\t\treg = <0>;\n\t\t\t\treplicator_out_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&tpiu_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tport@1 {\n\t\t\t\treg = <1>;\n\t\t\t\treplicator_out_port1: endpoint {\n\t\t\t\t\tremote-endpoint = <&etb_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tin-ports {\n\t\t\t/* replicator input port */\n\t\t\tport {\n\t\t\t\treplicator_in_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&funnel_out_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tamba: axi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"apb_pclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\", \"arm,primecell\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: mmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: mmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\tetb@f8801000 {\n\t\t\tcompatible = \"arm,coresight-etb10\", \"arm,primecell\";\n\t\t\treg = <0xf8801000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\tetb_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ttpiu@f8803000 {\n\t\t\tcompatible = \"arm,coresight-tpiu\", \"arm,primecell\";\n\t\t\treg = <0xf8803000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\ttpiu_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tfunnel@f8804000 {\n\t\t\tcompatible = \"arm,coresight-static-funnel\", \"arm,primecell\";\n\t\t\treg = <0xf8804000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\t\t/* funnel output ports */\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tfunnel_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint =\n\t\t\t\t\t\t\t<&replicator_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tin-ports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\t/* funnel input ports */\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tfunnel0_in_port0: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm0_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tfunnel0_in_port1: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm1_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tfunnel0_in_port2: endpoint {\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t/* The other input ports are not connect to anything */\n\t\t\t};\n\t\t};\n\n\t\tptm@f889c000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889c000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu0>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm0_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889d000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889d000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu1>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm1_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/zynqmp/zynqmp-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-zynqmp-clk.h\"\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL0_REF>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL1_REF>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL2_REF>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL3_REF>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tdp_aclk: dp_aclk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&zynqmp_firmware {\n\tzynqmp_clk: clock-controller {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,\n\t\t\t <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\",\n\t\t\t \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t};\n};\n\n&can0 {\n\tclocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&can1 {\n\tclocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&cpu0 {\n\tclocks = <&zynqmp_clk ACPU>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gpu {\n\tclocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&nand0 {\n\tclocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gem0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>,\n\t\t <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>,\n\t\t <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>,\n\t\t <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>,\n\t\t <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gpio {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&i2c0 {\n\tclocks = <&zynqmp_clk I2C0_REF>;\n};\n\n&i2c1 {\n\tclocks = <&zynqmp_clk I2C1_REF>;\n};\n\n&perf_monitor_ocm {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&perf_monitor_ddr {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_cci {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_lpd {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&pcie {\n\tclocks = <&zynqmp_clk PCIE_REF>;\n};\n\n&qspi {\n\tclocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&sata {\n\tclocks = <&zynqmp_clk SATA_REF>;\n};\n\n&sdhci0 {\n\tclocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&sdhci1 {\n\tclocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&spi0 {\n\tclocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&spi1 {\n\tclocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart0 {\n\tclocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart1 {\n\tclocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&usb0 {\n\tclocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&usb1 {\n\tclocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&watchdog0 {\n\tclocks = <&zynqmp_clk WDT>;\n};\n\n&lpd_watchdog {\n\tclocks = <&zynqmp_clk LPD_WDT>;\n};\n\n&xilinx_ams {\n\tclocks = <&zynqmp_clk AMS_REF>;\n};\n\n&zynqmp_dpdma {\n\tclocks = <&zynqmp_clk DPDMA_REF>;\n};\n\n&zynqmp_dpsub {\n\tclocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>;\n};\n\n&zynqmp_dp_snd_codec0 {\n\tclocks = <&zynqmp_clk DP_AUDIO_REF>;\n};\n\n&zynqmp_pcap {\n\tclocks = <&zynqmp_clk PCAP>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.1/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n#include \"include/dt-bindings/dma/xlnx-zynqmp-dpdma.h\"\n#include \"include/dt-bindings/power/xlnx-zynqmp-power.h\"\n#include \"include/dt-bindings/reset/xlnx-zynqmp-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu-opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tzynqmp_ipi: zynqmp_ipi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t\txlnx,ipi-id = <0>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff990400 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\treg = <0x0 0xff9905c0 0x0 0x20>,\n\t\t\t <0x0 0xff9905e0 0x0 0x20>,\n\t\t\t <0x0 0xff990e80 0x0 0x20>,\n\t\t\t <0x0 0xff990ea0 0x0 0x20>;\n\t\t\treg-names = \"local_request_region\",\n\t\t\t\t \"local_response_region\",\n\t\t\t\t \"remote_request_region\",\n\t\t\t\t \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <4>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tzynqmp_firmware: zynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x1>;\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tnvmem_firmware {\n\t\t\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tsoc_revision: soc_revision@0 {\n\t\t\t\t\treg = <0x0 0x4>;\n\t\t\t\t};\n\t\t\t\t/* efuse access */\n\t\t\t\tefuse_dna: efuse_dna@c {\n\t\t\t\t\treg = <0xc 0xc>;\n\t\t\t\t};\n\t\t\t\tefuse_usr0: efuse_usr0@20 {\n\t\t\t\t\treg = <0x20 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr1: efuse_usr1@24 {\n\t\t\t\t\treg = <0x24 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr2: efuse_usr2@28 {\n\t\t\t\t\treg = <0x28 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr3: efuse_usr3@2c {\n\t\t\t\t\treg = <0x2c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr4: efuse_usr4@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr5: efuse_usr5@34 {\n\t\t\t\t\treg = <0x34 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr6: efuse_usr6@38 {\n\t\t\t\t\treg = <0x38 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr7: efuse_usr7@3c {\n\t\t\t\t\treg = <0x3c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_miscusr: efuse_miscusr@40 {\n\t\t\t\t\treg = <0x40 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_chash: efuse_chash@50 {\n\t\t\t\t\treg = <0x50 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_pufmisc: efuse_pufmisc@54 {\n\t\t\t\t\treg = <0x54 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_sec: efuse_sec@58 {\n\t\t\t\t\treg = <0x58 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_spkid: efuse_spkid@5c {\n\t\t\t\t\treg = <0x5c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_ppk0hash: efuse_ppk0hash@a0 {\n\t\t\t\t\treg = <0xa0 0x30>;\n\t\t\t\t};\n\t\t\t\tefuse_ppk1hash: efuse_ppk1hash@d0 {\n\t\t\t\t\treg = <0xd0 0x30>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tzynqmp_pcap: pcap {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t\t\t\tclock-names = \"ref_clk\";\n\t\t\t};\n\n\t\t\txlnx_aes: zynqmp-aes {\n\t\t\t\tcompatible = \"xlnx,zynqmp-aes\";\n\t\t\t};\n\n\t\t\tzynqmp_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\txlnx_keccak_384: sha384 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-keccak-384\";\n\t\t\t};\n\n\t\t\txlnx_rsa: zynqmp-rsa {\n\t\t\t\tcompatible = \"xlnx,zynqmp-rsa\";\n\t\t\t};\n\n\t\t\tmodepin_gpio: gpio {\n\t\t\t\tcompatible = \"xlnx,zynqmp-gpio-modepin\";\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&zynqmp_pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t};\n\n\n\tsmmu: smmu@fd800000 {\n\t\tcompatible = \"arm,mmu-500\";\n\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t#iommu-cells = <1>;\n\t\tstatus = \"disabled\";\n\t\t#global-interrupts = <1>;\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x0 0x10000>,\n\t\t\t <0x0 0xf9020000 0x0 0x20000>,\n\t\t\t <0x0 0xf9040000 0x0 0x20000>,\n\t\t\t <0x0 0xf9060000 0x0 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\", \"gpu_pp0\", \"gpu_pp1\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPU>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand-controller@ff100000 {\n\t\t\tcompatible = \"xlnx,zynqmp-nand-controller\", \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"controller\", \"bus\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_NAND>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPIO>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tperf_monitor_ocm: perf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa00000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_ddr: perf-monitor@fd0b0000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd0b0000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <6>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <10>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_cci: perf-monitor@fd490000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd490000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_lpd: perf-monitor@ffa10000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa10000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x4d0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_PCIE>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_QSPI>;\n\t\t};\n\n\t\tpsgtr: phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\";\n\t\t\t#phy-cells = <4>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SATA>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SATA>;\n\t\t\t#stream-id-cells = <4>;\n\t\t/*\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;*/\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_0>;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_1>;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_1>;\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_0>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\t\t\treset-gpio = <&modepin_gpio 1 0>;\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>, <0 75 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t\t/* snps,enable-hibernation; */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb1@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_1>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\n\t\t\tranges;\n\t\t\tnvmem-cells = <&soc_revision>;\n\t\t\tnvmem-cell-names = \"soc_revision\";\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>, <0 76 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <60>;\n\t\t\treset-on-timeout;\n\t\t};\n\n\t\tlpd_watchdog: watchdog@ff150000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 52 1>;\n\t\t\treg = <0x0 0xff150000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges;\n\n\t\t\tams_ps: ams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50800 0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50c00 0x0 0x400>;\n\t\t\t};\n\t\t};\n\n\t\tzynqmp_dpdma: dma-controller@fd4c0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tdma-channels = <6>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0xce4>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tzynqmp_dpsub: display@fd4a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"dp\", \"blend\", \"av_buf\", \"aud\";\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0xce3>;\n\t\t\tclock-names = \"dp_apb_clk\", \"dp_aud_clk\", \"dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_DP>;\n\t\t\tdma-names = \"vid0\", \"vid1\", \"vid2\", \"gfx0\";\n\t\t\tdmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;\n\n\t\t\t/* dummy node to to indicate there's no child i2c device */\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&zynqmp_dpdma 4>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm\";\n\t\t\t\tdmas = <&zynqmp_dpdma 5>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card0: zynqmp_dp_snd_card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,\n\t\t\t\t\t\t <&zynqmp_dp_snd_pcm1>;\n\t\t\t\txlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n\n\tsi5335_0: si5335_0 { /* clk0_usb - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5335_1: si5335_1 { /* clk1_dp - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 IRQ_TYPE_LEVEL_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO3\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO2\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO1\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n};\n\n&psgtr {\n\t/* usb3, dp */\n\tclocks = <&si5335_0>, <&si5335_1>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"super-speed\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/kcu105-tmr.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&tmr_0_MB1_axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/sp701-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze sp701.\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@1 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x3>;\n\t\t\tti,tx-internal-delay = <0x3>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/vcu118-rev2.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze vcu118\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@3 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\tti,sgmii-ref-clock-output-enable;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\treg = <3>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-a2197-sc-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller RevA\";\n\tcompatible = \"xlnx,versal-sc-revA\", \"xlnx,versal-sc\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = &eeprom; \n\t};\n\n\t/* SC Bank 43\n\tFIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS\n\tSYSCTLR_GPIO0 - 5 - conneced to versal */\n\t/* cpu thermal for MAX6643 fan control */\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tdc38_led {\n\t\t\tlabel = \"ds38-green\"; /* sc AB11 500_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc37_led {\n\t\t\tlabel = \"ds37-green\"; /* sc AD10 501_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc36_led {\n\t\t\tlabel = \"ds36-green\"; /* sc AD11 502_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t};\n};\n\n/* usb - type C - pl\n and micro usb 2.0, gt\n*/\n/* Feb 28/2019 version */\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n/* TODO\nUSB0 MIO52-63\nUSB1 MIO64-75\n*/\n\n/*eth MDIO 76/77\neth reset MIO42\nmarwell m88e1512 - SGMII */\n&gem0 {\n\tphy-handle = <&phy0>;\n\t/* phy-mode = \"sgmii\"; DTG generates this properly */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: phy@21 {\n\t\treg = <21>; /* FIXME */\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5- 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 0 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\"; /* FIXME no linux driver */\n\t\t\t\treg = <0xc0>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <10000000>; /* 10 ohm */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\ti2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* FIXME connection to Samtec J212D */\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t/* FIXME connection to Samtec J53C */\n\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@5d { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@5d { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@5d { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"LPDDR4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-emu-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-emu-itr8\", \"xlnx,versal-emu\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal EMU ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:9600\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n\n\tclk0212: clk0212 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <212000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n};\n\n&timer {\n clock-frequency = <440000>;\n};\n\n&serial0 {\n status = \"okay\";\n clocks = <&clk0212 &clk0212>;\n\tcurrent-speed = <9600>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-spp-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-spp-itr8-cn13940875\", \"xlnx,versal-spp-itr8\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal SPP ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &ospi;\n\t\tspi2 = &spi0;\n\t\tspi3 = &spi1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tusb0 = &usb0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>;\n\t};\n\tchosen {\n\t\tbootargs = \"rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n};\n\n&timer {\n\tclock-frequency = <2720000>;\n};\n\n&serial0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tmaximum-speed = \"high-speed\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n phy0: phy@0 {\n\t\treg = <0x0>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n phy1: phy@1 {\n\t\treg = <0x1>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <0x1>;\n\treg = <0x0 0xf1030000 0x0 0x1000>;\n\tclocks = <&clk125 &clk125>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot-boot.bin\";\n\t\t\t\treg = <0x0 0x6400000>;\n\t\t\t};\n\t\t\tpartition@6400000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x6400000 0x500000>;\n\t\t\t};\n\t\t\tpartition@6900000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x6900000 0x20000>;\n\t\t\t};\n\t\t\tpartition@6920000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x6920000 0x5E0000>;\n\t\t\t};\n\t\t\tpartition@7f40000 {\n\t\t\t\tlabel = \"qspi-bootenv\";\n\t\t\t\treg = <0x7f40000 0x40000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ospi {\n\tstatus = \"disabled\";\n\tclocks = <&clk125 &clk125>;\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\tcdns,fifo-depth = <508>;\n\tcdns,fifo-width = <4>;\n\tcdns,is-dma = <1>;\n\tcdns,is-stig-pgm = <1>;\n\tcdns,trigger-address = <0x00000000>;\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t};\n\t\t\tpartition@600000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t};\n\t\t\tpartition@620000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <1>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <3>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\treg = <0x0 0x84000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-v350-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal v350 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-v350-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal v350 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tspi0 = &ospi;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-01 revA OSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n compatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n \"xlnx,versal-vc-p-a2197-00\",\n \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n model = \"Xilinx Versal A2197 Processor board revA\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tgpio0 = &gpio;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-01 revA QSPI\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-02 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>; /* u9 */\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@1 { /* Marvell 88E1512; U9 */\n\t\treg = <1>;\n\t};\n};\n\n\n&sdhci0 {\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&sdhci1 { /* U1A */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tno-1-8-v;\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* U4 */\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"high-speed\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* U12 Catalyst EEPROM - AT24 should be equivalent */\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U13 and U15 */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U18 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <3>;\t/* FIXME - check SPI1_SS0-2_B */\n\n\tflash@0 { /* U19 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst26vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-03 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tserial0 = &serial0;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t};\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* Must be enabled via J90/J91 */\n\teeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <1>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 64Mb */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x800000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* J99 MIO28 - MIO33 */\n\txlnx,mio-bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n\tno-1-8-v;\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U6 - IS25LQ032B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lq032b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-04 revA OSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem1 {\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <1>; /* FIXME */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"disabled\"; /* u93 and u92 and u161 and u160 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio-bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-04 revA QSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem1 {\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <2>;\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <1>;\n\tis-dual = <0>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 512MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x20000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio-bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-05 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem0 {\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 { /* 88e1510 */\n\t\treg = <1>;\n\t};\n\tphy2: phy@2 { /* VSC8531 */\n\t\treg = <2>;\n\t\tvsc8531,rx-delay = <6>;\n\t\tvsc8531,tx-delay = <6>;\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>;\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tspi-tx-bus-width = <1>;\n\tspi-rx-bus-width = <4>;\n\n\tflash@0 { /* MX25U12835 128Mbit */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 16MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <104000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x1000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc0 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n\tno-1-8-v;\n};\n\n&sdhci1 { /* connector */\n\txlnx,mio-bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA\";\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 {\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA (QSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tsdhci-caps-mask = <0 0x200000>;\n\tsdhci-caps = <0 0>;\n\tmax-frequency = <19000000>;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&qspi {\n num-cs = <1>;\n spi-tx-bus-width = <1>;\n spi-rx-bus-width = <4>;\n #address-cells = <1>;\n #size-cells = <0>;\n is-dual = <1>;\n flash@0 {\n #address-cells = <1>;\n #size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 256MB */\n reg = <0>;\n spi-tx-bus-width = <1>;\n spi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <150000000>;\n partition@0 {\n label = \"spi0-flash0\";\n reg = <0x0 0x10000000>;\n };\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA-x-ebm-02-revA\",\n\t\t \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA (EMMC)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tno-1-8-v;\n\tsdhci-caps-mask = <0 0x200000>;\n\tsdhci-caps = <0 0>;\n\tmax-frequency = <19000000>;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci0 {\n\t/* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA-x-ebm-03-revA\",\n\t\t \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA (OSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tsdhci-caps-mask = <0 0x200000>;\n\tsdhci-caps = <0 0>;\n\tmax-frequency = <19000000>;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&ospi {\n\t/* U97 MT35XU02G */\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck190 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tsdhci-caps-mask = <0 0x200000>;\n\tsdhci-caps = <0 0>;\n\tmax-frequency = <19000000>;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck5000-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck5000 revA\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vck5000-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck5000 board revA\";\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tspi0 = &ospi;\n\t};\n\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x10000000>;\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-virt.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-virt\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal Virtual\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tclk2: clk2 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <2670000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t\tclock-frequency = <2720000>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */\n\t\t\t <0x0 0xf9080000 0x0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x1 0x9 4>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x2>;\n\t\tranges;\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff060000 0x0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff070000 0x0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom1: eeprom@53 {\n\t\t\t\treg = <0x53>;\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t};\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom2: eeprom@55 {\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x55>;\n\t\t\t};\n\t\t};\n\n\t\tgpio: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tethernet0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 56 4>, <0x0 56 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy0: phy@0 {\n\t\t\t\treg = <0x0>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tethernet1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 58 4>, <0x0 58 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy1: phy@1 {\n\t\t\t\treg = <0x1>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xf12a0000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tnum-cs = <0x1>;\n\t\t\treg = <0x0 0xf1030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"n25q512a\", \"micron,m25p80\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <108000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@100000 {\n\t\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@600000 {\n\t\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@620000 {\n\t\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <1>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <3>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0x0 0x84000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\treg = <0x0 0xf1040000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <0>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\treg = <0x0 0xf1050000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <1>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\t#address-cells = <0x2>;\n\t\t\t#size-cells = <0x2>;\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tranges;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125 &clk125>;\n\n\t\t\tdwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x10000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = ðernet0;\n\t\tethernet1 = ðernet1;\n\t\tqspi = &qspi;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA (QSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tsdhci-caps-mask = <0 0x200000>;\n\tsdhci-caps = <0 0>;\n\tmax-frequency = <19000000>;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&qspi {\n\tnum-cs = <1>;\n\tspi-tx-bus-width = <1>;\n\tspi-rx-bus-width = <4>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tis-dual = <1>;\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 256MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <150000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x10000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA-x-ebm-02-revA\",\n\t\t \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA (EMMC)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tno-1-8-v;\n\tsdhci-caps-mask = <0 0x200000>;\n\tsdhci-caps = <0 0>;\n\tmax-frequency = <19000000>;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci0 {\n\t/* emmc MIO 0-13 - MTFC8GAKAJCN */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA-x-ebm-03-revA\",\n\t\t \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA (OSPI)\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tsdhci-caps-mask = <0 0x200000>;\n\tsdhci-caps = <0 0>;\n\tmax-frequency = <19000000>;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&ospi {\n\t/* U97 MT35XU02G */\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tsdhci-caps-mask = <0 0x200000>;\n\tsdhci-caps = <0 0>;\n\tmax-frequency = <19000000>;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vp-x-a2785-00 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vp-x-a2785-00 Eval board revA\";\n\tcompatible = \"xlnx,versal-vp-x-a2785-00-revA\",\n\t\t \"xlnx,versal-vp-x-a2785-00\", \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tstatus = \"okay\"; /* u93 and u92 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\tstatus = \"okay\";\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n/* PWM via MIO 41/FAN TACH MIO 49 - FIXME */\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk120 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk120 Eval board revA\";\n\tcompatible = \"xlnx,versal-vpk120-revA\", \"xlnx,versal-vpk120\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vpk120-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk120 revB\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk120 Eval board revB\";\n\tcompatible = \"xlnx,versal-vpk120-revB\", \"xlnx,versal-vpk120\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n\t/* Use for storing information about board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\tclock_si5338_0: clk27 {\t/* u55 SI5338-GM */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tclock_si5338_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_si5338_3: clk150 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <150000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&psgtr {\n\tstatus = \"okay\";\n\t/* dp, usb3, sata */\n\tclocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: ethernet-phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"soft\";\n\t\tnand-ecc-algo = \"bch\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-0\";\n\t\tnand-ecc-step-size = <1024>;\n\t\tnand-ecc-strength = <24>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"soft\";\n\t\tnand-ecc-algo = \"bch\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-1\";\n\t\tnand-ecc-step-size = <1024>;\n\t\tnand-ecc-strength = <24>;\n\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: flash@0 {\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: flash@0 {\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t\tsw13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&amba {\n\tocm: sram@fffc0000 {\n\t\tcompatible = \"mmio-sram\";\n\t\treg = <0xfffc0000 0x10000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0xfffc0000 0x10000>;\n\t\tocm-sram@0 {\n\t\t\treg = <0x0 0x10000>;\n\t\t};\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@34 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x34>;\n\t\t\t};\n\t\t\thwmon@35 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\thwmon@36 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&watchdog0 {\n\treset-on-timeout;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu100-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio-bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu100-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n\n\tsi5335_0: si5335_0 { /* clk0_usb - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5335_1: si5335_1 { /* clk1_dp - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 IRQ_TYPE_LEVEL_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO3\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO2\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO1\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* usb3, dp */\n\tclocks = <&si5335_0>, <&si5335_1>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"super-speed\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_4: out@4 {\n\t\t\t\t\t/* refclk4 for PS-GT, used for PCIE slot */\n\t\t\t\t\treg = <4>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 for PS-GT, used for PCIE */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* pcie, sata, usb3, dp */\n\tclocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * 1.0 revision has level shifter and this property should be\n\t * removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_4: out@4 {\n\t\t\t\t\t/* refclk4 for PS-GT, used for PCIE slot */\n\t\t\t\t\treg = <4>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 for PS-GT, used for PCIE */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* pcie, sata, usb3, dp */\n\tclocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\t/*\n\t * 1.0 revision has level shifter and this property should be\n\t * removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphyc: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\t/*\n\t\t * Enable all GTs to out from U-Boot\n\t\t * i2c mw 20 6 0 - setup IO to output\n\t\t * i2c mw 20 2 ef - setup output values on pins 0-7\n\t\t * i2c mw 20 3 ff - setup output values on pins 10-17\n\t\t */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n/*\t\t\tdrivers/hwmon/pmbus/Kconfig:86: be called max20751.\ndrivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o\n*/\n\t\t\tmax20751@72 { /* u95 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n\n\t/* FIXME PMOD - j160 */\n\t/* FIXME MSP430F - u41 - not detected */\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* FIXME PL i2c via PCA9306 - u45 */\n\t/* FIXME MSP430 - u41 - not detected */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 { /* i2c mw 74 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* i2c mw 74 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator1@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_4: out@4 {\n\t\t\t\t\t/* refclk4 for PS-GT, used for PCIE slot */\n\t\t\t\t\treg = <4>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 for PS-GT, used for PCIE */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 { /* i2c mw 74 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator2@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* i2c mw 74 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* i2c mw 74 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator4@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* pcie, sata, usb3, dp */\n\tclocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* 8T49N287 - u182 */\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@20 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu104-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revC\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;\n\t};\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - IRPS5401_ALERT_B\n\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t * 2 - MAX6643_OT_B\n\t\t * 3 - MAX6643_FANFAIL_B\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t * 4, 10 - 17 - not connected\n\t\t */\n\t};\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* 8T49N287 - u182 */\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tu183: ina226@40 { /* u183 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 4, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\txlnx,mio-bank = <1>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tina226-u67 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;\n\t};\n\tina226-u59 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n\tina226-u69 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;\n\t};\n\tina226-u66 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;\n\t};\n\tina226-u71 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u73 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tu67: ina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u67\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu59: ina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u59\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu61: ina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu60: ina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu64: ina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu69: ina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u69\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu66: ina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u66\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu63: ina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu3: ina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u3\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu71: ina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u71\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu73: ina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u73\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u57 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SI5382 - u48 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection FIXME */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, dp, usb3, sata */\n\tclocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revA\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1275-revb.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU1275 RevB\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revB\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t* 1.0 revision has level shifter and this property should be\n\t* removed for supporting UHS mode\n\t*/\n\tno-1-8-v;\n};\n\n&gem1 {\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1285-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU1285 RevA\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1285 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1285-revA\", \"xlnx,zynqmp-zcu1285\", \"xlnx,zynqmp\";\n\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PMBUS */\n\t\t\tmax20751@74 { /* u23 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x74>;\n\t\t\t};\n\t\t\tmax20751@70 { /* u89 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x70>;\n\t\t\t};\n\t\t\tmax15301@a { /* u28 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u48 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@d { /* u27 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\tmax15303@e { /* u11 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\tmax15303@f { /* u96 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\tmax15303@11 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\tmax15303@12 { /* u24 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u29 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u51 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u30 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u102 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15301@17 { /* u50 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u31 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* CM_I2C */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYS_EEPROM */\n\t\t\teeprom: eeprom@54 { /* u101 */\n\t\t\t\tcompatible = \"atmel,24c32\"; /* 24LC32A */\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FMC1 */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FMC2 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* ANALOG_PMBUS */\n\t\t\tu60: ina226@40 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu61: ina226@41 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu63: ina226@42 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu65: ina226@43 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu64: ina226@44 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* ANALOG_CM_I2C */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FMC3 */\n\t\t};\n\t};\n};\n\n&gem1 {\n\tmdio {\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu208-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU208\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU208 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu208-revA\", \"xlnx,zynqmp-zcu208\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu216-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU216\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU216 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu216-revA\", \"xlnx,zynqmp-zcu216\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu670-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR)\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU670 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu670-revA\", \"xlnx,zynqmp-zcu670\",\n\t\t \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\"; /* DS1 */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5381_6: si5381_6 { /* refclk_usb3 - u43 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"SFP3_TX_DISABLE\", \"SFP2_TX_DISABLE\", \"SFP1_TX_DISABLE\", /* 25 - 29 */\n\t\t \"SFP0_TX_DISABLE\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"SD_PWR_RST\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"SI5381_INT_ALM\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* Not in schematics */\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5381: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SI5381 - u43 */\n\t\t\t/*si5381: clock-generator@68 {\n\t\t\t\treg = <0x68>;\n\t\t\t};*/\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_psrefclk: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"si570_ps_ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 2Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&psgtr {\n\t/* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */\n\tclocks = <&si5381_6>;\n\tclock-names = \"ref2\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zcu670-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU670 (67DR) revB\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU670 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu670-revB\", \"xlnx,zynqmp-zcu670\",\n\t\t \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\"; /* DS1 */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5381_6: si5381_6 { /* refclk_usb3 - u43 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"SFP3_TX_DISABLE\", \"SFP2_TX_DISABLE\", \"SFP1_TX_DISABLE\", /* 25 - 29 */\n\t\t \"SFP0_TX_DISABLE\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"SD_PWR_RST\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"SI5381_INT_ALM\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* Not in schematics */\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5381: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SI5381 - u43 */\n\t\t\t/*si5381: clock-generator@68 {\n\t\t\t\treg = <0x68>;\n\t\t\t};*/\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_psrefclk: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"si570_ps_ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 2Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\tclk-phase-sd-hs = <120>, <60>;\n\tclk-phase-uhs-sdr25 = <132>, <60>;\n\tclk-phase-uhs-ddr50 = <153>, <48>;\n};\n\n&psgtr {\n\t/* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */\n\tclocks = <&si5381_6>;\n\tclock-names = \"ref2\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-a2197-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Versal System Controller on a2197 board RevA\";\n\tcompatible = \"xlnx,zynqmp-a2197-revA\", \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = &eeprom1;\n\t\tnvmem1 = &eeprom0;\n\t};\n};\n\n&i2c0 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* this cover MGT board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* This cover processor board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-e-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevA\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tsi570_ddrdimm1_clk: si570_ddrdimm1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tsi570_lpddr4_clk2: si570_lpddr4_clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570_lpddr4_clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk1>;\n\t};\n\n\tsi570_hsdp_clk: si570_hsdp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi570_zsfp_clk: si570_zsfp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_zsfp>;\n\t};\n\n\tsi570_user1_clk: si570_user1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_user1>;\n\t};\n\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vcc-soc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;\n\t};\n\tina226-vcc-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc-pslp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;\n\t};\n\tina226-vcc-psfp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;\n\t};\n\tina226-vccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;\n\t};\n\tina226-vccaux-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;\n\t};\n\tina226-vcco-500 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;\n\t};\n\tina226-vcco-501 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;\n\t};\n\tina226-vcco-502 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;\n\t};\n\tina226-vcco-503 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;\n\t};\n\tina226-vcc-1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;\n\t};\n\tina226-vcc-3v3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;\n\t};\n\tina226-vcc-1v2-ddr4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;\n\t};\n\tina226-vcc-1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtyavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;\n\t};\n\tina226-mgtyavtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;\n\t};\n\tina226-mgtyvccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;\n\t};\n\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* u131 M88E1512 */\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"ZU4_TRIGGER\", \"SYSCTLR_PB\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"\", /* 85 - 89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"PMBUS_ALERT\", \"\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* u152 IR35215 0x16/0x46 vcc_soc */\n\t\t\t/* u179 ir38164 0x19/0x49 vcco_500 */\n\t\t\t/* u181 ir38164 0x1a/0x4a vcco_501 */\n\t\t\t/* u183 ir38164 0x1b/0x4b vcco_502 */\n\t\t\t/* u185 ir38164 0x1e/0x4e vadj_fmc */\n\t\t\t/* u187 ir38164 0x1F/0x4f mgtyavcc */\n\t\t\t/* u189 ir38164 0x20/0x50 mgtyavtt */\n\t\t\t/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */\n\t\t\t/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */\n\n\t\t\tirps5401_47: irps5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* pmbus / i2c 0x17 */\n\t\t\t};\n\t\t\tirps5401_4c: irps5401@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* pmbus / i2c 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: irps5401@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* pmbus / i2c 0x1d */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <500>; /* R440 */\n\t\t\t\t/* 0.80V @ 32A 1 of 6 Phases*/\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-soc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <500>; /* R1702 */\n\t\t\t\t/* 0.80V @ 18A */\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pmc\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* R1214 */\n\t\t\t\t/* 0.78V @ 500mA */\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u162 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r1221 */\n\t\t\t\t/* 0.78V @ 4A */\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pslp\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>; /* R1216 */\n\t\t\t\t/* 0.78V @ 1A */\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-psfp\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1219 */\n\t\t\t\t/* 0.78V @ 2A */\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* R382 */\n\t\t\t\t/* 1.5V @ 3A */\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux-pmc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>; /* R1246 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u178 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-500\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>; /* R1300 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u180 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-501\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <2000>; /* R1313 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u182 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-502\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <2000>; /* R1330 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-503\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1229 */\n\t\t\t\t/* 1.8V @ 2A */\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u173 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v8\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>; /* R400 */\n\t\t\t\t/* 1.8V @ 6A */\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-3v3\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* R1232 */\n\t\t\t\t/* 3.3V @ 500mA */\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v2-ddr4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>; /* R1275 */\n\t\t\t\t/* 1.2V @ 4A */\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>; /* R1286 */\n\t\t\t\t/* 1.1V @ 4A */\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>; /* R1350 */\n\t\t\t\t/* 1.5V @ 10A */\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavcc\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <2000>; /* R1367 */\n\t\t\t\t/* 0.88V @ 6A */\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavtt\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>; /* R1384 */\n\t\t\t\t/* 1.2V @ 10A */\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyvccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>; /* r1679 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t\ti2c@5 { /* zSFP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_zsfp: clock-generator@5d { /* u192 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_zsfp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* USER_SI570_1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_user1: clock-generator@5d { /* u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>; /* FIXME check address */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"si570_user1\";\n\t\t\t};\n\n\t\t};\n\t\ti2c@7 { /* USER_SI570_2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* 0x5c too */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* and connector J212D */\n\t\t};\n\t\tfmc1: i2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t};\n\t\tfmc2: i2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LPDDR4_SI570_CLK2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_lpddr4clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4clk1: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* 8A34001 - U219B and J310 connector */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n\ti2c-mux@75 { /* u214 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\ti2c@0 { /* SFP0_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* SFP0 */\n\t\t};\n\t\ti2c@1 { /* SFP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@2 { /* QSFP1_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* QSFP1 */\n\t\t};\n\t\t/* 3 - 7 unused */\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-g-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 MGT Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-g-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u82 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&gem0 { /* eth MDIO 76/77 */\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 */\n\t\treg = <0>;\n\t\treset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 5 - 9 */\n\t\t \"\", \"\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"\", \"\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\ti2c-mux@74 { /* u94 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* CM_I2C_SCL - Samtec */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* PMBUS - AFX_PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\ttps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\ttps544@10 { /* u73 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\ttps544@11 { /* u76 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\ttps544@12 { /* u77 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\ttps544@13 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\ttps544@14 { /* u81 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\ttps544@15 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\ttps544@16 { /* u63 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\ttps544@17 { /* u66 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\ttps544@18 { /* u67 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\ttps544@19 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\ttps544@1d { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\ttps544@1e { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\ttps544@1f { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t\ttps544@20 { /* u71 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\t\t\tu74: ina226@40 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu75: ina226@41 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\"\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@43 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu82: ina226@44 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u82\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu84: ina226@45 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\ttps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* fmc1 via JA2G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom_fmc1: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* fmc2 via JA3G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\teeprom_fmc2: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* fmc3 via JA4G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\teeprom_fmc3: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* ddr dimm */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&usb0 { /* USB0 MIO52-63 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"high-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-01-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\tina226-vcc0v6-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc0v6_lp4: ina226@49 { /* u101 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc0v6-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@5d { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n status = \"disabled\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n /delete-property/ phy-names ;\n /delete-property/ phys ;\n maximum-speed = \"high-speed\";\n snps,dis_u2_susphy_quirk ;\n snps,dis_u3_susphy_quirk ;\n status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-02-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_vpp_2v5_ddr4: tps544@1x { /* u3007 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>; /* FIXME wrong in schematics */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* C0_DDR4_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\ti2c@6 { /* C2_DDR5_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\ti2c@7 { /* C3_DDR4_UDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_RLD3 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_RLD3_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_DDR5 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_DDR5_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-03-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_vpp_2v5_ddr4: tps544@1x { /* u3007 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>; /* FIXME wrong in schematics */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* DDR4_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_SODIMM_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_QDRIV */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_QDRIV_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-01-revA\", \"xlnx,zynqmp-x-prc-01\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\",\"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-02-revA\", \"xlnx,zynqmp-x-prc-02\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-03-revA\", \"xlnx,zynqmp-x-prc-03\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>; \n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tx_prc_si5338: clock-generator@70 { /* U9 */\n\t\t\t\tcompatible = \"silabs,si5338\";\n\t\t\t\treg = <0x70>; /* FIXME */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-04-revA\", \"xlnx,zynqmp-x-prc-04\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-05-revA\", \"xlnx,zynqmp-x-prc-05\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-sc-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP Generic System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP Generic System Controller\";\n\tcompatible = \"xlnx,zynqmp-sc-revB\", \"xlnx,zynqmp-sc\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"sw16\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds40-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t\tds44-led {\n\t\t\tlabel = \"status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tsi5332_2: si5332_2 { /* u42 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy0>;\n\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;\n\t\treset-delay-us = <2>;\n\n\t\tphy0: ethernet-phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 24-25 */\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\t/* No reason to do pinctrl setup at u-boot stage */\n\t/* Use for storing information about SC board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tu-boot,dm-pre-reloc;\n\t};\n};\n\n/* USB 3.0 only */\n&psgtr {\n\t/* nc, nc, usb3 */\n\tclocks = <&si5332_2>;\n\tclock-names = \"ref2\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"mt25qu512a\", \"m25p80\", \"jedec,spi-nor\"; /* mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart1 { /* uart0 MIO36-37 */\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tpinctrl-names = \"default\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-sm-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SM-K26 rev1/B/A\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP SM-K26 Rev1/B/A\";\n\tcompatible = \"xlnx,zynqmp-sm-k26-rev1\", \"xlnx,zynqmp-sm-k26-revB\",\n\t\t \"xlnx,zynqmp-sm-k26-revA\", \"xlnx,zynqmp-sm-k26\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36-led {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tflash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\n\t\t};\n\t};\n};\n\n&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues to be fixed in next board revision.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-smk-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP SMK-K26 Rev1/B/A\";\n\tcompatible = \"xlnx,zynqmp-smk-k26-rev1\", \"xlnx,zynqmp-smk-k26-revB\",\n\t\t \"xlnx,zynqmp-smk-k26-revA\", \"xlnx,zynqmp-smk-k26\",\n\t\t \"xlnx,zynqmp\";\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35 {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36 {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tflash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\n\t\t};\n\t};\n};\n\n&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues to be fixed in next board revision.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on vp-x-a2785-00 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vp-x-a2785-00-revA\",\n\t\t \"xlnx,zynqmp-vp-x-a2785-00\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tj383 {\n\t\t\tlabel = \"j383\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds52 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* u285 - mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>; /* maybe 4 here */\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* sd MIO 45-51 */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 { /* u131 - M88e1512 */\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"\", \"\", \"\", \"VCCINT_FAULT_B\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\treg_vccint: tps53681@c0 { /* u266 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@10 { /* u274 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@11 { /* u275 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@12 { /* u276 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc_cpm: tps544@14 { /* u272 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_util_3v3: tps544@1d { /* u278 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvcc_cpm: ina226@44 { /* u273 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpcie_smbus: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tpcie2_smbus: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tlpddr4_si570_clk3_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\t/* 6-7 unused */\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VPK120 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on VPK120 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vpk120-revA\",\n\t\t \"xlnx,zynqmp-vpk120\", \"xlnx,zynqmp\";\n\n\tsi570_user1_fmc_clk: si570_user1_fmc_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&user_si570_1>;\n\t};\n\n\tsi570_ref_clk: si570_ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&ref_clk>;\n\t};\n\n\tsi570_lpddr4_clk3: si570_lpddr4_clk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk3>;\n\t};\n\n\tsi570_lpddr4_clk2: si570_lpddr4_clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570_lpddr4_clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk1>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw16 {\n\t\t\tlabel = \"sw16\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds40 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"\", \"\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"\", /* 85 - 89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"QSFPDD1_MODSELL\", \"QSFPDD1_MODSELL\", /* 0 - 3 */\n\t\t\t\t \"PMBUS2_INA226_ALERT\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP1_FMC_PRSNT_M2C_B\", \"\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\tir38060_41: regulator@41 { /* IR38060 - u259 */\n\t\t\t\tcompatible = \"infineon,ir38060\", \"infineon,ir38064\";\n\t\t\t\treg = <0x41>; /* i2c addr 0x11 */\n\t\t\t};\n\t\t\tir38164_43: regulator@43 { /* IR38164 - u13 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x43>; /* i2c addr 0x13 */\n\t\t\t};\n\t\t\tir35221_45: pmic@46 { /* IR35221 - u152 */\n\t\t\t\tcompatible = \"infineon,ir35221\";\n\t\t\t\treg = <0x46>; /* PMBUS - 0x16 */\n\t\t\t};\n\t\t\tirps5401_47: pmic5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* i2c addr 0x17 */\n\t\t\t};\n\t\t\tir38164_49: regulator@49 { /* IR38164 - u189 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x49>; /* i2c addr 0x19 */\n\t\t\t};\n\t\t\tirps5401_4c: pmic@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: pmic@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tir38164_4e: regulator@4e { /* IR38164 - u184 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4e>; /* i2c addr 0x1e */\n\t\t\t};\n\t\t\tir38164_4f: regulator@4f { /* IR38164 - u187 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4f>; /* i2c addr 0x1f */\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u5 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpmbus2_ina226_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@42 { /* u265 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v5: ina226@43 { /* u264 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_mio: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavtt: ina226@46 { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtvccaux: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyavcc: ina226@4b { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tlpdmgtyavtt: ina226@4c { /* u260 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tuser_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"fmc_si570\";\n\t\t\t};\n\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tref_clk_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\tfmcp1_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tlpddr4_si570_clk3_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlpddr4_clk3: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk3\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\tqsfpdd_i2c: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* J1/J2 connectors */\n\t\t};\n\t\tidt8a34001_i2c: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* Via J310 connector */\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u219B */\n\t\t\t\treg = <0x5b>; /* FIXME not in schematics */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/clock/xlnx-versal-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_VERSAL_H\n#define _DT_BINDINGS_CLK_VERSAL_H\n\n#define PMC_PLL\t\t\t\t\t1\n#define APU_PLL\t\t\t\t\t2\n#define RPU_PLL\t\t\t\t\t3\n#define CPM_PLL\t\t\t\t\t4\n#define NOC_PLL\t\t\t\t\t5\n#define PLL_MAX\t\t\t\t\t6\n#define PMC_PRESRC\t\t\t\t7\n#define PMC_POSTCLK\t\t\t\t8\n#define PMC_PLL_OUT\t\t\t\t9\n#define PPLL\t\t\t\t\t10\n#define NOC_PRESRC\t\t\t\t11\n#define NOC_POSTCLK\t\t\t\t12\n#define NOC_PLL_OUT\t\t\t\t13\n#define NPLL\t\t\t\t\t14\n#define APU_PRESRC\t\t\t\t15\n#define APU_POSTCLK\t\t\t\t16\n#define APU_PLL_OUT\t\t\t\t17\n#define APLL\t\t\t\t\t18\n#define RPU_PRESRC\t\t\t\t19\n#define RPU_POSTCLK\t\t\t\t20\n#define RPU_PLL_OUT\t\t\t\t21\n#define RPLL\t\t\t\t\t22\n#define CPM_PRESRC\t\t\t\t23\n#define CPM_POSTCLK\t\t\t\t24\n#define CPM_PLL_OUT\t\t\t\t25\n#define CPLL\t\t\t\t\t26\n#define PPLL_TO_XPD\t\t\t\t27\n#define NPLL_TO_XPD\t\t\t\t28\n#define APLL_TO_XPD\t\t\t\t29\n#define RPLL_TO_XPD\t\t\t\t30\n#define EFUSE_REF\t\t\t\t31\n#define SYSMON_REF\t\t\t\t32\n#define IRO_SUSPEND_REF\t\t\t\t33\n#define USB_SUSPEND\t\t\t\t34\n#define SWITCH_TIMEOUT\t\t\t\t35\n#define RCLK_PMC\t\t\t\t36\n#define RCLK_LPD\t\t\t\t37\n#define WDT\t\t\t\t\t38\n#define TTC0\t\t\t\t\t39\n#define TTC1\t\t\t\t\t40\n#define TTC2\t\t\t\t\t41\n#define TTC3\t\t\t\t\t42\n#define GEM_TSU\t\t\t\t\t43\n#define GEM_TSU_LB\t\t\t\t44\n#define MUXED_IRO_DIV2\t\t\t\t45\n#define MUXED_IRO_DIV4\t\t\t\t46\n#define PSM_REF\t\t\t\t\t47\n#define GEM0_RX\t\t\t\t\t48\n#define GEM0_TX\t\t\t\t\t49\n#define GEM1_RX\t\t\t\t\t50\n#define GEM1_TX\t\t\t\t\t51\n#define CPM_CORE_REF\t\t\t\t52\n#define CPM_LSBUS_REF\t\t\t\t53\n#define CPM_DBG_REF\t\t\t\t54\n#define CPM_AUX0_REF\t\t\t\t55\n#define CPM_AUX1_REF\t\t\t\t56\n#define QSPI_REF\t\t\t\t57\n#define OSPI_REF\t\t\t\t58\n#define SDIO0_REF\t\t\t\t59\n#define SDIO1_REF\t\t\t\t60\n#define PMC_LSBUS_REF\t\t\t\t61\n#define I2C_REF\t\t\t\t\t62\n#define TEST_PATTERN_REF\t\t\t63\n#define DFT_OSC_REF\t\t\t\t64\n#define PMC_PL0_REF\t\t\t\t65\n#define PMC_PL1_REF\t\t\t\t66\n#define PMC_PL2_REF\t\t\t\t67\n#define PMC_PL3_REF\t\t\t\t68\n#define CFU_REF\t\t\t\t\t69\n#define SPARE_REF\t\t\t\t70\n#define NPI_REF\t\t\t\t\t71\n#define HSM0_REF\t\t\t\t72\n#define HSM1_REF\t\t\t\t73\n#define SD_DLL_REF\t\t\t\t74\n#define FPD_TOP_SWITCH\t\t\t\t75\n#define FPD_LSBUS\t\t\t\t76\n#define ACPU\t\t\t\t\t77\n#define DBG_TRACE\t\t\t\t78\n#define DBG_FPD\t\t\t\t\t79\n#define LPD_TOP_SWITCH\t\t\t\t80\n#define ADMA\t\t\t\t\t81\n#define LPD_LSBUS\t\t\t\t82\n#define CPU_R5\t\t\t\t\t83\n#define CPU_R5_CORE\t\t\t\t84\n#define CPU_R5_OCM\t\t\t\t85\n#define CPU_R5_OCM2\t\t\t\t86\n#define IOU_SWITCH\t\t\t\t87\n#define GEM0_REF\t\t\t\t88\n#define GEM1_REF\t\t\t\t89\n#define GEM_TSU_REF\t\t\t\t90\n#define USB0_BUS_REF\t\t\t\t91\n#define UART0_REF\t\t\t\t92\n#define UART1_REF\t\t\t\t93\n#define SPI0_REF\t\t\t\t94\n#define SPI1_REF\t\t\t\t95\n#define CAN0_REF\t\t\t\t96\n#define CAN1_REF\t\t\t\t97\n#define I2C0_REF\t\t\t\t98\n#define I2C1_REF\t\t\t\t99\n#define DBG_LPD\t\t\t\t\t100\n#define TIMESTAMP_REF\t\t\t\t101\n#define DBG_TSTMP\t\t\t\t102\n#define CPM_TOPSW_REF\t\t\t\t103\n#define USB3_DUAL_REF\t\t\t\t104\n#define OUTCLK_MAX\t\t\t\t105\n#define REF_CLK\t\t\t\t\t106\n#define PL_ALT_REF_CLK\t\t\t\t107\n#define MUXED_IRO\t\t\t\t108\n#define PL_EXT\t\t\t\t\t109\n#define PL_LB\t\t\t\t\t110\n#define MIO_50_OR_51\t\t\t\t111\n#define MIO_24_OR_25\t\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Xilinx Zynq MPSoC Firmware layer\n *\n * Copyright (C) 2014-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_ZYNQMP_H\n#define _DT_BINDINGS_CLK_ZYNQMP_H\n\n#define IOPLL\t\t\t0\n#define RPLL\t\t\t1\n#define APLL\t\t\t2\n#define DPLL\t\t\t3\n#define VPLL\t\t\t4\n#define IOPLL_TO_FPD\t\t5\n#define RPLL_TO_FPD\t\t6\n#define APLL_TO_LPD\t\t7\n#define DPLL_TO_LPD\t\t8\n#define VPLL_TO_LPD\t\t9\n#define ACPU\t\t\t10\n#define ACPU_HALF\t\t11\n#define DBF_FPD\t\t\t12\n#define DBF_LPD\t\t\t13\n#define DBG_TRACE\t\t14\n#define DBG_TSTMP\t\t15\n#define DP_VIDEO_REF\t\t16\n#define DP_AUDIO_REF\t\t17\n#define DP_STC_REF\t\t18\n#define GDMA_REF\t\t19\n#define DPDMA_REF\t\t20\n#define DDR_REF\t\t\t21\n#define SATA_REF\t\t22\n#define PCIE_REF\t\t23\n#define GPU_REF\t\t\t24\n#define GPU_PP0_REF\t\t25\n#define GPU_PP1_REF\t\t26\n#define TOPSW_MAIN\t\t27\n#define TOPSW_LSBUS\t\t28\n#define GTGREF0_REF\t\t29\n#define LPD_SWITCH\t\t30\n#define LPD_LSBUS\t\t31\n#define USB0_BUS_REF\t\t32\n#define USB1_BUS_REF\t\t33\n#define USB3_DUAL_REF\t\t34\n#define USB0\t\t\t35\n#define USB1\t\t\t36\n#define CPU_R5\t\t\t37\n#define CPU_R5_CORE\t\t38\n#define CSU_SPB\t\t\t39\n#define CSU_PLL\t\t\t40\n#define PCAP\t\t\t41\n#define IOU_SWITCH\t\t42\n#define GEM_TSU_REF\t\t43\n#define GEM_TSU\t\t\t44\n#define GEM0_TX\t\t\t45\n#define GEM1_TX\t\t\t46\n#define GEM2_TX\t\t\t47\n#define GEM3_TX\t\t\t48\n#define GEM0_RX\t\t\t49\n#define GEM1_RX\t\t\t50\n#define GEM2_RX\t\t\t51\n#define GEM3_RX\t\t\t52\n#define QSPI_REF\t\t53\n#define SDIO0_REF\t\t54\n#define SDIO1_REF\t\t55\n#define UART0_REF\t\t56\n#define UART1_REF\t\t57\n#define SPI0_REF\t\t58\n#define SPI1_REF\t\t59\n#define NAND_REF\t\t60\n#define I2C0_REF\t\t61\n#define I2C1_REF\t\t62\n#define CAN0_REF\t\t63\n#define CAN1_REF\t\t64\n#define CAN0\t\t\t65\n#define CAN1\t\t\t66\n#define DLL_REF\t\t\t67\n#define ADMA_REF\t\t68\n#define TIMESTAMP_REF\t\t69\n#define AMS_REF\t\t\t70\n#define PL0_REF\t\t\t71\n#define PL1_REF\t\t\t72\n#define PL2_REF\t\t\t73\n#define PL3_REF\t\t\t74\n#define WDT\t\t\t75\n#define IOPLL_INT\t\t76\n#define IOPLL_PRE_SRC\t\t77\n#define IOPLL_HALF\t\t78\n#define IOPLL_INT_MUX\t\t79\n#define IOPLL_POST_SRC\t\t80\n#define RPLL_INT\t\t81\n#define RPLL_PRE_SRC\t\t82\n#define RPLL_HALF\t\t83\n#define RPLL_INT_MUX\t\t84\n#define RPLL_POST_SRC\t\t85\n#define APLL_INT\t\t86\n#define APLL_PRE_SRC\t\t87\n#define APLL_HALF\t\t88\n#define APLL_INT_MUX\t\t89\n#define APLL_POST_SRC\t\t90\n#define DPLL_INT\t\t91\n#define DPLL_PRE_SRC\t\t92\n#define DPLL_HALF\t\t93\n#define DPLL_INT_MUX\t\t94\n#define DPLL_POST_SRC\t\t95\n#define VPLL_INT\t\t96\n#define VPLL_PRE_SRC\t\t97\n#define VPLL_HALF\t\t98\n#define VPLL_INT_MUX\t\t99\n#define VPLL_POST_SRC\t\t100\n#define CAN0_MIO\t\t101\n#define CAN1_MIO\t\t102\n#define ACPU_FULL\t\t103\n#define GEM0_REF\t\t104\n#define GEM1_REF\t\t105\n#define GEM2_REF\t\t106\n#define GEM3_REF\t\t107\n#define GEM0_REF_UNG\t\t108\n#define GEM1_REF_UNG\t\t109\n#define GEM2_REF_UNG\t\t110\n#define GEM3_REF_UNG\t\t111\n#define LPD_WDT\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h", "content": "/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */\n/*\n * Copyright 2019 Laurent Pinchart \n */\n\n#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n\n#define ZYNQMP_DPDMA_VIDEO0\t\t0\n#define ZYNQMP_DPDMA_VIDEO1\t\t1\n#define ZYNQMP_DPDMA_VIDEO2\t\t2\n#define ZYNQMP_DPDMA_GRAPHICS\t\t3\n#define ZYNQMP_DPDMA_AUDIO0\t\t4\n#define ZYNQMP_DPDMA_AUDIO1\t\t5\n\n#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/gpio/gpio.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most GPIO bindings.\n *\n * Most GPIO bindings include a flags cell as part of the GPIO specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_GPIO_GPIO_H\n#define _DT_BINDINGS_GPIO_GPIO_H\n\n/* Bit 0 express polarity */\n#define GPIO_ACTIVE_HIGH 0\n#define GPIO_ACTIVE_LOW 1\n\n/* Bit 1 express single-endedness */\n#define GPIO_PUSH_PULL 0\n#define GPIO_SINGLE_ENDED 2\n\n/* Bit 2 express Open drain or open source */\n#define GPIO_LINE_OPEN_SOURCE 0\n#define GPIO_LINE_OPEN_DRAIN 4\n\n/*\n * * Open Drain/Collector is the combination of single-ended open drain interface.\n * * Open Source/Emitter is the combination of single-ended open source interface.\n * */\n#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)\n#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)\n\n/* Bit 3 express GPIO suspend/resume persistence */\n#define GPIO_SLEEP_MAINTAIN_VALUE 0\n#define GPIO_SLEEP_MAY_LOOSE_VALUE 8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/input/input.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most input bindings.\n *\n * Most input bindings include key code, matrix key code format.\n * In most cases, key code and matrix key code format uses\n * the standard values/macro defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INPUT_INPUT_H\n#define _DT_BINDINGS_INPUT_INPUT_H\n\n/*\n * Device properties and quirks\n */\n\n#define INPUT_PROP_POINTER\t\t0x00\t/* needs a pointer */\n#define INPUT_PROP_DIRECT\t\t0x01\t/* direct input devices */\n#define INPUT_PROP_BUTTONPAD\t\t0x02\t/* has button(s) under pad */\n#define INPUT_PROP_SEMI_MT\t\t0x03\t/* touch rectangle only */\n#define INPUT_PROP_TOPBUTTONPAD\t\t0x04\t/* softbuttons at top of pad */\n#define INPUT_PROP_POINTING_STICK\t0x05\t/* is a pointing stick */\n#define INPUT_PROP_ACCELEROMETER\t0x06\t/* has accelerometer */\n\n#define INPUT_PROP_MAX\t\t\t0x1f\n#define INPUT_PROP_CNT\t\t\t(INPUT_PROP_MAX + 1)\n\n\n/*\n * Event types\n */\n\n#define EV_SYN\t\t\t0x00\n#define EV_KEY\t\t\t0x01\n#define EV_REL\t\t\t0x02\n#define EV_ABS\t\t\t0x03\n#define EV_MSC\t\t\t0x04\n#define EV_SW\t\t\t0x05\n#define EV_LED\t\t\t0x11\n#define EV_SND\t\t\t0x12\n#define EV_REP\t\t\t0x14\n#define EV_FF\t\t\t0x15\n#define EV_PWR\t\t\t0x16\n#define EV_FF_STATUS\t\t0x17\n#define EV_MAX\t\t\t0x1f\n#define EV_CNT\t\t\t(EV_MAX+1)\n\n/*\n * Synchronization events.\n */\n\n#define SYN_REPORT\t\t0\n#define SYN_CONFIG\t\t1\n#define SYN_MT_REPORT\t\t2\n#define SYN_DROPPED\t\t3\n#define SYN_MAX\t\t\t0xf\n#define SYN_CNT\t\t\t(SYN_MAX+1)\n\n/*\n * Keys and buttons\n *\n * Most of the keys/buttons are modeled after USB HUT 1.12\n * (see http://www.usb.org/developers/hidpage).\n * Abbreviations in the comments:\n * AC - Application Control\n * AL - Application Launch Button\n * SC - System Control\n */\n\n#define KEY_RESERVED\t\t0\n#define KEY_ESC\t\t\t1\n#define KEY_1\t\t\t2\n#define KEY_2\t\t\t3\n#define KEY_3\t\t\t4\n#define KEY_4\t\t\t5\n#define KEY_5\t\t\t6\n#define KEY_6\t\t\t7\n#define KEY_7\t\t\t8\n#define KEY_8\t\t\t9\n#define KEY_9\t\t\t10\n#define KEY_0\t\t\t11\n#define KEY_MINUS\t\t12\n#define KEY_EQUAL\t\t13\n#define KEY_BACKSPACE\t\t14\n#define KEY_TAB\t\t\t15\n#define KEY_Q\t\t\t16\n#define KEY_W\t\t\t17\n#define KEY_E\t\t\t18\n#define KEY_R\t\t\t19\n#define KEY_T\t\t\t20\n#define KEY_Y\t\t\t21\n#define KEY_U\t\t\t22\n#define KEY_I\t\t\t23\n#define KEY_O\t\t\t24\n#define KEY_P\t\t\t25\n#define KEY_LEFTBRACE\t\t26\n#define KEY_RIGHTBRACE\t\t27\n#define KEY_ENTER\t\t28\n#define KEY_LEFTCTRL\t\t29\n#define KEY_A\t\t\t30\n#define KEY_S\t\t\t31\n#define KEY_D\t\t\t32\n#define KEY_F\t\t\t33\n#define KEY_G\t\t\t34\n#define KEY_H\t\t\t35\n#define KEY_J\t\t\t36\n#define KEY_K\t\t\t37\n#define KEY_L\t\t\t38\n#define KEY_SEMICOLON\t\t39\n#define KEY_APOSTROPHE\t\t40\n#define KEY_GRAVE\t\t41\n#define KEY_LEFTSHIFT\t\t42\n#define KEY_BACKSLASH\t\t43\n#define KEY_Z\t\t\t44\n#define KEY_X\t\t\t45\n#define KEY_C\t\t\t46\n#define KEY_V\t\t\t47\n#define KEY_B\t\t\t48\n#define KEY_N\t\t\t49\n#define KEY_M\t\t\t50\n#define KEY_COMMA\t\t51\n#define KEY_DOT\t\t\t52\n#define KEY_SLASH\t\t53\n#define KEY_RIGHTSHIFT\t\t54\n#define KEY_KPASTERISK\t\t55\n#define KEY_LEFTALT\t\t56\n#define KEY_SPACE\t\t57\n#define KEY_CAPSLOCK\t\t58\n#define KEY_F1\t\t\t59\n#define KEY_F2\t\t\t60\n#define KEY_F3\t\t\t61\n#define KEY_F4\t\t\t62\n#define KEY_F5\t\t\t63\n#define KEY_F6\t\t\t64\n#define KEY_F7\t\t\t65\n#define KEY_F8\t\t\t66\n#define KEY_F9\t\t\t67\n#define KEY_F10\t\t\t68\n#define KEY_NUMLOCK\t\t69\n#define KEY_SCROLLLOCK\t\t70\n#define KEY_KP7\t\t\t71\n#define KEY_KP8\t\t\t72\n#define KEY_KP9\t\t\t73\n#define KEY_KPMINUS\t\t74\n#define KEY_KP4\t\t\t75\n#define KEY_KP5\t\t\t76\n#define KEY_KP6\t\t\t77\n#define KEY_KPPLUS\t\t78\n#define KEY_KP1\t\t\t79\n#define KEY_KP2\t\t\t80\n#define KEY_KP3\t\t\t81\n#define KEY_KP0\t\t\t82\n#define KEY_KPDOT\t\t83\n\n#define KEY_ZENKAKUHANKAKU\t85\n#define KEY_102ND\t\t86\n#define KEY_F11\t\t\t87\n#define KEY_F12\t\t\t88\n#define KEY_RO\t\t\t89\n#define KEY_KATAKANA\t\t90\n#define KEY_HIRAGANA\t\t91\n#define KEY_HENKAN\t\t92\n#define KEY_KATAKANAHIRAGANA\t93\n#define KEY_MUHENKAN\t\t94\n#define KEY_KPJPCOMMA\t\t95\n#define KEY_KPENTER\t\t96\n#define KEY_RIGHTCTRL\t\t97\n#define KEY_KPSLASH\t\t98\n#define KEY_SYSRQ\t\t99\n#define KEY_RIGHTALT\t\t100\n#define KEY_LINEFEED\t\t101\n#define KEY_HOME\t\t102\n#define KEY_UP\t\t\t103\n#define KEY_PAGEUP\t\t104\n#define KEY_LEFT\t\t105\n#define KEY_RIGHT\t\t106\n#define KEY_END\t\t\t107\n#define KEY_DOWN\t\t108\n#define KEY_PAGEDOWN\t\t109\n#define KEY_INSERT\t\t110\n#define KEY_DELETE\t\t111\n#define KEY_MACRO\t\t112\n#define KEY_MUTE\t\t113\n#define KEY_VOLUMEDOWN\t\t114\n#define KEY_VOLUMEUP\t\t115\n#define KEY_POWER\t\t116\t/* SC System Power Down */\n#define KEY_KPEQUAL\t\t117\n#define KEY_KPPLUSMINUS\t\t118\n#define KEY_PAUSE\t\t119\n#define KEY_SCALE\t\t120\t/* AL Compiz Scale (Expose) */\n\n#define KEY_KPCOMMA\t\t121\n#define KEY_HANGEUL\t\t122\n#define KEY_HANGUEL\t\tKEY_HANGEUL\n#define KEY_HANJA\t\t123\n#define KEY_YEN\t\t\t124\n#define KEY_LEFTMETA\t\t125\n#define KEY_RIGHTMETA\t\t126\n#define KEY_COMPOSE\t\t127\n#define KEY_STOP\t\t128\t/* AC Stop */\n#define KEY_AGAIN\t\t129\n#define KEY_PROPS\t\t130\t/* AC Properties */\n#define KEY_UNDO\t\t131\t/* AC Undo */\n#define KEY_FRONT\t\t132\n#define KEY_COPY\t\t133\t/* AC Copy */\n#define KEY_OPEN\t\t134\t/* AC Open */\n#define KEY_PASTE\t\t135\t/* AC Paste */\n#define KEY_FIND\t\t136\t/* AC Search */\n#define KEY_CUT\t\t\t137\t/* AC Cut */\n#define KEY_HELP\t\t138\t/* AL Integrated Help Center */\n#define KEY_MENU\t\t139\t/* Menu (show menu) */\n#define KEY_CALC\t\t140\t/* AL Calculator */\n#define KEY_SETUP\t\t141\n#define KEY_SLEEP\t\t142\t/* SC System Sleep */\n#define KEY_WAKEUP\t\t143\t/* System Wake Up */\n#define KEY_FILE\t\t144\t/* AL Local Machine Browser */\n#define KEY_SENDFILE\t\t145\n#define KEY_DELETEFILE\t\t146\n#define KEY_XFER\t\t147\n#define KEY_PROG1\t\t148\n#define KEY_PROG2\t\t149\n#define KEY_WWW\t\t\t150\t/* AL Internet Browser */\n#define KEY_MSDOS\t\t151\n#define KEY_COFFEE\t\t152\t/* AL Terminal Lock/Screensaver */\n#define KEY_SCREENLOCK\t\tKEY_COFFEE\n#define KEY_ROTATE_DISPLAY\t153\t/* Display orientation for e.g. tablets */\n#define KEY_DIRECTION\t\tKEY_ROTATE_DISPLAY\n#define KEY_CYCLEWINDOWS\t154\n#define KEY_MAIL\t\t155\n#define KEY_BOOKMARKS\t\t156\t/* AC Bookmarks */\n#define KEY_COMPUTER\t\t157\n#define KEY_BACK\t\t158\t/* AC Back */\n#define KEY_FORWARD\t\t159\t/* AC Forward */\n#define KEY_CLOSECD\t\t160\n#define KEY_EJECTCD\t\t161\n#define KEY_EJECTCLOSECD\t162\n#define KEY_NEXTSONG\t\t163\n#define KEY_PLAYPAUSE\t\t164\n#define KEY_PREVIOUSSONG\t165\n#define KEY_STOPCD\t\t166\n#define KEY_RECORD\t\t167\n#define KEY_REWIND\t\t168\n#define KEY_PHONE\t\t169\t/* Media Select Telephone */\n#define KEY_ISO\t\t\t170\n#define KEY_CONFIG\t\t171\t/* AL Consumer Control Configuration */\n#define KEY_HOMEPAGE\t\t172\t/* AC Home */\n#define KEY_REFRESH\t\t173\t/* AC Refresh */\n#define KEY_EXIT\t\t174\t/* AC Exit */\n#define KEY_MOVE\t\t175\n#define KEY_EDIT\t\t176\n#define KEY_SCROLLUP\t\t177\n#define KEY_SCROLLDOWN\t\t178\n#define KEY_KPLEFTPAREN\t\t179\n#define KEY_KPRIGHTPAREN\t180\n#define KEY_NEW\t\t\t181\t/* AC New */\n#define KEY_REDO\t\t182\t/* AC Redo/Repeat */\n\n#define KEY_F13\t\t\t183\n#define KEY_F14\t\t\t184\n#define KEY_F15\t\t\t185\n#define KEY_F16\t\t\t186\n#define KEY_F17\t\t\t187\n#define KEY_F18\t\t\t188\n#define KEY_F19\t\t\t189\n#define KEY_F20\t\t\t190\n#define KEY_F21\t\t\t191\n#define KEY_F22\t\t\t192\n#define KEY_F23\t\t\t193\n#define KEY_F24\t\t\t194\n\n#define KEY_PLAYCD\t\t200\n#define KEY_PAUSECD\t\t201\n#define KEY_PROG3\t\t202\n#define KEY_PROG4\t\t203\n#define KEY_DASHBOARD\t\t204\t/* AL Dashboard */\n#define KEY_SUSPEND\t\t205\n#define KEY_CLOSE\t\t206\t/* AC Close */\n#define KEY_PLAY\t\t207\n#define KEY_FASTFORWARD\t\t208\n#define KEY_BASSBOOST\t\t209\n#define KEY_PRINT\t\t210\t/* AC Print */\n#define KEY_HP\t\t\t211\n#define KEY_CAMERA\t\t212\n#define KEY_SOUND\t\t213\n#define KEY_QUESTION\t\t214\n#define KEY_EMAIL\t\t215\n#define KEY_CHAT\t\t216\n#define KEY_SEARCH\t\t217\n#define KEY_CONNECT\t\t218\n#define KEY_FINANCE\t\t219\t/* AL Checkbook/Finance */\n#define KEY_SPORT\t\t220\n#define KEY_SHOP\t\t221\n#define KEY_ALTERASE\t\t222\n#define KEY_CANCEL\t\t223\t/* AC Cancel */\n#define KEY_BRIGHTNESSDOWN\t224\n#define KEY_BRIGHTNESSUP\t225\n#define KEY_MEDIA\t\t226\n\n#define KEY_SWITCHVIDEOMODE\t227\t/* Cycle between available video\n\t\t\t\t\t outputs (Monitor/LCD/TV-out/etc) */\n#define KEY_KBDILLUMTOGGLE\t228\n#define KEY_KBDILLUMDOWN\t229\n#define KEY_KBDILLUMUP\t\t230\n\n#define KEY_SEND\t\t231\t/* AC Send */\n#define KEY_REPLY\t\t232\t/* AC Reply */\n#define KEY_FORWARDMAIL\t\t233\t/* AC Forward Msg */\n#define KEY_SAVE\t\t234\t/* AC Save */\n#define KEY_DOCUMENTS\t\t235\n\n#define KEY_BATTERY\t\t236\n\n#define KEY_BLUETOOTH\t\t237\n#define KEY_WLAN\t\t238\n#define KEY_UWB\t\t\t239\n\n#define KEY_UNKNOWN\t\t240\n#define KEY_VIDEO_NEXT\t\t241\t/* drive next video source */\n#define KEY_VIDEO_PREV\t\t242\t/* drive previous video source */\n#define KEY_BRIGHTNESS_CYCLE\t243\t/* brightness up, after max is min */\n#define KEY_BRIGHTNESS_AUTO\t244\t/* Set Auto Brightness: manual\n\t\t\t\t\t brightness control is off,\n\t\t\t\t\t rely on ambient */\n#define KEY_BRIGHTNESS_ZERO\tKEY_BRIGHTNESS_AUTO\n#define KEY_DISPLAY_OFF\t\t245\t/* display device to off state */\n\n#define KEY_WWAN\t\t246\t/* Wireless WAN (LTE, UMTS, GSM, etc.) */\n#define KEY_WIMAX\t\tKEY_WWAN\n#define KEY_RFKILL\t\t247\t/* Key that controls all radios */\n\n#define KEY_MICMUTE\t\t248\t/* Mute / unmute the microphone */\n\n/* Code 255 is reserved for special needs of AT keyboard driver */\n\n#define BTN_MISC\t\t0x100\n#define BTN_0\t\t\t0x100\n#define BTN_1\t\t\t0x101\n#define BTN_2\t\t\t0x102\n#define BTN_3\t\t\t0x103\n#define BTN_4\t\t\t0x104\n#define BTN_5\t\t\t0x105\n#define BTN_6\t\t\t0x106\n#define BTN_7\t\t\t0x107\n#define BTN_8\t\t\t0x108\n#define BTN_9\t\t\t0x109\n\n#define BTN_MOUSE\t\t0x110\n#define BTN_LEFT\t\t0x110\n#define BTN_RIGHT\t\t0x111\n#define BTN_MIDDLE\t\t0x112\n#define BTN_SIDE\t\t0x113\n#define BTN_EXTRA\t\t0x114\n#define BTN_FORWARD\t\t0x115\n#define BTN_BACK\t\t0x116\n#define BTN_TASK\t\t0x117\n\n#define BTN_JOYSTICK\t\t0x120\n#define BTN_TRIGGER\t\t0x120\n#define BTN_THUMB\t\t0x121\n#define BTN_THUMB2\t\t0x122\n#define BTN_TOP\t\t\t0x123\n#define BTN_TOP2\t\t0x124\n#define BTN_PINKIE\t\t0x125\n#define BTN_BASE\t\t0x126\n#define BTN_BASE2\t\t0x127\n#define BTN_BASE3\t\t0x128\n#define BTN_BASE4\t\t0x129\n#define BTN_BASE5\t\t0x12a\n#define BTN_BASE6\t\t0x12b\n#define BTN_DEAD\t\t0x12f\n\n#define BTN_GAMEPAD\t\t0x130\n#define BTN_SOUTH\t\t0x130\n#define BTN_A\t\t\tBTN_SOUTH\n#define BTN_EAST\t\t0x131\n#define BTN_B\t\t\tBTN_EAST\n#define BTN_C\t\t\t0x132\n#define BTN_NORTH\t\t0x133\n#define BTN_X\t\t\tBTN_NORTH\n#define BTN_WEST\t\t0x134\n#define BTN_Y\t\t\tBTN_WEST\n#define BTN_Z\t\t\t0x135\n#define BTN_TL\t\t\t0x136\n#define BTN_TR\t\t\t0x137\n#define BTN_TL2\t\t\t0x138\n#define BTN_TR2\t\t\t0x139\n#define BTN_SELECT\t\t0x13a\n#define BTN_START\t\t0x13b\n#define BTN_MODE\t\t0x13c\n#define BTN_THUMBL\t\t0x13d\n#define BTN_THUMBR\t\t0x13e\n\n#define BTN_DIGI\t\t0x140\n#define BTN_TOOL_PEN\t\t0x140\n#define BTN_TOOL_RUBBER\t\t0x141\n#define BTN_TOOL_BRUSH\t\t0x142\n#define BTN_TOOL_PENCIL\t\t0x143\n#define BTN_TOOL_AIRBRUSH\t0x144\n#define BTN_TOOL_FINGER\t\t0x145\n#define BTN_TOOL_MOUSE\t\t0x146\n#define BTN_TOOL_LENS\t\t0x147\n#define BTN_TOOL_QUINTTAP\t0x148\t/* Five fingers on trackpad */\n#define BTN_TOUCH\t\t0x14a\n#define BTN_STYLUS\t\t0x14b\n#define BTN_STYLUS2\t\t0x14c\n#define BTN_TOOL_DOUBLETAP\t0x14d\n#define BTN_TOOL_TRIPLETAP\t0x14e\n#define BTN_TOOL_QUADTAP\t0x14f\t/* Four fingers on trackpad */\n\n#define BTN_WHEEL\t\t0x150\n#define BTN_GEAR_DOWN\t\t0x150\n#define BTN_GEAR_UP\t\t0x151\n\n#define KEY_OK\t\t\t0x160\n#define KEY_SELECT\t\t0x161\n#define KEY_GOTO\t\t0x162\n#define KEY_CLEAR\t\t0x163\n#define KEY_POWER2\t\t0x164\n#define KEY_OPTION\t\t0x165\n#define KEY_INFO\t\t0x166\t/* AL OEM Features/Tips/Tutorial */\n#define KEY_TIME\t\t0x167\n#define KEY_VENDOR\t\t0x168\n#define KEY_ARCHIVE\t\t0x169\n#define KEY_PROGRAM\t\t0x16a\t/* Media Select Program Guide */\n#define KEY_CHANNEL\t\t0x16b\n#define KEY_FAVORITES\t\t0x16c\n#define KEY_EPG\t\t\t0x16d\n#define KEY_PVR\t\t\t0x16e\t/* Media Select Home */\n#define KEY_MHP\t\t\t0x16f\n#define KEY_LANGUAGE\t\t0x170\n#define KEY_TITLE\t\t0x171\n#define KEY_SUBTITLE\t\t0x172\n#define KEY_ANGLE\t\t0x173\n#define KEY_ZOOM\t\t0x174\n#define KEY_MODE\t\t0x175\n#define KEY_KEYBOARD\t\t0x176\n#define KEY_SCREEN\t\t0x177\n#define KEY_PC\t\t\t0x178\t/* Media Select Computer */\n#define KEY_TV\t\t\t0x179\t/* Media Select TV */\n#define KEY_TV2\t\t\t0x17a\t/* Media Select Cable */\n#define KEY_VCR\t\t\t0x17b\t/* Media Select VCR */\n#define KEY_VCR2\t\t0x17c\t/* VCR Plus */\n#define KEY_SAT\t\t\t0x17d\t/* Media Select Satellite */\n#define KEY_SAT2\t\t0x17e\n#define KEY_CD\t\t\t0x17f\t/* Media Select CD */\n#define KEY_TAPE\t\t0x180\t/* Media Select Tape */\n#define KEY_RADIO\t\t0x181\n#define KEY_TUNER\t\t0x182\t/* Media Select Tuner */\n#define KEY_PLAYER\t\t0x183\n#define KEY_TEXT\t\t0x184\n#define KEY_DVD\t\t\t0x185\t/* Media Select DVD */\n#define KEY_AUX\t\t\t0x186\n#define KEY_MP3\t\t\t0x187\n#define KEY_AUDIO\t\t0x188\t/* AL Audio Browser */\n#define KEY_VIDEO\t\t0x189\t/* AL Movie Browser */\n#define KEY_DIRECTORY\t\t0x18a\n#define KEY_LIST\t\t0x18b\n#define KEY_MEMO\t\t0x18c\t/* Media Select Messages */\n#define KEY_CALENDAR\t\t0x18d\n#define KEY_RED\t\t\t0x18e\n#define KEY_GREEN\t\t0x18f\n#define KEY_YELLOW\t\t0x190\n#define KEY_BLUE\t\t0x191\n#define KEY_CHANNELUP\t\t0x192\t/* Channel Increment */\n#define KEY_CHANNELDOWN\t\t0x193\t/* Channel Decrement */\n#define KEY_FIRST\t\t0x194\n#define KEY_LAST\t\t0x195\t/* Recall Last */\n#define KEY_AB\t\t\t0x196\n#define KEY_NEXT\t\t0x197\n#define KEY_RESTART\t\t0x198\n#define KEY_SLOW\t\t0x199\n#define KEY_SHUFFLE\t\t0x19a\n#define KEY_BREAK\t\t0x19b\n#define KEY_PREVIOUS\t\t0x19c\n#define KEY_DIGITS\t\t0x19d\n#define KEY_TEEN\t\t0x19e\n#define KEY_TWEN\t\t0x19f\n#define KEY_VIDEOPHONE\t\t0x1a0\t/* Media Select Video Phone */\n#define KEY_GAMES\t\t0x1a1\t/* Media Select Games */\n#define KEY_ZOOMIN\t\t0x1a2\t/* AC Zoom In */\n#define KEY_ZOOMOUT\t\t0x1a3\t/* AC Zoom Out */\n#define KEY_ZOOMRESET\t\t0x1a4\t/* AC Zoom */\n#define KEY_WORDPROCESSOR\t0x1a5\t/* AL Word Processor */\n#define KEY_EDITOR\t\t0x1a6\t/* AL Text Editor */\n#define KEY_SPREADSHEET\t\t0x1a7\t/* AL Spreadsheet */\n#define KEY_GRAPHICSEDITOR\t0x1a8\t/* AL Graphics Editor */\n#define KEY_PRESENTATION\t0x1a9\t/* AL Presentation App */\n#define KEY_DATABASE\t\t0x1aa\t/* AL Database App */\n#define KEY_NEWS\t\t0x1ab\t/* AL Newsreader */\n#define KEY_VOICEMAIL\t\t0x1ac\t/* AL Voicemail */\n#define KEY_ADDRESSBOOK\t\t0x1ad\t/* AL Contacts/Address Book */\n#define KEY_MESSENGER\t\t0x1ae\t/* AL Instant Messaging */\n#define KEY_DISPLAYTOGGLE\t0x1af\t/* Turn display (LCD) on and off */\n#define KEY_BRIGHTNESS_TOGGLE\tKEY_DISPLAYTOGGLE\n#define KEY_SPELLCHECK\t\t0x1b0 /* AL Spell Check */\n#define KEY_LOGOFF\t\t0x1b1 /* AL Logoff */\n\n#define KEY_DOLLAR\t\t0x1b2\n#define KEY_EURO\t\t0x1b3\n\n#define KEY_FRAMEBACK\t\t0x1b4\t/* Consumer - transport controls */\n#define KEY_FRAMEFORWARD\t0x1b5\n#define KEY_CONTEXT_MENU\t0x1b6\t/* GenDesc - system context menu */\n#define KEY_MEDIA_REPEAT\t0x1b7\t/* Consumer - transport control */\n#define KEY_10CHANNELSUP\t0x1b8\t/* 10 channels up (10+) */\n#define KEY_10CHANNELSDOWN\t0x1b9\t/* 10 channels down (10-) */\n#define KEY_IMAGES\t\t0x1ba\t/* AL Image Browser */\n\n#define KEY_DEL_EOL\t\t0x1c0\n#define KEY_DEL_EOS\t\t0x1c1\n#define KEY_INS_LINE\t\t0x1c2\n#define KEY_DEL_LINE\t\t0x1c3\n\n#define KEY_FN\t\t\t0x1d0\n#define KEY_FN_ESC\t\t0x1d1\n#define KEY_FN_F1\t\t0x1d2\n#define KEY_FN_F2\t\t0x1d3\n#define KEY_FN_F3\t\t0x1d4\n#define KEY_FN_F4\t\t0x1d5\n#define KEY_FN_F5\t\t0x1d6\n#define KEY_FN_F6\t\t0x1d7\n#define KEY_FN_F7\t\t0x1d8\n#define KEY_FN_F8\t\t0x1d9\n#define KEY_FN_F9\t\t0x1da\n#define KEY_FN_F10\t\t0x1db\n#define KEY_FN_F11\t\t0x1dc\n#define KEY_FN_F12\t\t0x1dd\n#define KEY_FN_1\t\t0x1de\n#define KEY_FN_2\t\t0x1df\n#define KEY_FN_D\t\t0x1e0\n#define KEY_FN_E\t\t0x1e1\n#define KEY_FN_F\t\t0x1e2\n#define KEY_FN_S\t\t0x1e3\n#define KEY_FN_B\t\t0x1e4\n\n#define KEY_BRL_DOT1\t\t0x1f1\n#define KEY_BRL_DOT2\t\t0x1f2\n#define KEY_BRL_DOT3\t\t0x1f3\n#define KEY_BRL_DOT4\t\t0x1f4\n#define KEY_BRL_DOT5\t\t0x1f5\n#define KEY_BRL_DOT6\t\t0x1f6\n#define KEY_BRL_DOT7\t\t0x1f7\n#define KEY_BRL_DOT8\t\t0x1f8\n#define KEY_BRL_DOT9\t\t0x1f9\n#define KEY_BRL_DOT10\t\t0x1fa\n\n#define KEY_NUMERIC_0\t\t0x200\t/* used by phones, remote controls, */\n#define KEY_NUMERIC_1\t\t0x201\t/* and other keypads */\n#define KEY_NUMERIC_2\t\t0x202\n#define KEY_NUMERIC_3\t\t0x203\n#define KEY_NUMERIC_4\t\t0x204\n#define KEY_NUMERIC_5\t\t0x205\n#define KEY_NUMERIC_6\t\t0x206\n#define KEY_NUMERIC_7\t\t0x207\n#define KEY_NUMERIC_8\t\t0x208\n#define KEY_NUMERIC_9\t\t0x209\n#define KEY_NUMERIC_STAR\t0x20a\n#define KEY_NUMERIC_POUND\t0x20b\n#define KEY_NUMERIC_A\t\t0x20c\t/* Phone key A - HUT Telephony 0xb9 */\n#define KEY_NUMERIC_B\t\t0x20d\n#define KEY_NUMERIC_C\t\t0x20e\n#define KEY_NUMERIC_D\t\t0x20f\n\n#define KEY_CAMERA_FOCUS\t0x210\n#define KEY_WPS_BUTTON\t\t0x211\t/* WiFi Protected Setup key */\n\n#define KEY_TOUCHPAD_TOGGLE\t0x212\t/* Request switch touchpad on or off */\n#define KEY_TOUCHPAD_ON\t\t0x213\n#define KEY_TOUCHPAD_OFF\t0x214\n\n#define KEY_CAMERA_ZOOMIN\t0x215\n#define KEY_CAMERA_ZOOMOUT\t0x216\n#define KEY_CAMERA_UP\t\t0x217\n#define KEY_CAMERA_DOWN\t\t0x218\n#define KEY_CAMERA_LEFT\t\t0x219\n#define KEY_CAMERA_RIGHT\t0x21a\n\n#define KEY_ATTENDANT_ON\t0x21b\n#define KEY_ATTENDANT_OFF\t0x21c\n#define KEY_ATTENDANT_TOGGLE\t0x21d\t/* Attendant call on or off */\n#define KEY_LIGHTS_TOGGLE\t0x21e\t/* Reading light on or off */\n\n#define BTN_DPAD_UP\t\t0x220\n#define BTN_DPAD_DOWN\t\t0x221\n#define BTN_DPAD_LEFT\t\t0x222\n#define BTN_DPAD_RIGHT\t\t0x223\n\n#define KEY_ALS_TOGGLE\t\t0x230\t/* Ambient light sensor */\n\n#define KEY_BUTTONCONFIG\t\t0x240\t/* AL Button Configuration */\n#define KEY_TASKMANAGER\t\t0x241\t/* AL Task/Project Manager */\n#define KEY_JOURNAL\t\t0x242\t/* AL Log/Journal/Timecard */\n#define KEY_CONTROLPANEL\t\t0x243\t/* AL Control Panel */\n#define KEY_APPSELECT\t\t0x244\t/* AL Select Task/Application */\n#define KEY_SCREENSAVER\t\t0x245\t/* AL Screen Saver */\n#define KEY_VOICECOMMAND\t\t0x246\t/* Listening Voice Command */\n#define KEY_ASSISTANT\t\t0x247\t/* AL Context-aware desktop assistant */\n\n#define KEY_BRIGHTNESS_MIN\t\t0x250\t/* Set Brightness to Minimum */\n#define KEY_BRIGHTNESS_MAX\t\t0x251\t/* Set Brightness to Maximum */\n\n#define KEY_KBDINPUTASSIST_PREV\t\t0x260\n#define KEY_KBDINPUTASSIST_NEXT\t\t0x261\n#define KEY_KBDINPUTASSIST_PREVGROUP\t\t0x262\n#define KEY_KBDINPUTASSIST_NEXTGROUP\t\t0x263\n#define KEY_KBDINPUTASSIST_ACCEPT\t\t0x264\n#define KEY_KBDINPUTASSIST_CANCEL\t\t0x265\n\n/* Diagonal movement keys */\n#define KEY_RIGHT_UP\t\t\t0x266\n#define KEY_RIGHT_DOWN\t\t\t0x267\n#define KEY_LEFT_UP\t\t\t0x268\n#define KEY_LEFT_DOWN\t\t\t0x269\n\n#define KEY_ROOT_MENU\t\t\t0x26a /* Show Device's Root Menu */\n/* Show Top Menu of the Media (e.g. DVD) */\n#define KEY_MEDIA_TOP_MENU\t\t0x26b\n#define KEY_NUMERIC_11\t\t\t0x26c\n#define KEY_NUMERIC_12\t\t\t0x26d\n/*\n * Toggle Audio Description: refers to an audio service that helps blind and\n * visually impaired consumers understand the action in a program. Note: in\n * some countries this is referred to as \"Video Description\".\n */\n#define KEY_AUDIO_DESC\t\t\t0x26e\n#define KEY_3D_MODE\t\t\t0x26f\n#define KEY_NEXT_FAVORITE\t\t0x270\n#define KEY_STOP_RECORD\t\t\t0x271\n#define KEY_PAUSE_RECORD\t\t0x272\n#define KEY_VOD\t\t\t\t0x273 /* Video on Demand */\n#define KEY_UNMUTE\t\t\t0x274\n#define KEY_FASTREVERSE\t\t\t0x275\n#define KEY_SLOWREVERSE\t\t\t0x276\n/*\n * Control a data application associated with the currently viewed channel,\n * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)\n */\n#define KEY_DATA\t\t\t0x277\n#define KEY_ONSCREEN_KEYBOARD\t\t0x278\n\n#define BTN_TRIGGER_HAPPY\t\t0x2c0\n#define BTN_TRIGGER_HAPPY1\t\t0x2c0\n#define BTN_TRIGGER_HAPPY2\t\t0x2c1\n#define BTN_TRIGGER_HAPPY3\t\t0x2c2\n#define BTN_TRIGGER_HAPPY4\t\t0x2c3\n#define BTN_TRIGGER_HAPPY5\t\t0x2c4\n#define BTN_TRIGGER_HAPPY6\t\t0x2c5\n#define BTN_TRIGGER_HAPPY7\t\t0x2c6\n#define BTN_TRIGGER_HAPPY8\t\t0x2c7\n#define BTN_TRIGGER_HAPPY9\t\t0x2c8\n#define BTN_TRIGGER_HAPPY10\t\t0x2c9\n#define BTN_TRIGGER_HAPPY11\t\t0x2ca\n#define BTN_TRIGGER_HAPPY12\t\t0x2cb\n#define BTN_TRIGGER_HAPPY13\t\t0x2cc\n#define BTN_TRIGGER_HAPPY14\t\t0x2cd\n#define BTN_TRIGGER_HAPPY15\t\t0x2ce\n#define BTN_TRIGGER_HAPPY16\t\t0x2cf\n#define BTN_TRIGGER_HAPPY17\t\t0x2d0\n#define BTN_TRIGGER_HAPPY18\t\t0x2d1\n#define BTN_TRIGGER_HAPPY19\t\t0x2d2\n#define BTN_TRIGGER_HAPPY20\t\t0x2d3\n#define BTN_TRIGGER_HAPPY21\t\t0x2d4\n#define BTN_TRIGGER_HAPPY22\t\t0x2d5\n#define BTN_TRIGGER_HAPPY23\t\t0x2d6\n#define BTN_TRIGGER_HAPPY24\t\t0x2d7\n#define BTN_TRIGGER_HAPPY25\t\t0x2d8\n#define BTN_TRIGGER_HAPPY26\t\t0x2d9\n#define BTN_TRIGGER_HAPPY27\t\t0x2da\n#define BTN_TRIGGER_HAPPY28\t\t0x2db\n#define BTN_TRIGGER_HAPPY29\t\t0x2dc\n#define BTN_TRIGGER_HAPPY30\t\t0x2dd\n#define BTN_TRIGGER_HAPPY31\t\t0x2de\n#define BTN_TRIGGER_HAPPY32\t\t0x2df\n#define BTN_TRIGGER_HAPPY33\t\t0x2e0\n#define BTN_TRIGGER_HAPPY34\t\t0x2e1\n#define BTN_TRIGGER_HAPPY35\t\t0x2e2\n#define BTN_TRIGGER_HAPPY36\t\t0x2e3\n#define BTN_TRIGGER_HAPPY37\t\t0x2e4\n#define BTN_TRIGGER_HAPPY38\t\t0x2e5\n#define BTN_TRIGGER_HAPPY39\t\t0x2e6\n#define BTN_TRIGGER_HAPPY40\t\t0x2e7\n\n/* We avoid low common keys in module aliases so they don't get huge. */\n#define KEY_MIN_INTERESTING\tKEY_MUTE\n#define KEY_MAX\t\t\t0x2ff\n#define KEY_CNT\t\t\t(KEY_MAX+1)\n\n/*\n * Relative axes\n */\n\n#define REL_X\t\t\t0x00\n#define REL_Y\t\t\t0x01\n#define REL_Z\t\t\t0x02\n#define REL_RX\t\t\t0x03\n#define REL_RY\t\t\t0x04\n#define REL_RZ\t\t\t0x05\n#define REL_HWHEEL\t\t0x06\n#define REL_DIAL\t\t0x07\n#define REL_WHEEL\t\t0x08\n#define REL_MISC\t\t0x09\n#define REL_MAX\t\t\t0x0f\n#define REL_CNT\t\t\t(REL_MAX+1)\n\n/*\n * Absolute axes\n */\n\n#define ABS_X\t\t\t0x00\n#define ABS_Y\t\t\t0x01\n#define ABS_Z\t\t\t0x02\n#define ABS_RX\t\t\t0x03\n#define ABS_RY\t\t\t0x04\n#define ABS_RZ\t\t\t0x05\n#define ABS_THROTTLE\t\t0x06\n#define ABS_RUDDER\t\t0x07\n#define ABS_WHEEL\t\t0x08\n#define ABS_GAS\t\t\t0x09\n#define ABS_BRAKE\t\t0x0a\n#define ABS_HAT0X\t\t0x10\n#define ABS_HAT0Y\t\t0x11\n#define ABS_HAT1X\t\t0x12\n#define ABS_HAT1Y\t\t0x13\n#define ABS_HAT2X\t\t0x14\n#define ABS_HAT2Y\t\t0x15\n#define ABS_HAT3X\t\t0x16\n#define ABS_HAT3Y\t\t0x17\n#define ABS_PRESSURE\t\t0x18\n#define ABS_DISTANCE\t\t0x19\n#define ABS_TILT_X\t\t0x1a\n#define ABS_TILT_Y\t\t0x1b\n#define ABS_TOOL_WIDTH\t\t0x1c\n\n#define ABS_VOLUME\t\t0x20\n\n#define ABS_MISC\t\t0x28\n\n#define ABS_MT_SLOT\t\t0x2f\t/* MT slot being modified */\n#define ABS_MT_TOUCH_MAJOR\t0x30\t/* Major axis of touching ellipse */\n#define ABS_MT_TOUCH_MINOR\t0x31\t/* Minor axis (omit if circular) */\n#define ABS_MT_WIDTH_MAJOR\t0x32\t/* Major axis of approaching ellipse */\n#define ABS_MT_WIDTH_MINOR\t0x33\t/* Minor axis (omit if circular) */\n#define ABS_MT_ORIENTATION\t0x34\t/* Ellipse orientation */\n#define ABS_MT_POSITION_X\t0x35\t/* Center X touch position */\n#define ABS_MT_POSITION_Y\t0x36\t/* Center Y touch position */\n#define ABS_MT_TOOL_TYPE\t0x37\t/* Type of touching device */\n#define ABS_MT_BLOB_ID\t\t0x38\t/* Group a set of packets as a blob */\n#define ABS_MT_TRACKING_ID\t0x39\t/* Unique ID of initiated contact */\n#define ABS_MT_PRESSURE\t\t0x3a\t/* Pressure on contact area */\n#define ABS_MT_DISTANCE\t\t0x3b\t/* Contact hover distance */\n#define ABS_MT_TOOL_X\t\t0x3c\t/* Center X tool position */\n#define ABS_MT_TOOL_Y\t\t0x3d\t/* Center Y tool position */\n\n\n#define ABS_MAX\t\t\t0x3f\n#define ABS_CNT\t\t\t(ABS_MAX+1)\n\n/*\n * Switch events\n */\n\n#define SW_LID\t\t\t0x00 /* set = lid shut */\n#define SW_TABLET_MODE\t\t0x01 /* set = tablet mode */\n#define SW_HEADPHONE_INSERT\t0x02 /* set = inserted */\n#define SW_RFKILL_ALL\t\t0x03 /* rfkill master switch, type \"any\"\n\t\t\t\t\t set = radio enabled */\n#define SW_RADIO\t\tSW_RFKILL_ALL\t/* deprecated */\n#define SW_MICROPHONE_INSERT\t0x04 /* set = inserted */\n#define SW_DOCK\t\t\t0x05 /* set = plugged into dock */\n#define SW_LINEOUT_INSERT\t0x06 /* set = inserted */\n#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */\n#define SW_VIDEOOUT_INSERT\t0x08 /* set = inserted */\n#define SW_CAMERA_LENS_COVER\t0x09 /* set = lens covered */\n#define SW_KEYPAD_SLIDE\t\t0x0a /* set = keypad slide out */\n#define SW_FRONT_PROXIMITY\t0x0b /* set = front proximity sensor active */\n#define SW_ROTATE_LOCK\t\t0x0c /* set = rotate locked/disabled */\n#define SW_LINEIN_INSERT\t0x0d /* set = inserted */\n#define SW_MUTE_DEVICE\t\t0x0e /* set = device disabled */\n#define SW_PEN_INSERTED\t\t0x0f /* set = pen inserted */\n#define SW_MAX\t\t\t0x0f\n#define SW_CNT\t\t\t(SW_MAX+1)\n\n/*\n * Misc events\n */\n\n#define MSC_SERIAL\t\t0x00\n#define MSC_PULSELED\t\t0x01\n#define MSC_GESTURE\t\t0x02\n#define MSC_RAW\t\t\t0x03\n#define MSC_SCAN\t\t0x04\n#define MSC_TIMESTAMP\t\t0x05\n#define MSC_MAX\t\t\t0x07\n#define MSC_CNT\t\t\t(MSC_MAX+1)\n\n/*\n * LEDs\n */\n\n#define LED_NUML\t\t0x00\n#define LED_CAPSL\t\t0x01\n#define LED_SCROLLL\t\t0x02\n#define LED_COMPOSE\t\t0x03\n#define LED_KANA\t\t0x04\n#define LED_SLEEP\t\t0x05\n#define LED_SUSPEND\t\t0x06\n#define LED_MUTE\t\t0x07\n#define LED_MISC\t\t0x08\n#define LED_MAIL\t\t0x09\n#define LED_CHARGING\t\t0x0a\n#define LED_MAX\t\t\t0x0f\n#define LED_CNT\t\t\t(LED_MAX+1)\n\n/*\n * Autorepeat values\n */\n\n#define REP_DELAY\t\t0x00\n#define REP_PERIOD\t\t0x01\n#define REP_MAX\t\t\t0x01\n#define REP_CNT\t\t\t(REP_MAX+1)\n\n/*\n * Sounds\n */\n\n#define SND_CLICK\t\t0x00\n#define SND_BELL\t\t0x01\n#define SND_TONE\t\t0x02\n#define SND_MAX\t\t\t0x07\n#define SND_CNT\t\t\t(SND_MAX+1)\n\n#define MATRIX_KEY(row, col, code)\t\\\n\t((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))\n\n#endif /* _DT_BINDINGS_INPUT_INPUT_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/interrupt-controller/irq.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most IRQ bindings.\n *\n * Most IRQ bindings include a flags cell as part of the IRQ specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n\n#define IRQ_TYPE_NONE\t\t0\n#define IRQ_TYPE_EDGE_RISING\t1\n#define IRQ_TYPE_EDGE_FALLING\t2\n#define IRQ_TYPE_EDGE_BOTH\t(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)\n#define IRQ_TYPE_LEVEL_HIGH\t4\n#define IRQ_TYPE_LEVEL_LOW\t8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/phy/phy.h", "content": "/*\n *\n * This header provides constants for the phy framework\n *\n * Copyright (C) 2014 STMicroelectronics\n * Author: Gabriel Fernandez \n * License terms: GNU General Public License (GPL), version 2\n */\n\n#ifndef _DT_BINDINGS_PHY\n#define _DT_BINDINGS_PHY\n\n#define PHY_NONE\t\t0\n#define PHY_TYPE_SATA\t\t1\n#define PHY_TYPE_PCIE\t\t2\n#define PHY_TYPE_USB2\t\t3\n#define PHY_TYPE_USB3\t\t4\n#define PHY_TYPE_UFS\t\t5\n#define PHY_TYPE_DP\t\t6\n#define PHY_TYPE_SGMII\t\t7\n\n#endif /* _DT_BINDINGS_PHY */\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h", "content": "/*\n * MIO pin configuration defines for Xilinx ZynqMP\n *\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Author: Chirag Parekh \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * version 2 as published by the Free Software Foundation.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program. If not, see .\n */\n\n#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H\n#define _DT_BINDINGS_PINCTRL_ZYNQMP_H\n\n/* Bit value for IO standards */\n#define IO_STANDARD_LVCMOS33 0\n#define IO_STANDARD_LVCMOS18 1\n\n/* Bit values for Slew Rates */\n#define SLEW_RATE_FAST 0\n#define SLEW_RATE_SLOW 1\n\n/* Bit values for Pin inputs */\n#define PIN_INPUT_TYPE_CMOS 0\n#define PIN_INPUT_TYPE_SCHMITT 1\n\n/* Bit values for drive control*/\n#define DRIVE_STRENGTH_2MA 2\n#define DRIVE_STRENGTH_4MA 4\n#define DRIVE_STRENGTH_8MA 8\n#define DRIVE_STRENGTH_12MA 12\n\n#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/power/xlnx-versal-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_POWER_H\n#define _DT_BINDINGS_VERSAL_POWER_H\n\n#define PM_DEV_RPU0_0\t\t\t\t(0x18110005U)\n#define PM_DEV_RPU0_1\t\t\t\t(0x18110006U)\n#define PM_DEV_OCM_0\t\t\t\t(0x18314007U)\n#define PM_DEV_OCM_1\t\t\t\t(0x18314008U)\n#define PM_DEV_OCM_2\t\t\t\t(0x18314009U)\n#define PM_DEV_OCM_3\t\t\t\t(0x1831400aU)\n#define PM_DEV_TCM_0_A\t\t\t\t(0x1831800bU)\n#define PM_DEV_TCM_0_B\t\t\t\t(0x1831800cU)\n#define PM_DEV_TCM_1_A\t\t\t\t(0x1831800dU)\n#define PM_DEV_TCM_1_B\t\t\t\t(0x1831800eU)\n#define PM_DEV_USB_0\t\t\t\t(0x18224018U)\n#define PM_DEV_GEM_0\t\t\t\t(0x18224019U)\n#define PM_DEV_GEM_1\t\t\t\t(0x1822401aU)\n#define PM_DEV_SPI_0\t\t\t\t(0x1822401bU)\n#define PM_DEV_SPI_1\t\t\t\t(0x1822401cU)\n#define PM_DEV_I2C_0\t\t\t\t(0x1822401dU)\n#define PM_DEV_I2C_1\t\t\t\t(0x1822401eU)\n#define PM_DEV_CAN_FD_0\t\t\t\t(0x1822401fU)\n#define PM_DEV_CAN_FD_1\t\t\t\t(0x18224020U)\n#define PM_DEV_UART_0\t\t\t\t(0x18224021U)\n#define PM_DEV_UART_1\t\t\t\t(0x18224022U)\n#define PM_DEV_GPIO\t\t\t\t(0x18224023U)\n#define PM_DEV_TTC_0\t\t\t\t(0x18224024U)\n#define PM_DEV_TTC_1\t\t\t\t(0x18224025U)\n#define PM_DEV_TTC_2\t\t\t\t(0x18224026U)\n#define PM_DEV_TTC_3\t\t\t\t(0x18224027U)\n#define PM_DEV_SWDT_FPD\t\t\t\t(0x18224029U)\n#define PM_DEV_OSPI\t\t\t\t(0x1822402aU)\n#define PM_DEV_QSPI\t\t\t\t(0x1822402bU)\n#define PM_DEV_GPIO_PMC\t\t\t\t(0x1822402cU)\n#define PM_DEV_SDIO_0\t\t\t\t(0x1822402eU)\n#define PM_DEV_SDIO_1\t\t\t\t(0x1822402fU)\n#define PM_DEV_RTC\t\t\t\t(0x18224034U)\n#define PM_DEV_ADMA_0\t\t\t\t(0x18224035U)\n#define PM_DEV_ADMA_1\t\t\t\t(0x18224036U)\n#define PM_DEV_ADMA_2\t\t\t\t(0x18224037U)\n#define PM_DEV_ADMA_3\t\t\t\t(0x18224038U)\n#define PM_DEV_ADMA_4\t\t\t\t(0x18224039U)\n#define PM_DEV_ADMA_5\t\t\t\t(0x1822403aU)\n#define PM_DEV_ADMA_6\t\t\t\t(0x1822403bU)\n#define PM_DEV_ADMA_7\t\t\t\t(0x1822403cU)\n#define PM_DEV_AI\t\t\t\t(0x18224072U)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/power/xlnx-zynqmp-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_POWER_H\n#define _DT_BINDINGS_ZYNQMP_POWER_H\n\n#define\t\tPD_RPU\t\t6\n#define\t\tPD_RPU_0\t7\n#define\t\tPD_RPU_1\t8\n#define\t\tPD_OCM_0\t11\n#define\t\tPD_OCM_1\t12\n#define\t\tPD_OCM_2\t13\n#define\t\tPD_OCM_3\t14\n#define\t\tPD_TCM_0_A\t15\n#define\t\tPD_TCM_0_B\t16\n#define\t\tPD_TCM_1_A\t17\n#define\t\tPD_TCM_1_B\t18\n#define\t\tPD_USB_0\t22\n#define\t\tPD_USB_1\t23\n#define\t\tPD_TTC_0\t24\n#define\t\tPD_TTC_1\t25\n#define\t\tPD_TTC_2\t26\n#define\t\tPD_TTC_3\t27\n#define\t\tPD_SATA\t\t28\n#define\t\tPD_ETH_0\t29\n#define\t\tPD_ETH_1\t30\n#define\t\tPD_ETH_2\t31\n#define\t\tPD_ETH_3\t32\n#define\t\tPD_UART_0\t33\n#define\t\tPD_UART_1\t34\n#define\t\tPD_SPI_0\t35\n#define\t\tPD_SPI_1\t36\n#define\t\tPD_I2C_0\t37\n#define\t\tPD_I2C_1\t38\n#define\t\tPD_SD_0\t\t39\n#define\t\tPD_SD_1\t\t40\n#define\t\tPD_DP\t\t41\n#define\t\tPD_GDMA\t\t42\n#define\t\tPD_ADMA\t\t43\n#define\t\tPD_NAND\t\t44\n#define\t\tPD_QSPI\t\t45\n#define\t\tPD_GPIO\t\t46\n#define\t\tPD_CAN_0\t47\n#define\t\tPD_CAN_1\t48\n#define\t\tPD_GPU\t\t58\n#define\t\tPD_PCIE\t\t59\n#define\t\tPD_PL\t\t69\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H\n#define _DT_BINDINGS_ZYNQMP_RESETS_H\n\n#define\t\tZYNQMP_RESET_PCIE_CFG\t\t0\n#define\t\tZYNQMP_RESET_PCIE_BRIDGE\t1\n#define\t\tZYNQMP_RESET_PCIE_CTRL\t\t2\n#define\t\tZYNQMP_RESET_DP\t\t\t3\n#define\t\tZYNQMP_RESET_SWDT_CRF\t\t4\n#define\t\tZYNQMP_RESET_AFI_FM5\t\t5\n#define\t\tZYNQMP_RESET_AFI_FM4\t\t6\n#define\t\tZYNQMP_RESET_AFI_FM3\t\t7\n#define\t\tZYNQMP_RESET_AFI_FM2\t\t8\n#define\t\tZYNQMP_RESET_AFI_FM1\t\t9\n#define\t\tZYNQMP_RESET_AFI_FM0\t\t10\n#define\t\tZYNQMP_RESET_GDMA\t\t11\n#define\t\tZYNQMP_RESET_GPU_PP1\t\t12\n#define\t\tZYNQMP_RESET_GPU_PP0\t\t13\n#define\t\tZYNQMP_RESET_GPU\t\t14\n#define\t\tZYNQMP_RESET_GT\t\t\t15\n#define\t\tZYNQMP_RESET_SATA\t\t16\n#define\t\tZYNQMP_RESET_ACPU3_PWRON\t17\n#define\t\tZYNQMP_RESET_ACPU2_PWRON\t18\n#define\t\tZYNQMP_RESET_ACPU1_PWRON\t19\n#define\t\tZYNQMP_RESET_ACPU0_PWRON\t20\n#define\t\tZYNQMP_RESET_APU_L2\t\t21\n#define\t\tZYNQMP_RESET_ACPU3\t\t22\n#define\t\tZYNQMP_RESET_ACPU2\t\t23\n#define\t\tZYNQMP_RESET_ACPU1\t\t24\n#define\t\tZYNQMP_RESET_ACPU0\t\t25\n#define\t\tZYNQMP_RESET_DDR\t\t26\n#define\t\tZYNQMP_RESET_APM_FPD\t\t27\n#define\t\tZYNQMP_RESET_SOFT\t\t28\n#define\t\tZYNQMP_RESET_GEM0\t\t29\n#define\t\tZYNQMP_RESET_GEM1\t\t30\n#define\t\tZYNQMP_RESET_GEM2\t\t31\n#define\t\tZYNQMP_RESET_GEM3\t\t32\n#define\t\tZYNQMP_RESET_QSPI\t\t33\n#define\t\tZYNQMP_RESET_UART0\t\t34\n#define\t\tZYNQMP_RESET_UART1\t\t35\n#define\t\tZYNQMP_RESET_SPI0\t\t36\n#define\t\tZYNQMP_RESET_SPI1\t\t37\n#define\t\tZYNQMP_RESET_SDIO0\t\t38\n#define\t\tZYNQMP_RESET_SDIO1\t\t39\n#define\t\tZYNQMP_RESET_CAN0\t\t40\n#define\t\tZYNQMP_RESET_CAN1\t\t41\n#define\t\tZYNQMP_RESET_I2C0\t\t42\n#define\t\tZYNQMP_RESET_I2C1\t\t43\n#define\t\tZYNQMP_RESET_TTC0\t\t44\n#define\t\tZYNQMP_RESET_TTC1\t\t45\n#define\t\tZYNQMP_RESET_TTC2\t\t46\n#define\t\tZYNQMP_RESET_TTC3\t\t47\n#define\t\tZYNQMP_RESET_SWDT_CRL\t\t48\n#define\t\tZYNQMP_RESET_NAND\t\t49\n#define\t\tZYNQMP_RESET_ADMA\t\t50\n#define\t\tZYNQMP_RESET_GPIO\t\t51\n#define\t\tZYNQMP_RESET_IOU_CC\t\t52\n#define\t\tZYNQMP_RESET_TIMESTAMP\t\t53\n#define\t\tZYNQMP_RESET_RPU_R50\t\t54\n#define\t\tZYNQMP_RESET_RPU_R51\t\t55\n#define\t\tZYNQMP_RESET_RPU_AMBA\t\t56\n#define\t\tZYNQMP_RESET_OCM\t\t57\n#define\t\tZYNQMP_RESET_RPU_PGE\t\t58\n#define\t\tZYNQMP_RESET_USB0_CORERESET\t59\n#define\t\tZYNQMP_RESET_USB1_CORERESET\t60\n#define\t\tZYNQMP_RESET_USB0_HIBERRESET\t61\n#define\t\tZYNQMP_RESET_USB1_HIBERRESET\t62\n#define\t\tZYNQMP_RESET_USB0_APB\t\t63\n#define\t\tZYNQMP_RESET_USB1_APB\t\t64\n#define\t\tZYNQMP_RESET_IPI\t\t65\n#define\t\tZYNQMP_RESET_APM_LPD\t\t66\n#define\t\tZYNQMP_RESET_RTC\t\t67\n#define\t\tZYNQMP_RESET_SYSMON\t\t68\n#define\t\tZYNQMP_RESET_AFI_FM6\t\t69\n#define\t\tZYNQMP_RESET_LPD_SWDT\t\t70\n#define\t\tZYNQMP_RESET_FPD\t\t71\n#define\t\tZYNQMP_RESET_RPU_DBG1\t\t72\n#define\t\tZYNQMP_RESET_RPU_DBG0\t\t73\n#define\t\tZYNQMP_RESET_DBG_LPD\t\t74\n#define\t\tZYNQMP_RESET_DBG_FPD\t\t75\n#define\t\tZYNQMP_RESET_APLL\t\t76\n#define\t\tZYNQMP_RESET_DPLL\t\t77\n#define\t\tZYNQMP_RESET_VPLL\t\t78\n#define\t\tZYNQMP_RESET_IOPLL\t\t79\n#define\t\tZYNQMP_RESET_RPLL\t\t80\n#define\t\tZYNQMP_RESET_GPO3_PL_0\t\t81\n#define\t\tZYNQMP_RESET_GPO3_PL_1\t\t82\n#define\t\tZYNQMP_RESET_GPO3_PL_2\t\t83\n#define\t\tZYNQMP_RESET_GPO3_PL_3\t\t84\n#define\t\tZYNQMP_RESET_GPO3_PL_4\t\t85\n#define\t\tZYNQMP_RESET_GPO3_PL_5\t\t86\n#define\t\tZYNQMP_RESET_GPO3_PL_6\t\t87\n#define\t\tZYNQMP_RESET_GPO3_PL_7\t\t88\n#define\t\tZYNQMP_RESET_GPO3_PL_8\t\t89\n#define\t\tZYNQMP_RESET_GPO3_PL_9\t\t90\n#define\t\tZYNQMP_RESET_GPO3_PL_10\t\t91\n#define\t\tZYNQMP_RESET_GPO3_PL_11\t\t92\n#define\t\tZYNQMP_RESET_GPO3_PL_12\t\t93\n#define\t\tZYNQMP_RESET_GPO3_PL_13\t\t94\n#define\t\tZYNQMP_RESET_GPO3_PL_14\t\t95\n#define\t\tZYNQMP_RESET_GPO3_PL_15\t\t96\n#define\t\tZYNQMP_RESET_GPO3_PL_16\t\t97\n#define\t\tZYNQMP_RESET_GPO3_PL_17\t\t98\n#define\t\tZYNQMP_RESET_GPO3_PL_18\t\t99\n#define\t\tZYNQMP_RESET_GPO3_PL_19\t\t100\n#define\t\tZYNQMP_RESET_GPO3_PL_20\t\t101\n#define\t\tZYNQMP_RESET_GPO3_PL_21\t\t102\n#define\t\tZYNQMP_RESET_GPO3_PL_22\t\t103\n#define\t\tZYNQMP_RESET_GPO3_PL_23\t\t104\n#define\t\tZYNQMP_RESET_GPO3_PL_24\t\t105\n#define\t\tZYNQMP_RESET_GPO3_PL_25\t\t106\n#define\t\tZYNQMP_RESET_GPO3_PL_26\t\t107\n#define\t\tZYNQMP_RESET_GPO3_PL_27\t\t108\n#define\t\tZYNQMP_RESET_GPO3_PL_28\t\t109\n#define\t\tZYNQMP_RESET_GPO3_PL_29\t\t110\n#define\t\tZYNQMP_RESET_GPO3_PL_30\t\t111\n#define\t\tZYNQMP_RESET_GPO3_PL_31\t\t112\n#define\t\tZYNQMP_RESET_RPU_LS\t\t113\n#define\t\tZYNQMP_RESET_PS_ONLY\t\t114\n#define\t\tZYNQMP_RESET_PL\t\t\t115\n#define\t\tZYNQMP_RESET_PS_PL0\t\t116\n#define\t\tZYNQMP_RESET_PS_PL1\t\t117\n#define\t\tZYNQMP_RESET_PS_PL2\t\t118\n#define\t\tZYNQMP_RESET_PS_PL3\t\t119\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/versal/versal-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-versal-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-power.h\"\n/ {\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tcan0_clk: can0_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN0_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tcan1_clk: can1_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN1_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk ACPU>;\n};\n\n&can0 {\n\tclocks = <&can0_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_0>;\n};\n\n&can1 {\n\tclocks = <&can1_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_1>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_0>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_1>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk PMC_LSBUS_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO_PMC>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk I2C0_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_0>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk I2C1_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_1>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_0>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_1>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_2>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_3>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_4>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_5>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_6>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_7>;\n};\n\n&qspi {\n\tclocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_QSPI>;\n};\n\n&ospi {\n\tclocks = <&versal_clk OSPI_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_OSPI>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware PM_DEV_RTC>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_0>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_1>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_0>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_1>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_0>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_1>;\n};\n\n&ttc0 {\n\tclocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_0>;\n};\n\n&ttc1 {\n\tclocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_1>;\n};\n\n&ttc2 {\n\tclocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_2>;\n};\n\n&ttc3 {\n\tclocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_3>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_USB_0>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SWDT_FPD>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/versal/versal-spp-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\talt_ref_clk: alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware-wip\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"alt_ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk 77>;\n};\n\n&can0 {\n\tclocks = <&versal_clk 96>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401f>;\n};\n\n&can1 {\n\tclocks = <&versal_clk 97>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224020>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x18224019>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x1822401a>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk 61>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk 98>;\n\tpower-domains = <&versal_firmware 0x1822401d>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk 99>;\n\tpower-domains = <&versal_firmware 0x1822401e>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224035>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224036>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224037>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224038>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224039>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403a>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403b>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403c>;\n};\n\n&qspi {\n\tclocks = <&versal_clk 57>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402b>;\n};\n\n&ospi {\n\tclocks = <&versal_clk 58>, <&versal_clk 82>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware 0x18224034>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk 92>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224021>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk 93>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224022>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk 59>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402e>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk 60>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402f>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk 94>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401b>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk 95>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401c>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk 91>, <&versal_clk 104>;\n\tpower-domains = <&versal_firmware 0x18224018>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk 82>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/versal/versal.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal\";\n\n\tcpus: cpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <1>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tfpga: fpga {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&versal_fpga>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tpsci: psci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t};\n\n\tversal_fpga: versal_fpga {\n\t\tcompatible = \"xlnx,versal-fpga\";\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t\tinterrupt-parent = <&gic>;\n\t\tu-boot,dm-pre-reloc;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\t\t\treg = <0 0xf9000000 0 0x80000>, /* GICD */\n\t\t\t <0 0xf9080000 0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\n\t\t\tgic_its: gic-its@f9020000 {\n\t\t\t\tcompatible = \"arm,gic-v3-its\";\n\t\t\t\tmsi-controller;\n\t\t\t\tmsi-cells = <1>;\n\t\t\t\treg = <0 0xf9020000 0 0x20000>;\n\t\t\t};\n\t\t};\n\n\t\tapm: performance-monitor@f0920000 {\n\t\t\tcompatible = \"xlnx,flexnoc-pm-2.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg-names = \"funnel\", \"baselpd\", \"basefpd\";\n\t\t\treg = <0x0 0xf0920000 0x0 0x1000>,\n\t\t\t <0x0 0xf0980000 0x0 0x9000>,\n\t\t\t <0x0 0xf0b80000 0x0 0x9000>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff060000 0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff070000 0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcci: cci@fd000000 {\n\t\t\tcompatible = \"arm,cci-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd000000 0 0x10000>;\n\t\t\tranges = <0 0 0xfd000000 0xa0000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcci_pmu: pmu@10000 {\n\t\t\t\tcompatible = \"arm,cci-500-pmu,r0\";\n\t\t\t\treg = <0x10000 0x90000>;\n\t\t\t\tinterrupts = <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>;\n\t\t\t};\n\t\t};\n\n\t\tlpd_dma_chan0: dma@ffa80000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa80000 0 0x1000>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa90000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa90000 0 0x1000>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffaa0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaa0000 0 0x1000>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\n\t\tlpd_dma_chan3: dma@ffab0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffab0000 0 0x1000>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffac0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffac0000 0 0x1000>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffad0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffad0000 0 0x1000>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffae0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffae0000 0 0x1000>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffaf0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaf0000 0 0x1000>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tgem0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,versal-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0c0000 0 0x1000>;\n\t\t\tinterrupts = <0 56 4>, <0 56 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,versal-gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0d0000 0 0x1000>;\n\t\t\tinterrupts = <0 58 4>, <0 58 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tgpio0: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0b0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff020000 0 0x1000>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff030000 0 0x1000>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tmc0: memory-controller@f6150000\t{\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <0>;\n\t\t};\n\n\t\tmc1: memory-controller@f62c0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <1>;\n\t\t};\n\n\t\tmc2: memory-controller@f6430000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <2>;\n\t\t};\n\n\t\tmc3: memory-controller@f65a0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <3>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tcalibration = <0x7FFF>;\n\t\t};\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff000000 0 0x1000>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tserial1: serial@ff010000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff010000 0 0x1000>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd800000 0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 124 4>, <0 124 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,is-stig-pgm = <1>;\n\t\t\tcdns,trigger-address = <0xC0000000>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff040000 0 0x1000>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff050000 0 0x1000>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsysmon: sysmon@f1270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\treg = <0x0 0xf1270000 0x0 0x4000>;\n\t\t\tinterrupts = <0 144 4>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tttc0: timer@ff0e0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff0f0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 40 4>, <0 41 4>, <0 42 4>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff100000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 46 4>, <0 47 4>, <0 48 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tusb0: usb@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff9d0000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0 0xfe200000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"usb-wakeup\";\n\t\t\t\tinterrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,mask_phy_reset;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\tcpm_pciea: pci@fca10000 {\n\t\t\t#address-cells = <3>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"xlnx,versal-cpm-host-1.00\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc_0 0>,\n\t\t\t\t\t<0 0 0 2 &pcie_intc_0 1>,\n\t\t\t\t\t<0 0 0 3 &pcie_intc_0 2>,\n\t\t\t\t\t<0 0 0 4 &pcie_intc_0 3>;\n\t\t\tinterrupt-map-mask = <0 0 0 7>;\n\t\t\tinterrupt-names = \"misc\";\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>,\n\t\t\t\t <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>;\n\t\t\tmsi-map = <0x0 &gic_its 0x0 0x10000>;\n\t\t\treg = <0x0 0xfca10000 0x0 0x1000>,\n\t\t\t <0x6 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"cpm_slcr\", \"cfg\";\n\t\t\tpcie_intc_0: pci-interrupt-controller {\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\tinterrupt-controller ;\n\t\t\t};\n\t\t};\n\n\t\twatchdog: watchdog@fd4d0000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd4d0000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 0x64 1>, <0 0x6D 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t};\n\t};\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/zynq/zynq-7000.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\treplicator {\n\t\tcompatible = \"arm,coresight-static-replicator\";\n\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\tout-ports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\t/* replicator output ports */\n\t\t\tport@0 {\n\t\t\t\treg = <0>;\n\t\t\t\treplicator_out_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&tpiu_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tport@1 {\n\t\t\t\treg = <1>;\n\t\t\t\treplicator_out_port1: endpoint {\n\t\t\t\t\tremote-endpoint = <&etb_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tin-ports {\n\t\t\t/* replicator input port */\n\t\t\tport {\n\t\t\t\treplicator_in_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&funnel_out_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tamba: axi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"apb_pclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\", \"arm,primecell\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tranges ;\n\t\t\treg = <0xe000e000 0x1000>;\n\t\t\tnand0: flash@e1000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0xe1000000 0x1000000>;\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x1>;\n\t\t\t};\n\t\t\tnor0: flash@e2000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <0xe2000000 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsdhci0: mmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: mmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\tetb@f8801000 {\n\t\t\tcompatible = \"arm,coresight-etb10\", \"arm,primecell\";\n\t\t\treg = <0xf8801000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\tetb_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ttpiu@f8803000 {\n\t\t\tcompatible = \"arm,coresight-tpiu\", \"arm,primecell\";\n\t\t\treg = <0xf8803000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\ttpiu_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tfunnel@f8804000 {\n\t\t\tcompatible = \"arm,coresight-static-funnel\", \"arm,primecell\";\n\t\t\treg = <0xf8804000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\t\t/* funnel output ports */\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tfunnel_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint =\n\t\t\t\t\t\t\t<&replicator_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tin-ports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\t/* funnel input ports */\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tfunnel0_in_port0: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm0_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tfunnel0_in_port1: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm1_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tfunnel0_in_port2: endpoint {\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t/* The other input ports are not connect to anything */\n\t\t\t};\n\t\t};\n\n\t\tptm@f889c000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889c000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu0>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm0_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889d000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889d000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu1>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm1_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/zynqmp/zynqmp-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-zynqmp-clk.h\"\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL0_REF>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL1_REF>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL2_REF>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL3_REF>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tdp_aclk: dp_aclk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&zynqmp_firmware {\n\tzynqmp_clk: clock-controller {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,\n\t\t\t <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\",\n\t\t\t \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t};\n};\n\n&can0 {\n\tclocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&can1 {\n\tclocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&cpu0 {\n\tclocks = <&zynqmp_clk ACPU>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gpu {\n\tclocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&nand0 {\n\tclocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gem0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>,\n\t\t <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>,\n\t\t <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>,\n\t\t <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gem3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>,\n\t\t <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>;\n\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n};\n\n&gpio {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&i2c0 {\n\tclocks = <&zynqmp_clk I2C0_REF>;\n};\n\n&i2c1 {\n\tclocks = <&zynqmp_clk I2C1_REF>;\n};\n\n&perf_monitor_ocm {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&perf_monitor_ddr {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_cci {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_lpd {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&pcie {\n\tclocks = <&zynqmp_clk PCIE_REF>;\n};\n\n&qspi {\n\tclocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&sata {\n\tclocks = <&zynqmp_clk SATA_REF>;\n};\n\n&sdhci0 {\n\tclocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&sdhci1 {\n\tclocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&spi0 {\n\tclocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&spi1 {\n\tclocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart0 {\n\tclocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart1 {\n\tclocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&usb0 {\n\tclocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&usb1 {\n\tclocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&watchdog0 {\n\tclocks = <&zynqmp_clk WDT>;\n};\n\n&lpd_watchdog {\n\tclocks = <&zynqmp_clk LPD_WDT>;\n};\n\n&xilinx_ams {\n\tclocks = <&zynqmp_clk AMS_REF>;\n};\n\n&zynqmp_dpdma {\n\tclocks = <&zynqmp_clk DPDMA_REF>;\n};\n\n&zynqmp_dpsub {\n\tclocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>;\n};\n\n&zynqmp_dp_snd_codec0 {\n\tclocks = <&zynqmp_clk DP_AUDIO_REF>;\n};\n\n&zynqmp_pcap {\n\tclocks = <&zynqmp_clk PCAP>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2021.2/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n#include \"include/dt-bindings/dma/xlnx-zynqmp-dpdma.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/power/xlnx-zynqmp-power.h\"\n#include \"include/dt-bindings/reset/xlnx-zynqmp-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu-opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tzynqmp_ipi: zynqmp_ipi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t\txlnx,ipi-id = <0>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff990400 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\treg = <0x0 0xff9905c0 0x0 0x20>,\n\t\t\t <0x0 0xff9905e0 0x0 0x20>,\n\t\t\t <0x0 0xff990e80 0x0 0x20>,\n\t\t\t <0x0 0xff990ea0 0x0 0x20>;\n\t\t\treg-names = \"local_request_region\",\n\t\t\t\t \"local_response_region\",\n\t\t\t\t \"remote_request_region\",\n\t\t\t\t \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <4>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tzynqmp_firmware: zynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x1>;\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tnvmem_firmware {\n\t\t\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tsoc_revision: soc_revision@0 {\n\t\t\t\t\treg = <0x0 0x4>;\n\t\t\t\t};\n\t\t\t\t/* efuse access */\n\t\t\t\tefuse_dna: efuse_dna@c {\n\t\t\t\t\treg = <0xc 0xc>;\n\t\t\t\t};\n\t\t\t\tefuse_usr0: efuse_usr0@20 {\n\t\t\t\t\treg = <0x20 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr1: efuse_usr1@24 {\n\t\t\t\t\treg = <0x24 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr2: efuse_usr2@28 {\n\t\t\t\t\treg = <0x28 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr3: efuse_usr3@2c {\n\t\t\t\t\treg = <0x2c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr4: efuse_usr4@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr5: efuse_usr5@34 {\n\t\t\t\t\treg = <0x34 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr6: efuse_usr6@38 {\n\t\t\t\t\treg = <0x38 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr7: efuse_usr7@3c {\n\t\t\t\t\treg = <0x3c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_miscusr: efuse_miscusr@40 {\n\t\t\t\t\treg = <0x40 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_chash: efuse_chash@50 {\n\t\t\t\t\treg = <0x50 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_pufmisc: efuse_pufmisc@54 {\n\t\t\t\t\treg = <0x54 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_sec: efuse_sec@58 {\n\t\t\t\t\treg = <0x58 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_spkid: efuse_spkid@5c {\n\t\t\t\t\treg = <0x5c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_ppk0hash: efuse_ppk0hash@a0 {\n\t\t\t\t\treg = <0xa0 0x30>;\n\t\t\t\t};\n\t\t\t\tefuse_ppk1hash: efuse_ppk1hash@d0 {\n\t\t\t\t\treg = <0xd0 0x30>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tzynqmp_pcap: pcap {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t\t\t\tclock-names = \"ref_clk\";\n\t\t\t};\n\n\t\t\txlnx_aes: zynqmp-aes {\n\t\t\t\tcompatible = \"xlnx,zynqmp-aes\";\n\t\t\t};\n\n\t\t\tzynqmp_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\txlnx_keccak_384: sha384 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-keccak-384\";\n\t\t\t};\n\n\t\t\txlnx_rsa: zynqmp-rsa {\n\t\t\t\tcompatible = \"xlnx,zynqmp-rsa\";\n\t\t\t};\n\n\t\t\tmodepin_gpio: gpio {\n\t\t\t\tcompatible = \"xlnx,zynqmp-gpio-modepin\";\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&zynqmp_pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t};\n\n\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x0 0x10000>,\n\t\t\t <0x0 0xf9020000 0x0 0x20000>,\n\t\t\t <0x0 0xf9040000 0x0 0x20000>,\n\t\t\t <0x0 0xf9060000 0x0 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\", \"gpu_pp0\", \"gpu_pp1\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPU>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand-controller@ff100000 {\n\t\t\tcompatible = \"xlnx,zynqmp-nand-controller\", \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"controller\", \"bus\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_NAND>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPIO>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tperf_monitor_ocm: perf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa00000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_ddr: perf-monitor@fd0b0000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd0b0000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <6>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <10>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_cci: perf-monitor@fd490000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd490000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_lpd: perf-monitor@ffa10000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa10000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x4d0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_PCIE>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_QSPI>;\n\t\t};\n\n\t\tpsgtr: phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\";\n\t\t\t#phy-cells = <4>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x7FFF>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SATA>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SATA>;\n\t\t\t#stream-id-cells = <4>;\n\t\t/*\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;*/\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_0>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_1>;\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_0>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\t\t\treset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tranges;\n\n\t\t\tdwc3_0: dwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>, <0 75 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t\t/* snps,enable-hibernation; */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb1@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_1>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\n\t\t\tranges;\n\n\t\t\tdwc3_1: dwc3@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>, <0 76 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <60>;\n\t\t\treset-on-timeout;\n\t\t};\n\n\t\tlpd_watchdog: watchdog@ff150000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 52 1>;\n\t\t\treg = <0x0 0xff150000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges;\n\n\t\t\tams_ps: ams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50800 0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50c00 0x0 0x400>;\n\t\t\t};\n\t\t};\n\n\t\tzynqmp_dpdma: dma-controller@fd4c0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tdma-channels = <6>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0xce4>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tzynqmp_dpsub: display@fd4a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t\treg-names = \"dp\", \"blend\", \"av_buf\", \"aud\";\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0xce3>;\n\t\t\tclock-names = \"dp_apb_clk\", \"dp_aud_clk\", \"dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_DP>;\n\t\t\tdma-names = \"vid0\", \"vid1\", \"vid2\", \"gfx0\";\n\t\t\tdmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;\n\n\t\t\t/* dummy node to to indicate there's no child i2c device */\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm0\";\n\t\t\t\tdmas = <&zynqmp_dpdma 4>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm1\";\n\t\t\t\tdmas = <&zynqmp_dpdma 5>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card0: zynqmp_dp_snd_card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,\n\t\t\t\t\t\t <&zynqmp_dp_snd_pcm1>;\n\t\t\t\txlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n\n\tsi5335_0: si5335_0 { /* clk0_usb - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5335_1: si5335_1 { /* clk1_dp - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 IRQ_TYPE_LEVEL_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO3\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO2\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO1\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n};\n\n&psgtr {\n\t/* usb3, dp */\n\tclocks = <&si5335_0>, <&si5335_1>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"super-speed\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/kcu105-tmr.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&tmr_0_MB1_axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/sp701-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze sp701.\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@1 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x3>;\n\t\t\tti,tx-internal-delay = <0x3>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/vcu118-rev2.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze vcu118\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@3 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\tti,sgmii-ref-clock-output-enable;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\treg = <3>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-a2197-sc-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller RevA\";\n\tcompatible = \"xlnx,versal-sc-revA\", \"xlnx,versal-sc\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = &eeprom; \n\t};\n\n\t/* SC Bank 43\n\tFIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS\n\tSYSCTLR_GPIO0 - 5 - conneced to versal */\n\t/* cpu thermal for MAX6643 fan control */\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tdc38_led {\n\t\t\tlabel = \"ds38-green\"; /* sc AB11 500_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc37_led {\n\t\t\tlabel = \"ds37-green\"; /* sc AD10 501_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc36_led {\n\t\t\tlabel = \"ds36-green\"; /* sc AD11 502_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t};\n};\n\n/* usb - type C - pl\n and micro usb 2.0, gt\n*/\n/* Feb 28/2019 version */\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n/* TODO\nUSB0 MIO52-63\nUSB1 MIO64-75\n*/\n\n/*eth MDIO 76/77\neth reset MIO42\nmarwell m88e1512 - SGMII */\n&gem0 {\n\tphy-handle = <&phy0>;\n\t/* phy-mode = \"sgmii\"; DTG generates this properly */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: phy@21 {\n\t\treg = <21>; /* FIXME */\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5- 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 0 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\"; /* FIXME no linux driver */\n\t\t\t\treg = <0xc0>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <10000000>; /* 10 ohm */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\ti2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* FIXME connection to Samtec J212D */\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t/* FIXME connection to Samtec J53C */\n\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@5d { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@5d { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@5d { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"LPDDR4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-emu-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-emu-itr8\", \"xlnx,versal-emu\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal EMU ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:9600\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n\n\tclk0212: clk0212 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <212000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n};\n\n&timer {\n clock-frequency = <440000>;\n};\n\n&serial0 {\n status = \"okay\";\n clocks = <&clk0212 &clk0212>;\n\tcurrent-speed = <9600>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-spp-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-spp-itr8-cn13940875\", \"xlnx,versal-spp-itr8\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal SPP ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &ospi;\n\t\tspi2 = &spi0;\n\t\tspi3 = &spi1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tusb0 = &usb0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>;\n\t};\n\tchosen {\n\t\tbootargs = \"rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n};\n\n&timer {\n\tclock-frequency = <2720000>;\n};\n\n&serial0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tmaximum-speed = \"high-speed\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n phy0: phy@0 {\n\t\treg = <0x0>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n phy1: phy@1 {\n\t\treg = <0x1>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <0x1>;\n\treg = <0x0 0xf1030000 0x0 0x1000>;\n\tclocks = <&clk125 &clk125>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot-boot.bin\";\n\t\t\t\treg = <0x0 0x6400000>;\n\t\t\t};\n\t\t\tpartition@6400000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x6400000 0x500000>;\n\t\t\t};\n\t\t\tpartition@6900000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x6900000 0x20000>;\n\t\t\t};\n\t\t\tpartition@6920000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x6920000 0x5E0000>;\n\t\t\t};\n\t\t\tpartition@7f40000 {\n\t\t\t\tlabel = \"qspi-bootenv\";\n\t\t\t\treg = <0x7f40000 0x40000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ospi {\n\tstatus = \"disabled\";\n\tclocks = <&clk125 &clk125>;\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\tcdns,fifo-depth = <508>;\n\tcdns,fifo-width = <4>;\n\tcdns,is-dma = <1>;\n\tcdns,is-stig-pgm = <1>;\n\tcdns,trigger-address = <0x00000000>;\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t};\n\t\t\tpartition@600000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t};\n\t\t\tpartition@620000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <1>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <3>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\treg = <0x0 0x84000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-v350-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal v350 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-v350-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal v350 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tspi0 = &ospi;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-01 revA OSPI\";\n\n\taliases {\n\t\tspi0 = &ospi;\n\t};\n};\n\n/* Mutually exclusive */\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n compatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n \"xlnx,versal-vc-p-a2197-00\",\n \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n model = \"Xilinx Versal A2197 Processor board revA\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tgpio0 = &gpio;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-01 revA QSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-02 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem0 {\n\tphy-handle = <&phy0>; /* u9 */\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@1 { /* Marvell 88E1512; U9 */\n\t\treg = <1>;\n\t};\n};\n\n&sdhci0 {\n\txlnx,mio-bank = <1>;\n};\n\n&sdhci1 { /* U1A */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* U4 */\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"high-speed\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* U12 Catalyst EEPROM - AT24 should be equivalent */\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U13 and U15 */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U18 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <3>;\t/* FIXME - check SPI1_SS0-2_B */\n\n\tflash@0 { /* U19 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst26vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-03 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tserial0 = &serial0;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* Must be enabled via J90/J91 */\n\teeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 64Mb */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x800000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* J99 MIO28 - MIO33 */\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U6 - IS25LQ032B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lq032b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-04 revA OSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem1 {\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <1>; /* FIXME */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"disabled\"; /* u93 and u92 and u161 and u160 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio-bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-04 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <2>;\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <1>;\n\tis-dual = <0>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 512MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x20000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-05 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem0 {\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 { /* 88e1510 */\n\t\treg = <1>;\n\t};\n\tphy2: phy@2 { /* VSC8531 */\n\t\treg = <2>;\n\t\tvsc8531,rx-delay = <6>;\n\t\tvsc8531,tx-delay = <6>;\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>;\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tspi-tx-bus-width = <4>;\n\tspi-rx-bus-width = <4>;\n\n\tflash@0 { /* MX25U12835 128Mbit */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 16MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <104000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x1000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc0 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n};\n\n&sdhci1 { /* connector */\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA\";\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 {\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-01-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-01-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (QSPI)\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-02-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-02-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (EMMC)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-03-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-03-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (OSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva-x-ebm-01-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-01-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (QSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva-x-ebm-02-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-02-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (EMMC)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva-x-ebm-03-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-03-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (OSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck5000-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck5000 revA\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vck5000-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck5000 board revA\";\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tspi0 = &ospi;\n\t};\n\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x10000000>;\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vhk158-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VHK158 revA\n *\n * (C) Copyright 2022-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vhk158-revA\", \"xlnx,versal-vhk158\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vhk158 Eval board revA\";\n\n\tmemory: memory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* ZU4_TRIGGER - PMC MIO37 */\n/* PCIE_PWRBRK - PMC MIO38 */\n/* I2C SYSMON - PMC MIO39 - 41 */\n/* VCCPSLP_EN - PMC MIO49 */\n/* PCIE_WAKE - PMC MIO50 */\n/* SOC_EN - LPD MIO13 */\n/* PSFP_EN - LPD MIO15 */\n/* AUX_1V2_EN - LPD MIO16 */\n/* HBM_EN - LPD MIO17 */\n/* PCIE_PERST - LPD MIO18/19 */\n/* VCC_PL_EN - LPD MIO20 */\n/* FAN - LPD MIO21/22 */\n/* VADJ_FMC_EN - LPD MIO23 */\n\n&ospi { /* PMC MIO0 - 12, U297 MT35XU02G */\n\tstatus = \"okay\";\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = ;\n\t\t\tti,tx-internal-delay = ;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-virt.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-virt\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal Virtual\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tclk2: clk2 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <2670000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t\tclock-frequency = <2720000>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */\n\t\t\t <0x0 0xf9080000 0x0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x1 0x9 4>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x2>;\n\t\tranges;\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff060000 0x0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff070000 0x0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom1: eeprom@53 {\n\t\t\t\treg = <0x53>;\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t};\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom2: eeprom@55 {\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x55>;\n\t\t\t};\n\t\t};\n\n\t\tgpio: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tethernet0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 56 4>, <0x0 56 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy0: phy@0 {\n\t\t\t\treg = <0x0>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tethernet1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 58 4>, <0x0 58 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy1: phy@1 {\n\t\t\t\treg = <0x1>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xf12a0000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tnum-cs = <0x1>;\n\t\t\treg = <0x0 0xf1030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"n25q512a\", \"micron,m25p80\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-tx-bus-width = <4>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <108000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@100000 {\n\t\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@600000 {\n\t\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@620000 {\n\t\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <1>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <3>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0x0 0x84000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\treg = <0x0 0xf1040000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <0>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\treg = <0x0 0xf1050000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <1>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\t#address-cells = <0x2>;\n\t\t\t#size-cells = <0x2>;\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tranges;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125 &clk125>;\n\n\t\t\tdwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x10000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = ðernet0;\n\t\tethernet1 = ðernet1;\n\t\tqspi = &qspi;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1 (QSPI)\";\n};\n\n&qspi {\n#include \"versal-x-ebm-01-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-02-revA\",\n\t\t \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1 (EMMC)\";\n};\n\n&sdhci1 {\n#include \"versal-x-ebm-02-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-03-revA\",\n \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board rev1.1 (OSPI)\";\n};\n\n&ospi {\n#include \"versal-x-ebm-03-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-01-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (QSPI)\";\n};\n\n&qspi {\n#include \"versal-x-ebm-01-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-02-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (EMMC)\";\n};\n\n&sdhci1 {\n#include \"versal-x-ebm-02-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-03-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (OSPI)\";\n\n aliases {\n spi0 = &ospi;\n };\n};\n\n&ospi {\n#include \"versal-x-ebm-03-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vp-x-a2785-00 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vp-x-a2785-00 Eval board revA\";\n\tcompatible = \"xlnx,versal-vp-x-a2785-00-revA\",\n\t\t \"xlnx,versal-vp-x-a2785-00\", \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tstatus = \"okay\"; /* u93 and u92 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\tstatus = \"okay\";\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n/* PWM via MIO 41/FAN TACH MIO 49 - FIXME */\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk120 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk120 Eval board revA\";\n\tcompatible = \"xlnx,versal-vpk120-revA\", \"xlnx,versal-vpk120\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk120-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk120 revB\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk120 Eval board revB\";\n\tcompatible = \"xlnx,versal-vpk120-revB\", \"xlnx,versal-vpk120\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n\t/* Use for storing information about board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk180 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk180 Eval board revA\";\n\tcompatible = \"xlnx,versal-vpk180-revA\", \"xlnx,versal-vpk180\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n\n\t/* Use for storing information about board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tu-boot,dm-pre-reloc;\n\t};\n};\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio0 {\n\t/* FIXME Fill names when versal starts */\n};\n\n&gpio1 {\n\t/* FIXME Fill names when versal starts */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-01 revA for vck190/vmk180\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\nnum-cs = <1>;\nspi-tx-bus-width = <4>;\nspi-rx-bus-width = <4>;\n#address-cells = <1>;\n#size-cells = <0>;\nis-dual = <1>;\nflash@0 {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 256MB */\n\treg = <0>;\n\tspi-tx-bus-width = <4>;\n\tspi-rx-bus-width = <4>;\n\tspi-max-frequency = <150000000>;\n\tpartition@0 {\n\t\tlabel = \"spi0-flash0\";\n\t\treg = <0x0 0x10000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-02 revA for vck190/vmk180\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/* emmc MIO 0-13 - MTFC8GAKAJCN */\nnon-removable;\ndisable-wp;\nbus-width = <8>;\nxlnx,mio-bank = <0>;\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-03 revA for vck190/vmk180\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n/* U97 MT35XU02G */\ncompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\nbus-num = <2>;\nnum-cs = <1>;\n#stream-id-cells = <1>;\n#address-cells = <1>;\n#size-cells = <0>;\nreset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\nflash@0 {\n\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\treg = <0>;\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcdns,read-delay = <0x0>;\n\tcdns,tshsl-ns = <0x0>;\n\tcdns,tsd2d-ns = <0x0>;\n\tcdns,tchsh-ns = <0x1>;\n\tcdns,tslch-ns = <0x1>;\n\tspi-tx-bus-width = <8>;\n\tspi-rx-bus-width = <8>;\n\tspi-max-frequency = <20000000>;\n\tpartition@0 {\n\t\tlabel = \"spi0-flash0\";\n\t\treg = <0x0 0x8000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\tclock_si5338_0: clk27 {\t/* u55 SI5338-GM */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tclock_si5338_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_si5338_3: clk150 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <150000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&psgtr {\n\tstatus = \"okay\";\n\t/* dp, usb3, sata */\n\tclocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: ethernet-phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"soft\";\n\t\tnand-ecc-algo = \"bch\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-0\";\n\t\tnand-ecc-step-size = <1024>;\n\t\tnand-ecc-strength = <24>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"soft\";\n\t\tnand-ecc-algo = \"bch\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-1\";\n\t\tnand-ecc-step-size = <1024>;\n\t\tnand-ecc-strength = <24>;\n\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: flash@0 {\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: flash@0 {\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t\tsw13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&amba {\n\tocm: sram@fffc0000 {\n\t\tcompatible = \"mmio-sram\";\n\t\treg = <0xfffc0000 0x10000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0xfffc0000 0x10000>;\n\t\tocm-sram@0 {\n\t\t\treg = <0x0 0x10000>;\n\t\t};\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@34 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x34>;\n\t\t\t};\n\t\t\thwmon@35 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\thwmon@36 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&watchdog0 {\n\treset-on-timeout;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu100-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio-bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu100-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n\n\tsi5335_0: si5335_0 { /* clk0_usb - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5335_1: si5335_1 { /* clk1_dp - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 IRQ_TYPE_LEVEL_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO3\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO2\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO1\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* usb3, dp */\n\tclocks = <&si5335_0>, <&si5335_1>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"super-speed\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zcu102-revb.dtsi\"\n\n/ {\n model = \"ZynqMP ZCU102 Rev1.0\";\n compatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n};\n\n&eeprom {\n #address-cells = <1>;\n #size-cells = <1>;\n\n board_sn: board-sn@0 {\n reg = <0x0 0x14>;\n };\n\n eth_mac: eth-mac@20 {\n reg = <0x20 0x6>;\n };\n\n board_name: board-name@d0 {\n reg = <0xd0 0x6>;\n };\n\n board_revision: board-revision@e0 {\n reg = <0xe0 0x3>;\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_4: out@4 {\n\t\t\t\t\t/* refclk4 for PS-GT, used for PCIE slot */\n\t\t\t\t\treg = <4>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 for PS-GT, used for PCIE */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* pcie, sata, usb3, dp */\n\tclocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n/*\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;*/\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\t/*\n\t * 1.0 revision has level shifter and this property should be\n\t * removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zcu102-reva.dtsi\"\n\n/ {\n model = \"ZynqMP ZCU102 RevB\";\n compatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n};\n\n&gem3 {\n phy-handle = <&phyc>;\n phyc: ethernet-phy@c {\n reg = <0xc>;\n ti,rx-internal-delay = <0x8>;\n ti,tx-internal-delay = <0xa>;\n ti,fifo-depth = <0x1>;\n ti,dp83867-rxctrl-strap-quirk;\n /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n };\n /* Cleanup from RevA */\n /delete-node/ ethernet-phy@21;\n};\n\n/* Fix collision with u61 */\n&i2c0 {\n i2c-mux@75 {\n i2c@2 {\n max15303@1b { /* u8 */\n compatible = \"maxim,max15303\";\n reg = <0x1b>;\n };\n /delete-node/ max15303@20;\n };\n };\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* 8T49N287 - u182 */\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@20 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu104-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revC\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;\n\t};\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - IRPS5401_ALERT_B\n\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t * 2 - MAX6643_OT_B\n\t\t * 3 - MAX6643_FANFAIL_B\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t * 4, 10 - 17 - not connected\n\t\t */\n\t};\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* 8T49N287 - u182 */\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tu183: ina226@40 { /* u183 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 4, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\txlnx,mio-bank = <1>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tina226-u67 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;\n\t};\n\tina226-u59 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n\tina226-u69 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;\n\t};\n\tina226-u66 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;\n\t};\n\tina226-u71 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u73 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tu67: ina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u67\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu59: ina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u59\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu61: ina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu60: ina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu64: ina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu69: ina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u69\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu66: ina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u66\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu63: ina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu3: ina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u3\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu71: ina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u71\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu73: ina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u73\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u57 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SI5382 - u48 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection FIXME */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, dp, usb3, sata */\n\tclocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revA\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1275-revb.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU1275 RevB\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revB\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t* 1.0 revision has level shifter and this property should be\n\t* removed for supporting UHS mode\n\t*/\n\tno-1-8-v;\n};\n\n&gem1 {\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1285-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU1285 RevA\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1285 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1285-revA\", \"xlnx,zynqmp-zcu1285\", \"xlnx,zynqmp\";\n\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PMBUS */\n\t\t\tmax20751@74 { /* u23 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x74>;\n\t\t\t};\n\t\t\tmax20751@70 { /* u89 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x70>;\n\t\t\t};\n\t\t\tmax15301@a { /* u28 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u48 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@d { /* u27 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\tmax15303@e { /* u11 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\tmax15303@f { /* u96 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\tmax15303@11 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\tmax15303@12 { /* u24 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u29 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u51 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u30 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u102 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15301@17 { /* u50 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u31 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* CM_I2C */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYS_EEPROM */\n\t\t\teeprom: eeprom@54 { /* u101 */\n\t\t\t\tcompatible = \"atmel,24c32\"; /* 24LC32A */\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FMC1 */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FMC2 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* ANALOG_PMBUS */\n\t\t\tu60: ina226@40 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu61: ina226@41 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu63: ina226@42 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu65: ina226@43 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu64: ina226@44 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* ANALOG_CM_I2C */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FMC3 */\n\t\t};\n\t};\n};\n\n&gem1 {\n\tmdio {\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu208-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU208\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU208 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu208-revA\", \"xlnx,zynqmp-zcu208\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu216-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU216\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU216 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu216-revA\", \"xlnx,zynqmp-zcu216\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu670-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR)\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU670 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu670-revA\", \"xlnx,zynqmp-zcu670\",\n\t\t \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\"; /* DS1 */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5381_6: si5381_6 { /* refclk_usb3 - u43 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"SFP3_TX_DISABLE\", \"SFP2_TX_DISABLE\", \"SFP1_TX_DISABLE\", /* 25 - 29 */\n\t\t \"SFP0_TX_DISABLE\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"SD_PWR_RST\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"SI5381_INT_ALM\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* Not in schematics */\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5381: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SI5381 - u43 */\n\t\t\t/*si5381: clock-generator@68 {\n\t\t\t\treg = <0x68>;\n\t\t\t};*/\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_psrefclk: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"si570_ps_ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 2Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&psgtr {\n\t/* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */\n\tclocks = <&si5381_6>;\n\tclock-names = \"ref2\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zcu670-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU670 (67DR) revB\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU670 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu670-revB\", \"xlnx,zynqmp-zcu670\",\n\t\t \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\"; /* DS1 */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5381_6: si5381_6 { /* refclk_usb3 - u43 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"SFP3_TX_DISABLE\", \"SFP2_TX_DISABLE\", \"SFP1_TX_DISABLE\", /* 25 - 29 */\n\t\t \"SFP0_TX_DISABLE\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"SD_PWR_RST\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"SI5381_INT_ALM\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* Not in schematics */\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5381: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SI5381 - u43 */\n\t\t\t/*si5381: clock-generator@68 {\n\t\t\t\treg = <0x68>;\n\t\t\t};*/\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_psrefclk: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"si570_ps_ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 2Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\tclk-phase-sd-hs = <120>, <60>;\n\tclk-phase-uhs-sdr25 = <132>, <60>;\n\tclk-phase-uhs-ddr50 = <153>, <48>;\n};\n\n&psgtr {\n\t/* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */\n\tclocks = <&si5381_6>;\n\tclock-names = \"ref2\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-a2197-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Versal System Controller on a2197 board RevA\";\n\tcompatible = \"xlnx,zynqmp-a2197-revA\", \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = &eeprom1;\n\t\tnvmem1 = &eeprom0;\n\t};\n};\n\n&i2c0 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* this cover MGT board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* This cover processor board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-e-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevA\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t\tnvmem1 = &eeprom_ebm;\n\t\tnvmem2 = &eeprom_fmc1;\n\t\tnvmem3 = &eeprom_fmc2;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tsi570_ddrdimm1_clk: si570_ddrdimm1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tsi570_lpddr4_clk2: si570_lpddr4_clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570_lpddr4_clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk1>;\n\t};\n\n\tsi570_hsdp_clk: si570_hsdp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi570_zsfp_clk: si570_zsfp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_zsfp>;\n\t};\n\n\tsi570_user1_clk: si570_user1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_user1>;\n\t};\n\n\tsi5332_1: si5332_1 { /* u142 - GEM0 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vcc-soc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;\n\t};\n\tina226-vcc-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc-pslp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;\n\t};\n\tina226-vcc-psfp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;\n\t};\n\tina226-vccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;\n\t};\n\tina226-vccaux-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;\n\t};\n\tina226-vcco-500 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;\n\t};\n\tina226-vcco-501 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;\n\t};\n\tina226-vcco-502 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;\n\t};\n\tina226-vcco-503 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;\n\t};\n\tina226-vcc-1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;\n\t};\n\tina226-vcc-3v3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;\n\t};\n\tina226-vcc-1v2-ddr4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;\n\t};\n\tina226-vcc-1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtyavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;\n\t};\n\tina226-mgtyavtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;\n\t};\n\tina226-mgtyvccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;\n\t};\n\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n/* GEM SGMII */\n&psgtr {\n\tstatus = \"okay\";\n\t/* gem0 */\n\tclocks = <&si5332_1>;\n\tclock-names = \"ref0\";\n};\n\n&gem0 {\n\tphys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* u131 M88E1512 */\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"ZU4_TRIGGER\", \"SYSCTLR_PB\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"\", /* 85 - 89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"PMBUS_ALERT\", \"\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* u152 IR35215 0x16/0x46 vcc_soc */\n\t\t\t/* u179 ir38164 0x19/0x49 vcco_500 */\n\t\t\t/* u181 ir38164 0x1a/0x4a vcco_501 */\n\t\t\t/* u183 ir38164 0x1b/0x4b vcco_502 */\n\t\t\t/* u185 ir38164 0x1e/0x4e vadj_fmc */\n\t\t\t/* u187 ir38164 0x1F/0x4f mgtyavcc */\n\t\t\t/* u189 ir38164 0x20/0x50 mgtyavtt */\n\t\t\t/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */\n\t\t\t/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */\n\n\t\t\tirps5401_47: irps5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* pmbus / i2c 0x17 */\n\t\t\t};\n\t\t\tirps5401_4c: irps5401@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* pmbus / i2c 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: irps5401@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* pmbus / i2c 0x1d */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <500>; /* R440 */\n\t\t\t\t/* 0.80V @ 32A 1 of 6 Phases*/\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-soc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <500>; /* R1702 */\n\t\t\t\t/* 0.80V @ 18A */\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pmc\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* R1214 */\n\t\t\t\t/* 0.78V @ 500mA */\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u162 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r1221 */\n\t\t\t\t/* 0.78V @ 4A */\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pslp\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>; /* R1216 */\n\t\t\t\t/* 0.78V @ 1A */\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-psfp\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1219 */\n\t\t\t\t/* 0.78V @ 2A */\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* R382 */\n\t\t\t\t/* 1.5V @ 3A */\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux-pmc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>; /* R1246 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u178 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-500\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>; /* R1300 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u180 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-501\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <2000>; /* R1313 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u182 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-502\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <2000>; /* R1330 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-503\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1229 */\n\t\t\t\t/* 1.8V @ 2A */\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u173 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v8\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>; /* R400 */\n\t\t\t\t/* 1.8V @ 6A */\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-3v3\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* R1232 */\n\t\t\t\t/* 3.3V @ 500mA */\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v2-ddr4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>; /* R1275 */\n\t\t\t\t/* 1.2V @ 4A */\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>; /* R1286 */\n\t\t\t\t/* 1.1V @ 4A */\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>; /* R1350 */\n\t\t\t\t/* 1.5V @ 10A */\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavcc\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <2000>; /* R1367 */\n\t\t\t\t/* 0.88V @ 6A */\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavtt\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>; /* R1384 */\n\t\t\t\t/* 1.2V @ 10A */\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyvccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>; /* r1679 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t\ti2c@5 { /* zSFP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_zsfp: clock-generator@5d { /* u192 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_zsfp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* USER_SI570_1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_user1: clock-generator@5d { /* u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>; /* FIXME check address */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"si570_user1\";\n\t\t\t};\n\n\t\t};\n\t\ti2c@7 { /* USER_SI570_2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* 0x5c too */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* and connector J212D */\n\t\t\teeprom_ebm: eeprom@52 { /* x-ebm module */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\t\t};\n\t\tfmc1: i2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t\teeprom_fmc1: eeprom@50 {\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\tfmc2: i2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t\teeprom_fmc2: eeprom@50 {\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LPDDR4_SI570_CLK2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_lpddr4clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4clk1: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* 8A34001 - U219B and J310 connector */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n\ti2c-mux@75 { /* u214 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\ti2c@0 { /* SFP0_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* SFP0 */\n\t\t};\n\t\ti2c@1 { /* SFP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@2 { /* QSFP1_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* QSFP1 */\n\t\t};\n\t\t/* 3 - 7 unused */\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-g-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 MGT Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-g-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u82 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&gem0 { /* eth MDIO 76/77 */\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 */\n\t\treg = <0>;\n\t\treset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 5 - 9 */\n\t\t \"\", \"\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"\", \"\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\ti2c-mux@74 { /* u94 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* CM_I2C_SCL - Samtec */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* PMBUS - AFX_PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\ttps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\ttps544@10 { /* u73 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\ttps544@11 { /* u76 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\ttps544@12 { /* u77 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\ttps544@13 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\ttps544@14 { /* u81 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\ttps544@15 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\ttps544@16 { /* u63 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\ttps544@17 { /* u66 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\ttps544@18 { /* u67 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\ttps544@19 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\ttps544@1d { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\ttps544@1e { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\ttps544@1f { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t\ttps544@20 { /* u71 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\t\t\tu74: ina226@40 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu75: ina226@41 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\"\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@43 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu82: ina226@44 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u82\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu84: ina226@45 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\ttps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* fmc1 via JA2G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom_fmc1: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* fmc2 via JA3G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\teeprom_fmc2: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* fmc3 via JA4G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\teeprom_fmc3: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* ddr dimm */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&usb0 { /* USB0 MIO52-63 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"high-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-01-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\tina226-vcc0v6-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc0v6_lp4: ina226@49 { /* u101 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc0v6-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@5d { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n status = \"disabled\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n /delete-property/ phy-names ;\n /delete-property/ phys ;\n maximum-speed = \"high-speed\";\n snps,dis_u2_susphy_quirk ;\n snps,dis_u3_susphy_quirk ;\n status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-02-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_vpp_2v5_ddr4: tps544@1x { /* u3007 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>; /* FIXME wrong in schematics */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* C0_DDR4_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\ti2c@6 { /* C2_DDR5_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\ti2c@7 { /* C3_DDR4_UDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_RLD3 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_RLD3_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_DDR5 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_DDR5_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-03-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_vpp_2v5_ddr4: tps544@1x { /* u3007 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>; /* FIXME wrong in schematics */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@c0 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* DDR4_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_SODIMM_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_QDRIV */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_QDRIV_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-01-revA\", \"xlnx,zynqmp-x-prc-01\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\",\"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-02-revA\", \"xlnx,zynqmp-x-prc-02\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-03-revA\", \"xlnx,zynqmp-x-prc-03\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>; \n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tx_prc_si5338: clock-generator@70 { /* U9 */\n\t\t\t\tcompatible = \"silabs,si5338\";\n\t\t\t\treg = <0x70>; /* FIXME */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-04-revA\", \"xlnx,zynqmp-x-prc-04\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-05-revA\", \"xlnx,zynqmp-x-prc-05\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@60 { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* 570JAC000900DG */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@60 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-sc-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP Generic System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP Generic System Controller\";\n\tcompatible = \"xlnx,zynqmp-sc-revB\", \"xlnx,zynqmp-sc\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"sw16\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds40-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t\tds44-led {\n\t\t\tlabel = \"status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tsi5332_2: si5332_2 { /* u42 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\tpwm-fan {\n\t\tcompatible = \"pwm-fan\";\n\t\tpwms = <&ttc0 2 40000 0>;\n\t};\n\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\"QSPI_CS_B\", \"\", \"LED1\", \"LED2\", \"\", /* 5 - 9 */\n\t\t\"\", \"ZU4_TRIGGER\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\"I2C1_SDA\", \"UART0_RXD\", \"UART0_TXD\", \"\", \"\", /* 25 - 29 */\n\t\t\"\", \"\", \"\", \"\", \"I2C0_SCL\", /* 30 - 34 */\n\t\t\"I2C0_SDA\", \"UART1_TXD\", \"UART1_RXD\", \"GEM_TX_CLK\", \"GEM_TX_D0\", /* 35 - 39 */\n\t\t\"GEM_TX_D1\", \"GEM_TX_D2\", \"GEM_TX_D3\", \"GEM_TX_CTL\", \"GEM_RX_CLK\", /* 40 - 44 */\n\t\t\"GEM_RX_D0\", \"GEM_RX_D1\", \"GEM_RX_D2\", \"GEM_RX_D3\", \"GEM_RX_CTL\", /* 45 - 49 */\n\t\t\"GEM_MDC\", \"GEM_MDIO\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t\"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t\"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\"\", \"\", \"ETH_RESET_B\", /* 75 - 77, MIO end and EMIO start */\n\t\t\"\", \"\", /* 78 - 79 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy0>;\n\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;\n\t\treset-delay-us = <2>;\n\n\t\tphy0: ethernet-phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n\n&i2c0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n};\n\n&i2c1 { /* i2c1 MIO 24-25 */\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t/* No reason to do pinctrl setup at u-boot stage */\n\t/* Use for storing information about SC board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tu-boot,dm-pre-reloc;\n\t};\n};\n\n/* USB 3.0 only */\n&psgtr {\n\t/* nc, nc, usb3 */\n\tclocks = <&si5332_2>;\n\tclock-names = \"ref2\";\n};\n\n&qspi { /* MIO 0-5 */\n\t/* QSPI should also have PINCTRL setup */\n\tflash@0 {\n\t\tcompatible = \"mt25qu512a\", \"m25p80\", \"jedec,spi-nor\"; /* mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&ttc0 {\n\t#pwm-cells = <3>;\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-sm-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SM-K26 rev1/B/A\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP SM-K26 Rev1/B/A\";\n\tcompatible = \"xlnx,zynqmp-sm-k26-rev1\", \"xlnx,zynqmp-sm-k26-revB\",\n\t\t \"xlnx,zynqmp-sm-k26-revA\", \"xlnx,zynqmp-sm-k26\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36-led {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n\tpwm-fan {\n\t\tcompatible = \"pwm-fan\";\n\t\tpwms = <&ttc0 2 40000 0>;\n\t};\n};\n\n&modepin_gpio {\n\tlabel = \"modepin\";\n};\n\n&ttc0 {\n\t#pwm-cells = <3>;\n};\n\n&pinctrl0 {\n status = \"okay\";\n pinctrl_sdhci0_default: sdhci0-default {\n conf {\n groups = \"sdio0_0_grp\";\n slew-rate = ;\n power-source = ;\n bias-disable;\n };\n\n mux {\n groups = \"sdio0_0_grp\";\n function = \"sdio0\";\n };\n };\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tflash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\n\t\t};\n\t};\n};\n\n&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tassigned-clock-rates = <187498123>;\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues to be fixed in next board revision.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-smk-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sm-k26-reva.dtsi\"\n\n/ {\n model = \"ZynqMP SMK-K26 Rev1/B/A\";\n compatible = \"xlnx,zynqmp-smk-k26-rev1\", \"xlnx,zynqmp-smk-k26-revB\",\n \"xlnx,zynqmp-smk-k26-revA\", \"xlnx,zynqmp-smk-k26\",\n \"xlnx,zynqmp\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on vp-x-a2785-00 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vp-x-a2785-00-revA\",\n\t\t \"xlnx,zynqmp-vp-x-a2785-00\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tj383 {\n\t\t\tlabel = \"j383\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds52 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* u285 - mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>; /* maybe 4 here */\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* sd MIO 45-51 */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 { /* u131 - M88e1512 */\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"\", \"\", \"\", \"VCCINT_FAULT_B\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\treg_vccint: tps53681@c0 { /* u266 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0xc0>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@10 { /* u274 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@11 { /* u275 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@12 { /* u276 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc_cpm: tps544@14 { /* u272 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_util_3v3: tps544@1d { /* u278 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvcc_cpm: ina226@44 { /* u273 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpcie_smbus: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tpcie2_smbus: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tlpddr4_si570_clk3_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\t/* 6-7 unused */\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VPK120 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on VPK120 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vpk120-revA\",\n\t\t \"xlnx,zynqmp-vpk120\", \"xlnx,zynqmp\";\n\n\tsi570_user1_fmc_clk: si570_user1_fmc_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&user_si570_1>;\n\t};\n\n\tsi570_ref_clk: si570_ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&ref_clk>;\n\t};\n\n\tsi570_lpddr4_clk3: si570_lpddr4_clk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk3>;\n\t};\n\n\tsi570_lpddr4_clk2: si570_lpddr4_clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570_lpddr4_clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk1>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw16 {\n\t\t\tlabel = \"sw16\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds40 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"\", \"\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"\", /* 85 - 89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"QSFPDD1_MODSELL\", \"QSFPDD1_MODSELL\", /* 0 - 3 */\n\t\t\t\t \"PMBUS2_INA226_ALERT\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP1_FMC_PRSNT_M2C_B\", \"\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\tir38060_41: regulator@41 { /* IR38060 - u259 */\n\t\t\t\tcompatible = \"infineon,ir38060\", \"infineon,ir38064\";\n\t\t\t\treg = <0x41>; /* i2c addr 0x11 */\n\t\t\t};\n\t\t\tir38164_43: regulator@43 { /* IR38164 - u13 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x43>; /* i2c addr 0x13 */\n\t\t\t};\n\t\t\tir35221_45: pmic@46 { /* IR35221 - u152 */\n\t\t\t\tcompatible = \"infineon,ir35221\";\n\t\t\t\treg = <0x46>; /* PMBUS - 0x16 */\n\t\t\t};\n\t\t\tirps5401_47: pmic5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* i2c addr 0x17 */\n\t\t\t};\n\t\t\tir38164_49: regulator@49 { /* IR38164 - u189 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x49>; /* i2c addr 0x19 */\n\t\t\t};\n\t\t\tirps5401_4c: pmic@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: pmic@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tir38164_4e: regulator@4e { /* IR38164 - u184 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4e>; /* i2c addr 0x1e */\n\t\t\t};\n\t\t\tir38164_4f: regulator@4f { /* IR38164 - u187 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4f>; /* i2c addr 0x1f */\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u5 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpmbus2_ina226_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@42 { /* u265 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v5: ina226@43 { /* u264 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_mio: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavtt: ina226@46 { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtvccaux: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyavcc: ina226@4b { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tlpdmgtyavtt: ina226@4c { /* u260 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tuser_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"fmc_si570\";\n\t\t\t};\n\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tref_clk_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\tfmcp1_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tlpddr4_si570_clk3_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlpddr4_clk3: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk3\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\tqsfpdd_i2c: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* J1/J2 connectors */\n\t\t};\n\t\tidt8a34001_i2c: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* Via J310 connector */\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u219B */\n\t\t\t\treg = <0x5b>; /* FIXME not in schematics */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/clock/xlnx-versal-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_VERSAL_H\n#define _DT_BINDINGS_CLK_VERSAL_H\n\n#define PMC_PLL\t\t\t\t\t1\n#define APU_PLL\t\t\t\t\t2\n#define RPU_PLL\t\t\t\t\t3\n#define CPM_PLL\t\t\t\t\t4\n#define NOC_PLL\t\t\t\t\t5\n#define PLL_MAX\t\t\t\t\t6\n#define PMC_PRESRC\t\t\t\t7\n#define PMC_POSTCLK\t\t\t\t8\n#define PMC_PLL_OUT\t\t\t\t9\n#define PPLL\t\t\t\t\t10\n#define NOC_PRESRC\t\t\t\t11\n#define NOC_POSTCLK\t\t\t\t12\n#define NOC_PLL_OUT\t\t\t\t13\n#define NPLL\t\t\t\t\t14\n#define APU_PRESRC\t\t\t\t15\n#define APU_POSTCLK\t\t\t\t16\n#define APU_PLL_OUT\t\t\t\t17\n#define APLL\t\t\t\t\t18\n#define RPU_PRESRC\t\t\t\t19\n#define RPU_POSTCLK\t\t\t\t20\n#define RPU_PLL_OUT\t\t\t\t21\n#define RPLL\t\t\t\t\t22\n#define CPM_PRESRC\t\t\t\t23\n#define CPM_POSTCLK\t\t\t\t24\n#define CPM_PLL_OUT\t\t\t\t25\n#define CPLL\t\t\t\t\t26\n#define PPLL_TO_XPD\t\t\t\t27\n#define NPLL_TO_XPD\t\t\t\t28\n#define APLL_TO_XPD\t\t\t\t29\n#define RPLL_TO_XPD\t\t\t\t30\n#define EFUSE_REF\t\t\t\t31\n#define SYSMON_REF\t\t\t\t32\n#define IRO_SUSPEND_REF\t\t\t\t33\n#define USB_SUSPEND\t\t\t\t34\n#define SWITCH_TIMEOUT\t\t\t\t35\n#define RCLK_PMC\t\t\t\t36\n#define RCLK_LPD\t\t\t\t37\n#define WDT\t\t\t\t\t38\n#define TTC0\t\t\t\t\t39\n#define TTC1\t\t\t\t\t40\n#define TTC2\t\t\t\t\t41\n#define TTC3\t\t\t\t\t42\n#define GEM_TSU\t\t\t\t\t43\n#define GEM_TSU_LB\t\t\t\t44\n#define MUXED_IRO_DIV2\t\t\t\t45\n#define MUXED_IRO_DIV4\t\t\t\t46\n#define PSM_REF\t\t\t\t\t47\n#define GEM0_RX\t\t\t\t\t48\n#define GEM0_TX\t\t\t\t\t49\n#define GEM1_RX\t\t\t\t\t50\n#define GEM1_TX\t\t\t\t\t51\n#define CPM_CORE_REF\t\t\t\t52\n#define CPM_LSBUS_REF\t\t\t\t53\n#define CPM_DBG_REF\t\t\t\t54\n#define CPM_AUX0_REF\t\t\t\t55\n#define CPM_AUX1_REF\t\t\t\t56\n#define QSPI_REF\t\t\t\t57\n#define OSPI_REF\t\t\t\t58\n#define SDIO0_REF\t\t\t\t59\n#define SDIO1_REF\t\t\t\t60\n#define PMC_LSBUS_REF\t\t\t\t61\n#define I2C_REF\t\t\t\t\t62\n#define TEST_PATTERN_REF\t\t\t63\n#define DFT_OSC_REF\t\t\t\t64\n#define PMC_PL0_REF\t\t\t\t65\n#define PMC_PL1_REF\t\t\t\t66\n#define PMC_PL2_REF\t\t\t\t67\n#define PMC_PL3_REF\t\t\t\t68\n#define CFU_REF\t\t\t\t\t69\n#define SPARE_REF\t\t\t\t70\n#define NPI_REF\t\t\t\t\t71\n#define HSM0_REF\t\t\t\t72\n#define HSM1_REF\t\t\t\t73\n#define SD_DLL_REF\t\t\t\t74\n#define FPD_TOP_SWITCH\t\t\t\t75\n#define FPD_LSBUS\t\t\t\t76\n#define ACPU\t\t\t\t\t77\n#define DBG_TRACE\t\t\t\t78\n#define DBG_FPD\t\t\t\t\t79\n#define LPD_TOP_SWITCH\t\t\t\t80\n#define ADMA\t\t\t\t\t81\n#define LPD_LSBUS\t\t\t\t82\n#define CPU_R5\t\t\t\t\t83\n#define CPU_R5_CORE\t\t\t\t84\n#define CPU_R5_OCM\t\t\t\t85\n#define CPU_R5_OCM2\t\t\t\t86\n#define IOU_SWITCH\t\t\t\t87\n#define GEM0_REF\t\t\t\t88\n#define GEM1_REF\t\t\t\t89\n#define GEM_TSU_REF\t\t\t\t90\n#define USB0_BUS_REF\t\t\t\t91\n#define UART0_REF\t\t\t\t92\n#define UART1_REF\t\t\t\t93\n#define SPI0_REF\t\t\t\t94\n#define SPI1_REF\t\t\t\t95\n#define CAN0_REF\t\t\t\t96\n#define CAN1_REF\t\t\t\t97\n#define I2C0_REF\t\t\t\t98\n#define I2C1_REF\t\t\t\t99\n#define DBG_LPD\t\t\t\t\t100\n#define TIMESTAMP_REF\t\t\t\t101\n#define DBG_TSTMP\t\t\t\t102\n#define CPM_TOPSW_REF\t\t\t\t103\n#define USB3_DUAL_REF\t\t\t\t104\n#define OUTCLK_MAX\t\t\t\t105\n#define REF_CLK\t\t\t\t\t106\n#define PL_ALT_REF_CLK\t\t\t\t107\n#define MUXED_IRO\t\t\t\t108\n#define PL_EXT\t\t\t\t\t109\n#define PL_LB\t\t\t\t\t110\n#define MIO_50_OR_51\t\t\t\t111\n#define MIO_24_OR_25\t\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Xilinx Zynq MPSoC Firmware layer\n *\n * Copyright (C) 2014-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_ZYNQMP_H\n#define _DT_BINDINGS_CLK_ZYNQMP_H\n\n#define IOPLL\t\t\t0\n#define RPLL\t\t\t1\n#define APLL\t\t\t2\n#define DPLL\t\t\t3\n#define VPLL\t\t\t4\n#define IOPLL_TO_FPD\t\t5\n#define RPLL_TO_FPD\t\t6\n#define APLL_TO_LPD\t\t7\n#define DPLL_TO_LPD\t\t8\n#define VPLL_TO_LPD\t\t9\n#define ACPU\t\t\t10\n#define ACPU_HALF\t\t11\n#define DBF_FPD\t\t\t12\n#define DBF_LPD\t\t\t13\n#define DBG_TRACE\t\t14\n#define DBG_TSTMP\t\t15\n#define DP_VIDEO_REF\t\t16\n#define DP_AUDIO_REF\t\t17\n#define DP_STC_REF\t\t18\n#define GDMA_REF\t\t19\n#define DPDMA_REF\t\t20\n#define DDR_REF\t\t\t21\n#define SATA_REF\t\t22\n#define PCIE_REF\t\t23\n#define GPU_REF\t\t\t24\n#define GPU_PP0_REF\t\t25\n#define GPU_PP1_REF\t\t26\n#define TOPSW_MAIN\t\t27\n#define TOPSW_LSBUS\t\t28\n#define GTGREF0_REF\t\t29\n#define LPD_SWITCH\t\t30\n#define LPD_LSBUS\t\t31\n#define USB0_BUS_REF\t\t32\n#define USB1_BUS_REF\t\t33\n#define USB3_DUAL_REF\t\t34\n#define USB0\t\t\t35\n#define USB1\t\t\t36\n#define CPU_R5\t\t\t37\n#define CPU_R5_CORE\t\t38\n#define CSU_SPB\t\t\t39\n#define CSU_PLL\t\t\t40\n#define PCAP\t\t\t41\n#define IOU_SWITCH\t\t42\n#define GEM_TSU_REF\t\t43\n#define GEM_TSU\t\t\t44\n#define GEM0_TX\t\t\t45\n#define GEM1_TX\t\t\t46\n#define GEM2_TX\t\t\t47\n#define GEM3_TX\t\t\t48\n#define GEM0_RX\t\t\t49\n#define GEM1_RX\t\t\t50\n#define GEM2_RX\t\t\t51\n#define GEM3_RX\t\t\t52\n#define QSPI_REF\t\t53\n#define SDIO0_REF\t\t54\n#define SDIO1_REF\t\t55\n#define UART0_REF\t\t56\n#define UART1_REF\t\t57\n#define SPI0_REF\t\t58\n#define SPI1_REF\t\t59\n#define NAND_REF\t\t60\n#define I2C0_REF\t\t61\n#define I2C1_REF\t\t62\n#define CAN0_REF\t\t63\n#define CAN1_REF\t\t64\n#define CAN0\t\t\t65\n#define CAN1\t\t\t66\n#define DLL_REF\t\t\t67\n#define ADMA_REF\t\t68\n#define TIMESTAMP_REF\t\t69\n#define AMS_REF\t\t\t70\n#define PL0_REF\t\t\t71\n#define PL1_REF\t\t\t72\n#define PL2_REF\t\t\t73\n#define PL3_REF\t\t\t74\n#define WDT\t\t\t75\n#define IOPLL_INT\t\t76\n#define IOPLL_PRE_SRC\t\t77\n#define IOPLL_HALF\t\t78\n#define IOPLL_INT_MUX\t\t79\n#define IOPLL_POST_SRC\t\t80\n#define RPLL_INT\t\t81\n#define RPLL_PRE_SRC\t\t82\n#define RPLL_HALF\t\t83\n#define RPLL_INT_MUX\t\t84\n#define RPLL_POST_SRC\t\t85\n#define APLL_INT\t\t86\n#define APLL_PRE_SRC\t\t87\n#define APLL_HALF\t\t88\n#define APLL_INT_MUX\t\t89\n#define APLL_POST_SRC\t\t90\n#define DPLL_INT\t\t91\n#define DPLL_PRE_SRC\t\t92\n#define DPLL_HALF\t\t93\n#define DPLL_INT_MUX\t\t94\n#define DPLL_POST_SRC\t\t95\n#define VPLL_INT\t\t96\n#define VPLL_PRE_SRC\t\t97\n#define VPLL_HALF\t\t98\n#define VPLL_INT_MUX\t\t99\n#define VPLL_POST_SRC\t\t100\n#define CAN0_MIO\t\t101\n#define CAN1_MIO\t\t102\n#define ACPU_FULL\t\t103\n#define GEM0_REF\t\t104\n#define GEM1_REF\t\t105\n#define GEM2_REF\t\t106\n#define GEM3_REF\t\t107\n#define GEM0_REF_UNG\t\t108\n#define GEM1_REF_UNG\t\t109\n#define GEM2_REF_UNG\t\t110\n#define GEM3_REF_UNG\t\t111\n#define LPD_WDT\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h", "content": "/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */\n/*\n * Copyright 2019 Laurent Pinchart \n */\n\n#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n\n#define ZYNQMP_DPDMA_VIDEO0\t\t0\n#define ZYNQMP_DPDMA_VIDEO1\t\t1\n#define ZYNQMP_DPDMA_VIDEO2\t\t2\n#define ZYNQMP_DPDMA_GRAPHICS\t\t3\n#define ZYNQMP_DPDMA_AUDIO0\t\t4\n#define ZYNQMP_DPDMA_AUDIO1\t\t5\n\n#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/gpio/gpio.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most GPIO bindings.\n *\n * Most GPIO bindings include a flags cell as part of the GPIO specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_GPIO_GPIO_H\n#define _DT_BINDINGS_GPIO_GPIO_H\n\n/* Bit 0 express polarity */\n#define GPIO_ACTIVE_HIGH 0\n#define GPIO_ACTIVE_LOW 1\n\n/* Bit 1 express single-endedness */\n#define GPIO_PUSH_PULL 0\n#define GPIO_SINGLE_ENDED 2\n\n/* Bit 2 express Open drain or open source */\n#define GPIO_LINE_OPEN_SOURCE 0\n#define GPIO_LINE_OPEN_DRAIN 4\n\n/*\n * Open Drain/Collector is the combination of single-ended open drain interface.\n * Open Source/Emitter is the combination of single-ended open source interface.\n */\n#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)\n#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)\n\n/* Bit 3 express GPIO suspend/resume and reset persistence */\n#define GPIO_PERSISTENT 0\n#define GPIO_TRANSITORY 8\n\n/* Bit 4 express pull up */\n#define GPIO_PULL_UP 16\n\n/* Bit 5 express pull down */\n#define GPIO_PULL_DOWN 32\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/input/input.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most input bindings.\n *\n * Most input bindings include key code, matrix key code format.\n * In most cases, key code and matrix key code format uses\n * the standard values/macro defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INPUT_INPUT_H\n#define _DT_BINDINGS_INPUT_INPUT_H\n\n/*\n * Device properties and quirks\n */\n\n#define INPUT_PROP_POINTER\t\t0x00\t/* needs a pointer */\n#define INPUT_PROP_DIRECT\t\t0x01\t/* direct input devices */\n#define INPUT_PROP_BUTTONPAD\t\t0x02\t/* has button(s) under pad */\n#define INPUT_PROP_SEMI_MT\t\t0x03\t/* touch rectangle only */\n#define INPUT_PROP_TOPBUTTONPAD\t\t0x04\t/* softbuttons at top of pad */\n#define INPUT_PROP_POINTING_STICK\t0x05\t/* is a pointing stick */\n#define INPUT_PROP_ACCELEROMETER\t0x06\t/* has accelerometer */\n\n#define INPUT_PROP_MAX\t\t\t0x1f\n#define INPUT_PROP_CNT\t\t\t(INPUT_PROP_MAX + 1)\n\n\n/*\n * Event types\n */\n\n#define EV_SYN\t\t\t0x00\n#define EV_KEY\t\t\t0x01\n#define EV_REL\t\t\t0x02\n#define EV_ABS\t\t\t0x03\n#define EV_MSC\t\t\t0x04\n#define EV_SW\t\t\t0x05\n#define EV_LED\t\t\t0x11\n#define EV_SND\t\t\t0x12\n#define EV_REP\t\t\t0x14\n#define EV_FF\t\t\t0x15\n#define EV_PWR\t\t\t0x16\n#define EV_FF_STATUS\t\t0x17\n#define EV_MAX\t\t\t0x1f\n#define EV_CNT\t\t\t(EV_MAX+1)\n\n/*\n * Synchronization events.\n */\n\n#define SYN_REPORT\t\t0\n#define SYN_CONFIG\t\t1\n#define SYN_MT_REPORT\t\t2\n#define SYN_DROPPED\t\t3\n#define SYN_MAX\t\t\t0xf\n#define SYN_CNT\t\t\t(SYN_MAX+1)\n\n/*\n * Keys and buttons\n *\n * Most of the keys/buttons are modeled after USB HUT 1.12\n * (see http://www.usb.org/developers/hidpage).\n * Abbreviations in the comments:\n * AC - Application Control\n * AL - Application Launch Button\n * SC - System Control\n */\n\n#define KEY_RESERVED\t\t0\n#define KEY_ESC\t\t\t1\n#define KEY_1\t\t\t2\n#define KEY_2\t\t\t3\n#define KEY_3\t\t\t4\n#define KEY_4\t\t\t5\n#define KEY_5\t\t\t6\n#define KEY_6\t\t\t7\n#define KEY_7\t\t\t8\n#define KEY_8\t\t\t9\n#define KEY_9\t\t\t10\n#define KEY_0\t\t\t11\n#define KEY_MINUS\t\t12\n#define KEY_EQUAL\t\t13\n#define KEY_BACKSPACE\t\t14\n#define KEY_TAB\t\t\t15\n#define KEY_Q\t\t\t16\n#define KEY_W\t\t\t17\n#define KEY_E\t\t\t18\n#define KEY_R\t\t\t19\n#define KEY_T\t\t\t20\n#define KEY_Y\t\t\t21\n#define KEY_U\t\t\t22\n#define KEY_I\t\t\t23\n#define KEY_O\t\t\t24\n#define KEY_P\t\t\t25\n#define KEY_LEFTBRACE\t\t26\n#define KEY_RIGHTBRACE\t\t27\n#define KEY_ENTER\t\t28\n#define KEY_LEFTCTRL\t\t29\n#define KEY_A\t\t\t30\n#define KEY_S\t\t\t31\n#define KEY_D\t\t\t32\n#define KEY_F\t\t\t33\n#define KEY_G\t\t\t34\n#define KEY_H\t\t\t35\n#define KEY_J\t\t\t36\n#define KEY_K\t\t\t37\n#define KEY_L\t\t\t38\n#define KEY_SEMICOLON\t\t39\n#define KEY_APOSTROPHE\t\t40\n#define KEY_GRAVE\t\t41\n#define KEY_LEFTSHIFT\t\t42\n#define KEY_BACKSLASH\t\t43\n#define KEY_Z\t\t\t44\n#define KEY_X\t\t\t45\n#define KEY_C\t\t\t46\n#define KEY_V\t\t\t47\n#define KEY_B\t\t\t48\n#define KEY_N\t\t\t49\n#define KEY_M\t\t\t50\n#define KEY_COMMA\t\t51\n#define KEY_DOT\t\t\t52\n#define KEY_SLASH\t\t53\n#define KEY_RIGHTSHIFT\t\t54\n#define KEY_KPASTERISK\t\t55\n#define KEY_LEFTALT\t\t56\n#define KEY_SPACE\t\t57\n#define KEY_CAPSLOCK\t\t58\n#define KEY_F1\t\t\t59\n#define KEY_F2\t\t\t60\n#define KEY_F3\t\t\t61\n#define KEY_F4\t\t\t62\n#define KEY_F5\t\t\t63\n#define KEY_F6\t\t\t64\n#define KEY_F7\t\t\t65\n#define KEY_F8\t\t\t66\n#define KEY_F9\t\t\t67\n#define KEY_F10\t\t\t68\n#define KEY_NUMLOCK\t\t69\n#define KEY_SCROLLLOCK\t\t70\n#define KEY_KP7\t\t\t71\n#define KEY_KP8\t\t\t72\n#define KEY_KP9\t\t\t73\n#define KEY_KPMINUS\t\t74\n#define KEY_KP4\t\t\t75\n#define KEY_KP5\t\t\t76\n#define KEY_KP6\t\t\t77\n#define KEY_KPPLUS\t\t78\n#define KEY_KP1\t\t\t79\n#define KEY_KP2\t\t\t80\n#define KEY_KP3\t\t\t81\n#define KEY_KP0\t\t\t82\n#define KEY_KPDOT\t\t83\n\n#define KEY_ZENKAKUHANKAKU\t85\n#define KEY_102ND\t\t86\n#define KEY_F11\t\t\t87\n#define KEY_F12\t\t\t88\n#define KEY_RO\t\t\t89\n#define KEY_KATAKANA\t\t90\n#define KEY_HIRAGANA\t\t91\n#define KEY_HENKAN\t\t92\n#define KEY_KATAKANAHIRAGANA\t93\n#define KEY_MUHENKAN\t\t94\n#define KEY_KPJPCOMMA\t\t95\n#define KEY_KPENTER\t\t96\n#define KEY_RIGHTCTRL\t\t97\n#define KEY_KPSLASH\t\t98\n#define KEY_SYSRQ\t\t99\n#define KEY_RIGHTALT\t\t100\n#define KEY_LINEFEED\t\t101\n#define KEY_HOME\t\t102\n#define KEY_UP\t\t\t103\n#define KEY_PAGEUP\t\t104\n#define KEY_LEFT\t\t105\n#define KEY_RIGHT\t\t106\n#define KEY_END\t\t\t107\n#define KEY_DOWN\t\t108\n#define KEY_PAGEDOWN\t\t109\n#define KEY_INSERT\t\t110\n#define KEY_DELETE\t\t111\n#define KEY_MACRO\t\t112\n#define KEY_MUTE\t\t113\n#define KEY_VOLUMEDOWN\t\t114\n#define KEY_VOLUMEUP\t\t115\n#define KEY_POWER\t\t116\t/* SC System Power Down */\n#define KEY_KPEQUAL\t\t117\n#define KEY_KPPLUSMINUS\t\t118\n#define KEY_PAUSE\t\t119\n#define KEY_SCALE\t\t120\t/* AL Compiz Scale (Expose) */\n\n#define KEY_KPCOMMA\t\t121\n#define KEY_HANGEUL\t\t122\n#define KEY_HANGUEL\t\tKEY_HANGEUL\n#define KEY_HANJA\t\t123\n#define KEY_YEN\t\t\t124\n#define KEY_LEFTMETA\t\t125\n#define KEY_RIGHTMETA\t\t126\n#define KEY_COMPOSE\t\t127\n#define KEY_STOP\t\t128\t/* AC Stop */\n#define KEY_AGAIN\t\t129\n#define KEY_PROPS\t\t130\t/* AC Properties */\n#define KEY_UNDO\t\t131\t/* AC Undo */\n#define KEY_FRONT\t\t132\n#define KEY_COPY\t\t133\t/* AC Copy */\n#define KEY_OPEN\t\t134\t/* AC Open */\n#define KEY_PASTE\t\t135\t/* AC Paste */\n#define KEY_FIND\t\t136\t/* AC Search */\n#define KEY_CUT\t\t\t137\t/* AC Cut */\n#define KEY_HELP\t\t138\t/* AL Integrated Help Center */\n#define KEY_MENU\t\t139\t/* Menu (show menu) */\n#define KEY_CALC\t\t140\t/* AL Calculator */\n#define KEY_SETUP\t\t141\n#define KEY_SLEEP\t\t142\t/* SC System Sleep */\n#define KEY_WAKEUP\t\t143\t/* System Wake Up */\n#define KEY_FILE\t\t144\t/* AL Local Machine Browser */\n#define KEY_SENDFILE\t\t145\n#define KEY_DELETEFILE\t\t146\n#define KEY_XFER\t\t147\n#define KEY_PROG1\t\t148\n#define KEY_PROG2\t\t149\n#define KEY_WWW\t\t\t150\t/* AL Internet Browser */\n#define KEY_MSDOS\t\t151\n#define KEY_COFFEE\t\t152\t/* AL Terminal Lock/Screensaver */\n#define KEY_SCREENLOCK\t\tKEY_COFFEE\n#define KEY_ROTATE_DISPLAY\t153\t/* Display orientation for e.g. tablets */\n#define KEY_DIRECTION\t\tKEY_ROTATE_DISPLAY\n#define KEY_CYCLEWINDOWS\t154\n#define KEY_MAIL\t\t155\n#define KEY_BOOKMARKS\t\t156\t/* AC Bookmarks */\n#define KEY_COMPUTER\t\t157\n#define KEY_BACK\t\t158\t/* AC Back */\n#define KEY_FORWARD\t\t159\t/* AC Forward */\n#define KEY_CLOSECD\t\t160\n#define KEY_EJECTCD\t\t161\n#define KEY_EJECTCLOSECD\t162\n#define KEY_NEXTSONG\t\t163\n#define KEY_PLAYPAUSE\t\t164\n#define KEY_PREVIOUSSONG\t165\n#define KEY_STOPCD\t\t166\n#define KEY_RECORD\t\t167\n#define KEY_REWIND\t\t168\n#define KEY_PHONE\t\t169\t/* Media Select Telephone */\n#define KEY_ISO\t\t\t170\n#define KEY_CONFIG\t\t171\t/* AL Consumer Control Configuration */\n#define KEY_HOMEPAGE\t\t172\t/* AC Home */\n#define KEY_REFRESH\t\t173\t/* AC Refresh */\n#define KEY_EXIT\t\t174\t/* AC Exit */\n#define KEY_MOVE\t\t175\n#define KEY_EDIT\t\t176\n#define KEY_SCROLLUP\t\t177\n#define KEY_SCROLLDOWN\t\t178\n#define KEY_KPLEFTPAREN\t\t179\n#define KEY_KPRIGHTPAREN\t180\n#define KEY_NEW\t\t\t181\t/* AC New */\n#define KEY_REDO\t\t182\t/* AC Redo/Repeat */\n\n#define KEY_F13\t\t\t183\n#define KEY_F14\t\t\t184\n#define KEY_F15\t\t\t185\n#define KEY_F16\t\t\t186\n#define KEY_F17\t\t\t187\n#define KEY_F18\t\t\t188\n#define KEY_F19\t\t\t189\n#define KEY_F20\t\t\t190\n#define KEY_F21\t\t\t191\n#define KEY_F22\t\t\t192\n#define KEY_F23\t\t\t193\n#define KEY_F24\t\t\t194\n\n#define KEY_PLAYCD\t\t200\n#define KEY_PAUSECD\t\t201\n#define KEY_PROG3\t\t202\n#define KEY_PROG4\t\t203\n#define KEY_DASHBOARD\t\t204\t/* AL Dashboard */\n#define KEY_SUSPEND\t\t205\n#define KEY_CLOSE\t\t206\t/* AC Close */\n#define KEY_PLAY\t\t207\n#define KEY_FASTFORWARD\t\t208\n#define KEY_BASSBOOST\t\t209\n#define KEY_PRINT\t\t210\t/* AC Print */\n#define KEY_HP\t\t\t211\n#define KEY_CAMERA\t\t212\n#define KEY_SOUND\t\t213\n#define KEY_QUESTION\t\t214\n#define KEY_EMAIL\t\t215\n#define KEY_CHAT\t\t216\n#define KEY_SEARCH\t\t217\n#define KEY_CONNECT\t\t218\n#define KEY_FINANCE\t\t219\t/* AL Checkbook/Finance */\n#define KEY_SPORT\t\t220\n#define KEY_SHOP\t\t221\n#define KEY_ALTERASE\t\t222\n#define KEY_CANCEL\t\t223\t/* AC Cancel */\n#define KEY_BRIGHTNESSDOWN\t224\n#define KEY_BRIGHTNESSUP\t225\n#define KEY_MEDIA\t\t226\n\n#define KEY_SWITCHVIDEOMODE\t227\t/* Cycle between available video\n\t\t\t\t\t outputs (Monitor/LCD/TV-out/etc) */\n#define KEY_KBDILLUMTOGGLE\t228\n#define KEY_KBDILLUMDOWN\t229\n#define KEY_KBDILLUMUP\t\t230\n\n#define KEY_SEND\t\t231\t/* AC Send */\n#define KEY_REPLY\t\t232\t/* AC Reply */\n#define KEY_FORWARDMAIL\t\t233\t/* AC Forward Msg */\n#define KEY_SAVE\t\t234\t/* AC Save */\n#define KEY_DOCUMENTS\t\t235\n\n#define KEY_BATTERY\t\t236\n\n#define KEY_BLUETOOTH\t\t237\n#define KEY_WLAN\t\t238\n#define KEY_UWB\t\t\t239\n\n#define KEY_UNKNOWN\t\t240\n#define KEY_VIDEO_NEXT\t\t241\t/* drive next video source */\n#define KEY_VIDEO_PREV\t\t242\t/* drive previous video source */\n#define KEY_BRIGHTNESS_CYCLE\t243\t/* brightness up, after max is min */\n#define KEY_BRIGHTNESS_AUTO\t244\t/* Set Auto Brightness: manual\n\t\t\t\t\t brightness control is off,\n\t\t\t\t\t rely on ambient */\n#define KEY_BRIGHTNESS_ZERO\tKEY_BRIGHTNESS_AUTO\n#define KEY_DISPLAY_OFF\t\t245\t/* display device to off state */\n\n#define KEY_WWAN\t\t246\t/* Wireless WAN (LTE, UMTS, GSM, etc.) */\n#define KEY_WIMAX\t\tKEY_WWAN\n#define KEY_RFKILL\t\t247\t/* Key that controls all radios */\n\n#define KEY_MICMUTE\t\t248\t/* Mute / unmute the microphone */\n\n/* Code 255 is reserved for special needs of AT keyboard driver */\n\n#define BTN_MISC\t\t0x100\n#define BTN_0\t\t\t0x100\n#define BTN_1\t\t\t0x101\n#define BTN_2\t\t\t0x102\n#define BTN_3\t\t\t0x103\n#define BTN_4\t\t\t0x104\n#define BTN_5\t\t\t0x105\n#define BTN_6\t\t\t0x106\n#define BTN_7\t\t\t0x107\n#define BTN_8\t\t\t0x108\n#define BTN_9\t\t\t0x109\n\n#define BTN_MOUSE\t\t0x110\n#define BTN_LEFT\t\t0x110\n#define BTN_RIGHT\t\t0x111\n#define BTN_MIDDLE\t\t0x112\n#define BTN_SIDE\t\t0x113\n#define BTN_EXTRA\t\t0x114\n#define BTN_FORWARD\t\t0x115\n#define BTN_BACK\t\t0x116\n#define BTN_TASK\t\t0x117\n\n#define BTN_JOYSTICK\t\t0x120\n#define BTN_TRIGGER\t\t0x120\n#define BTN_THUMB\t\t0x121\n#define BTN_THUMB2\t\t0x122\n#define BTN_TOP\t\t\t0x123\n#define BTN_TOP2\t\t0x124\n#define BTN_PINKIE\t\t0x125\n#define BTN_BASE\t\t0x126\n#define BTN_BASE2\t\t0x127\n#define BTN_BASE3\t\t0x128\n#define BTN_BASE4\t\t0x129\n#define BTN_BASE5\t\t0x12a\n#define BTN_BASE6\t\t0x12b\n#define BTN_DEAD\t\t0x12f\n\n#define BTN_GAMEPAD\t\t0x130\n#define BTN_SOUTH\t\t0x130\n#define BTN_A\t\t\tBTN_SOUTH\n#define BTN_EAST\t\t0x131\n#define BTN_B\t\t\tBTN_EAST\n#define BTN_C\t\t\t0x132\n#define BTN_NORTH\t\t0x133\n#define BTN_X\t\t\tBTN_NORTH\n#define BTN_WEST\t\t0x134\n#define BTN_Y\t\t\tBTN_WEST\n#define BTN_Z\t\t\t0x135\n#define BTN_TL\t\t\t0x136\n#define BTN_TR\t\t\t0x137\n#define BTN_TL2\t\t\t0x138\n#define BTN_TR2\t\t\t0x139\n#define BTN_SELECT\t\t0x13a\n#define BTN_START\t\t0x13b\n#define BTN_MODE\t\t0x13c\n#define BTN_THUMBL\t\t0x13d\n#define BTN_THUMBR\t\t0x13e\n\n#define BTN_DIGI\t\t0x140\n#define BTN_TOOL_PEN\t\t0x140\n#define BTN_TOOL_RUBBER\t\t0x141\n#define BTN_TOOL_BRUSH\t\t0x142\n#define BTN_TOOL_PENCIL\t\t0x143\n#define BTN_TOOL_AIRBRUSH\t0x144\n#define BTN_TOOL_FINGER\t\t0x145\n#define BTN_TOOL_MOUSE\t\t0x146\n#define BTN_TOOL_LENS\t\t0x147\n#define BTN_TOOL_QUINTTAP\t0x148\t/* Five fingers on trackpad */\n#define BTN_TOUCH\t\t0x14a\n#define BTN_STYLUS\t\t0x14b\n#define BTN_STYLUS2\t\t0x14c\n#define BTN_TOOL_DOUBLETAP\t0x14d\n#define BTN_TOOL_TRIPLETAP\t0x14e\n#define BTN_TOOL_QUADTAP\t0x14f\t/* Four fingers on trackpad */\n\n#define BTN_WHEEL\t\t0x150\n#define BTN_GEAR_DOWN\t\t0x150\n#define BTN_GEAR_UP\t\t0x151\n\n#define KEY_OK\t\t\t0x160\n#define KEY_SELECT\t\t0x161\n#define KEY_GOTO\t\t0x162\n#define KEY_CLEAR\t\t0x163\n#define KEY_POWER2\t\t0x164\n#define KEY_OPTION\t\t0x165\n#define KEY_INFO\t\t0x166\t/* AL OEM Features/Tips/Tutorial */\n#define KEY_TIME\t\t0x167\n#define KEY_VENDOR\t\t0x168\n#define KEY_ARCHIVE\t\t0x169\n#define KEY_PROGRAM\t\t0x16a\t/* Media Select Program Guide */\n#define KEY_CHANNEL\t\t0x16b\n#define KEY_FAVORITES\t\t0x16c\n#define KEY_EPG\t\t\t0x16d\n#define KEY_PVR\t\t\t0x16e\t/* Media Select Home */\n#define KEY_MHP\t\t\t0x16f\n#define KEY_LANGUAGE\t\t0x170\n#define KEY_TITLE\t\t0x171\n#define KEY_SUBTITLE\t\t0x172\n#define KEY_ANGLE\t\t0x173\n#define KEY_ZOOM\t\t0x174\n#define KEY_MODE\t\t0x175\n#define KEY_KEYBOARD\t\t0x176\n#define KEY_SCREEN\t\t0x177\n#define KEY_PC\t\t\t0x178\t/* Media Select Computer */\n#define KEY_TV\t\t\t0x179\t/* Media Select TV */\n#define KEY_TV2\t\t\t0x17a\t/* Media Select Cable */\n#define KEY_VCR\t\t\t0x17b\t/* Media Select VCR */\n#define KEY_VCR2\t\t0x17c\t/* VCR Plus */\n#define KEY_SAT\t\t\t0x17d\t/* Media Select Satellite */\n#define KEY_SAT2\t\t0x17e\n#define KEY_CD\t\t\t0x17f\t/* Media Select CD */\n#define KEY_TAPE\t\t0x180\t/* Media Select Tape */\n#define KEY_RADIO\t\t0x181\n#define KEY_TUNER\t\t0x182\t/* Media Select Tuner */\n#define KEY_PLAYER\t\t0x183\n#define KEY_TEXT\t\t0x184\n#define KEY_DVD\t\t\t0x185\t/* Media Select DVD */\n#define KEY_AUX\t\t\t0x186\n#define KEY_MP3\t\t\t0x187\n#define KEY_AUDIO\t\t0x188\t/* AL Audio Browser */\n#define KEY_VIDEO\t\t0x189\t/* AL Movie Browser */\n#define KEY_DIRECTORY\t\t0x18a\n#define KEY_LIST\t\t0x18b\n#define KEY_MEMO\t\t0x18c\t/* Media Select Messages */\n#define KEY_CALENDAR\t\t0x18d\n#define KEY_RED\t\t\t0x18e\n#define KEY_GREEN\t\t0x18f\n#define KEY_YELLOW\t\t0x190\n#define KEY_BLUE\t\t0x191\n#define KEY_CHANNELUP\t\t0x192\t/* Channel Increment */\n#define KEY_CHANNELDOWN\t\t0x193\t/* Channel Decrement */\n#define KEY_FIRST\t\t0x194\n#define KEY_LAST\t\t0x195\t/* Recall Last */\n#define KEY_AB\t\t\t0x196\n#define KEY_NEXT\t\t0x197\n#define KEY_RESTART\t\t0x198\n#define KEY_SLOW\t\t0x199\n#define KEY_SHUFFLE\t\t0x19a\n#define KEY_BREAK\t\t0x19b\n#define KEY_PREVIOUS\t\t0x19c\n#define KEY_DIGITS\t\t0x19d\n#define KEY_TEEN\t\t0x19e\n#define KEY_TWEN\t\t0x19f\n#define KEY_VIDEOPHONE\t\t0x1a0\t/* Media Select Video Phone */\n#define KEY_GAMES\t\t0x1a1\t/* Media Select Games */\n#define KEY_ZOOMIN\t\t0x1a2\t/* AC Zoom In */\n#define KEY_ZOOMOUT\t\t0x1a3\t/* AC Zoom Out */\n#define KEY_ZOOMRESET\t\t0x1a4\t/* AC Zoom */\n#define KEY_WORDPROCESSOR\t0x1a5\t/* AL Word Processor */\n#define KEY_EDITOR\t\t0x1a6\t/* AL Text Editor */\n#define KEY_SPREADSHEET\t\t0x1a7\t/* AL Spreadsheet */\n#define KEY_GRAPHICSEDITOR\t0x1a8\t/* AL Graphics Editor */\n#define KEY_PRESENTATION\t0x1a9\t/* AL Presentation App */\n#define KEY_DATABASE\t\t0x1aa\t/* AL Database App */\n#define KEY_NEWS\t\t0x1ab\t/* AL Newsreader */\n#define KEY_VOICEMAIL\t\t0x1ac\t/* AL Voicemail */\n#define KEY_ADDRESSBOOK\t\t0x1ad\t/* AL Contacts/Address Book */\n#define KEY_MESSENGER\t\t0x1ae\t/* AL Instant Messaging */\n#define KEY_DISPLAYTOGGLE\t0x1af\t/* Turn display (LCD) on and off */\n#define KEY_BRIGHTNESS_TOGGLE\tKEY_DISPLAYTOGGLE\n#define KEY_SPELLCHECK\t\t0x1b0 /* AL Spell Check */\n#define KEY_LOGOFF\t\t0x1b1 /* AL Logoff */\n\n#define KEY_DOLLAR\t\t0x1b2\n#define KEY_EURO\t\t0x1b3\n\n#define KEY_FRAMEBACK\t\t0x1b4\t/* Consumer - transport controls */\n#define KEY_FRAMEFORWARD\t0x1b5\n#define KEY_CONTEXT_MENU\t0x1b6\t/* GenDesc - system context menu */\n#define KEY_MEDIA_REPEAT\t0x1b7\t/* Consumer - transport control */\n#define KEY_10CHANNELSUP\t0x1b8\t/* 10 channels up (10+) */\n#define KEY_10CHANNELSDOWN\t0x1b9\t/* 10 channels down (10-) */\n#define KEY_IMAGES\t\t0x1ba\t/* AL Image Browser */\n\n#define KEY_DEL_EOL\t\t0x1c0\n#define KEY_DEL_EOS\t\t0x1c1\n#define KEY_INS_LINE\t\t0x1c2\n#define KEY_DEL_LINE\t\t0x1c3\n\n#define KEY_FN\t\t\t0x1d0\n#define KEY_FN_ESC\t\t0x1d1\n#define KEY_FN_F1\t\t0x1d2\n#define KEY_FN_F2\t\t0x1d3\n#define KEY_FN_F3\t\t0x1d4\n#define KEY_FN_F4\t\t0x1d5\n#define KEY_FN_F5\t\t0x1d6\n#define KEY_FN_F6\t\t0x1d7\n#define KEY_FN_F7\t\t0x1d8\n#define KEY_FN_F8\t\t0x1d9\n#define KEY_FN_F9\t\t0x1da\n#define KEY_FN_F10\t\t0x1db\n#define KEY_FN_F11\t\t0x1dc\n#define KEY_FN_F12\t\t0x1dd\n#define KEY_FN_1\t\t0x1de\n#define KEY_FN_2\t\t0x1df\n#define KEY_FN_D\t\t0x1e0\n#define KEY_FN_E\t\t0x1e1\n#define KEY_FN_F\t\t0x1e2\n#define KEY_FN_S\t\t0x1e3\n#define KEY_FN_B\t\t0x1e4\n\n#define KEY_BRL_DOT1\t\t0x1f1\n#define KEY_BRL_DOT2\t\t0x1f2\n#define KEY_BRL_DOT3\t\t0x1f3\n#define KEY_BRL_DOT4\t\t0x1f4\n#define KEY_BRL_DOT5\t\t0x1f5\n#define KEY_BRL_DOT6\t\t0x1f6\n#define KEY_BRL_DOT7\t\t0x1f7\n#define KEY_BRL_DOT8\t\t0x1f8\n#define KEY_BRL_DOT9\t\t0x1f9\n#define KEY_BRL_DOT10\t\t0x1fa\n\n#define KEY_NUMERIC_0\t\t0x200\t/* used by phones, remote controls, */\n#define KEY_NUMERIC_1\t\t0x201\t/* and other keypads */\n#define KEY_NUMERIC_2\t\t0x202\n#define KEY_NUMERIC_3\t\t0x203\n#define KEY_NUMERIC_4\t\t0x204\n#define KEY_NUMERIC_5\t\t0x205\n#define KEY_NUMERIC_6\t\t0x206\n#define KEY_NUMERIC_7\t\t0x207\n#define KEY_NUMERIC_8\t\t0x208\n#define KEY_NUMERIC_9\t\t0x209\n#define KEY_NUMERIC_STAR\t0x20a\n#define KEY_NUMERIC_POUND\t0x20b\n#define KEY_NUMERIC_A\t\t0x20c\t/* Phone key A - HUT Telephony 0xb9 */\n#define KEY_NUMERIC_B\t\t0x20d\n#define KEY_NUMERIC_C\t\t0x20e\n#define KEY_NUMERIC_D\t\t0x20f\n\n#define KEY_CAMERA_FOCUS\t0x210\n#define KEY_WPS_BUTTON\t\t0x211\t/* WiFi Protected Setup key */\n\n#define KEY_TOUCHPAD_TOGGLE\t0x212\t/* Request switch touchpad on or off */\n#define KEY_TOUCHPAD_ON\t\t0x213\n#define KEY_TOUCHPAD_OFF\t0x214\n\n#define KEY_CAMERA_ZOOMIN\t0x215\n#define KEY_CAMERA_ZOOMOUT\t0x216\n#define KEY_CAMERA_UP\t\t0x217\n#define KEY_CAMERA_DOWN\t\t0x218\n#define KEY_CAMERA_LEFT\t\t0x219\n#define KEY_CAMERA_RIGHT\t0x21a\n\n#define KEY_ATTENDANT_ON\t0x21b\n#define KEY_ATTENDANT_OFF\t0x21c\n#define KEY_ATTENDANT_TOGGLE\t0x21d\t/* Attendant call on or off */\n#define KEY_LIGHTS_TOGGLE\t0x21e\t/* Reading light on or off */\n\n#define BTN_DPAD_UP\t\t0x220\n#define BTN_DPAD_DOWN\t\t0x221\n#define BTN_DPAD_LEFT\t\t0x222\n#define BTN_DPAD_RIGHT\t\t0x223\n\n#define KEY_ALS_TOGGLE\t\t0x230\t/* Ambient light sensor */\n\n#define KEY_BUTTONCONFIG\t\t0x240\t/* AL Button Configuration */\n#define KEY_TASKMANAGER\t\t0x241\t/* AL Task/Project Manager */\n#define KEY_JOURNAL\t\t0x242\t/* AL Log/Journal/Timecard */\n#define KEY_CONTROLPANEL\t\t0x243\t/* AL Control Panel */\n#define KEY_APPSELECT\t\t0x244\t/* AL Select Task/Application */\n#define KEY_SCREENSAVER\t\t0x245\t/* AL Screen Saver */\n#define KEY_VOICECOMMAND\t\t0x246\t/* Listening Voice Command */\n\n#define KEY_BRIGHTNESS_MIN\t\t0x250\t/* Set Brightness to Minimum */\n#define KEY_BRIGHTNESS_MAX\t\t0x251\t/* Set Brightness to Maximum */\n\n#define KEY_KBDINPUTASSIST_PREV\t\t0x260\n#define KEY_KBDINPUTASSIST_NEXT\t\t0x261\n#define KEY_KBDINPUTASSIST_PREVGROUP\t\t0x262\n#define KEY_KBDINPUTASSIST_NEXTGROUP\t\t0x263\n#define KEY_KBDINPUTASSIST_ACCEPT\t\t0x264\n#define KEY_KBDINPUTASSIST_CANCEL\t\t0x265\n\n#define BTN_TRIGGER_HAPPY\t\t0x2c0\n#define BTN_TRIGGER_HAPPY1\t\t0x2c0\n#define BTN_TRIGGER_HAPPY2\t\t0x2c1\n#define BTN_TRIGGER_HAPPY3\t\t0x2c2\n#define BTN_TRIGGER_HAPPY4\t\t0x2c3\n#define BTN_TRIGGER_HAPPY5\t\t0x2c4\n#define BTN_TRIGGER_HAPPY6\t\t0x2c5\n#define BTN_TRIGGER_HAPPY7\t\t0x2c6\n#define BTN_TRIGGER_HAPPY8\t\t0x2c7\n#define BTN_TRIGGER_HAPPY9\t\t0x2c8\n#define BTN_TRIGGER_HAPPY10\t\t0x2c9\n#define BTN_TRIGGER_HAPPY11\t\t0x2ca\n#define BTN_TRIGGER_HAPPY12\t\t0x2cb\n#define BTN_TRIGGER_HAPPY13\t\t0x2cc\n#define BTN_TRIGGER_HAPPY14\t\t0x2cd\n#define BTN_TRIGGER_HAPPY15\t\t0x2ce\n#define BTN_TRIGGER_HAPPY16\t\t0x2cf\n#define BTN_TRIGGER_HAPPY17\t\t0x2d0\n#define BTN_TRIGGER_HAPPY18\t\t0x2d1\n#define BTN_TRIGGER_HAPPY19\t\t0x2d2\n#define BTN_TRIGGER_HAPPY20\t\t0x2d3\n#define BTN_TRIGGER_HAPPY21\t\t0x2d4\n#define BTN_TRIGGER_HAPPY22\t\t0x2d5\n#define BTN_TRIGGER_HAPPY23\t\t0x2d6\n#define BTN_TRIGGER_HAPPY24\t\t0x2d7\n#define BTN_TRIGGER_HAPPY25\t\t0x2d8\n#define BTN_TRIGGER_HAPPY26\t\t0x2d9\n#define BTN_TRIGGER_HAPPY27\t\t0x2da\n#define BTN_TRIGGER_HAPPY28\t\t0x2db\n#define BTN_TRIGGER_HAPPY29\t\t0x2dc\n#define BTN_TRIGGER_HAPPY30\t\t0x2dd\n#define BTN_TRIGGER_HAPPY31\t\t0x2de\n#define BTN_TRIGGER_HAPPY32\t\t0x2df\n#define BTN_TRIGGER_HAPPY33\t\t0x2e0\n#define BTN_TRIGGER_HAPPY34\t\t0x2e1\n#define BTN_TRIGGER_HAPPY35\t\t0x2e2\n#define BTN_TRIGGER_HAPPY36\t\t0x2e3\n#define BTN_TRIGGER_HAPPY37\t\t0x2e4\n#define BTN_TRIGGER_HAPPY38\t\t0x2e5\n#define BTN_TRIGGER_HAPPY39\t\t0x2e6\n#define BTN_TRIGGER_HAPPY40\t\t0x2e7\n\n/* We avoid low common keys in module aliases so they don't get huge. */\n#define KEY_MIN_INTERESTING\tKEY_MUTE\n#define KEY_MAX\t\t\t0x2ff\n#define KEY_CNT\t\t\t(KEY_MAX+1)\n\n/*\n * Relative axes\n */\n\n#define REL_X\t\t\t0x00\n#define REL_Y\t\t\t0x01\n#define REL_Z\t\t\t0x02\n#define REL_RX\t\t\t0x03\n#define REL_RY\t\t\t0x04\n#define REL_RZ\t\t\t0x05\n#define REL_HWHEEL\t\t0x06\n#define REL_DIAL\t\t0x07\n#define REL_WHEEL\t\t0x08\n#define REL_MISC\t\t0x09\n#define REL_MAX\t\t\t0x0f\n#define REL_CNT\t\t\t(REL_MAX+1)\n\n/*\n * Absolute axes\n */\n\n#define ABS_X\t\t\t0x00\n#define ABS_Y\t\t\t0x01\n#define ABS_Z\t\t\t0x02\n#define ABS_RX\t\t\t0x03\n#define ABS_RY\t\t\t0x04\n#define ABS_RZ\t\t\t0x05\n#define ABS_THROTTLE\t\t0x06\n#define ABS_RUDDER\t\t0x07\n#define ABS_WHEEL\t\t0x08\n#define ABS_GAS\t\t\t0x09\n#define ABS_BRAKE\t\t0x0a\n#define ABS_HAT0X\t\t0x10\n#define ABS_HAT0Y\t\t0x11\n#define ABS_HAT1X\t\t0x12\n#define ABS_HAT1Y\t\t0x13\n#define ABS_HAT2X\t\t0x14\n#define ABS_HAT2Y\t\t0x15\n#define ABS_HAT3X\t\t0x16\n#define ABS_HAT3Y\t\t0x17\n#define ABS_PRESSURE\t\t0x18\n#define ABS_DISTANCE\t\t0x19\n#define ABS_TILT_X\t\t0x1a\n#define ABS_TILT_Y\t\t0x1b\n#define ABS_TOOL_WIDTH\t\t0x1c\n\n#define ABS_VOLUME\t\t0x20\n\n#define ABS_MISC\t\t0x28\n\n#define ABS_MT_SLOT\t\t0x2f\t/* MT slot being modified */\n#define ABS_MT_TOUCH_MAJOR\t0x30\t/* Major axis of touching ellipse */\n#define ABS_MT_TOUCH_MINOR\t0x31\t/* Minor axis (omit if circular) */\n#define ABS_MT_WIDTH_MAJOR\t0x32\t/* Major axis of approaching ellipse */\n#define ABS_MT_WIDTH_MINOR\t0x33\t/* Minor axis (omit if circular) */\n#define ABS_MT_ORIENTATION\t0x34\t/* Ellipse orientation */\n#define ABS_MT_POSITION_X\t0x35\t/* Center X touch position */\n#define ABS_MT_POSITION_Y\t0x36\t/* Center Y touch position */\n#define ABS_MT_TOOL_TYPE\t0x37\t/* Type of touching device */\n#define ABS_MT_BLOB_ID\t\t0x38\t/* Group a set of packets as a blob */\n#define ABS_MT_TRACKING_ID\t0x39\t/* Unique ID of initiated contact */\n#define ABS_MT_PRESSURE\t\t0x3a\t/* Pressure on contact area */\n#define ABS_MT_DISTANCE\t\t0x3b\t/* Contact hover distance */\n#define ABS_MT_TOOL_X\t\t0x3c\t/* Center X tool position */\n#define ABS_MT_TOOL_Y\t\t0x3d\t/* Center Y tool position */\n\n\n#define ABS_MAX\t\t\t0x3f\n#define ABS_CNT\t\t\t(ABS_MAX+1)\n\n/*\n * Switch events\n */\n\n#define SW_LID\t\t\t0x00 /* set = lid shut */\n#define SW_TABLET_MODE\t\t0x01 /* set = tablet mode */\n#define SW_HEADPHONE_INSERT\t0x02 /* set = inserted */\n#define SW_RFKILL_ALL\t\t0x03 /* rfkill master switch, type \"any\"\n\t\t\t\t\t set = radio enabled */\n#define SW_RADIO\t\tSW_RFKILL_ALL\t/* deprecated */\n#define SW_MICROPHONE_INSERT\t0x04 /* set = inserted */\n#define SW_DOCK\t\t\t0x05 /* set = plugged into dock */\n#define SW_LINEOUT_INSERT\t0x06 /* set = inserted */\n#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */\n#define SW_VIDEOOUT_INSERT\t0x08 /* set = inserted */\n#define SW_CAMERA_LENS_COVER\t0x09 /* set = lens covered */\n#define SW_KEYPAD_SLIDE\t\t0x0a /* set = keypad slide out */\n#define SW_FRONT_PROXIMITY\t0x0b /* set = front proximity sensor active */\n#define SW_ROTATE_LOCK\t\t0x0c /* set = rotate locked/disabled */\n#define SW_LINEIN_INSERT\t0x0d /* set = inserted */\n#define SW_MUTE_DEVICE\t\t0x0e /* set = device disabled */\n#define SW_MAX\t\t\t0x0f\n#define SW_CNT\t\t\t(SW_MAX+1)\n\n/*\n * Misc events\n */\n\n#define MSC_SERIAL\t\t0x00\n#define MSC_PULSELED\t\t0x01\n#define MSC_GESTURE\t\t0x02\n#define MSC_RAW\t\t\t0x03\n#define MSC_SCAN\t\t0x04\n#define MSC_TIMESTAMP\t\t0x05\n#define MSC_MAX\t\t\t0x07\n#define MSC_CNT\t\t\t(MSC_MAX+1)\n\n/*\n * LEDs\n */\n\n#define LED_NUML\t\t0x00\n#define LED_CAPSL\t\t0x01\n#define LED_SCROLLL\t\t0x02\n#define LED_COMPOSE\t\t0x03\n#define LED_KANA\t\t0x04\n#define LED_SLEEP\t\t0x05\n#define LED_SUSPEND\t\t0x06\n#define LED_MUTE\t\t0x07\n#define LED_MISC\t\t0x08\n#define LED_MAIL\t\t0x09\n#define LED_CHARGING\t\t0x0a\n#define LED_MAX\t\t\t0x0f\n#define LED_CNT\t\t\t(LED_MAX+1)\n\n/*\n * Autorepeat values\n */\n\n#define REP_DELAY\t\t0x00\n#define REP_PERIOD\t\t0x01\n#define REP_MAX\t\t\t0x01\n#define REP_CNT\t\t\t(REP_MAX+1)\n\n/*\n * Sounds\n */\n\n#define SND_CLICK\t\t0x00\n#define SND_BELL\t\t0x01\n#define SND_TONE\t\t0x02\n#define SND_MAX\t\t\t0x07\n#define SND_CNT\t\t\t(SND_MAX+1)\n\n#define MATRIX_KEY(row, col, code)\t\\\n\t((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))\n\n#endif /* _DT_BINDINGS_INPUT_INPUT_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/interrupt-controller/irq.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most IRQ bindings.\n *\n * Most IRQ bindings include a flags cell as part of the IRQ specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n\n#define IRQ_TYPE_NONE\t\t0\n#define IRQ_TYPE_EDGE_RISING\t1\n#define IRQ_TYPE_EDGE_FALLING\t2\n#define IRQ_TYPE_EDGE_BOTH\t(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)\n#define IRQ_TYPE_LEVEL_HIGH\t4\n#define IRQ_TYPE_LEVEL_LOW\t8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/net/ti-dp83867.h", "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Device Tree constants for the Texas Instruments DP83867 PHY\n *\n * Author: Dan Murphy \n *\n * Copyright: (C) 2015 Texas Instruments, Inc.\n */\n\n#ifndef _DT_BINDINGS_TI_DP83867_H\n#define _DT_BINDINGS_TI_DP83867_H\n\n/* PHY CTRL bits */\n#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB\t0x00\n#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB\t0x01\n#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB\t0x02\n#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB\t0x03\n\n/* RGMIIDCTL internal delay for rx and tx */\n#define\tDP83867_RGMIIDCTL_250_PS\t0x0\n#define\tDP83867_RGMIIDCTL_500_PS\t0x1\n#define\tDP83867_RGMIIDCTL_750_PS\t0x2\n#define\tDP83867_RGMIIDCTL_1_NS\t\t0x3\n#define\tDP83867_RGMIIDCTL_1_25_NS\t0x4\n#define\tDP83867_RGMIIDCTL_1_50_NS\t0x5\n#define\tDP83867_RGMIIDCTL_1_75_NS\t0x6\n#define\tDP83867_RGMIIDCTL_2_00_NS\t0x7\n#define\tDP83867_RGMIIDCTL_2_25_NS\t0x8\n#define\tDP83867_RGMIIDCTL_2_50_NS\t0x9\n#define\tDP83867_RGMIIDCTL_2_75_NS\t0xa\n#define\tDP83867_RGMIIDCTL_3_00_NS\t0xb\n#define\tDP83867_RGMIIDCTL_3_25_NS\t0xc\n#define\tDP83867_RGMIIDCTL_3_50_NS\t0xd\n#define\tDP83867_RGMIIDCTL_3_75_NS\t0xe\n#define\tDP83867_RGMIIDCTL_4_00_NS\t0xf\n\n/* IO_MUX_CFG - Clock output selection */\n#define DP83867_CLK_O_SEL_CHN_A_RCLK\t\t0x0\n#define DP83867_CLK_O_SEL_CHN_B_RCLK\t\t0x1\n#define DP83867_CLK_O_SEL_CHN_C_RCLK\t\t0x2\n#define DP83867_CLK_O_SEL_CHN_D_RCLK\t\t0x3\n#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5\t0x4\n#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5\t0x5\n#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5\t0x6\n#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5\t0x7\n#define DP83867_CLK_O_SEL_CHN_A_TCLK\t\t0x8\n#define DP83867_CLK_O_SEL_CHN_B_TCLK\t\t0x9\n#define DP83867_CLK_O_SEL_CHN_C_TCLK\t\t0xA\n#define DP83867_CLK_O_SEL_CHN_D_TCLK\t\t0xB\n#define DP83867_CLK_O_SEL_REF_CLK\t\t0xC\n/* Special flag to indicate clock should be off */\n#define DP83867_CLK_O_SEL_OFF\t\t\t0xFFFFFFFF\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/phy/phy.h", "content": "/*\n *\n * This header provides constants for the phy framework\n *\n * Copyright (C) 2014 STMicroelectronics\n * Author: Gabriel Fernandez \n * License terms: GNU General Public License (GPL), version 2\n */\n\n#ifndef _DT_BINDINGS_PHY\n#define _DT_BINDINGS_PHY\n\n#define PHY_NONE\t\t0\n#define PHY_TYPE_SATA\t\t1\n#define PHY_TYPE_PCIE\t\t2\n#define PHY_TYPE_USB2\t\t3\n#define PHY_TYPE_USB3\t\t4\n#define PHY_TYPE_UFS\t\t5\n#define PHY_TYPE_DP\t\t6\n#define PHY_TYPE_XPCS\t\t7\n#define PHY_TYPE_SGMII\t\t8\n#define PHY_TYPE_QSGMII\t\t9\n\n#endif /* _DT_BINDINGS_PHY */\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * MIO pin configuration defines for Xilinx ZynqMP\n *\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H\n#define _DT_BINDINGS_PINCTRL_ZYNQMP_H\n\n/* Bit value for different voltage levels */\n#define IO_STANDARD_LVCMOS33\t0\n#define IO_STANDARD_LVCMOS18\t1\n\n/* Bit values for Slew Rates */\n#define SLEW_RATE_FAST\t\t0\n#define SLEW_RATE_SLOW\t\t1\n\n/* Bit values for Pin drive strength */\n#define DRIVE_STRENGTH_2MA\t2\n#define DRIVE_STRENGTH_4MA\t4\n#define DRIVE_STRENGTH_8MA\t8\n#define DRIVE_STRENGTH_12MA\t12\n\n#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/power/xlnx-versal-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_POWER_H\n#define _DT_BINDINGS_VERSAL_POWER_H\n\n#define PM_DEV_USB_0\t\t\t\t(0x18224018U)\n#define PM_DEV_GEM_0\t\t\t\t(0x18224019U)\n#define PM_DEV_GEM_1\t\t\t\t(0x1822401aU)\n#define PM_DEV_SPI_0\t\t\t\t(0x1822401bU)\n#define PM_DEV_SPI_1\t\t\t\t(0x1822401cU)\n#define PM_DEV_I2C_0\t\t\t\t(0x1822401dU)\n#define PM_DEV_I2C_1\t\t\t\t(0x1822401eU)\n#define PM_DEV_I2C_PMC (0x1822402dU)\n#define PM_DEV_CAN_FD_0\t\t\t\t(0x1822401fU)\n#define PM_DEV_CAN_FD_1\t\t\t\t(0x18224020U)\n#define PM_DEV_UART_0\t\t\t\t(0x18224021U)\n#define PM_DEV_UART_1\t\t\t\t(0x18224022U)\n#define PM_DEV_GPIO\t\t\t\t(0x18224023U)\n#define PM_DEV_TTC_0\t\t\t\t(0x18224024U)\n#define PM_DEV_TTC_1\t\t\t\t(0x18224025U)\n#define PM_DEV_TTC_2\t\t\t\t(0x18224026U)\n#define PM_DEV_TTC_3\t\t\t\t(0x18224027U)\n#define PM_DEV_SWDT_FPD\t\t\t\t(0x18224029U)\n#define PM_DEV_OSPI\t\t\t\t(0x1822402aU)\n#define PM_DEV_QSPI\t\t\t\t(0x1822402bU)\n#define PM_DEV_GPIO_PMC\t\t\t\t(0x1822402cU)\n#define PM_DEV_SDIO_0\t\t\t\t(0x1822402eU)\n#define PM_DEV_SDIO_1\t\t\t\t(0x1822402fU)\n#define PM_DEV_RTC\t\t\t\t(0x18224034U)\n#define PM_DEV_ADMA_0\t\t\t\t(0x18224035U)\n#define PM_DEV_ADMA_1\t\t\t\t(0x18224036U)\n#define PM_DEV_ADMA_2\t\t\t\t(0x18224037U)\n#define PM_DEV_ADMA_3\t\t\t\t(0x18224038U)\n#define PM_DEV_ADMA_4\t\t\t\t(0x18224039U)\n#define PM_DEV_ADMA_5\t\t\t\t(0x1822403aU)\n#define PM_DEV_ADMA_6\t\t\t\t(0x1822403bU)\n#define PM_DEV_ADMA_7\t\t\t\t(0x1822403cU)\n#define PM_DEV_AI\t\t\t\t(0x18224072U)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/power/xlnx-zynqmp-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_POWER_H\n#define _DT_BINDINGS_ZYNQMP_POWER_H\n\n#define\t\tPD_USB_0\t22\n#define\t\tPD_USB_1\t23\n#define\t\tPD_TTC_0\t24\n#define\t\tPD_TTC_1\t25\n#define\t\tPD_TTC_2\t26\n#define\t\tPD_TTC_3\t27\n#define\t\tPD_SATA\t\t28\n#define\t\tPD_ETH_0\t29\n#define\t\tPD_ETH_1\t30\n#define\t\tPD_ETH_2\t31\n#define\t\tPD_ETH_3\t32\n#define\t\tPD_UART_0\t33\n#define\t\tPD_UART_1\t34\n#define\t\tPD_SPI_0\t35\n#define\t\tPD_SPI_1\t36\n#define\t\tPD_I2C_0\t37\n#define\t\tPD_I2C_1\t38\n#define\t\tPD_SD_0\t\t39\n#define\t\tPD_SD_1\t\t40\n#define\t\tPD_DP\t\t41\n#define\t\tPD_GDMA\t\t42\n#define\t\tPD_ADMA\t\t43\n#define\t\tPD_NAND\t\t44\n#define\t\tPD_QSPI\t\t45\n#define\t\tPD_GPIO\t\t46\n#define\t\tPD_CAN_0\t47\n#define\t\tPD_CAN_1\t48\n#define\t\tPD_GPU\t\t58\n#define\t\tPD_PCIE\t\t59\n#define\t\tPD_PL\t\t69\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H\n#define _DT_BINDINGS_ZYNQMP_RESETS_H\n\n#define\t\tZYNQMP_RESET_PCIE_CFG\t\t0\n#define\t\tZYNQMP_RESET_PCIE_BRIDGE\t1\n#define\t\tZYNQMP_RESET_PCIE_CTRL\t\t2\n#define\t\tZYNQMP_RESET_DP\t\t\t3\n#define\t\tZYNQMP_RESET_SWDT_CRF\t\t4\n#define\t\tZYNQMP_RESET_AFI_FM5\t\t5\n#define\t\tZYNQMP_RESET_AFI_FM4\t\t6\n#define\t\tZYNQMP_RESET_AFI_FM3\t\t7\n#define\t\tZYNQMP_RESET_AFI_FM2\t\t8\n#define\t\tZYNQMP_RESET_AFI_FM1\t\t9\n#define\t\tZYNQMP_RESET_AFI_FM0\t\t10\n#define\t\tZYNQMP_RESET_GDMA\t\t11\n#define\t\tZYNQMP_RESET_GPU_PP1\t\t12\n#define\t\tZYNQMP_RESET_GPU_PP0\t\t13\n#define\t\tZYNQMP_RESET_GPU\t\t14\n#define\t\tZYNQMP_RESET_GT\t\t\t15\n#define\t\tZYNQMP_RESET_SATA\t\t16\n#define\t\tZYNQMP_RESET_ACPU3_PWRON\t17\n#define\t\tZYNQMP_RESET_ACPU2_PWRON\t18\n#define\t\tZYNQMP_RESET_ACPU1_PWRON\t19\n#define\t\tZYNQMP_RESET_ACPU0_PWRON\t20\n#define\t\tZYNQMP_RESET_APU_L2\t\t21\n#define\t\tZYNQMP_RESET_ACPU3\t\t22\n#define\t\tZYNQMP_RESET_ACPU2\t\t23\n#define\t\tZYNQMP_RESET_ACPU1\t\t24\n#define\t\tZYNQMP_RESET_ACPU0\t\t25\n#define\t\tZYNQMP_RESET_DDR\t\t26\n#define\t\tZYNQMP_RESET_APM_FPD\t\t27\n#define\t\tZYNQMP_RESET_SOFT\t\t28\n#define\t\tZYNQMP_RESET_GEM0\t\t29\n#define\t\tZYNQMP_RESET_GEM1\t\t30\n#define\t\tZYNQMP_RESET_GEM2\t\t31\n#define\t\tZYNQMP_RESET_GEM3\t\t32\n#define\t\tZYNQMP_RESET_QSPI\t\t33\n#define\t\tZYNQMP_RESET_UART0\t\t34\n#define\t\tZYNQMP_RESET_UART1\t\t35\n#define\t\tZYNQMP_RESET_SPI0\t\t36\n#define\t\tZYNQMP_RESET_SPI1\t\t37\n#define\t\tZYNQMP_RESET_SDIO0\t\t38\n#define\t\tZYNQMP_RESET_SDIO1\t\t39\n#define\t\tZYNQMP_RESET_CAN0\t\t40\n#define\t\tZYNQMP_RESET_CAN1\t\t41\n#define\t\tZYNQMP_RESET_I2C0\t\t42\n#define\t\tZYNQMP_RESET_I2C1\t\t43\n#define\t\tZYNQMP_RESET_TTC0\t\t44\n#define\t\tZYNQMP_RESET_TTC1\t\t45\n#define\t\tZYNQMP_RESET_TTC2\t\t46\n#define\t\tZYNQMP_RESET_TTC3\t\t47\n#define\t\tZYNQMP_RESET_SWDT_CRL\t\t48\n#define\t\tZYNQMP_RESET_NAND\t\t49\n#define\t\tZYNQMP_RESET_ADMA\t\t50\n#define\t\tZYNQMP_RESET_GPIO\t\t51\n#define\t\tZYNQMP_RESET_IOU_CC\t\t52\n#define\t\tZYNQMP_RESET_TIMESTAMP\t\t53\n#define\t\tZYNQMP_RESET_RPU_R50\t\t54\n#define\t\tZYNQMP_RESET_RPU_R51\t\t55\n#define\t\tZYNQMP_RESET_RPU_AMBA\t\t56\n#define\t\tZYNQMP_RESET_OCM\t\t57\n#define\t\tZYNQMP_RESET_RPU_PGE\t\t58\n#define\t\tZYNQMP_RESET_USB0_CORERESET\t59\n#define\t\tZYNQMP_RESET_USB1_CORERESET\t60\n#define\t\tZYNQMP_RESET_USB0_HIBERRESET\t61\n#define\t\tZYNQMP_RESET_USB1_HIBERRESET\t62\n#define\t\tZYNQMP_RESET_USB0_APB\t\t63\n#define\t\tZYNQMP_RESET_USB1_APB\t\t64\n#define\t\tZYNQMP_RESET_IPI\t\t65\n#define\t\tZYNQMP_RESET_APM_LPD\t\t66\n#define\t\tZYNQMP_RESET_RTC\t\t67\n#define\t\tZYNQMP_RESET_SYSMON\t\t68\n#define\t\tZYNQMP_RESET_AFI_FM6\t\t69\n#define\t\tZYNQMP_RESET_LPD_SWDT\t\t70\n#define\t\tZYNQMP_RESET_FPD\t\t71\n#define\t\tZYNQMP_RESET_RPU_DBG1\t\t72\n#define\t\tZYNQMP_RESET_RPU_DBG0\t\t73\n#define\t\tZYNQMP_RESET_DBG_LPD\t\t74\n#define\t\tZYNQMP_RESET_DBG_FPD\t\t75\n#define\t\tZYNQMP_RESET_APLL\t\t76\n#define\t\tZYNQMP_RESET_DPLL\t\t77\n#define\t\tZYNQMP_RESET_VPLL\t\t78\n#define\t\tZYNQMP_RESET_IOPLL\t\t79\n#define\t\tZYNQMP_RESET_RPLL\t\t80\n#define\t\tZYNQMP_RESET_GPO3_PL_0\t\t81\n#define\t\tZYNQMP_RESET_GPO3_PL_1\t\t82\n#define\t\tZYNQMP_RESET_GPO3_PL_2\t\t83\n#define\t\tZYNQMP_RESET_GPO3_PL_3\t\t84\n#define\t\tZYNQMP_RESET_GPO3_PL_4\t\t85\n#define\t\tZYNQMP_RESET_GPO3_PL_5\t\t86\n#define\t\tZYNQMP_RESET_GPO3_PL_6\t\t87\n#define\t\tZYNQMP_RESET_GPO3_PL_7\t\t88\n#define\t\tZYNQMP_RESET_GPO3_PL_8\t\t89\n#define\t\tZYNQMP_RESET_GPO3_PL_9\t\t90\n#define\t\tZYNQMP_RESET_GPO3_PL_10\t\t91\n#define\t\tZYNQMP_RESET_GPO3_PL_11\t\t92\n#define\t\tZYNQMP_RESET_GPO3_PL_12\t\t93\n#define\t\tZYNQMP_RESET_GPO3_PL_13\t\t94\n#define\t\tZYNQMP_RESET_GPO3_PL_14\t\t95\n#define\t\tZYNQMP_RESET_GPO3_PL_15\t\t96\n#define\t\tZYNQMP_RESET_GPO3_PL_16\t\t97\n#define\t\tZYNQMP_RESET_GPO3_PL_17\t\t98\n#define\t\tZYNQMP_RESET_GPO3_PL_18\t\t99\n#define\t\tZYNQMP_RESET_GPO3_PL_19\t\t100\n#define\t\tZYNQMP_RESET_GPO3_PL_20\t\t101\n#define\t\tZYNQMP_RESET_GPO3_PL_21\t\t102\n#define\t\tZYNQMP_RESET_GPO3_PL_22\t\t103\n#define\t\tZYNQMP_RESET_GPO3_PL_23\t\t104\n#define\t\tZYNQMP_RESET_GPO3_PL_24\t\t105\n#define\t\tZYNQMP_RESET_GPO3_PL_25\t\t106\n#define\t\tZYNQMP_RESET_GPO3_PL_26\t\t107\n#define\t\tZYNQMP_RESET_GPO3_PL_27\t\t108\n#define\t\tZYNQMP_RESET_GPO3_PL_28\t\t109\n#define\t\tZYNQMP_RESET_GPO3_PL_29\t\t110\n#define\t\tZYNQMP_RESET_GPO3_PL_30\t\t111\n#define\t\tZYNQMP_RESET_GPO3_PL_31\t\t112\n#define\t\tZYNQMP_RESET_RPU_LS\t\t113\n#define\t\tZYNQMP_RESET_PS_ONLY\t\t114\n#define\t\tZYNQMP_RESET_PL\t\t\t115\n#define\t\tZYNQMP_RESET_PS_PL0\t\t116\n#define\t\tZYNQMP_RESET_PS_PL1\t\t117\n#define\t\tZYNQMP_RESET_PS_PL2\t\t118\n#define\t\tZYNQMP_RESET_PS_PL3\t\t119\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/versal/versal-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-versal-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-power.h\"\n/ {\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tcan0_clk: can0_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN0_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tcan1_clk: can1_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN1_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t\tversal_sec_cfg: versal-sec-cfg {\n\t\t\t\tcompatible = \"xlnx,versal-sec-cfg\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tbbram_zeroize: bbram-zeroize@4 {\n\t\t\t\t\treg = <0x04 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_key: bbram-key@10 {\n\t\t\t\t\treg = <0x10 0x20>;\n\t\t\t\t};\n\n\t\t\t\tbbram_usr: bbram-usr@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_lock: bbram-lock@48 {\n\t\t\t\t\treg = <0x48 0x4>;\n\t\t\t\t};\n\n\t\t\t\tuser_key0: user-key@110 {\n\t\t\t\t\treg = <0x110 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key1: user-key@130 {\n\t\t\t\t\treg = <0x130 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key2: user-key@150 {\n\t\t\t\t\treg = <0x150 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key3: user-key@170 {\n\t\t\t\t\treg = <0x170 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key4: user-key@190 {\n\t\t\t\t\treg = <0x190 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key5: user-key@1b0 {\n\t\t\t\t\treg = <0x1b0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key6: user-key@1d0 {\n\t\t\t\t\treg = <0x1d0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key7: user-key@1f0 {\n\t\t\t\t\treg = <0x1f0 0x20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk ACPU>;\n};\n\n&can0 {\n\tclocks = <&can0_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_0>;\n};\n\n&can1 {\n\tclocks = <&can1_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_1>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_0>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_1>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk PMC_LSBUS_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO_PMC>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk I2C0_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_0>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk I2C1_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_1>;\n};\n\n&i2c2 {\n\tclocks = <&versal_clk I2C_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_PMC>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_0>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_1>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_2>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_3>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_4>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_5>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_6>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_7>;\n};\n\n&qspi {\n\tclocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_QSPI>;\n};\n\n&ospi {\n\tclocks = <&versal_clk OSPI_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_OSPI>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware PM_DEV_RTC>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_0>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_1>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_0>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_1>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_0>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_1>;\n};\n\n&ttc0 {\n\tclocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_0>;\n};\n\n&ttc1 {\n\tclocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_1>;\n};\n\n&ttc2 {\n\tclocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_2>;\n};\n\n&ttc3 {\n\tclocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_3>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_USB_0>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SWDT_FPD>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/versal/versal-spp-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\talt_ref_clk: alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware-wip\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"alt_ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk 77>;\n};\n\n&can0 {\n\tclocks = <&versal_clk 96>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401f>;\n};\n\n&can1 {\n\tclocks = <&versal_clk 97>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224020>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x18224019>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x1822401a>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk 61>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk 98>;\n\tpower-domains = <&versal_firmware 0x1822401d>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk 99>;\n\tpower-domains = <&versal_firmware 0x1822401e>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224035>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224036>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224037>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224038>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224039>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403a>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403b>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403c>;\n};\n\n&qspi {\n\tclocks = <&versal_clk 57>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402b>;\n};\n\n&ospi {\n\tclocks = <&versal_clk 58>, <&versal_clk 82>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware 0x18224034>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk 92>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224021>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk 93>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224022>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk 59>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402e>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk 60>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402f>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk 94>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401b>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk 95>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401c>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk 91>, <&versal_clk 104>;\n\tpower-domains = <&versal_firmware 0x18224018>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk 82>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/versal/versal.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal\";\n\n\tcpus: cpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <1>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tfpga: fpga {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&versal_fpga>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tpsci: psci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 7 0x304>;\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t};\n\n\tversal_fpga: versal_fpga {\n\t\tcompatible = \"xlnx,versal-fpga\";\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t\tinterrupt-parent = <&gic>;\n\t\tu-boot,dm-pre-reloc;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\t\t\treg = <0 0xf9000000 0 0x80000>, /* GICD */\n\t\t\t <0 0xf9080000 0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\n\t\t\tgic_its: gic-its@f9020000 {\n\t\t\t\tcompatible = \"arm,gic-v3-its\";\n\t\t\t\tmsi-controller;\n\t\t\t\tmsi-cells = <1>;\n\t\t\t\treg = <0 0xf9020000 0 0x20000>;\n\t\t\t};\n\t\t};\n\n\t\tapm: performance-monitor@f0920000 {\n\t\t\tcompatible = \"xlnx,flexnoc-pm-2.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg-names = \"funnel\", \"baselpd\", \"basefpd\";\n\t\t\treg = <0x0 0xf0920000 0x0 0x1000>,\n\t\t\t <0x0 0xf0980000 0x0 0x9000>,\n\t\t\t <0x0 0xf0b80000 0x0 0x9000>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff060000 0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff070000 0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcci: cci@fd000000 {\n\t\t\tcompatible = \"arm,cci-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd000000 0 0x10000>;\n\t\t\tranges = <0 0 0xfd000000 0xa0000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcci_pmu: pmu@10000 {\n\t\t\t\tcompatible = \"arm,cci-500-pmu,r0\";\n\t\t\t\treg = <0x10000 0x90000>;\n\t\t\t\tinterrupts = <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>;\n\t\t\t};\n\t\t};\n\n\t\tlpd_dma_chan0: dma@ffa80000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa80000 0 0x1000>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa90000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa90000 0 0x1000>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffaa0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaa0000 0 0x1000>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\n\t\tlpd_dma_chan3: dma@ffab0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffab0000 0 0x1000>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffac0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffac0000 0 0x1000>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffad0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffad0000 0 0x1000>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffae0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffae0000 0 0x1000>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffaf0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaf0000 0 0x1000>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tgem0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0c0000 0 0x1000>;\n\t\t\tinterrupts = <0 56 4>, <0 56 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0d0000 0 0x1000>;\n\t\t\tinterrupts = <0 58 4>, <0 58 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tgpio0: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0b0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff020000 0 0x1000>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff030000 0 0x1000>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c2: i2c@f1000000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1000000 0 0x1000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tmc0: memory-controller@f6150000\t{\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <0>;\n\t\t};\n\n\t\tmc1: memory-controller@f62c0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <1>;\n\t\t};\n\n\t\tmc2: memory-controller@f6430000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <2>;\n\t\t};\n\n\t\tmc3: memory-controller@f65a0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <3>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tcalibration = <0x7FFF>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff000000 0 0x1000>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tserial1: serial@ff010000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff010000 0 0x1000>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd800000 0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 124 4>, <0 124 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,is-stig-pgm = <1>;\n\t\t\tcdns,trigger-address = <0xC0000000>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#stream-id-cells = <1>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff040000 0 0x1000>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff050000 0 0x1000>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsysmon0: sysmon@f1270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\treg = <0x0 0xf1270000 0x0 0x4000>;\n\t\t\tinterrupts = <0 144 4>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\t\tsysmon1: sysmon@109270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x09270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tsysmon2: sysmon@111270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x11270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\t\tsysmon3: sysmon@119270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x19270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\t\tttc0: timer@ff0e0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff0f0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 40 4>, <0 41 4>, <0 42 4>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff100000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 46 4>, <0 47 4>, <0 48 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tusb0: usb@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff9d0000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_0: usb@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0 0xfe200000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"usb-wakeup\";\n\t\t\t\tinterrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,mask_phy_reset;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\tcpm_pciea: pci@fca10000 {\n\t\t\t#address-cells = <3>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"xlnx,versal-cpm-host-1.00\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc_0 0>,\n\t\t\t\t\t<0 0 0 2 &pcie_intc_0 1>,\n\t\t\t\t\t<0 0 0 3 &pcie_intc_0 2>,\n\t\t\t\t\t<0 0 0 4 &pcie_intc_0 3>;\n\t\t\tinterrupt-map-mask = <0 0 0 7>;\n\t\t\tinterrupt-names = \"misc\";\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>,\n\t\t\t\t <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>;\n\t\t\tmsi-map = <0x0 &gic_its 0x0 0x10000>;\n\t\t\treg = <0x0 0xfca10000 0x0 0x1000>,\n\t\t\t <0x6 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"cpm_slcr\", \"cfg\";\n\t\t\tpcie_intc_0: pci-interrupt-controller {\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\tinterrupt-controller ;\n\t\t\t};\n\t\t};\n\n\t\twatchdog: watchdog@fd4d0000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd4d0000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 0x64 1>, <0 0x6D 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t};\n\t};\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/zynq/zynq-7000.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\treplicator {\n\t\tcompatible = \"arm,coresight-static-replicator\";\n\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\tout-ports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\t/* replicator output ports */\n\t\t\tport@0 {\n\t\t\t\treg = <0>;\n\t\t\t\treplicator_out_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&tpiu_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tport@1 {\n\t\t\t\treg = <1>;\n\t\t\t\treplicator_out_port1: endpoint {\n\t\t\t\t\tremote-endpoint = <&etb_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tin-ports {\n\t\t\t/* replicator input port */\n\t\t\tport {\n\t\t\t\treplicator_in_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&funnel_out_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tamba: axi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocmc: ocmc@f800c000 {\n\t\t\tcompatible = \"xlnx,zynq-ocmc-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 3 4>;\n\t\t\treg = <0xf800c000 0x1000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\", \"arm,primecell\";\n\t\t\treg = <0xe000e000 0x0001000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"apb_pclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */\n\t\t\t\t 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */\n\t\t\t\t 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tnfc0: nand-controller@0,0 {\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0 0 0x1000000>;\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t};\n\t\t\tnor0: flash@1,0 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <1 0 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tsdhci0: mmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: mmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\tetb@f8801000 {\n\t\t\tcompatible = \"arm,coresight-etb10\", \"arm,primecell\";\n\t\t\treg = <0xf8801000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\tetb_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ttpiu@f8803000 {\n\t\t\tcompatible = \"arm,coresight-tpiu\", \"arm,primecell\";\n\t\t\treg = <0xf8803000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\ttpiu_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tfunnel@f8804000 {\n\t\t\tcompatible = \"arm,coresight-static-funnel\", \"arm,primecell\";\n\t\t\treg = <0xf8804000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\t\t/* funnel output ports */\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tfunnel_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint =\n\t\t\t\t\t\t\t<&replicator_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tin-ports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\t/* funnel input ports */\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tfunnel0_in_port0: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm0_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tfunnel0_in_port1: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm1_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tfunnel0_in_port2: endpoint {\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t/* The other input ports are not connect to anything */\n\t\t\t};\n\t\t};\n\n\t\tptm@f889c000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889c000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu0>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm0_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889d000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889d000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu1>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm1_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/zynqmp/zynqmp-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-zynqmp-clk.h\"\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL0_REF>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL1_REF>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL2_REF>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL3_REF>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tdp_aclk: dp_aclk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&zynqmp_firmware {\n\tzynqmp_clk: clock-controller {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,\n\t\t\t <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\",\n\t\t\t \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t};\n};\n\n&can0 {\n\tclocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&can1 {\n\tclocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&cpu0 {\n\tclocks = <&zynqmp_clk ACPU>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gpu {\n\tclocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&nand0 {\n\tclocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gem0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>,\n\t\t <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>;\n};\n\n&gem1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>,\n\t\t <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>;\n};\n\n&gem2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>,\n\t\t <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>;\n};\n\n&gem3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>,\n\t\t <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>;\n};\n\n&gpio {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&i2c0 {\n\tclocks = <&zynqmp_clk I2C0_REF>;\n};\n\n&i2c1 {\n\tclocks = <&zynqmp_clk I2C1_REF>;\n};\n\n&perf_monitor_ocm {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&perf_monitor_ddr {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_cci {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_lpd {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&pcie {\n\tclocks = <&zynqmp_clk PCIE_REF>;\n};\n\n&qspi {\n\tclocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&sata {\n\tclocks = <&zynqmp_clk SATA_REF>;\n};\n\n&sdhci0 {\n\tclocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;\n\tassigned-clocks = <&zynqmp_clk SDIO0_REF>;\n};\n\n&sdhci1 {\n\tclocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;\n\tassigned-clocks = <&zynqmp_clk SDIO1_REF>;\n};\n\n&spi0 {\n\tclocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&spi1 {\n\tclocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart0 {\n\tclocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart1 {\n\tclocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&usb0 {\n\tclocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n\tassigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&usb1 {\n\tclocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n\tassigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&watchdog0 {\n\tclocks = <&zynqmp_clk WDT>;\n};\n\n&lpd_watchdog {\n\tclocks = <&zynqmp_clk LPD_WDT>;\n};\n\n&xilinx_ams {\n\tclocks = <&zynqmp_clk AMS_REF>;\n};\n\n&zynqmp_dpdma {\n\tclocks = <&zynqmp_clk DPDMA_REF>;\n\tassigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */\n};\n\n&zynqmp_dpsub {\n\tclocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>;\n\tassigned-clocks = <&zynqmp_clk DP_STC_REF>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */\n};\n\n&zynqmp_dp_snd_codec0 {\n\tclocks = <&zynqmp_clk DP_AUDIO_REF>;\n};\n\n&zynqmp_pcap {\n\tclocks = <&zynqmp_clk PCAP>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.1/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n#include \"include/dt-bindings/dma/xlnx-zynqmp-dpdma.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/power/xlnx-zynqmp-power.h\"\n#include \"include/dt-bindings/reset/xlnx-zynqmp-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu-opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tzynqmp_ipi: zynqmp_ipi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t\txlnx,ipi-id = <0>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff990400 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\treg = <0x0 0xff9905c0 0x0 0x20>,\n\t\t\t <0x0 0xff9905e0 0x0 0x20>,\n\t\t\t <0x0 0xff990e80 0x0 0x20>,\n\t\t\t <0x0 0xff990ea0 0x0 0x20>;\n\t\t\treg-names = \"local_request_region\",\n\t\t\t\t \"local_response_region\",\n\t\t\t\t \"remote_request_region\",\n\t\t\t\t \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <4>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tzynqmp_firmware: zynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x1>;\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tnvmem_firmware {\n\t\t\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tsoc_revision: soc_revision@0 {\n\t\t\t\t\treg = <0x0 0x4>;\n\t\t\t\t};\n\t\t\t\t/* efuse access */\n\t\t\t\tefuse_dna: efuse_dna@c {\n\t\t\t\t\treg = <0xc 0xc>;\n\t\t\t\t};\n\t\t\t\tefuse_usr0: efuse_usr0@20 {\n\t\t\t\t\treg = <0x20 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr1: efuse_usr1@24 {\n\t\t\t\t\treg = <0x24 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr2: efuse_usr2@28 {\n\t\t\t\t\treg = <0x28 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr3: efuse_usr3@2c {\n\t\t\t\t\treg = <0x2c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr4: efuse_usr4@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr5: efuse_usr5@34 {\n\t\t\t\t\treg = <0x34 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr6: efuse_usr6@38 {\n\t\t\t\t\treg = <0x38 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr7: efuse_usr7@3c {\n\t\t\t\t\treg = <0x3c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_miscusr: efuse_miscusr@40 {\n\t\t\t\t\treg = <0x40 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_chash: efuse_chash@50 {\n\t\t\t\t\treg = <0x50 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_pufmisc: efuse_pufmisc@54 {\n\t\t\t\t\treg = <0x54 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_sec: efuse_sec@58 {\n\t\t\t\t\treg = <0x58 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_spkid: efuse_spkid@5c {\n\t\t\t\t\treg = <0x5c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_ppk0hash: efuse_ppk0hash@a0 {\n\t\t\t\t\treg = <0xa0 0x30>;\n\t\t\t\t};\n\t\t\t\tefuse_ppk1hash: efuse_ppk1hash@d0 {\n\t\t\t\t\treg = <0xd0 0x30>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tzynqmp_pcap: pcap {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t\t\t\tclock-names = \"ref_clk\";\n\t\t\t};\n\n\t\t\txlnx_aes: zynqmp-aes {\n\t\t\t\tcompatible = \"xlnx,zynqmp-aes\";\n\t\t\t};\n\n\t\t\tzynqmp_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\txlnx_keccak_384: sha384 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-keccak-384\";\n\t\t\t};\n\n\t\t\txlnx_rsa: zynqmp-rsa {\n\t\t\t\tcompatible = \"xlnx,zynqmp-rsa\";\n\t\t\t};\n\n\t\t\tmodepin_gpio: gpio {\n\t\t\t\tcompatible = \"xlnx,zynqmp-gpio-modepin\";\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&zynqmp_pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t\tpower-domains = <&zynqmp_firmware PD_PL>;\n\t};\n\n\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma-controller@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma-controller@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma-controller@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma-controller@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma-controller@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma-controller@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma-controller@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma-controller@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x0 0x10000>,\n\t\t\t <0x0 0xf9020000 0x0 0x20000>,\n\t\t\t <0x0 0xf9040000 0x0 0x20000>,\n\t\t\t <0x0 0xf9060000 0x0 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\", \"gpu_pp0\", \"gpu_pp1\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPU>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma-controller@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma-controller@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma-controller@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma-controller@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma-controller@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma-controller@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma-controller@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma-controller@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t\t#stream-id-cells = <1>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand-controller@ff100000 {\n\t\t\tcompatible = \"xlnx,zynqmp-nand-controller\", \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"controller\", \"bus\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_NAND>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_0>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_1>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_2>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_3>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPIO>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tperf_monitor_ocm: perf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa00000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_ddr: perf-monitor@fd0b0000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd0b0000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <6>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <10>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_cci: perf-monitor@fd490000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd490000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_lpd: perf-monitor@ffa10000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa10000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x4d0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_PCIE>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_QSPI>;\n\t\t};\n\n\t\tpsgtr: phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\";\n\t\t\t#phy-cells = <4>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x7FFF>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SATA>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SATA>;\n\t\t\t#stream-id-cells = <4>;\n\t\t/*\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;*/\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_0>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-uart\", \"cdns,uart-r1p12\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-uart\", \"cdns,uart-r1p12\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_1>;\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_0>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\t\t\treset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tranges;\n\n\t\t\tdwc3_0: usb@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>, <0 75 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t\t/* snps,enable-hibernation; */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb1@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_1>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\n\t\t\tranges;\n\n\t\t\tdwc3_1: usb@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>, <0 76 4>;\n\t\t\t\t#stream-id-cells = <1>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <60>;\n\t\t\treset-on-timeout;\n\t\t};\n\n\t\tlpd_watchdog: watchdog@ff150000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 52 1>;\n\t\t\treg = <0x0 0xff150000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges;\n\n\t\t\tams_ps: ams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50800 0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50c00 0x0 0x400>;\n\t\t\t};\n\t\t};\n\n\t\tzynqmp_dpdma: dma-controller@fd4c0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tdma-channels = <6>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0xce4>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tzynqmp_dpaud_setting: dp_aud@fd4ac000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpaud-setting\", \"syscon\";\n\t\t\treg = <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t};\n\n\t\tzynqmp_dpsub: display@fd4a0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>;\n\t\t\treg-names = \"dp\", \"blend\", \"av_buf\";\n\t\t\txlnx,dpaud-reg = <&zynqmp_dpaud_setting>;\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\t#stream-id-cells = <1>;\n\t\t\tiommus = <&smmu 0xce3>;\n\t\t\tclock-names = \"dp_apb_clk\", \"dp_aud_clk\", \"dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_DP>;\n\t\t\tdma-names = \"vid0\", \"vid1\", \"vid2\", \"gfx0\";\n\t\t\tdmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;\n\n\t\t\t/* dummy node to to indicate there's no child i2c device */\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm0\";\n\t\t\t\tdmas = <&zynqmp_dpdma 4>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm1\";\n\t\t\t\tdmas = <&zynqmp_dpdma 5>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card0: zynqmp_dp_snd_card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,\n\t\t\t\t\t\t <&zynqmp_dp_snd_pcm1>;\n\t\t\t\txlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n i2c0 = &i2c1;\n rtc0 = &rtc;\n serial0 = &uart1;\n serial1 = &uart0;\n serial2 = &dcc;\n spi0 = &spi0;\n spi1 = &spi1;\n usb0 = &usb0;\n usb1 = &usb1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n\n\tsi5335_0: si5335_0 { /* clk0_usb - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5335_1: si5335_1 { /* clk1_dp - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 IRQ_TYPE_LEVEL_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO3\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO2\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO1\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n};\n\n&psgtr {\n\t/* usb3, dp */\n\tclocks = <&si5335_0>, <&si5335_1>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"super-speed\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/kcu105-tmr.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&tmr_0_MB1_axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/sp701-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze sp701.\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@1 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x3>;\n\t\t\tti,tx-internal-delay = <0x3>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/vcu118-rev2.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze vcu118\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@3 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\tti,sgmii-ref-clock-output-enable;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\treg = <3>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-a2197-sc-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller RevA\";\n\tcompatible = \"xlnx,versal-sc-revA\", \"xlnx,versal-sc\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\t/* SC Bank 43\n\tFIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS\n\tSYSCTLR_GPIO0 - 5 - conneced to versal */\n\t/* cpu thermal for MAX6643 fan control */\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tdc38_led {\n\t\t\tlabel = \"ds38-green\"; /* sc AB11 500_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc37_led {\n\t\t\tlabel = \"ds37-green\"; /* sc AD10 501_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc36_led {\n\t\t\tlabel = \"ds36-green\"; /* sc AD11 502_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t};\n};\n\n/* usb - type C - pl\n and micro usb 2.0, gt\n*/\n/* Feb 28/2019 version */\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n/* TODO\nUSB0 MIO52-63\nUSB1 MIO64-75\n*/\n\n/*eth MDIO 76/77\neth reset MIO42\nmarwell m88e1512 - SGMII */\n&gem0 {\n\tphy-handle = <&phy0>;\n\t/* phy-mode = \"sgmii\"; DTG generates this properly */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: phy@21 {\n\t\treg = <21>; /* FIXME */\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5- 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 0 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\"; /* FIXME no linux driver */\n\t\t\t\treg = <0xc0>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <10000000>; /* 10 ohm */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\ti2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* FIXME connection to Samtec J212D */\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t/* FIXME connection to Samtec J53C */\n\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@5d { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@5d { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@5d { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"LPDDR4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-emu-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-emu-itr8\", \"xlnx,versal-emu\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal EMU ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:9600\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n\n\tclk0212: clk0212 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <212000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n};\n\n&timer {\n clock-frequency = <440000>;\n};\n\n&serial0 {\n status = \"okay\";\n clocks = <&clk0212 &clk0212>;\n\tcurrent-speed = <9600>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-emu-rev1.9.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tcompatible = \"xlnx,versal-net-emu-1.9\", \"xlnx,versal-net-emu\";\n\tmodel = \"Xilinx Versal NET EMU 1.9\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t};\n\t};\n\n\tmemory: memory@0 {\n\t\treg = <0 0 0 0x10000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 rdinit=/bin/sh maxcpus=4\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tfirmware {\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tclk1: clk1 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <1000000>; /* it doesn't matter on EMU */\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&clk1>, <&clk1>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET IPP/SPP OSPI\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-net-ipp-rev1.9.dtsi\"\n\n/ {\n\tmodel = \"Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI\";\n};\n\n&ospi {\n\tstatus = \"okay\";\n};\n\n&qspi {\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/power/xlnx-versal-net-power.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-net-ipp-1.9\", \"xlnx,versal-net-spp-5.0\", \"xlnx,versal-net-spp\", \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal NET SPP 5.0/IPP 1.9\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t};\n\t};\n\n\tmemory: memory@0 {\n\t\treg = <0 0 0 0x80000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x01>;\n\t\t};\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t\tversal_net_reset: reset-controller {\n\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t#reset-cells = <1>;\n\t\t};\n\t};\n\n\tclk1: clk1 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <1000000>;\n\t};\n\n\tclk2_6: clk2_6 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <2670000>;\n\t};\n\n\tclk20: clk20 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <20000000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk60: clk60 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <60000000>;\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tadma0: dma-controller@ebd00000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd00000 0 0x1000>;\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tadma1: dma-controller@ebd10000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd10000 0 0x1000>;\n\t\t\tinterrupts = <0 73 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tadma2: dma-controller@ebd20000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd20000 0 0x1000>;\n\t\t\tinterrupts = <0 74 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tadma3: dma-controller@ebd30000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd30000 0 0x1000>;\n\t\t\tinterrupts = <0 75 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tadma4: dma-controller@ebd40000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd40000 0 0x1000>;\n\t\t\tinterrupts = <0 76 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tadma5: dma-controller@ebd50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd50000 0 0x1000>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tadma6: dma-controller@ebd60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd60000 0 0x1000>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tadma7: dma-controller@ebd70000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd70000 0 0x1000>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tcan0: can@f1980000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1980000 0 0x6000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&clk25>, <&clk25>;\n\t\t};\n\n\t\tcan1: can@f1990000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1990000 0 0x6000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&clk25>, <&clk25>;\n\t\t};\n\n\t\tgem0: ethernet@f19e0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19e0000 0 0x1000>;\n\t\t\tinterrupts = <0 39 4>, <0 39 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tclocks = <&clk2_6>, <&clk25>, <&clk25>, <&clk25>, <&clk25>;\n\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <11>;\n\t\t\t\tti,tx-internal-delay = <10>;\n\t\t\t\tti,fifo-depth = <1>;\n\t\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\t};\n\t\t};\n\n\t\tgem1: ethernet@f19f0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19f0000 0 0x1000>;\n\t\t\tinterrupts = <0 41 4>, <0 41 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy2>;\n\t\t\tphy-mode = \"rmii\";\n\t\t\tclocks = <&clk2_6>, <&clk25>, <&clk25>, <&clk25>, <&clk25>;\n\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t};\n\t\t};\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t};\n\n\t\tgpio0: gpio@f19d0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\treg = <0 0xf19d0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\t\ti2c0: i2c@f1940000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1940000 0 0x1000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\t\ti2c1: i2c@f1950000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1950000 0 0x1000>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\t\ti3c: i3c-master@f1948000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\treg = <0 0xf1948000 0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclocks = <&clk20>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 182 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,is-stig-pgm = <1>;\n\t\t\tcdns,trigger-address = <0xc0000000>;\n\t\t\tis-dual = <0>;\n\t\t\tis-stacked = <0>;\n\t\t\tclocks = <&clk20>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_OSPI>;\n\t\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\t\t\tmt35xu02g: flash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tcdns,read-delay = <0>;\n\t\t\t\tcdns,tshsl-ns = <0>;\n\t\t\t\tcdns,tsd2d-ns = <0>;\n\t\t\t\tcdns,tchsh-ns = <1>;\n\t\t\t\tcdns,tslch-ns = <1>;\n\t\t\t\tspi-tx-bus-width = <8>;\n\t\t\t\tspi-rx-bus-width = <8>;\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\tbroken-flash-reset;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"ospi-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"ospi-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 183 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tnum-cs = <1>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\t\t\tclocks = <&clk25>, <&clk25>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <10000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi0-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"qspi0-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupts = <0 200 4>, <0 201 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 184 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&clk20>, <&clk20>;\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 186 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&clk20>, <&clk20>;\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&clk1>, <&clk1>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tsmmu: smmu@ec000000 {\n\t\t\tcompatible = \"arm,smmu-v3\";\n\t\t\treg = <0 0xec000000 0 0x40000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tinterrupt-names = \"combined\";\n\t\t\tinterrupts = <0 169 4>;\n\t\t};\n\n\t\tspi0: spi@f1960000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupts = <0 23 4>;\n\t\t\treg = <0 0xf1960000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>, <&clk25>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@f1970000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0 0xf1970000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>, <&clk25>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tttc0: timer@f1dc0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dc0000 0x0 0x1000>;\n\t\t\tclocks = <&clk1>, <&clk1>;\n\t\t};\n\n\t\tusb0: usb@f1e00000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0 0xf1e00000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tclocks = <&clk60>, <&clk60>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_0>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_0>;\n\t\t\txlnx,usb-polarity = <0>;\n\t\t\txlnx,usb-reset-mode = <0>;\n\n\t\t\tdwc3_0: dwc3@f1b00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0 0xf1b00000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 29 4>, <0 33 4>, <0 98 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,mask_phy_reset;\n\t\t\t\tdr_mode = \"peripheral\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@f1e10000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0x0 0xf1e10000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tclocks = <&clk60 &clk60>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_1>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_1>;\n\t\t\txlnx,usb-polarity = <0x00>;\n\t\t\txlnx,usb-reset-mode = <0x00>;\n\n\t\t\tdwc3_1: dwc3@f1c00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0x0 0xf1c00000 0x0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 34 4>, <0 38 4>, <0 99 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,mask_phy_reset;\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\twwdt0: watchdog@ecc10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xecc10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 139 1>, <0 140 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\t\twwdt1: watchdog@ecd10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xecd10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 143 1>, <0 144 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\t\twwdt2: watchdog@ece10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xece10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 147 1>, <0 148 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\t\twwdt3: watchdog@ecf10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xecf10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 164 1>, <0 165 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-spp-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-spp-itr8-cn13940875\", \"xlnx,versal-spp-itr8\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal SPP ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &ospi;\n\t\tspi2 = &spi0;\n\t\tspi3 = &spi1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tusb0 = &usb0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>;\n\t};\n\tchosen {\n\t\tbootargs = \"rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n};\n\n&timer {\n\tclock-frequency = <2720000>;\n};\n\n&serial0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tmaximum-speed = \"high-speed\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n phy0: phy@0 {\n\t\treg = <0x0>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n phy1: phy@1 {\n\t\treg = <0x1>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <0x1>;\n\treg = <0x0 0xf1030000 0x0 0x1000>;\n\tclocks = <&clk125 &clk125>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot-boot.bin\";\n\t\t\t\treg = <0x0 0x6400000>;\n\t\t\t};\n\t\t\tpartition@6400000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x6400000 0x500000>;\n\t\t\t};\n\t\t\tpartition@6900000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x6900000 0x20000>;\n\t\t\t};\n\t\t\tpartition@6920000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x6920000 0x5E0000>;\n\t\t\t};\n\t\t\tpartition@7f40000 {\n\t\t\t\tlabel = \"qspi-bootenv\";\n\t\t\t\treg = <0x7f40000 0x40000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ospi {\n\tstatus = \"disabled\";\n\tclocks = <&clk125 &clk125>;\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\tcdns,fifo-depth = <508>;\n\tcdns,fifo-width = <4>;\n\tcdns,is-dma = <1>;\n\tcdns,is-stig-pgm = <1>;\n\tcdns,trigger-address = <0x00000000>;\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t};\n\t\t\tpartition@600000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t};\n\t\t\tpartition@620000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <1>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <3>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\treg = <0x0 0x84000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-v350-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal v350 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-v350-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal v350 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tspi0 = &ospi;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-01 revA OSPI\";\n\n\taliases {\n\t\tspi0 = &ospi;\n\t};\n};\n\n/* Mutually exclusive */\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\treset-names = \"qspi\";\n\tresets = <&versal_reset VERSAL_RST_OSPI>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n compatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n \"xlnx,versal-vc-p-a2197-00\",\n \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n model = \"Xilinx Versal A2197 Processor board revA\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tgpio0 = &gpio;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-01 revA QSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-02 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem0 {\n\tphy-handle = <&phy0>; /* u9 */\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@1 { /* Marvell 88E1512; U9 */\n\t\treg = <1>;\n\t};\n};\n\n&sdhci0 {\n\txlnx,mio-bank = <1>;\n};\n\n&sdhci1 { /* U1A */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* U4 */\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"high-speed\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* U12 Catalyst EEPROM - AT24 should be equivalent */\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U13 and U15 */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U18 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <3>;\t/* FIXME - check SPI1_SS0-2_B */\n\n\tflash@0 { /* U19 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst26vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-03 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tserial0 = &serial0;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* Must be enabled via J90/J91 */\n\teeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 64Mb */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x800000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* J99 MIO28 - MIO33 */\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U6 - IS25LQ032B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lq032b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA-x-prc-04 revA OSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem1 {\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <1>; /* FIXME */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tstatus = \"disabled\"; /* u93 and u92 and u161 and u160 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio-bank = <1>; /* FIXME */\n\tno-1-8-v;\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-04 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <2>;\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <1>;\n\tis-dual = <0>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 512MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x20000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-05 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem0 {\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 { /* 88e1510 */\n\t\treg = <1>;\n\t};\n\tphy2: phy@2 { /* VSC8531 */\n\t\treg = <2>;\n\t\tvsc8531,rx-delay = <6>;\n\t\tvsc8531,tx-delay = <6>;\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>;\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tspi-tx-bus-width = <4>;\n\tspi-rx-bus-width = <4>;\n\n\tflash@0 { /* MX25U12835 128Mbit */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 16MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <104000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x1000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc0 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n};\n\n&sdhci1 { /* connector */\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA\";\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 {\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-01-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-01-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (QSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-02-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-02-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (EMMC)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-03-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-03-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (OSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva-x-ebm-01-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-01-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (QSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva-x-ebm-02-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-02-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (EMMC)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva-x-ebm-03-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-03-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (OSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck5000-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck5000 revA\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vck5000-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck5000 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tspi0 = &ospi;\n\t};\n\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x10000000>;\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vek280-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VEK280 revA\n *\n * (C) Copyright 2022, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vek280-revA\", \"xlnx,versal-vek280\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vek280 Eval board revA\";\n\n\tmemory: memory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* VADJ_FMC_EN - LPD MIO23 */\n/* FAN - LPD MIO21/22 */\n/* VCC_PL_EN - LPD MIO20 */\n/* PCIE_PERST - LPD MIO18/19 */\n/* SD_BUSPWR - PMC MIO51 */\n/* PCIE_WAKE - PMC MIO50 */\n/* VCCPSLP_EN - PMC MIO49 */\n/* I2C SYSMON - PMC MIO39 - 41 */\n/* PCIE_PWRBRK - PMC MIO38 */\n/* ZU4_TRIGGER - PMC MIO37 */\n/* VCC_AUX_1V2 - MIO11 */\n\n&ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = ;\n\t\t\tti,tx-internal-delay = ;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vhk158-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VHK158 revA\n *\n * (C) Copyright 2022-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vhk158-revA\", \"xlnx,versal-vhk158\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vhk158 Eval board revA\";\n\n\tmemory: memory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* ZU4_TRIGGER - PMC MIO37 */\n/* PCIE_PWRBRK - PMC MIO38 */\n/* I2C SYSMON - PMC MIO39 - 41 */\n/* VCCPSLP_EN - PMC MIO49 */\n/* PCIE_WAKE - PMC MIO50 */\n/* SOC_EN - LPD MIO13 */\n/* PSFP_EN - LPD MIO15 */\n/* AUX_1V2_EN - LPD MIO16 */\n/* HBM_EN - LPD MIO17 */\n/* PCIE_PERST - LPD MIO18/19 */\n/* VCC_PL_EN - LPD MIO20 */\n/* FAN - LPD MIO21/22 */\n/* VADJ_FMC_EN - LPD MIO23 */\n\n&ospi { /* PMC MIO0 - 12, U297 MT35XU02G */\n\tstatus = \"okay\";\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = ;\n\t\t\tti,tx-internal-delay = ;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-virt.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-virt\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal Virtual\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tclk2: clk2 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <2670000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t\tclock-frequency = <2720000>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */\n\t\t\t <0x0 0xf9080000 0x0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x1 0x9 4>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x2>;\n\t\tranges;\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff060000 0x0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff070000 0x0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom1: eeprom@53 {\n\t\t\t\treg = <0x53>;\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t};\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom2: eeprom@55 {\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x55>;\n\t\t\t};\n\t\t};\n\n\t\tgpio: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tethernet0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 56 4>, <0x0 56 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy0: phy@0 {\n\t\t\t\treg = <0x0>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tethernet1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 58 4>, <0x0 58 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy1: phy@1 {\n\t\t\t\treg = <0x1>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xf12a0000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tnum-cs = <0x1>;\n\t\t\treg = <0x0 0xf1030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"n25q512a\", \"micron,m25p80\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-tx-bus-width = <4>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <108000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@100000 {\n\t\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@600000 {\n\t\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@620000 {\n\t\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <1>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <3>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0x0 0x84000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\treg = <0x0 0xf1040000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <0>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\treg = <0x0 0xf1050000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,device_id = <1>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\t#address-cells = <0x2>;\n\t\t\t#size-cells = <0x2>;\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tranges;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125 &clk125>;\n\n\t\t\tdwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x10000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = ðernet0;\n\t\tethernet1 = ðernet1;\n\t\tqspi = &qspi;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1 (QSPI)\";\n};\n\n&qspi {\n#include \"versal-x-ebm-01-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-02-revA\",\n\t\t \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1 (EMMC)\";\n};\n\n&sdhci1 {\n#include \"versal-x-ebm-02-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-03-revA\",\n \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board rev1.1 (OSPI)\";\n};\n\n&ospi {\n#include \"versal-x-ebm-03-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-01-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (QSPI)\";\n};\n\n&qspi {\n#include \"versal-x-ebm-01-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-02-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (EMMC)\";\n};\n\n&sdhci1 {\n#include \"versal-x-ebm-02-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-03-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (OSPI)\";\n\n aliases {\n spi0 = &ospi;\n };\n};\n\n&ospi {\n#include \"versal-x-ebm-03-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tphy2: ethernet-phy@2 { /* u134 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <2>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 49 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n&usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */\n\txlnx,usb-polarity = <0x0>;\n\txlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vp-x-a2785-00 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vp-x-a2785-00 Eval board revA\";\n\tcompatible = \"xlnx,versal-vp-x-a2785-00-revA\",\n\t\t \"xlnx,versal-vp-x-a2785-00\", \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tstatus = \"okay\"; /* u93 and u92 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */\n\tstatus = \"okay\";\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\tstatus = \"okay\";\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n/* PWM via MIO 41/FAN TACH MIO 49 - FIXME */\n\n&i2c0 { /* PMC_MIO46/47 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk120 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk120 Eval board revA\";\n\tcompatible = \"xlnx,versal-vpk120-revA\", \"xlnx,versal-vpk120\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk120-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk120 revB\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk120 Eval board revB\";\n\tcompatible = \"xlnx,versal-vpk120-revB\", \"xlnx,versal-vpk120\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n\t/* Use for storing information about board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk180 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk180 Eval board revA\";\n\tcompatible = \"xlnx,versal-vpk180-revA\", \"xlnx,versal-vpk180\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <1>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n\n&i2c0 { /* PMC_MIO46/47 */\n\tclock-frequency = <400000>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\tclock-frequency = <400000>;\n\n\t/* Use for storing information about board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tu-boot,dm-pre-reloc;\n\t};\n};\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio0 {\n\t/* FIXME Fill names when versal starts */\n};\n\n&gpio1 {\n\t/* FIXME Fill names when versal starts */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-01 revA for vck190/vmk180\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\nnum-cs = <1>;\nspi-tx-bus-width = <4>;\nspi-rx-bus-width = <4>;\n#address-cells = <1>;\n#size-cells = <0>;\nis-dual = <1>;\nflash@0 {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 256MB */\n\treg = <0>;\n\tspi-tx-bus-width = <4>;\n\tspi-rx-bus-width = <4>;\n\tspi-max-frequency = <150000000>;\n\tpartition@0 {\n\t\tlabel = \"spi0-flash0\";\n\t\treg = <0x0 0x10000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-02 revA for vck190/vmk180\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/* emmc MIO 0-13 - MTFC8GAKAJCN */\nnon-removable;\ndisable-wp;\nbus-width = <8>;\nxlnx,mio-bank = <0>;\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-03 revA for vck190/vmk180\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-resets.h\"\n/* U97 MT35XU02G */\ncompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\nbus-num = <2>;\nnum-cs = <1>;\n#address-cells = <1>;\n#size-cells = <0>;\nreset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\nreset-names = \"qspi\";\nresets = <&versal_reset VERSAL_RST_OSPI>;\n\nflash@0 {\n\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\treg = <0>;\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcdns,read-delay = <0x0>;\n\tcdns,tshsl-ns = <0x0>;\n\tcdns,tsd2d-ns = <0x0>;\n\tcdns,tchsh-ns = <0x1>;\n\tcdns,tslch-ns = <0x1>;\n\tspi-tx-bus-width = <8>;\n\tspi-rx-bus-width = <8>;\n\tspi-max-frequency = <20000000>;\n\tpartition@0 {\n\t\tlabel = \"spi0-flash0\";\n\t\treg = <0x0 0x8000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n\n\t aliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n rtc0 = &rtc;\n serial0 = &uart0;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tclock_si5338_0: clk27 {\t/* u55 SI5338-GM */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tclock_si5338_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_si5338_3: clk150 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <150000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&psgtr {\n\tstatus = \"okay\";\n\t/* dp, usb3, sata */\n\tclocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem2;\n i2c0 = &i2c0;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n spi0 = &spi0;\n spi1 = &spi1;\n usb0 = &usb1;\n };\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: ethernet-phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"soft\";\n\t\tnand-ecc-algo = \"bch\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-0\";\n\t\tnand-ecc-step-size = <1024>;\n\t\tnand-ecc-strength = <24>;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"soft\";\n\t\tnand-ecc-algo = \"bch\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-1\";\n\t\tnand-ecc-step-size = <1024>;\n\t\tnand-ecc-strength = <24>;\n\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: flash@0 {\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: flash@0 {\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n serial0 = &uart1;\n spi0 = &qspi;\n mmc0 = &sdhci0;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t\tsw13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@34 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x34>;\n\t\t\t};\n\t\t\thwmon@35 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\thwmon@36 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n serial0 = &uart1;\n spi0 = &qspi;\n mmc0 = &sdhci0;\n };\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&watchdog0 {\n\treset-on-timeout;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu100-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio-bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu100-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\t aliases {\n i2c0 = &i2c1;\n rtc0 = &rtc;\n serial0 = &uart1;\n serial1 = &uart0;\n serial2 = &dcc;\n spi0 = &spi0;\n spi1 = &spi1;\n usb0 = &usb0;\n usb1 = &usb1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n\n\tsi5335_0: si5335_0 { /* clk0_usb - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5335_1: si5335_1 { /* clk1_dp - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 IRQ_TYPE_LEVEL_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO3\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO2\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO1\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* usb3, dp */\n\tclocks = <&si5335_0>, <&si5335_1>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"super-speed\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zcu102-revb.dtsi\"\n\n/ {\n model = \"ZynqMP ZCU102 Rev1.0\";\n compatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n};\n\n&eeprom {\n #address-cells = <1>;\n #size-cells = <1>;\n\n board_sn: board-sn@0 {\n reg = <0x0 0x14>;\n };\n\n eth_mac: eth-mac@20 {\n reg = <0x20 0x6>;\n };\n\n board_name: board-name@d0 {\n reg = <0xd0 0x6>;\n };\n\n board_revision: board-revision@e0 {\n reg = <0xe0 0x3>;\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\txlnx,eeprom = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_4: out@4 {\n\t\t\t\t\t/* refclk4 for PS-GT, used for PCIE slot */\n\t\t\t\t\treg = <4>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 for PS-GT, used for PCIE */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* pcie, sata, usb3, dp */\n\tclocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\t/*\n\t * 1.0 revision has level shifter and this property should be\n\t * removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zcu102-reva.dtsi\"\n\n/ {\n model = \"ZynqMP ZCU102 RevB\";\n compatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n};\n\n&gem3 {\n phy-handle = <&phyc>;\n phyc: ethernet-phy@c {\n reg = <0xc>;\n ti,rx-internal-delay = <0x8>;\n ti,tx-internal-delay = <0xa>;\n ti,fifo-depth = <0x1>;\n ti,dp83867-rxctrl-strap-quirk;\n /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */\n };\n /* Cleanup from RevA */\n /delete-node/ ethernet-phy@21;\n};\n\n/* Fix collision with u61 */\n&i2c0 {\n i2c-mux@75 {\n i2c@2 {\n max15303@1b { /* u8 */\n compatible = \"maxim,max15303\";\n reg = <0x1b>;\n };\n /delete-node/ max15303@20;\n };\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* 8T49N287 - u182 */\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@20 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu104-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revC\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;\n\t};\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - IRPS5401_ALERT_B\n\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t * 2 - MAX6643_OT_B\n\t\t * 3 - MAX6643_FANFAIL_B\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t * 4, 10 - 17 - not connected\n\t\t */\n\t};\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* 8T49N287 - u182 */\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tu183: ina226@40 { /* u183 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 4, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\txlnx,mio-bank = <1>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tina226-u67 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;\n\t};\n\tina226-u59 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n\tina226-u69 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;\n\t};\n\tina226-u66 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;\n\t};\n\tina226-u71 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u73 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tu67: ina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u67\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu59: ina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u59\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu61: ina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu60: ina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu64: ina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu69: ina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u69\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu66: ina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u66\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu63: ina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu3: ina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u3\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu71: ina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u71\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu73: ina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u73\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u57 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SI5382 - u48 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection FIXME */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, dp, usb3, sata */\n\tclocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revA\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-revb.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU1275 RevB\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revB\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n mmc0 = &sdhci1;\n ethernet0 = &gem1;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t* 1.0 revision has level shifter and this property should be\n\t* removed for supporting UHS mode\n\t*/\n\tno-1-8-v;\n};\n\n&gem1 {\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1285-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU1285 RevA\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1285 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1285-revA\", \"xlnx,zynqmp-zcu1285\", \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n mmc0 = &sdhci1;\n ethernet0 = &gem1; /* EMIO */\n i2c = &i2c0; /* EMIO */\n };\n\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PMBUS */\n\t\t\tmax20751@74 { /* u23 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x74>;\n\t\t\t};\n\t\t\tmax20751@70 { /* u89 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x70>;\n\t\t\t};\n\t\t\tmax15301@a { /* u28 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u48 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@d { /* u27 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\tmax15303@e { /* u11 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\tmax15303@f { /* u96 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\tmax15303@11 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\tmax15303@12 { /* u24 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u29 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u51 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u30 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u102 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15301@17 { /* u50 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u31 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* CM_I2C */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYS_EEPROM */\n\t\t\teeprom: eeprom@54 { /* u101 */\n\t\t\t\tcompatible = \"atmel,24c32\"; /* 24LC32A */\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FMC1 */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FMC2 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* ANALOG_PMBUS */\n\t\t\tu60: ina226@40 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu61: ina226@41 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu63: ina226@42 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu65: ina226@43 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu64: ina226@44 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* ANALOG_CM_I2C */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FMC3 */\n\t\t};\n\t};\n};\n\n&gem1 {\n\tmdio {\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu208-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU208\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU208 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu208-revA\", \"xlnx,zynqmp-zcu208\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu216-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU216\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU216 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu216-revA\", \"xlnx,zynqmp-zcu216\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu670-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR)\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU670 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu670-revA\", \"xlnx,zynqmp-zcu670\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\"; /* DS1 */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5381_6: si5381_6 { /* refclk_usb3 - u43 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"SFP3_TX_DISABLE\", \"SFP2_TX_DISABLE\", \"SFP1_TX_DISABLE\", /* 25 - 29 */\n\t\t \"SFP0_TX_DISABLE\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"SD_PWR_RST\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"SI5381_INT_ALM\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* Not in schematics */\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5381: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SI5381 - u43 */\n\t\t\t/*si5381: clock-generator@68 {\n\t\t\t\treg = <0x68>;\n\t\t\t};*/\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_psrefclk: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"si570_ps_ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 2Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&psgtr {\n\t/* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */\n\tclocks = <&si5381_6>;\n\tclock-names = \"ref2\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zcu670-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU670 (67DR) revB\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU670 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu670-revB\", \"xlnx,zynqmp-zcu670\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tchosen {\n\t\tnvmem0 = &eeprom;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\"; /* DS1 */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5381_6: si5381_6 { /* refclk_usb3 - u43 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"SFP3_TX_DISABLE\", \"SFP2_TX_DISABLE\", \"SFP1_TX_DISABLE\", /* 25 - 29 */\n\t\t \"SFP0_TX_DISABLE\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"SD_PWR_RST\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"SI5381_INT_ALM\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* Not in schematics */\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5381: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SI5381 - u43 */\n\t\t\t/*si5381: clock-generator@68 {\n\t\t\t\treg = <0x68>;\n\t\t\t};*/\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_psrefclk: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"si570_ps_ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 2Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\tclk-phase-sd-hs = <120>, <60>;\n\tclk-phase-uhs-sdr25 = <132>, <60>;\n\tclk-phase-uhs-ddr50 = <153>, <48>;\n};\n\n&psgtr {\n\t/* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */\n\tclocks = <&si5381_6>;\n\tclock-names = \"ref2\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-a2197-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Versal System Controller on a2197 board RevA\";\n\tcompatible = \"xlnx,zynqmp-a2197-revA\", \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n i2c0 = &i2c0;\n nvmem0 = &eeprom1;\n nvmem1 = &eeprom0;\n serial0 = &uart0;\n };\n\n\tchosen {\n\t\tnvmem0 = &eeprom1;\n\t\tnvmem1 = &eeprom0;\n\t};\n};\n\n&i2c0 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* this cover MGT board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* This cover processor board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-e-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevA\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n nvmem1 = &eeprom_ebm;\n nvmem2 = &eeprom_fmc1;\n nvmem3 = &eeprom_fmc2;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n };\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t\tnvmem1 = &eeprom_ebm;\n\t\tnvmem2 = &eeprom_fmc1;\n\t\tnvmem3 = &eeprom_fmc2;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tsi570_ddrdimm1_clk: si570_ddrdimm1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tsi570_lpddr4_clk2: si570_lpddr4_clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570_lpddr4_clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk1>;\n\t};\n\n\tsi570_hsdp_clk: si570_hsdp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi570_zsfp_clk: si570_zsfp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_zsfp>;\n\t};\n\n\tsi570_user1_clk: si570_user1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_user1>;\n\t};\n\n\tsi5332_1: si5332_1 { /* u142 - GEM0 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vcc-soc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;\n\t};\n\tina226-vcc-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc-pslp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;\n\t};\n\tina226-vcc-psfp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;\n\t};\n\tina226-vccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;\n\t};\n\tina226-vccaux-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;\n\t};\n\tina226-vcco-500 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;\n\t};\n\tina226-vcco-501 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;\n\t};\n\tina226-vcco-502 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;\n\t};\n\tina226-vcco-503 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;\n\t};\n\tina226-vcc-1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;\n\t};\n\tina226-vcc-3v3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;\n\t};\n\tina226-vcc-1v2-ddr4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;\n\t};\n\tina226-vcc-1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtyavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;\n\t};\n\tina226-mgtyavtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;\n\t};\n\tina226-mgtyvccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;\n\t};\n\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n/* GEM SGMII */\n&psgtr {\n\tstatus = \"okay\";\n\t/* gem0 */\n\tclocks = <&si5332_1>;\n\tclock-names = \"ref0\";\n};\n\n&gem0 {\n\tphys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* u131 M88E1512 */\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"ZU4_TRIGGER\", \"SYSCTLR_PB\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"\", /* 85 - 89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"PMBUS_ALERT\", \"\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ttca6416_u233: gpio@20 { /* u233 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"\", \"\", /* 0 - 3 */\n\t\t\t\t\"PMBUS2_INA226_ALERT\", \"\", \"\", \"MAX6643_FULLSPD\", /* 4 - 7 */\n\t\t\t\t\"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 10 - 13 */\n\t\t\t\t\"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* u152 IR35215 0x16/0x46 vcc_soc */\n\t\t\t/* u179 ir38164 0x19/0x49 vcco_500 */\n\t\t\t/* u181 ir38164 0x1a/0x4a vcco_501 */\n\t\t\t/* u183 ir38164 0x1b/0x4b vcco_502 */\n\t\t\t/* u185 ir38164 0x1e/0x4e vadj_fmc */\n\t\t\t/* u187 ir38164 0x1F/0x4f mgtyavcc */\n\t\t\t/* u189 ir38164 0x20/0x50 mgtyavtt */\n\t\t\t/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */\n\t\t\t/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */\n\n\t\t\tirps5401_47: irps5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* pmbus / i2c 0x17 */\n\t\t\t};\n\t\t\tirps5401_4c: irps5401@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* pmbus / i2c 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: irps5401@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* pmbus / i2c 0x1d */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <500>; /* R440 */\n\t\t\t\t/* 0.80V @ 32A 1 of 6 Phases*/\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-soc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <500>; /* R1702 */\n\t\t\t\t/* 0.80V @ 18A */\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pmc\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* R1214 */\n\t\t\t\t/* 0.78V @ 500mA */\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u162 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r1221 */\n\t\t\t\t/* 0.78V @ 4A */\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pslp\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>; /* R1216 */\n\t\t\t\t/* 0.78V @ 1A */\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-psfp\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1219 */\n\t\t\t\t/* 0.78V @ 2A */\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* u39 8T49N240 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0x6c>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* R382 */\n\t\t\t\t/* 1.5V @ 3A */\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux-pmc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>; /* R1246 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u178 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-500\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>; /* R1300 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u180 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-501\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <2000>; /* R1313 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u182 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-502\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <2000>; /* R1330 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-503\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1229 */\n\t\t\t\t/* 1.8V @ 2A */\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u173 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v8\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>; /* R400 */\n\t\t\t\t/* 1.8V @ 6A */\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-3v3\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* R1232 */\n\t\t\t\t/* 3.3V @ 500mA */\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v2-ddr4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>; /* R1275 */\n\t\t\t\t/* 1.2V @ 4A */\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>; /* R1286 */\n\t\t\t\t/* 1.1V @ 4A */\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>; /* R1350 */\n\t\t\t\t/* 1.5V @ 10A */\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavcc\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <2000>; /* R1367 */\n\t\t\t\t/* 0.88V @ 6A */\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavtt\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>; /* R1384 */\n\t\t\t\t/* 1.2V @ 10A */\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyvccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>; /* r1679 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t\ti2c@5 { /* zSFP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_zsfp: clock-generator@5d { /* u192 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_zsfp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* USER_SI570_1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_user1: clock-generator@5d { /* u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME check address */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"si570_user1\";\n\t\t\t};\n\n\t\t};\n\t\ti2c@7 { /* USER_SI570_2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* 0x5c too */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* and connector J212D */\n\t\t\teeprom_ebm: eeprom@52 { /* x-ebm module */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\t\t};\n\t\tfmc1: i2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t\teeprom_fmc1: eeprom@50 {\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\tfmc2: i2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t\teeprom_fmc2: eeprom@50 {\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LPDDR4_SI570_CLK2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_lpddr4clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4clk1: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* 8A34001 - U219B and J310 connector */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n\ti2c-mux@75 { /* u214 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\ti2c@0 { /* SFP0_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* SFP0 */\n\t\t};\n\t\ti2c@1 { /* SFP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@2 { /* QSFP1_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* QSFP1 */\n\t\t};\n\t\t/* 3 - 7 unused */\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-e-a2197-00-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevB System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-e-a2197-00-reva.dtsi\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevB\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revB\", \"xlnx,zynqmp-a2197-revB\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\t/delete-node/ ina226-vcco-500;\n\t/delete-node/ ina226-vcco-501;\n\t/delete-node/ ina226-vcco-502;\n};\n\n&i2c0 {\n\ti2c-mux@74 { /* u33 */\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t/delete-node/ clock-generator@6c;\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t/delete-node/ ina226@42;\n\t\t\t/delete-node/ ina226@43;\n\t\t\t/delete-node/ ina226@44;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-g-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 MGT Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-g-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\t aliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n mmc0 = &sdhci0;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n usb0 = &usb0;\n };\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u82 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&gem0 { /* eth MDIO 76/77 */\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 */\n\t\treg = <0>;\n\t\treset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 5 - 9 */\n\t\t \"\", \"\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"\", \"\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\ti2c-mux@74 { /* u94 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* CM_I2C_SCL - Samtec */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* PMBUS - AFX_PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\ttps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\ttps544@10 { /* u73 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\ttps544@11 { /* u76 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\ttps544@12 { /* u77 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\ttps544@13 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\ttps544@14 { /* u81 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\ttps544@15 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\ttps544@16 { /* u63 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\ttps544@17 { /* u66 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\ttps544@18 { /* u67 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\ttps544@19 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\ttps544@1d { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\ttps544@1e { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\ttps544@1f { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t\ttps544@20 { /* u71 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\t\t\tu74: ina226@40 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu75: ina226@41 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\"\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@43 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu82: ina226@44 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u82\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu84: ina226@45 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\ttps53681@60 { /* u53- 0xc0 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* fmc1 via JA2G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom_fmc1: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* fmc2 via JA3G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\teeprom_fmc2: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* fmc3 via JA4G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\teeprom_fmc3: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* ddr dimm */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&usb0 { /* USB0 MIO52-63 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"high-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-01-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n spi0 = &qspi;\n };\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\tina226-vcc0v6-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc0v6_lp4: ina226@49 { /* u101 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc0v6-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@60 { /* u69 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@5d { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n status = \"disabled\"; /* not at mem board */\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n /delete-property/ phy-names ;\n /delete-property/ phys ;\n maximum-speed = \"high-speed\";\n snps,dis_u2_susphy_quirk ;\n snps,dis_u3_susphy_quirk ;\n status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-02-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n spi0 = &qspi;\n };\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@60 { /* u69 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* C0_DDR4_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\ti2c@6 { /* C2_DDR5_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\ti2c@7 { /* C3_DDR4_UDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_RLD3 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_RLD3_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_DDR5 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_DDR5_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-03-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n spi0 = &qspi;\n };\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@18 { /* u3022 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@60 { /* u69 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* DDR4_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_SODIMM_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_QDRIV */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_QDRIV_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-01-revA\", \"xlnx,zynqmp-x-prc-01\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\",\"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-02-revA\", \"xlnx,zynqmp-x-prc-02\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-03-revA\", \"xlnx,zynqmp-x-prc-03\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tx_prc_si5338: clock-generator@70 { /* U9 */\n\t\t\t\tcompatible = \"silabs,si5338\";\n\t\t\t\treg = <0x70>; /* FIXME */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-04-revA\", \"xlnx,zynqmp-x-prc-04\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-05-revA\", \"xlnx,zynqmp-x-prc-05\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n };\n\n\tchosen {\n\t\tnvmem0 = <&eeprom>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@60 { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* 570JAC000900DG */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@60 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&usb1 {\n xlnx,usb-polarity = <0x0>;\n xlnx,usb-reset-mode = <0x0>;\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-sc-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP Generic System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP Generic System Controller\";\n\tcompatible = \"xlnx,zynqmp-sc-revB\", \"xlnx,zynqmp-sc\", \"xlnx,zynqmp\";\n\n\taliases {\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n spi1 = &spi0;\n spi2 = &spi1;\n usb0 = &usb0;\n usb1 = &usb1;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"sw16\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds40-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t\tds44-led {\n\t\t\tlabel = \"status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tsi5332_2: si5332_2 { /* u42 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\tpwm-fan {\n\t\tcompatible = \"pwm-fan\";\n\t\tpwms = <&ttc0 2 40000 1>;\n\t};\n\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\"QSPI_CS_B\", \"\", \"LED1\", \"LED2\", \"\", /* 5 - 9 */\n\t\t\"\", \"ZU4_TRIGGER\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\"I2C1_SDA\", \"UART0_RXD\", \"UART0_TXD\", \"\", \"\", /* 25 - 29 */\n\t\t\"\", \"\", \"\", \"\", \"I2C0_SCL\", /* 30 - 34 */\n\t\t\"I2C0_SDA\", \"UART1_TXD\", \"UART1_RXD\", \"GEM_TX_CLK\", \"GEM_TX_D0\", /* 35 - 39 */\n\t\t\"GEM_TX_D1\", \"GEM_TX_D2\", \"GEM_TX_D3\", \"GEM_TX_CTL\", \"GEM_RX_CLK\", /* 40 - 44 */\n\t\t\"GEM_RX_D0\", \"GEM_RX_D1\", \"GEM_RX_D2\", \"GEM_RX_D3\", \"GEM_RX_CTL\", /* 45 - 49 */\n\t\t\"GEM_MDC\", \"GEM_MDIO\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t\"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t\"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\"\", \"\", \"ETH_RESET_B\", /* 75 - 77, MIO end and EMIO start */\n\t\t\"\", \"\", /* 78 - 79 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem1_default>;\n\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy0: ethernet-phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t};\n\t};\n};\n\n&i2c0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n};\n\n&i2c1 { /* i2c1 MIO 24-25 */\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t/* No reason to do pinctrl setup at u-boot stage */\n\t/* Use for storing information about SC board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tu-boot,dm-pre-reloc;\n\t};\n};\n\n/* USB 3.0 only */\n&psgtr {\n\t/* nc, nc, usb3 */\n\tclocks = <&si5332_2>;\n\tclock-names = \"ref2\";\n};\n\n&qspi { /* MIO 0-5 */\n\t/* QSPI should also have PINCTRL setup */\n\tflash@0 {\n\t\tcompatible = \"mt25qu512a\", \"m25p80\", \"jedec,spi-nor\"; /* mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&ttc0 {\n\t#pwm-cells = <3>;\n};\n\n&uart1 { /* uart0 MIO36-37 */\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 { /* required by spec */\n\tstatus = \"okay\";\n\tpinctrl_uart1_default: uart1-default {\n\t\tconf {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO37\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO36\";\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tconf {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tconf {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\t};\n\n\tpinctrl_gem1_default: gem1-default {\n\t\tconf {\n\t\t\tgroups = \"ethernet1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO44\", \"MIO46\", \"MIO48\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-bootstrap {\n\t\t\tpins = \"MIO45\", \"MIO47\", \"MIO49\";\n\t\t\tbias-disable;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO38\", \"MIO39\", \"MIO40\",\n\t\t\t\t\"MIO41\", \"MIO42\", \"MIO43\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio1\";\n\t\t\tgroups = \"mdio1_0_grp\";\n\t\t};\n\n\t\tmux {\n\t\t\tfunction = \"ethernet1\";\n\t\t\tgroups = \"ethernet1_0_grp\";\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t\"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-sm-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SM-K26 rev1/B/A\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP SM-K26 Rev1/B/A\";\n\tcompatible = \"xlnx,zynqmp-sm-k26-rev1\", \"xlnx,zynqmp-sm-k26-revB\",\n\t\t \"xlnx,zynqmp-sm-k26-revA\", \"xlnx,zynqmp-sm-k26\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36-led {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n\tpwm-fan {\n\t\tcompatible = \"pwm-fan\";\n\t\tpwms = <&ttc0 2 40000 0>;\n\t};\n};\n\n&modepin_gpio {\n\tlabel = \"modepin\";\n};\n\n&ttc0 {\n\t#pwm-cells = <3>;\n};\n\n&pinctrl0 {\n status = \"okay\";\n pinctrl_sdhci0_default: sdhci0-default {\n conf {\n groups = \"sdio0_0_grp\";\n slew-rate = ;\n power-source = ;\n bias-disable;\n };\n\n mux {\n groups = \"sdio0_0_grp\";\n function = \"sdio0\";\n };\n };\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tflash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x40000>; /* 256B but 256KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2280000 {\n\t\t\tlabel = \"Secure OS Storage\";\n\t\t\treg = <0x2280000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@22A0000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x22A0000 0x1db0000>; /* 29.5 MB */\n\n\t\t};\n\t};\n};\n\n&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tassigned-clock-rates = <187498123>;\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues to be fixed in next board revision.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-smk-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sm-k26-reva.dtsi\"\n\n/ {\n model = \"ZynqMP SMK-K26 Rev1/B/A\";\n compatible = \"xlnx,zynqmp-smk-k26-rev1\", \"xlnx,zynqmp-smk-k26-revB\",\n \"xlnx,zynqmp-smk-k26-revA\", \"xlnx,zynqmp-smk-k26\",\n \"xlnx,zynqmp\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on vp-x-a2785-00 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vp-x-a2785-00-revA\",\n\t\t \"xlnx,zynqmp-vp-x-a2785-00\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n usb1 = &usb1;\n nvmem0 = &eeprom;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tj383 {\n\t\t\tlabel = \"j383\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds52 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* u285 - mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>; /* maybe 4 here */\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* sd MIO 45-51 */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 { /* u131 - M88e1512 */\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"\", \"\", \"\", \"VCCINT_FAULT_B\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\treg_vccint: tps53681@60 { /* u266 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@10 { /* u274 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@11 { /* u275 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@12 { /* u276 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc_cpm: tps544@14 { /* u272 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_util_3v3: tps544@1d { /* u278 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvcc_cpm: ina226@44 { /* u273 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpcie_smbus: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tpcie2_smbus: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tlpddr4_si570_clk3_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\t/* 6-7 unused */\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VPK120 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on VPK120 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vpk120-revA\",\n\t\t \"xlnx,zynqmp-vpk120\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n usb1 = &usb1;\n nvmem0 = &eeprom;\n };\n\n\tsi570_user1_fmc_clk: si570_user1_fmc_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&user_si570_1>;\n\t};\n\n\tsi570_ref_clk: si570_ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&ref_clk>;\n\t};\n\n\tsi570_lpddr4_clk3: si570_lpddr4_clk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk3>;\n\t};\n\n\tsi570_lpddr4_clk2: si570_lpddr4_clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570_lpddr4_clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk1>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw16 {\n\t\t\tlabel = \"sw16\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds40 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"\", \"\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"\", /* 85 - 89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"QSFPDD1_MODSELL\", \"QSFPDD1_MODSELL\", /* 0 - 3 */\n\t\t\t\t \"PMBUS2_INA226_ALERT\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP1_FMC_PRSNT_M2C_B\", \"\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\tir38060_41: regulator@41 { /* IR38060 - u259 */\n\t\t\t\tcompatible = \"infineon,ir38060\", \"infineon,ir38064\";\n\t\t\t\treg = <0x41>; /* i2c addr 0x11 */\n\t\t\t};\n\t\t\tir38164_43: regulator@43 { /* IR38164 - u13 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x43>; /* i2c addr 0x13 */\n\t\t\t};\n\t\t\tir35221_45: pmic@46 { /* IR35221 - u152 */\n\t\t\t\tcompatible = \"infineon,ir35221\";\n\t\t\t\treg = <0x46>; /* PMBUS - 0x16 */\n\t\t\t};\n\t\t\tirps5401_47: pmic5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* i2c addr 0x17 */\n\t\t\t};\n\t\t\tir38164_49: regulator@49 { /* IR38164 - u189 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x49>; /* i2c addr 0x19 */\n\t\t\t};\n\t\t\tirps5401_4c: pmic@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: pmic@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tir38164_4e: regulator@4e { /* IR38164 - u184 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4e>; /* i2c addr 0x1e */\n\t\t\t};\n\t\t\tir38164_4f: regulator@4f { /* IR38164 - u187 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4f>; /* i2c addr 0x1f */\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u5 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpmbus2_ina226_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@42 { /* u265 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v5: ina226@43 { /* u264 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_mio: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavtt: ina226@46 { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtvccaux: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyavcc: ina226@4b { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tlpdmgtyavtt: ina226@4c { /* u260 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tuser_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"fmc_si570\";\n\t\t\t};\n\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tref_clk_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\tfmcp1_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tlpddr4_si570_clk3_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlpddr4_clk3: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk3\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\tqsfpdd_i2c: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* J1/J2 connectors */\n\t\t};\n\t\tidt8a34001_i2c: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* Via J310 connector */\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u219B */\n\t\t\t\treg = <0x5b>; /* FIXME not in schematics */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\txlnx,usb-polarity = <0>;\n\txlnx,usb-reset-mode = <0>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/clock/xlnx-versal-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_VERSAL_H\n#define _DT_BINDINGS_CLK_VERSAL_H\n\n#define PMC_PLL\t\t\t\t\t1\n#define APU_PLL\t\t\t\t\t2\n#define RPU_PLL\t\t\t\t\t3\n#define CPM_PLL\t\t\t\t\t4\n#define NOC_PLL\t\t\t\t\t5\n#define PLL_MAX\t\t\t\t\t6\n#define PMC_PRESRC\t\t\t\t7\n#define PMC_POSTCLK\t\t\t\t8\n#define PMC_PLL_OUT\t\t\t\t9\n#define PPLL\t\t\t\t\t10\n#define NOC_PRESRC\t\t\t\t11\n#define NOC_POSTCLK\t\t\t\t12\n#define NOC_PLL_OUT\t\t\t\t13\n#define NPLL\t\t\t\t\t14\n#define APU_PRESRC\t\t\t\t15\n#define APU_POSTCLK\t\t\t\t16\n#define APU_PLL_OUT\t\t\t\t17\n#define APLL\t\t\t\t\t18\n#define RPU_PRESRC\t\t\t\t19\n#define RPU_POSTCLK\t\t\t\t20\n#define RPU_PLL_OUT\t\t\t\t21\n#define RPLL\t\t\t\t\t22\n#define CPM_PRESRC\t\t\t\t23\n#define CPM_POSTCLK\t\t\t\t24\n#define CPM_PLL_OUT\t\t\t\t25\n#define CPLL\t\t\t\t\t26\n#define PPLL_TO_XPD\t\t\t\t27\n#define NPLL_TO_XPD\t\t\t\t28\n#define APLL_TO_XPD\t\t\t\t29\n#define RPLL_TO_XPD\t\t\t\t30\n#define EFUSE_REF\t\t\t\t31\n#define SYSMON_REF\t\t\t\t32\n#define IRO_SUSPEND_REF\t\t\t\t33\n#define USB_SUSPEND\t\t\t\t34\n#define SWITCH_TIMEOUT\t\t\t\t35\n#define RCLK_PMC\t\t\t\t36\n#define RCLK_LPD\t\t\t\t37\n#define WDT\t\t\t\t\t38\n#define TTC0\t\t\t\t\t39\n#define TTC1\t\t\t\t\t40\n#define TTC2\t\t\t\t\t41\n#define TTC3\t\t\t\t\t42\n#define GEM_TSU\t\t\t\t\t43\n#define GEM_TSU_LB\t\t\t\t44\n#define MUXED_IRO_DIV2\t\t\t\t45\n#define MUXED_IRO_DIV4\t\t\t\t46\n#define PSM_REF\t\t\t\t\t47\n#define GEM0_RX\t\t\t\t\t48\n#define GEM0_TX\t\t\t\t\t49\n#define GEM1_RX\t\t\t\t\t50\n#define GEM1_TX\t\t\t\t\t51\n#define CPM_CORE_REF\t\t\t\t52\n#define CPM_LSBUS_REF\t\t\t\t53\n#define CPM_DBG_REF\t\t\t\t54\n#define CPM_AUX0_REF\t\t\t\t55\n#define CPM_AUX1_REF\t\t\t\t56\n#define QSPI_REF\t\t\t\t57\n#define OSPI_REF\t\t\t\t58\n#define SDIO0_REF\t\t\t\t59\n#define SDIO1_REF\t\t\t\t60\n#define PMC_LSBUS_REF\t\t\t\t61\n#define I2C_REF\t\t\t\t\t62\n#define TEST_PATTERN_REF\t\t\t63\n#define DFT_OSC_REF\t\t\t\t64\n#define PMC_PL0_REF\t\t\t\t65\n#define PMC_PL1_REF\t\t\t\t66\n#define PMC_PL2_REF\t\t\t\t67\n#define PMC_PL3_REF\t\t\t\t68\n#define CFU_REF\t\t\t\t\t69\n#define SPARE_REF\t\t\t\t70\n#define NPI_REF\t\t\t\t\t71\n#define HSM0_REF\t\t\t\t72\n#define HSM1_REF\t\t\t\t73\n#define SD_DLL_REF\t\t\t\t74\n#define FPD_TOP_SWITCH\t\t\t\t75\n#define FPD_LSBUS\t\t\t\t76\n#define ACPU\t\t\t\t\t77\n#define DBG_TRACE\t\t\t\t78\n#define DBG_FPD\t\t\t\t\t79\n#define LPD_TOP_SWITCH\t\t\t\t80\n#define ADMA\t\t\t\t\t81\n#define LPD_LSBUS\t\t\t\t82\n#define CPU_R5\t\t\t\t\t83\n#define CPU_R5_CORE\t\t\t\t84\n#define CPU_R5_OCM\t\t\t\t85\n#define CPU_R5_OCM2\t\t\t\t86\n#define IOU_SWITCH\t\t\t\t87\n#define GEM0_REF\t\t\t\t88\n#define GEM1_REF\t\t\t\t89\n#define GEM_TSU_REF\t\t\t\t90\n#define USB0_BUS_REF\t\t\t\t91\n#define UART0_REF\t\t\t\t92\n#define UART1_REF\t\t\t\t93\n#define SPI0_REF\t\t\t\t94\n#define SPI1_REF\t\t\t\t95\n#define CAN0_REF\t\t\t\t96\n#define CAN1_REF\t\t\t\t97\n#define I2C0_REF\t\t\t\t98\n#define I2C1_REF\t\t\t\t99\n#define DBG_LPD\t\t\t\t\t100\n#define TIMESTAMP_REF\t\t\t\t101\n#define DBG_TSTMP\t\t\t\t102\n#define CPM_TOPSW_REF\t\t\t\t103\n#define USB3_DUAL_REF\t\t\t\t104\n#define OUTCLK_MAX\t\t\t\t105\n#define REF_CLK\t\t\t\t\t106\n#define PL_ALT_REF_CLK\t\t\t\t107\n#define MUXED_IRO\t\t\t\t108\n#define PL_EXT\t\t\t\t\t109\n#define PL_LB\t\t\t\t\t110\n#define MIO_50_OR_51\t\t\t\t111\n#define MIO_24_OR_25\t\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Xilinx Zynq MPSoC Firmware layer\n *\n * Copyright (C) 2014-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_ZYNQMP_H\n#define _DT_BINDINGS_CLK_ZYNQMP_H\n\n#define IOPLL\t\t\t0\n#define RPLL\t\t\t1\n#define APLL\t\t\t2\n#define DPLL\t\t\t3\n#define VPLL\t\t\t4\n#define IOPLL_TO_FPD\t\t5\n#define RPLL_TO_FPD\t\t6\n#define APLL_TO_LPD\t\t7\n#define DPLL_TO_LPD\t\t8\n#define VPLL_TO_LPD\t\t9\n#define ACPU\t\t\t10\n#define ACPU_HALF\t\t11\n#define DBF_FPD\t\t\t12\n#define DBF_LPD\t\t\t13\n#define DBG_TRACE\t\t14\n#define DBG_TSTMP\t\t15\n#define DP_VIDEO_REF\t\t16\n#define DP_AUDIO_REF\t\t17\n#define DP_STC_REF\t\t18\n#define GDMA_REF\t\t19\n#define DPDMA_REF\t\t20\n#define DDR_REF\t\t\t21\n#define SATA_REF\t\t22\n#define PCIE_REF\t\t23\n#define GPU_REF\t\t\t24\n#define GPU_PP0_REF\t\t25\n#define GPU_PP1_REF\t\t26\n#define TOPSW_MAIN\t\t27\n#define TOPSW_LSBUS\t\t28\n#define GTGREF0_REF\t\t29\n#define LPD_SWITCH\t\t30\n#define LPD_LSBUS\t\t31\n#define USB0_BUS_REF\t\t32\n#define USB1_BUS_REF\t\t33\n#define USB3_DUAL_REF\t\t34\n#define USB0\t\t\t35\n#define USB1\t\t\t36\n#define CPU_R5\t\t\t37\n#define CPU_R5_CORE\t\t38\n#define CSU_SPB\t\t\t39\n#define CSU_PLL\t\t\t40\n#define PCAP\t\t\t41\n#define IOU_SWITCH\t\t42\n#define GEM_TSU_REF\t\t43\n#define GEM_TSU\t\t\t44\n#define GEM0_TX\t\t\t45\n#define GEM1_TX\t\t\t46\n#define GEM2_TX\t\t\t47\n#define GEM3_TX\t\t\t48\n#define GEM0_RX\t\t\t49\n#define GEM1_RX\t\t\t50\n#define GEM2_RX\t\t\t51\n#define GEM3_RX\t\t\t52\n#define QSPI_REF\t\t53\n#define SDIO0_REF\t\t54\n#define SDIO1_REF\t\t55\n#define UART0_REF\t\t56\n#define UART1_REF\t\t57\n#define SPI0_REF\t\t58\n#define SPI1_REF\t\t59\n#define NAND_REF\t\t60\n#define I2C0_REF\t\t61\n#define I2C1_REF\t\t62\n#define CAN0_REF\t\t63\n#define CAN1_REF\t\t64\n#define CAN0\t\t\t65\n#define CAN1\t\t\t66\n#define DLL_REF\t\t\t67\n#define ADMA_REF\t\t68\n#define TIMESTAMP_REF\t\t69\n#define AMS_REF\t\t\t70\n#define PL0_REF\t\t\t71\n#define PL1_REF\t\t\t72\n#define PL2_REF\t\t\t73\n#define PL3_REF\t\t\t74\n#define WDT\t\t\t75\n#define IOPLL_INT\t\t76\n#define IOPLL_PRE_SRC\t\t77\n#define IOPLL_HALF\t\t78\n#define IOPLL_INT_MUX\t\t79\n#define IOPLL_POST_SRC\t\t80\n#define RPLL_INT\t\t81\n#define RPLL_PRE_SRC\t\t82\n#define RPLL_HALF\t\t83\n#define RPLL_INT_MUX\t\t84\n#define RPLL_POST_SRC\t\t85\n#define APLL_INT\t\t86\n#define APLL_PRE_SRC\t\t87\n#define APLL_HALF\t\t88\n#define APLL_INT_MUX\t\t89\n#define APLL_POST_SRC\t\t90\n#define DPLL_INT\t\t91\n#define DPLL_PRE_SRC\t\t92\n#define DPLL_HALF\t\t93\n#define DPLL_INT_MUX\t\t94\n#define DPLL_POST_SRC\t\t95\n#define VPLL_INT\t\t96\n#define VPLL_PRE_SRC\t\t97\n#define VPLL_HALF\t\t98\n#define VPLL_INT_MUX\t\t99\n#define VPLL_POST_SRC\t\t100\n#define CAN0_MIO\t\t101\n#define CAN1_MIO\t\t102\n#define ACPU_FULL\t\t103\n#define GEM0_REF\t\t104\n#define GEM1_REF\t\t105\n#define GEM2_REF\t\t106\n#define GEM3_REF\t\t107\n#define GEM0_REF_UNG\t\t108\n#define GEM1_REF_UNG\t\t109\n#define GEM2_REF_UNG\t\t110\n#define GEM3_REF_UNG\t\t111\n#define LPD_WDT\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h", "content": "/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */\n/*\n * Copyright 2019 Laurent Pinchart \n */\n\n#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n\n#define ZYNQMP_DPDMA_VIDEO0\t\t0\n#define ZYNQMP_DPDMA_VIDEO1\t\t1\n#define ZYNQMP_DPDMA_VIDEO2\t\t2\n#define ZYNQMP_DPDMA_GRAPHICS\t\t3\n#define ZYNQMP_DPDMA_AUDIO0\t\t4\n#define ZYNQMP_DPDMA_AUDIO1\t\t5\n\n#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/gpio/gpio.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most GPIO bindings.\n *\n * Most GPIO bindings include a flags cell as part of the GPIO specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_GPIO_GPIO_H\n#define _DT_BINDINGS_GPIO_GPIO_H\n\n/* Bit 0 express polarity */\n#define GPIO_ACTIVE_HIGH 0\n#define GPIO_ACTIVE_LOW 1\n\n/* Bit 1 express single-endedness */\n#define GPIO_PUSH_PULL 0\n#define GPIO_SINGLE_ENDED 2\n\n/* Bit 2 express Open drain or open source */\n#define GPIO_LINE_OPEN_SOURCE 0\n#define GPIO_LINE_OPEN_DRAIN 4\n\n/*\n * Open Drain/Collector is the combination of single-ended open drain interface.\n * Open Source/Emitter is the combination of single-ended open source interface.\n */\n#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)\n#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)\n\n/* Bit 3 express GPIO suspend/resume and reset persistence */\n#define GPIO_PERSISTENT 0\n#define GPIO_TRANSITORY 8\n\n/* Bit 4 express pull up */\n#define GPIO_PULL_UP 16\n\n/* Bit 5 express pull down */\n#define GPIO_PULL_DOWN 32\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/input/input.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most input bindings.\n *\n * Most input bindings include key code, matrix key code format.\n * In most cases, key code and matrix key code format uses\n * the standard values/macro defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INPUT_INPUT_H\n#define _DT_BINDINGS_INPUT_INPUT_H\n\n/*\n * Device properties and quirks\n */\n\n#define INPUT_PROP_POINTER\t\t0x00\t/* needs a pointer */\n#define INPUT_PROP_DIRECT\t\t0x01\t/* direct input devices */\n#define INPUT_PROP_BUTTONPAD\t\t0x02\t/* has button(s) under pad */\n#define INPUT_PROP_SEMI_MT\t\t0x03\t/* touch rectangle only */\n#define INPUT_PROP_TOPBUTTONPAD\t\t0x04\t/* softbuttons at top of pad */\n#define INPUT_PROP_POINTING_STICK\t0x05\t/* is a pointing stick */\n#define INPUT_PROP_ACCELEROMETER\t0x06\t/* has accelerometer */\n\n#define INPUT_PROP_MAX\t\t\t0x1f\n#define INPUT_PROP_CNT\t\t\t(INPUT_PROP_MAX + 1)\n\n\n/*\n * Event types\n */\n\n#define EV_SYN\t\t\t0x00\n#define EV_KEY\t\t\t0x01\n#define EV_REL\t\t\t0x02\n#define EV_ABS\t\t\t0x03\n#define EV_MSC\t\t\t0x04\n#define EV_SW\t\t\t0x05\n#define EV_LED\t\t\t0x11\n#define EV_SND\t\t\t0x12\n#define EV_REP\t\t\t0x14\n#define EV_FF\t\t\t0x15\n#define EV_PWR\t\t\t0x16\n#define EV_FF_STATUS\t\t0x17\n#define EV_MAX\t\t\t0x1f\n#define EV_CNT\t\t\t(EV_MAX+1)\n\n/*\n * Synchronization events.\n */\n\n#define SYN_REPORT\t\t0\n#define SYN_CONFIG\t\t1\n#define SYN_MT_REPORT\t\t2\n#define SYN_DROPPED\t\t3\n#define SYN_MAX\t\t\t0xf\n#define SYN_CNT\t\t\t(SYN_MAX+1)\n\n/*\n * Keys and buttons\n *\n * Most of the keys/buttons are modeled after USB HUT 1.12\n * (see http://www.usb.org/developers/hidpage).\n * Abbreviations in the comments:\n * AC - Application Control\n * AL - Application Launch Button\n * SC - System Control\n */\n\n#define KEY_RESERVED\t\t0\n#define KEY_ESC\t\t\t1\n#define KEY_1\t\t\t2\n#define KEY_2\t\t\t3\n#define KEY_3\t\t\t4\n#define KEY_4\t\t\t5\n#define KEY_5\t\t\t6\n#define KEY_6\t\t\t7\n#define KEY_7\t\t\t8\n#define KEY_8\t\t\t9\n#define KEY_9\t\t\t10\n#define KEY_0\t\t\t11\n#define KEY_MINUS\t\t12\n#define KEY_EQUAL\t\t13\n#define KEY_BACKSPACE\t\t14\n#define KEY_TAB\t\t\t15\n#define KEY_Q\t\t\t16\n#define KEY_W\t\t\t17\n#define KEY_E\t\t\t18\n#define KEY_R\t\t\t19\n#define KEY_T\t\t\t20\n#define KEY_Y\t\t\t21\n#define KEY_U\t\t\t22\n#define KEY_I\t\t\t23\n#define KEY_O\t\t\t24\n#define KEY_P\t\t\t25\n#define KEY_LEFTBRACE\t\t26\n#define KEY_RIGHTBRACE\t\t27\n#define KEY_ENTER\t\t28\n#define KEY_LEFTCTRL\t\t29\n#define KEY_A\t\t\t30\n#define KEY_S\t\t\t31\n#define KEY_D\t\t\t32\n#define KEY_F\t\t\t33\n#define KEY_G\t\t\t34\n#define KEY_H\t\t\t35\n#define KEY_J\t\t\t36\n#define KEY_K\t\t\t37\n#define KEY_L\t\t\t38\n#define KEY_SEMICOLON\t\t39\n#define KEY_APOSTROPHE\t\t40\n#define KEY_GRAVE\t\t41\n#define KEY_LEFTSHIFT\t\t42\n#define KEY_BACKSLASH\t\t43\n#define KEY_Z\t\t\t44\n#define KEY_X\t\t\t45\n#define KEY_C\t\t\t46\n#define KEY_V\t\t\t47\n#define KEY_B\t\t\t48\n#define KEY_N\t\t\t49\n#define KEY_M\t\t\t50\n#define KEY_COMMA\t\t51\n#define KEY_DOT\t\t\t52\n#define KEY_SLASH\t\t53\n#define KEY_RIGHTSHIFT\t\t54\n#define KEY_KPASTERISK\t\t55\n#define KEY_LEFTALT\t\t56\n#define KEY_SPACE\t\t57\n#define KEY_CAPSLOCK\t\t58\n#define KEY_F1\t\t\t59\n#define KEY_F2\t\t\t60\n#define KEY_F3\t\t\t61\n#define KEY_F4\t\t\t62\n#define KEY_F5\t\t\t63\n#define KEY_F6\t\t\t64\n#define KEY_F7\t\t\t65\n#define KEY_F8\t\t\t66\n#define KEY_F9\t\t\t67\n#define KEY_F10\t\t\t68\n#define KEY_NUMLOCK\t\t69\n#define KEY_SCROLLLOCK\t\t70\n#define KEY_KP7\t\t\t71\n#define KEY_KP8\t\t\t72\n#define KEY_KP9\t\t\t73\n#define KEY_KPMINUS\t\t74\n#define KEY_KP4\t\t\t75\n#define KEY_KP5\t\t\t76\n#define KEY_KP6\t\t\t77\n#define KEY_KPPLUS\t\t78\n#define KEY_KP1\t\t\t79\n#define KEY_KP2\t\t\t80\n#define KEY_KP3\t\t\t81\n#define KEY_KP0\t\t\t82\n#define KEY_KPDOT\t\t83\n\n#define KEY_ZENKAKUHANKAKU\t85\n#define KEY_102ND\t\t86\n#define KEY_F11\t\t\t87\n#define KEY_F12\t\t\t88\n#define KEY_RO\t\t\t89\n#define KEY_KATAKANA\t\t90\n#define KEY_HIRAGANA\t\t91\n#define KEY_HENKAN\t\t92\n#define KEY_KATAKANAHIRAGANA\t93\n#define KEY_MUHENKAN\t\t94\n#define KEY_KPJPCOMMA\t\t95\n#define KEY_KPENTER\t\t96\n#define KEY_RIGHTCTRL\t\t97\n#define KEY_KPSLASH\t\t98\n#define KEY_SYSRQ\t\t99\n#define KEY_RIGHTALT\t\t100\n#define KEY_LINEFEED\t\t101\n#define KEY_HOME\t\t102\n#define KEY_UP\t\t\t103\n#define KEY_PAGEUP\t\t104\n#define KEY_LEFT\t\t105\n#define KEY_RIGHT\t\t106\n#define KEY_END\t\t\t107\n#define KEY_DOWN\t\t108\n#define KEY_PAGEDOWN\t\t109\n#define KEY_INSERT\t\t110\n#define KEY_DELETE\t\t111\n#define KEY_MACRO\t\t112\n#define KEY_MUTE\t\t113\n#define KEY_VOLUMEDOWN\t\t114\n#define KEY_VOLUMEUP\t\t115\n#define KEY_POWER\t\t116\t/* SC System Power Down */\n#define KEY_KPEQUAL\t\t117\n#define KEY_KPPLUSMINUS\t\t118\n#define KEY_PAUSE\t\t119\n#define KEY_SCALE\t\t120\t/* AL Compiz Scale (Expose) */\n\n#define KEY_KPCOMMA\t\t121\n#define KEY_HANGEUL\t\t122\n#define KEY_HANGUEL\t\tKEY_HANGEUL\n#define KEY_HANJA\t\t123\n#define KEY_YEN\t\t\t124\n#define KEY_LEFTMETA\t\t125\n#define KEY_RIGHTMETA\t\t126\n#define KEY_COMPOSE\t\t127\n#define KEY_STOP\t\t128\t/* AC Stop */\n#define KEY_AGAIN\t\t129\n#define KEY_PROPS\t\t130\t/* AC Properties */\n#define KEY_UNDO\t\t131\t/* AC Undo */\n#define KEY_FRONT\t\t132\n#define KEY_COPY\t\t133\t/* AC Copy */\n#define KEY_OPEN\t\t134\t/* AC Open */\n#define KEY_PASTE\t\t135\t/* AC Paste */\n#define KEY_FIND\t\t136\t/* AC Search */\n#define KEY_CUT\t\t\t137\t/* AC Cut */\n#define KEY_HELP\t\t138\t/* AL Integrated Help Center */\n#define KEY_MENU\t\t139\t/* Menu (show menu) */\n#define KEY_CALC\t\t140\t/* AL Calculator */\n#define KEY_SETUP\t\t141\n#define KEY_SLEEP\t\t142\t/* SC System Sleep */\n#define KEY_WAKEUP\t\t143\t/* System Wake Up */\n#define KEY_FILE\t\t144\t/* AL Local Machine Browser */\n#define KEY_SENDFILE\t\t145\n#define KEY_DELETEFILE\t\t146\n#define KEY_XFER\t\t147\n#define KEY_PROG1\t\t148\n#define KEY_PROG2\t\t149\n#define KEY_WWW\t\t\t150\t/* AL Internet Browser */\n#define KEY_MSDOS\t\t151\n#define KEY_COFFEE\t\t152\t/* AL Terminal Lock/Screensaver */\n#define KEY_SCREENLOCK\t\tKEY_COFFEE\n#define KEY_ROTATE_DISPLAY\t153\t/* Display orientation for e.g. tablets */\n#define KEY_DIRECTION\t\tKEY_ROTATE_DISPLAY\n#define KEY_CYCLEWINDOWS\t154\n#define KEY_MAIL\t\t155\n#define KEY_BOOKMARKS\t\t156\t/* AC Bookmarks */\n#define KEY_COMPUTER\t\t157\n#define KEY_BACK\t\t158\t/* AC Back */\n#define KEY_FORWARD\t\t159\t/* AC Forward */\n#define KEY_CLOSECD\t\t160\n#define KEY_EJECTCD\t\t161\n#define KEY_EJECTCLOSECD\t162\n#define KEY_NEXTSONG\t\t163\n#define KEY_PLAYPAUSE\t\t164\n#define KEY_PREVIOUSSONG\t165\n#define KEY_STOPCD\t\t166\n#define KEY_RECORD\t\t167\n#define KEY_REWIND\t\t168\n#define KEY_PHONE\t\t169\t/* Media Select Telephone */\n#define KEY_ISO\t\t\t170\n#define KEY_CONFIG\t\t171\t/* AL Consumer Control Configuration */\n#define KEY_HOMEPAGE\t\t172\t/* AC Home */\n#define KEY_REFRESH\t\t173\t/* AC Refresh */\n#define KEY_EXIT\t\t174\t/* AC Exit */\n#define KEY_MOVE\t\t175\n#define KEY_EDIT\t\t176\n#define KEY_SCROLLUP\t\t177\n#define KEY_SCROLLDOWN\t\t178\n#define KEY_KPLEFTPAREN\t\t179\n#define KEY_KPRIGHTPAREN\t180\n#define KEY_NEW\t\t\t181\t/* AC New */\n#define KEY_REDO\t\t182\t/* AC Redo/Repeat */\n\n#define KEY_F13\t\t\t183\n#define KEY_F14\t\t\t184\n#define KEY_F15\t\t\t185\n#define KEY_F16\t\t\t186\n#define KEY_F17\t\t\t187\n#define KEY_F18\t\t\t188\n#define KEY_F19\t\t\t189\n#define KEY_F20\t\t\t190\n#define KEY_F21\t\t\t191\n#define KEY_F22\t\t\t192\n#define KEY_F23\t\t\t193\n#define KEY_F24\t\t\t194\n\n#define KEY_PLAYCD\t\t200\n#define KEY_PAUSECD\t\t201\n#define KEY_PROG3\t\t202\n#define KEY_PROG4\t\t203\n#define KEY_DASHBOARD\t\t204\t/* AL Dashboard */\n#define KEY_SUSPEND\t\t205\n#define KEY_CLOSE\t\t206\t/* AC Close */\n#define KEY_PLAY\t\t207\n#define KEY_FASTFORWARD\t\t208\n#define KEY_BASSBOOST\t\t209\n#define KEY_PRINT\t\t210\t/* AC Print */\n#define KEY_HP\t\t\t211\n#define KEY_CAMERA\t\t212\n#define KEY_SOUND\t\t213\n#define KEY_QUESTION\t\t214\n#define KEY_EMAIL\t\t215\n#define KEY_CHAT\t\t216\n#define KEY_SEARCH\t\t217\n#define KEY_CONNECT\t\t218\n#define KEY_FINANCE\t\t219\t/* AL Checkbook/Finance */\n#define KEY_SPORT\t\t220\n#define KEY_SHOP\t\t221\n#define KEY_ALTERASE\t\t222\n#define KEY_CANCEL\t\t223\t/* AC Cancel */\n#define KEY_BRIGHTNESSDOWN\t224\n#define KEY_BRIGHTNESSUP\t225\n#define KEY_MEDIA\t\t226\n\n#define KEY_SWITCHVIDEOMODE\t227\t/* Cycle between available video\n\t\t\t\t\t outputs (Monitor/LCD/TV-out/etc) */\n#define KEY_KBDILLUMTOGGLE\t228\n#define KEY_KBDILLUMDOWN\t229\n#define KEY_KBDILLUMUP\t\t230\n\n#define KEY_SEND\t\t231\t/* AC Send */\n#define KEY_REPLY\t\t232\t/* AC Reply */\n#define KEY_FORWARDMAIL\t\t233\t/* AC Forward Msg */\n#define KEY_SAVE\t\t234\t/* AC Save */\n#define KEY_DOCUMENTS\t\t235\n\n#define KEY_BATTERY\t\t236\n\n#define KEY_BLUETOOTH\t\t237\n#define KEY_WLAN\t\t238\n#define KEY_UWB\t\t\t239\n\n#define KEY_UNKNOWN\t\t240\n#define KEY_VIDEO_NEXT\t\t241\t/* drive next video source */\n#define KEY_VIDEO_PREV\t\t242\t/* drive previous video source */\n#define KEY_BRIGHTNESS_CYCLE\t243\t/* brightness up, after max is min */\n#define KEY_BRIGHTNESS_AUTO\t244\t/* Set Auto Brightness: manual\n\t\t\t\t\t brightness control is off,\n\t\t\t\t\t rely on ambient */\n#define KEY_BRIGHTNESS_ZERO\tKEY_BRIGHTNESS_AUTO\n#define KEY_DISPLAY_OFF\t\t245\t/* display device to off state */\n\n#define KEY_WWAN\t\t246\t/* Wireless WAN (LTE, UMTS, GSM, etc.) */\n#define KEY_WIMAX\t\tKEY_WWAN\n#define KEY_RFKILL\t\t247\t/* Key that controls all radios */\n\n#define KEY_MICMUTE\t\t248\t/* Mute / unmute the microphone */\n\n/* Code 255 is reserved for special needs of AT keyboard driver */\n\n#define BTN_MISC\t\t0x100\n#define BTN_0\t\t\t0x100\n#define BTN_1\t\t\t0x101\n#define BTN_2\t\t\t0x102\n#define BTN_3\t\t\t0x103\n#define BTN_4\t\t\t0x104\n#define BTN_5\t\t\t0x105\n#define BTN_6\t\t\t0x106\n#define BTN_7\t\t\t0x107\n#define BTN_8\t\t\t0x108\n#define BTN_9\t\t\t0x109\n\n#define BTN_MOUSE\t\t0x110\n#define BTN_LEFT\t\t0x110\n#define BTN_RIGHT\t\t0x111\n#define BTN_MIDDLE\t\t0x112\n#define BTN_SIDE\t\t0x113\n#define BTN_EXTRA\t\t0x114\n#define BTN_FORWARD\t\t0x115\n#define BTN_BACK\t\t0x116\n#define BTN_TASK\t\t0x117\n\n#define BTN_JOYSTICK\t\t0x120\n#define BTN_TRIGGER\t\t0x120\n#define BTN_THUMB\t\t0x121\n#define BTN_THUMB2\t\t0x122\n#define BTN_TOP\t\t\t0x123\n#define BTN_TOP2\t\t0x124\n#define BTN_PINKIE\t\t0x125\n#define BTN_BASE\t\t0x126\n#define BTN_BASE2\t\t0x127\n#define BTN_BASE3\t\t0x128\n#define BTN_BASE4\t\t0x129\n#define BTN_BASE5\t\t0x12a\n#define BTN_BASE6\t\t0x12b\n#define BTN_DEAD\t\t0x12f\n\n#define BTN_GAMEPAD\t\t0x130\n#define BTN_SOUTH\t\t0x130\n#define BTN_A\t\t\tBTN_SOUTH\n#define BTN_EAST\t\t0x131\n#define BTN_B\t\t\tBTN_EAST\n#define BTN_C\t\t\t0x132\n#define BTN_NORTH\t\t0x133\n#define BTN_X\t\t\tBTN_NORTH\n#define BTN_WEST\t\t0x134\n#define BTN_Y\t\t\tBTN_WEST\n#define BTN_Z\t\t\t0x135\n#define BTN_TL\t\t\t0x136\n#define BTN_TR\t\t\t0x137\n#define BTN_TL2\t\t\t0x138\n#define BTN_TR2\t\t\t0x139\n#define BTN_SELECT\t\t0x13a\n#define BTN_START\t\t0x13b\n#define BTN_MODE\t\t0x13c\n#define BTN_THUMBL\t\t0x13d\n#define BTN_THUMBR\t\t0x13e\n\n#define BTN_DIGI\t\t0x140\n#define BTN_TOOL_PEN\t\t0x140\n#define BTN_TOOL_RUBBER\t\t0x141\n#define BTN_TOOL_BRUSH\t\t0x142\n#define BTN_TOOL_PENCIL\t\t0x143\n#define BTN_TOOL_AIRBRUSH\t0x144\n#define BTN_TOOL_FINGER\t\t0x145\n#define BTN_TOOL_MOUSE\t\t0x146\n#define BTN_TOOL_LENS\t\t0x147\n#define BTN_TOOL_QUINTTAP\t0x148\t/* Five fingers on trackpad */\n#define BTN_TOUCH\t\t0x14a\n#define BTN_STYLUS\t\t0x14b\n#define BTN_STYLUS2\t\t0x14c\n#define BTN_TOOL_DOUBLETAP\t0x14d\n#define BTN_TOOL_TRIPLETAP\t0x14e\n#define BTN_TOOL_QUADTAP\t0x14f\t/* Four fingers on trackpad */\n\n#define BTN_WHEEL\t\t0x150\n#define BTN_GEAR_DOWN\t\t0x150\n#define BTN_GEAR_UP\t\t0x151\n\n#define KEY_OK\t\t\t0x160\n#define KEY_SELECT\t\t0x161\n#define KEY_GOTO\t\t0x162\n#define KEY_CLEAR\t\t0x163\n#define KEY_POWER2\t\t0x164\n#define KEY_OPTION\t\t0x165\n#define KEY_INFO\t\t0x166\t/* AL OEM Features/Tips/Tutorial */\n#define KEY_TIME\t\t0x167\n#define KEY_VENDOR\t\t0x168\n#define KEY_ARCHIVE\t\t0x169\n#define KEY_PROGRAM\t\t0x16a\t/* Media Select Program Guide */\n#define KEY_CHANNEL\t\t0x16b\n#define KEY_FAVORITES\t\t0x16c\n#define KEY_EPG\t\t\t0x16d\n#define KEY_PVR\t\t\t0x16e\t/* Media Select Home */\n#define KEY_MHP\t\t\t0x16f\n#define KEY_LANGUAGE\t\t0x170\n#define KEY_TITLE\t\t0x171\n#define KEY_SUBTITLE\t\t0x172\n#define KEY_ANGLE\t\t0x173\n#define KEY_ZOOM\t\t0x174\n#define KEY_MODE\t\t0x175\n#define KEY_KEYBOARD\t\t0x176\n#define KEY_SCREEN\t\t0x177\n#define KEY_PC\t\t\t0x178\t/* Media Select Computer */\n#define KEY_TV\t\t\t0x179\t/* Media Select TV */\n#define KEY_TV2\t\t\t0x17a\t/* Media Select Cable */\n#define KEY_VCR\t\t\t0x17b\t/* Media Select VCR */\n#define KEY_VCR2\t\t0x17c\t/* VCR Plus */\n#define KEY_SAT\t\t\t0x17d\t/* Media Select Satellite */\n#define KEY_SAT2\t\t0x17e\n#define KEY_CD\t\t\t0x17f\t/* Media Select CD */\n#define KEY_TAPE\t\t0x180\t/* Media Select Tape */\n#define KEY_RADIO\t\t0x181\n#define KEY_TUNER\t\t0x182\t/* Media Select Tuner */\n#define KEY_PLAYER\t\t0x183\n#define KEY_TEXT\t\t0x184\n#define KEY_DVD\t\t\t0x185\t/* Media Select DVD */\n#define KEY_AUX\t\t\t0x186\n#define KEY_MP3\t\t\t0x187\n#define KEY_AUDIO\t\t0x188\t/* AL Audio Browser */\n#define KEY_VIDEO\t\t0x189\t/* AL Movie Browser */\n#define KEY_DIRECTORY\t\t0x18a\n#define KEY_LIST\t\t0x18b\n#define KEY_MEMO\t\t0x18c\t/* Media Select Messages */\n#define KEY_CALENDAR\t\t0x18d\n#define KEY_RED\t\t\t0x18e\n#define KEY_GREEN\t\t0x18f\n#define KEY_YELLOW\t\t0x190\n#define KEY_BLUE\t\t0x191\n#define KEY_CHANNELUP\t\t0x192\t/* Channel Increment */\n#define KEY_CHANNELDOWN\t\t0x193\t/* Channel Decrement */\n#define KEY_FIRST\t\t0x194\n#define KEY_LAST\t\t0x195\t/* Recall Last */\n#define KEY_AB\t\t\t0x196\n#define KEY_NEXT\t\t0x197\n#define KEY_RESTART\t\t0x198\n#define KEY_SLOW\t\t0x199\n#define KEY_SHUFFLE\t\t0x19a\n#define KEY_BREAK\t\t0x19b\n#define KEY_PREVIOUS\t\t0x19c\n#define KEY_DIGITS\t\t0x19d\n#define KEY_TEEN\t\t0x19e\n#define KEY_TWEN\t\t0x19f\n#define KEY_VIDEOPHONE\t\t0x1a0\t/* Media Select Video Phone */\n#define KEY_GAMES\t\t0x1a1\t/* Media Select Games */\n#define KEY_ZOOMIN\t\t0x1a2\t/* AC Zoom In */\n#define KEY_ZOOMOUT\t\t0x1a3\t/* AC Zoom Out */\n#define KEY_ZOOMRESET\t\t0x1a4\t/* AC Zoom */\n#define KEY_WORDPROCESSOR\t0x1a5\t/* AL Word Processor */\n#define KEY_EDITOR\t\t0x1a6\t/* AL Text Editor */\n#define KEY_SPREADSHEET\t\t0x1a7\t/* AL Spreadsheet */\n#define KEY_GRAPHICSEDITOR\t0x1a8\t/* AL Graphics Editor */\n#define KEY_PRESENTATION\t0x1a9\t/* AL Presentation App */\n#define KEY_DATABASE\t\t0x1aa\t/* AL Database App */\n#define KEY_NEWS\t\t0x1ab\t/* AL Newsreader */\n#define KEY_VOICEMAIL\t\t0x1ac\t/* AL Voicemail */\n#define KEY_ADDRESSBOOK\t\t0x1ad\t/* AL Contacts/Address Book */\n#define KEY_MESSENGER\t\t0x1ae\t/* AL Instant Messaging */\n#define KEY_DISPLAYTOGGLE\t0x1af\t/* Turn display (LCD) on and off */\n#define KEY_BRIGHTNESS_TOGGLE\tKEY_DISPLAYTOGGLE\n#define KEY_SPELLCHECK\t\t0x1b0 /* AL Spell Check */\n#define KEY_LOGOFF\t\t0x1b1 /* AL Logoff */\n\n#define KEY_DOLLAR\t\t0x1b2\n#define KEY_EURO\t\t0x1b3\n\n#define KEY_FRAMEBACK\t\t0x1b4\t/* Consumer - transport controls */\n#define KEY_FRAMEFORWARD\t0x1b5\n#define KEY_CONTEXT_MENU\t0x1b6\t/* GenDesc - system context menu */\n#define KEY_MEDIA_REPEAT\t0x1b7\t/* Consumer - transport control */\n#define KEY_10CHANNELSUP\t0x1b8\t/* 10 channels up (10+) */\n#define KEY_10CHANNELSDOWN\t0x1b9\t/* 10 channels down (10-) */\n#define KEY_IMAGES\t\t0x1ba\t/* AL Image Browser */\n\n#define KEY_DEL_EOL\t\t0x1c0\n#define KEY_DEL_EOS\t\t0x1c1\n#define KEY_INS_LINE\t\t0x1c2\n#define KEY_DEL_LINE\t\t0x1c3\n\n#define KEY_FN\t\t\t0x1d0\n#define KEY_FN_ESC\t\t0x1d1\n#define KEY_FN_F1\t\t0x1d2\n#define KEY_FN_F2\t\t0x1d3\n#define KEY_FN_F3\t\t0x1d4\n#define KEY_FN_F4\t\t0x1d5\n#define KEY_FN_F5\t\t0x1d6\n#define KEY_FN_F6\t\t0x1d7\n#define KEY_FN_F7\t\t0x1d8\n#define KEY_FN_F8\t\t0x1d9\n#define KEY_FN_F9\t\t0x1da\n#define KEY_FN_F10\t\t0x1db\n#define KEY_FN_F11\t\t0x1dc\n#define KEY_FN_F12\t\t0x1dd\n#define KEY_FN_1\t\t0x1de\n#define KEY_FN_2\t\t0x1df\n#define KEY_FN_D\t\t0x1e0\n#define KEY_FN_E\t\t0x1e1\n#define KEY_FN_F\t\t0x1e2\n#define KEY_FN_S\t\t0x1e3\n#define KEY_FN_B\t\t0x1e4\n\n#define KEY_BRL_DOT1\t\t0x1f1\n#define KEY_BRL_DOT2\t\t0x1f2\n#define KEY_BRL_DOT3\t\t0x1f3\n#define KEY_BRL_DOT4\t\t0x1f4\n#define KEY_BRL_DOT5\t\t0x1f5\n#define KEY_BRL_DOT6\t\t0x1f6\n#define KEY_BRL_DOT7\t\t0x1f7\n#define KEY_BRL_DOT8\t\t0x1f8\n#define KEY_BRL_DOT9\t\t0x1f9\n#define KEY_BRL_DOT10\t\t0x1fa\n\n#define KEY_NUMERIC_0\t\t0x200\t/* used by phones, remote controls, */\n#define KEY_NUMERIC_1\t\t0x201\t/* and other keypads */\n#define KEY_NUMERIC_2\t\t0x202\n#define KEY_NUMERIC_3\t\t0x203\n#define KEY_NUMERIC_4\t\t0x204\n#define KEY_NUMERIC_5\t\t0x205\n#define KEY_NUMERIC_6\t\t0x206\n#define KEY_NUMERIC_7\t\t0x207\n#define KEY_NUMERIC_8\t\t0x208\n#define KEY_NUMERIC_9\t\t0x209\n#define KEY_NUMERIC_STAR\t0x20a\n#define KEY_NUMERIC_POUND\t0x20b\n#define KEY_NUMERIC_A\t\t0x20c\t/* Phone key A - HUT Telephony 0xb9 */\n#define KEY_NUMERIC_B\t\t0x20d\n#define KEY_NUMERIC_C\t\t0x20e\n#define KEY_NUMERIC_D\t\t0x20f\n\n#define KEY_CAMERA_FOCUS\t0x210\n#define KEY_WPS_BUTTON\t\t0x211\t/* WiFi Protected Setup key */\n\n#define KEY_TOUCHPAD_TOGGLE\t0x212\t/* Request switch touchpad on or off */\n#define KEY_TOUCHPAD_ON\t\t0x213\n#define KEY_TOUCHPAD_OFF\t0x214\n\n#define KEY_CAMERA_ZOOMIN\t0x215\n#define KEY_CAMERA_ZOOMOUT\t0x216\n#define KEY_CAMERA_UP\t\t0x217\n#define KEY_CAMERA_DOWN\t\t0x218\n#define KEY_CAMERA_LEFT\t\t0x219\n#define KEY_CAMERA_RIGHT\t0x21a\n\n#define KEY_ATTENDANT_ON\t0x21b\n#define KEY_ATTENDANT_OFF\t0x21c\n#define KEY_ATTENDANT_TOGGLE\t0x21d\t/* Attendant call on or off */\n#define KEY_LIGHTS_TOGGLE\t0x21e\t/* Reading light on or off */\n\n#define BTN_DPAD_UP\t\t0x220\n#define BTN_DPAD_DOWN\t\t0x221\n#define BTN_DPAD_LEFT\t\t0x222\n#define BTN_DPAD_RIGHT\t\t0x223\n\n#define KEY_ALS_TOGGLE\t\t0x230\t/* Ambient light sensor */\n\n#define KEY_BUTTONCONFIG\t\t0x240\t/* AL Button Configuration */\n#define KEY_TASKMANAGER\t\t0x241\t/* AL Task/Project Manager */\n#define KEY_JOURNAL\t\t0x242\t/* AL Log/Journal/Timecard */\n#define KEY_CONTROLPANEL\t\t0x243\t/* AL Control Panel */\n#define KEY_APPSELECT\t\t0x244\t/* AL Select Task/Application */\n#define KEY_SCREENSAVER\t\t0x245\t/* AL Screen Saver */\n#define KEY_VOICECOMMAND\t\t0x246\t/* Listening Voice Command */\n\n#define KEY_BRIGHTNESS_MIN\t\t0x250\t/* Set Brightness to Minimum */\n#define KEY_BRIGHTNESS_MAX\t\t0x251\t/* Set Brightness to Maximum */\n\n#define KEY_KBDINPUTASSIST_PREV\t\t0x260\n#define KEY_KBDINPUTASSIST_NEXT\t\t0x261\n#define KEY_KBDINPUTASSIST_PREVGROUP\t\t0x262\n#define KEY_KBDINPUTASSIST_NEXTGROUP\t\t0x263\n#define KEY_KBDINPUTASSIST_ACCEPT\t\t0x264\n#define KEY_KBDINPUTASSIST_CANCEL\t\t0x265\n\n#define BTN_TRIGGER_HAPPY\t\t0x2c0\n#define BTN_TRIGGER_HAPPY1\t\t0x2c0\n#define BTN_TRIGGER_HAPPY2\t\t0x2c1\n#define BTN_TRIGGER_HAPPY3\t\t0x2c2\n#define BTN_TRIGGER_HAPPY4\t\t0x2c3\n#define BTN_TRIGGER_HAPPY5\t\t0x2c4\n#define BTN_TRIGGER_HAPPY6\t\t0x2c5\n#define BTN_TRIGGER_HAPPY7\t\t0x2c6\n#define BTN_TRIGGER_HAPPY8\t\t0x2c7\n#define BTN_TRIGGER_HAPPY9\t\t0x2c8\n#define BTN_TRIGGER_HAPPY10\t\t0x2c9\n#define BTN_TRIGGER_HAPPY11\t\t0x2ca\n#define BTN_TRIGGER_HAPPY12\t\t0x2cb\n#define BTN_TRIGGER_HAPPY13\t\t0x2cc\n#define BTN_TRIGGER_HAPPY14\t\t0x2cd\n#define BTN_TRIGGER_HAPPY15\t\t0x2ce\n#define BTN_TRIGGER_HAPPY16\t\t0x2cf\n#define BTN_TRIGGER_HAPPY17\t\t0x2d0\n#define BTN_TRIGGER_HAPPY18\t\t0x2d1\n#define BTN_TRIGGER_HAPPY19\t\t0x2d2\n#define BTN_TRIGGER_HAPPY20\t\t0x2d3\n#define BTN_TRIGGER_HAPPY21\t\t0x2d4\n#define BTN_TRIGGER_HAPPY22\t\t0x2d5\n#define BTN_TRIGGER_HAPPY23\t\t0x2d6\n#define BTN_TRIGGER_HAPPY24\t\t0x2d7\n#define BTN_TRIGGER_HAPPY25\t\t0x2d8\n#define BTN_TRIGGER_HAPPY26\t\t0x2d9\n#define BTN_TRIGGER_HAPPY27\t\t0x2da\n#define BTN_TRIGGER_HAPPY28\t\t0x2db\n#define BTN_TRIGGER_HAPPY29\t\t0x2dc\n#define BTN_TRIGGER_HAPPY30\t\t0x2dd\n#define BTN_TRIGGER_HAPPY31\t\t0x2de\n#define BTN_TRIGGER_HAPPY32\t\t0x2df\n#define BTN_TRIGGER_HAPPY33\t\t0x2e0\n#define BTN_TRIGGER_HAPPY34\t\t0x2e1\n#define BTN_TRIGGER_HAPPY35\t\t0x2e2\n#define BTN_TRIGGER_HAPPY36\t\t0x2e3\n#define BTN_TRIGGER_HAPPY37\t\t0x2e4\n#define BTN_TRIGGER_HAPPY38\t\t0x2e5\n#define BTN_TRIGGER_HAPPY39\t\t0x2e6\n#define BTN_TRIGGER_HAPPY40\t\t0x2e7\n\n/* We avoid low common keys in module aliases so they don't get huge. */\n#define KEY_MIN_INTERESTING\tKEY_MUTE\n#define KEY_MAX\t\t\t0x2ff\n#define KEY_CNT\t\t\t(KEY_MAX+1)\n\n/*\n * Relative axes\n */\n\n#define REL_X\t\t\t0x00\n#define REL_Y\t\t\t0x01\n#define REL_Z\t\t\t0x02\n#define REL_RX\t\t\t0x03\n#define REL_RY\t\t\t0x04\n#define REL_RZ\t\t\t0x05\n#define REL_HWHEEL\t\t0x06\n#define REL_DIAL\t\t0x07\n#define REL_WHEEL\t\t0x08\n#define REL_MISC\t\t0x09\n#define REL_MAX\t\t\t0x0f\n#define REL_CNT\t\t\t(REL_MAX+1)\n\n/*\n * Absolute axes\n */\n\n#define ABS_X\t\t\t0x00\n#define ABS_Y\t\t\t0x01\n#define ABS_Z\t\t\t0x02\n#define ABS_RX\t\t\t0x03\n#define ABS_RY\t\t\t0x04\n#define ABS_RZ\t\t\t0x05\n#define ABS_THROTTLE\t\t0x06\n#define ABS_RUDDER\t\t0x07\n#define ABS_WHEEL\t\t0x08\n#define ABS_GAS\t\t\t0x09\n#define ABS_BRAKE\t\t0x0a\n#define ABS_HAT0X\t\t0x10\n#define ABS_HAT0Y\t\t0x11\n#define ABS_HAT1X\t\t0x12\n#define ABS_HAT1Y\t\t0x13\n#define ABS_HAT2X\t\t0x14\n#define ABS_HAT2Y\t\t0x15\n#define ABS_HAT3X\t\t0x16\n#define ABS_HAT3Y\t\t0x17\n#define ABS_PRESSURE\t\t0x18\n#define ABS_DISTANCE\t\t0x19\n#define ABS_TILT_X\t\t0x1a\n#define ABS_TILT_Y\t\t0x1b\n#define ABS_TOOL_WIDTH\t\t0x1c\n\n#define ABS_VOLUME\t\t0x20\n\n#define ABS_MISC\t\t0x28\n\n#define ABS_MT_SLOT\t\t0x2f\t/* MT slot being modified */\n#define ABS_MT_TOUCH_MAJOR\t0x30\t/* Major axis of touching ellipse */\n#define ABS_MT_TOUCH_MINOR\t0x31\t/* Minor axis (omit if circular) */\n#define ABS_MT_WIDTH_MAJOR\t0x32\t/* Major axis of approaching ellipse */\n#define ABS_MT_WIDTH_MINOR\t0x33\t/* Minor axis (omit if circular) */\n#define ABS_MT_ORIENTATION\t0x34\t/* Ellipse orientation */\n#define ABS_MT_POSITION_X\t0x35\t/* Center X touch position */\n#define ABS_MT_POSITION_Y\t0x36\t/* Center Y touch position */\n#define ABS_MT_TOOL_TYPE\t0x37\t/* Type of touching device */\n#define ABS_MT_BLOB_ID\t\t0x38\t/* Group a set of packets as a blob */\n#define ABS_MT_TRACKING_ID\t0x39\t/* Unique ID of initiated contact */\n#define ABS_MT_PRESSURE\t\t0x3a\t/* Pressure on contact area */\n#define ABS_MT_DISTANCE\t\t0x3b\t/* Contact hover distance */\n#define ABS_MT_TOOL_X\t\t0x3c\t/* Center X tool position */\n#define ABS_MT_TOOL_Y\t\t0x3d\t/* Center Y tool position */\n\n\n#define ABS_MAX\t\t\t0x3f\n#define ABS_CNT\t\t\t(ABS_MAX+1)\n\n/*\n * Switch events\n */\n\n#define SW_LID\t\t\t0x00 /* set = lid shut */\n#define SW_TABLET_MODE\t\t0x01 /* set = tablet mode */\n#define SW_HEADPHONE_INSERT\t0x02 /* set = inserted */\n#define SW_RFKILL_ALL\t\t0x03 /* rfkill master switch, type \"any\"\n\t\t\t\t\t set = radio enabled */\n#define SW_RADIO\t\tSW_RFKILL_ALL\t/* deprecated */\n#define SW_MICROPHONE_INSERT\t0x04 /* set = inserted */\n#define SW_DOCK\t\t\t0x05 /* set = plugged into dock */\n#define SW_LINEOUT_INSERT\t0x06 /* set = inserted */\n#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */\n#define SW_VIDEOOUT_INSERT\t0x08 /* set = inserted */\n#define SW_CAMERA_LENS_COVER\t0x09 /* set = lens covered */\n#define SW_KEYPAD_SLIDE\t\t0x0a /* set = keypad slide out */\n#define SW_FRONT_PROXIMITY\t0x0b /* set = front proximity sensor active */\n#define SW_ROTATE_LOCK\t\t0x0c /* set = rotate locked/disabled */\n#define SW_LINEIN_INSERT\t0x0d /* set = inserted */\n#define SW_MUTE_DEVICE\t\t0x0e /* set = device disabled */\n#define SW_MAX\t\t\t0x0f\n#define SW_CNT\t\t\t(SW_MAX+1)\n\n/*\n * Misc events\n */\n\n#define MSC_SERIAL\t\t0x00\n#define MSC_PULSELED\t\t0x01\n#define MSC_GESTURE\t\t0x02\n#define MSC_RAW\t\t\t0x03\n#define MSC_SCAN\t\t0x04\n#define MSC_TIMESTAMP\t\t0x05\n#define MSC_MAX\t\t\t0x07\n#define MSC_CNT\t\t\t(MSC_MAX+1)\n\n/*\n * LEDs\n */\n\n#define LED_NUML\t\t0x00\n#define LED_CAPSL\t\t0x01\n#define LED_SCROLLL\t\t0x02\n#define LED_COMPOSE\t\t0x03\n#define LED_KANA\t\t0x04\n#define LED_SLEEP\t\t0x05\n#define LED_SUSPEND\t\t0x06\n#define LED_MUTE\t\t0x07\n#define LED_MISC\t\t0x08\n#define LED_MAIL\t\t0x09\n#define LED_CHARGING\t\t0x0a\n#define LED_MAX\t\t\t0x0f\n#define LED_CNT\t\t\t(LED_MAX+1)\n\n/*\n * Autorepeat values\n */\n\n#define REP_DELAY\t\t0x00\n#define REP_PERIOD\t\t0x01\n#define REP_MAX\t\t\t0x01\n#define REP_CNT\t\t\t(REP_MAX+1)\n\n/*\n * Sounds\n */\n\n#define SND_CLICK\t\t0x00\n#define SND_BELL\t\t0x01\n#define SND_TONE\t\t0x02\n#define SND_MAX\t\t\t0x07\n#define SND_CNT\t\t\t(SND_MAX+1)\n\n#define MATRIX_KEY(row, col, code)\t\\\n\t((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))\n\n#endif /* _DT_BINDINGS_INPUT_INPUT_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/interrupt-controller/irq.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most IRQ bindings.\n *\n * Most IRQ bindings include a flags cell as part of the IRQ specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n\n#define IRQ_TYPE_NONE\t\t0\n#define IRQ_TYPE_EDGE_RISING\t1\n#define IRQ_TYPE_EDGE_FALLING\t2\n#define IRQ_TYPE_EDGE_BOTH\t(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)\n#define IRQ_TYPE_LEVEL_HIGH\t4\n#define IRQ_TYPE_LEVEL_LOW\t8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/net/ti-dp83867.h", "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Device Tree constants for the Texas Instruments DP83867 PHY\n *\n * Author: Dan Murphy \n *\n * Copyright: (C) 2015 Texas Instruments, Inc.\n */\n\n#ifndef _DT_BINDINGS_TI_DP83867_H\n#define _DT_BINDINGS_TI_DP83867_H\n\n/* PHY CTRL bits */\n#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB\t0x00\n#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB\t0x01\n#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB\t0x02\n#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB\t0x03\n\n/* RGMIIDCTL internal delay for rx and tx */\n#define\tDP83867_RGMIIDCTL_250_PS\t0x0\n#define\tDP83867_RGMIIDCTL_500_PS\t0x1\n#define\tDP83867_RGMIIDCTL_750_PS\t0x2\n#define\tDP83867_RGMIIDCTL_1_NS\t\t0x3\n#define\tDP83867_RGMIIDCTL_1_25_NS\t0x4\n#define\tDP83867_RGMIIDCTL_1_50_NS\t0x5\n#define\tDP83867_RGMIIDCTL_1_75_NS\t0x6\n#define\tDP83867_RGMIIDCTL_2_00_NS\t0x7\n#define\tDP83867_RGMIIDCTL_2_25_NS\t0x8\n#define\tDP83867_RGMIIDCTL_2_50_NS\t0x9\n#define\tDP83867_RGMIIDCTL_2_75_NS\t0xa\n#define\tDP83867_RGMIIDCTL_3_00_NS\t0xb\n#define\tDP83867_RGMIIDCTL_3_25_NS\t0xc\n#define\tDP83867_RGMIIDCTL_3_50_NS\t0xd\n#define\tDP83867_RGMIIDCTL_3_75_NS\t0xe\n#define\tDP83867_RGMIIDCTL_4_00_NS\t0xf\n\n/* IO_MUX_CFG - Clock output selection */\n#define DP83867_CLK_O_SEL_CHN_A_RCLK\t\t0x0\n#define DP83867_CLK_O_SEL_CHN_B_RCLK\t\t0x1\n#define DP83867_CLK_O_SEL_CHN_C_RCLK\t\t0x2\n#define DP83867_CLK_O_SEL_CHN_D_RCLK\t\t0x3\n#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5\t0x4\n#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5\t0x5\n#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5\t0x6\n#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5\t0x7\n#define DP83867_CLK_O_SEL_CHN_A_TCLK\t\t0x8\n#define DP83867_CLK_O_SEL_CHN_B_TCLK\t\t0x9\n#define DP83867_CLK_O_SEL_CHN_C_TCLK\t\t0xA\n#define DP83867_CLK_O_SEL_CHN_D_TCLK\t\t0xB\n#define DP83867_CLK_O_SEL_REF_CLK\t\t0xC\n/* Special flag to indicate clock should be off */\n#define DP83867_CLK_O_SEL_OFF\t\t\t0xFFFFFFFF\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/phy/phy.h", "content": "/*\n *\n * This header provides constants for the phy framework\n *\n * Copyright (C) 2014 STMicroelectronics\n * Author: Gabriel Fernandez \n * License terms: GNU General Public License (GPL), version 2\n */\n\n#ifndef _DT_BINDINGS_PHY\n#define _DT_BINDINGS_PHY\n\n#define PHY_NONE\t\t0\n#define PHY_TYPE_SATA\t\t1\n#define PHY_TYPE_PCIE\t\t2\n#define PHY_TYPE_USB2\t\t3\n#define PHY_TYPE_USB3\t\t4\n#define PHY_TYPE_UFS\t\t5\n#define PHY_TYPE_DP\t\t6\n#define PHY_TYPE_XPCS\t\t7\n#define PHY_TYPE_SGMII\t\t8\n#define PHY_TYPE_QSGMII\t\t9\n\n#endif /* _DT_BINDINGS_PHY */\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * MIO pin configuration defines for Xilinx ZynqMP\n *\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H\n#define _DT_BINDINGS_PINCTRL_ZYNQMP_H\n\n/* Bit value for different voltage levels */\n#define IO_STANDARD_LVCMOS33\t0\n#define IO_STANDARD_LVCMOS18\t1\n\n/* Bit values for Slew Rates */\n#define SLEW_RATE_FAST\t\t0\n#define SLEW_RATE_SLOW\t\t1\n\n/* Bit values for Pin drive strength */\n#define DRIVE_STRENGTH_2MA\t2\n#define DRIVE_STRENGTH_4MA\t4\n#define DRIVE_STRENGTH_8MA\t8\n#define DRIVE_STRENGTH_12MA\t12\n\n#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-net-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2022-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_NET_POWER_H\n#define _DT_BINDINGS_VERSAL_NET_POWER_H\n\n#include \"xlnx-versal-power.h\"\n\n#define PM_DEV_USB_1\t\t\t\t(0x182240D7U)\n\n/* Remove Versal specific node IDs */\n#undef PM_DEV_RPU0_0\n#undef PM_DEV_RPU0_1\n#undef PM_DEV_OCM_0\n#undef PM_DEV_OCM_1\n#undef PM_DEV_OCM_2\n#undef PM_DEV_OCM_3\n#undef PM_DEV_TCM_0_A\n#undef PM_DEV_TCM_1_A\n#undef PM_DEV_TCM_0_B\n#undef PM_DEV_TCM_1_B\n#undef PM_DEV_SWDT_FPD\n#undef PM_DEV_ADMA_0\n#undef PM_DEV_ADMA_1\n#undef PM_DEV_ADMA_2\n#undef PM_DEV_ADMA_3\n#undef PM_DEV_ADMA_4\n#undef PM_DEV_ADMA_5\n#undef PM_DEV_ADMA_6\n#undef PM_DEV_ADMA_7\n#undef PM_DEV_AI\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_POWER_H\n#define _DT_BINDINGS_VERSAL_POWER_H\n\n#define PM_DEV_USB_0\t\t\t\t(0x18224018U)\n#define PM_DEV_GEM_0\t\t\t\t(0x18224019U)\n#define PM_DEV_GEM_1\t\t\t\t(0x1822401aU)\n#define PM_DEV_SPI_0\t\t\t\t(0x1822401bU)\n#define PM_DEV_SPI_1\t\t\t\t(0x1822401cU)\n#define PM_DEV_I2C_0\t\t\t\t(0x1822401dU)\n#define PM_DEV_I2C_1\t\t\t\t(0x1822401eU)\n#define PM_DEV_I2C_PMC (0x1822402dU)\n#define PM_DEV_CAN_FD_0\t\t\t\t(0x1822401fU)\n#define PM_DEV_CAN_FD_1\t\t\t\t(0x18224020U)\n#define PM_DEV_UART_0\t\t\t\t(0x18224021U)\n#define PM_DEV_UART_1\t\t\t\t(0x18224022U)\n#define PM_DEV_GPIO\t\t\t\t(0x18224023U)\n#define PM_DEV_TTC_0\t\t\t\t(0x18224024U)\n#define PM_DEV_TTC_1\t\t\t\t(0x18224025U)\n#define PM_DEV_TTC_2\t\t\t\t(0x18224026U)\n#define PM_DEV_TTC_3\t\t\t\t(0x18224027U)\n#define PM_DEV_SWDT_FPD\t\t\t\t(0x18224029U)\n#define PM_DEV_OSPI\t\t\t\t(0x1822402aU)\n#define PM_DEV_QSPI\t\t\t\t(0x1822402bU)\n#define PM_DEV_GPIO_PMC\t\t\t\t(0x1822402cU)\n#define PM_DEV_SDIO_0\t\t\t\t(0x1822402eU)\n#define PM_DEV_SDIO_1\t\t\t\t(0x1822402fU)\n#define PM_DEV_RTC\t\t\t\t(0x18224034U)\n#define PM_DEV_ADMA_0\t\t\t\t(0x18224035U)\n#define PM_DEV_ADMA_1\t\t\t\t(0x18224036U)\n#define PM_DEV_ADMA_2\t\t\t\t(0x18224037U)\n#define PM_DEV_ADMA_3\t\t\t\t(0x18224038U)\n#define PM_DEV_ADMA_4\t\t\t\t(0x18224039U)\n#define PM_DEV_ADMA_5\t\t\t\t(0x1822403aU)\n#define PM_DEV_ADMA_6\t\t\t\t(0x1822403bU)\n#define PM_DEV_ADMA_7\t\t\t\t(0x1822403cU)\n#define PM_DEV_AI\t\t\t\t(0x18224072U)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-regnode.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2022-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_REGNODE_H\n#define _DT_BINDINGS_VERSAL_REGNODE_H\n\n#define PM_REGNODE_SYSMON_ROOT_0\t\t\t(0x18224055U)\n#define PM_REGNODE_SYSMON_ROOT_1\t\t\t(0x18225055U)\n#define PM_REGNODE_SYSMON_ROOT_2\t\t\t(0x18226055U)\n#define PM_REGNODE_SYSMON_ROOT_3\t\t\t(0x18227055U)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-zynqmp-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_POWER_H\n#define _DT_BINDINGS_ZYNQMP_POWER_H\n\n#define\t\tPD_USB_0\t22\n#define\t\tPD_USB_1\t23\n#define\t\tPD_TTC_0\t24\n#define\t\tPD_TTC_1\t25\n#define\t\tPD_TTC_2\t26\n#define\t\tPD_TTC_3\t27\n#define\t\tPD_SATA\t\t28\n#define\t\tPD_ETH_0\t29\n#define\t\tPD_ETH_1\t30\n#define\t\tPD_ETH_2\t31\n#define\t\tPD_ETH_3\t32\n#define\t\tPD_UART_0\t33\n#define\t\tPD_UART_1\t34\n#define\t\tPD_SPI_0\t35\n#define\t\tPD_SPI_1\t36\n#define\t\tPD_I2C_0\t37\n#define\t\tPD_I2C_1\t38\n#define\t\tPD_SD_0\t\t39\n#define\t\tPD_SD_1\t\t40\n#define\t\tPD_DP\t\t41\n#define\t\tPD_GDMA\t\t42\n#define\t\tPD_ADMA\t\t43\n#define\t\tPD_NAND\t\t44\n#define\t\tPD_QSPI\t\t45\n#define\t\tPD_GPIO\t\t46\n#define\t\tPD_CAN_0\t47\n#define\t\tPD_CAN_1\t48\n#define\t\tPD_GPU\t\t58\n#define\t\tPD_PCIE\t\t59\n#define\t\tPD_PL\t\t69\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-versal-net-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H\n#define _DT_BINDINGS_VERSAL_NET_RESETS_H\n\n#include \"xlnx-versal-resets.h\"\n\n#define VERSAL_RST_USB_1\t\t\t(0xc4100c6U)\n\n/* Remove Versal specific reset IDs */\n#undef VERSAL_RST_ACPU_0_POR\n#undef VERSAL_RST_ACPU_1_POR\n#undef VERSAL_RST_OCM2_POR\n#undef VERSAL_RST_APU\n#undef VERSAL_RST_ACPU_0\n#undef VERSAL_RST_ACPU_1\n#undef VERSAL_RST_ACPU_L2\n#undef VERSAL_RST_RPU_ISLAND\n#undef VERSAL_RST_RPU_AMBA\n#undef VERSAL_RST_R5_0\n#undef VERSAL_RST_R5_1\n#undef VERSAL_RST_OCM2_RST\n#undef VERSAL_RST_I2C_PMC\n#undef VERSAL_RST_I2C_0\n#undef VERSAL_RST_I2C_1\n#undef VERSAL_RST_SWDT_FPD\n#undef VERSAL_RST_SWDT_LPD\n#undef VERSAL_RST_USB\n#undef VERSAL_RST_DPC\n#undef VERSAL_RST_DBG_TRACE\n#undef VERSAL_RST_DBG_TSTMP\n#undef VERSAL_RST_RPU0_DBG\n#undef VERSAL_RST_RPU1_DBG\n#undef VERSAL_RST_HSDP\n#undef VERSAL_RST_CPMDBG\n#undef VERSAL_RST_PCIE_CFG\n#undef VERSAL_RST_PCIE_CORE0\n#undef VERSAL_RST_PCIE_CORE1\n#undef VERSAL_RST_PCIE_DMA\n#undef VERSAL_RST_L2_0\n#undef VERSAL_RST_L2_1\n#undef VERSAL_RST_ADDR_REMAP\n#undef VERSAL_RST_CPI0\n#undef VERSAL_RST_CPI1\n#undef VERSAL_RST_XRAM\n#undef VERSAL_RST_AIE_ARRAY\n#undef VERSAL_RST_AIE_SHIM\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-versal-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_RESETS_H\n#define _DT_BINDINGS_VERSAL_RESETS_H\n\n#define VERSAL_RST_PMC_POR\t\t\t(0xc30c001U)\n#define VERSAL_RST_PMC\t\t\t\t(0xc410002U)\n#define VERSAL_RST_PS_POR\t\t\t(0xc30c003U)\n#define VERSAL_RST_PL_POR\t\t\t(0xc30c004U)\n#define VERSAL_RST_NOC_POR\t\t\t(0xc30c005U)\n#define VERSAL_RST_FPD_POR\t\t\t(0xc30c006U)\n#define VERSAL_RST_ACPU_0_POR\t\t\t(0xc30c007U)\n#define VERSAL_RST_ACPU_1_POR\t\t\t(0xc30c008U)\n#define VERSAL_RST_OCM2_POR\t\t\t(0xc30c009U)\n#define VERSAL_RST_PS_SRST\t\t\t(0xc41000aU)\n#define VERSAL_RST_PL_SRST\t\t\t(0xc41000bU)\n#define VERSAL_RST_NOC\t\t\t\t(0xc41000cU)\n#define VERSAL_RST_NPI\t\t\t\t(0xc41000dU)\n#define VERSAL_RST_SYS_RST_1\t\t\t(0xc41000eU)\n#define VERSAL_RST_SYS_RST_2\t\t\t(0xc41000fU)\n#define VERSAL_RST_SYS_RST_3\t\t\t(0xc410010U)\n#define VERSAL_RST_FPD\t\t\t\t(0xc410011U)\n#define VERSAL_RST_PL0\t\t\t\t(0xc410012U)\n#define VERSAL_RST_PL1\t\t\t\t(0xc410013U)\n#define VERSAL_RST_PL2\t\t\t\t(0xc410014U)\n#define VERSAL_RST_PL3\t\t\t\t(0xc410015U)\n#define VERSAL_RST_APU\t\t\t\t(0xc410016U)\n#define VERSAL_RST_ACPU_0\t\t\t(0xc410017U)\n#define VERSAL_RST_ACPU_1\t\t\t(0xc410018U)\n#define VERSAL_RST_ACPU_L2\t\t\t(0xc410019U)\n#define VERSAL_RST_ACPU_GIC\t\t\t(0xc41001aU)\n#define VERSAL_RST_RPU_ISLAND\t\t\t(0xc41001bU)\n#define VERSAL_RST_RPU_AMBA\t\t\t(0xc41001cU)\n#define VERSAL_RST_R5_0\t\t\t\t(0xc41001dU)\n#define VERSAL_RST_R5_1\t\t\t\t(0xc41001eU)\n#define VERSAL_RST_SYSMON_PMC_SEQ_RST\t\t(0xc41001fU)\n#define VERSAL_RST_SYSMON_PMC_CFG_RST\t\t(0xc410020U)\n#define VERSAL_RST_SYSMON_FPD_CFG_RST\t\t(0xc410021U)\n#define VERSAL_RST_SYSMON_FPD_SEQ_RST\t\t(0xc410022U)\n#define VERSAL_RST_SYSMON_LPD\t\t\t(0xc410023U)\n#define VERSAL_RST_PDMA_RST1\t\t\t(0xc410024U)\n#define VERSAL_RST_PDMA_RST0\t\t\t(0xc410025U)\n#define VERSAL_RST_ADMA\t\t\t\t(0xc410026U)\n#define VERSAL_RST_TIMESTAMP\t\t\t(0xc410027U)\n#define VERSAL_RST_OCM\t\t\t\t(0xc410028U)\n#define VERSAL_RST_OCM2_RST\t\t\t(0xc410029U)\n#define VERSAL_RST_IPI\t\t\t\t(0xc41002aU)\n#define VERSAL_RST_SBI\t\t\t\t(0xc41002bU)\n#define VERSAL_RST_LPD\t\t\t\t(0xc41002cU)\n#define VERSAL_RST_QSPI\t\t\t\t(0xc10402dU)\n#define VERSAL_RST_OSPI\t\t\t\t(0xc10402eU)\n#define VERSAL_RST_SDIO_0\t\t\t(0xc10402fU)\n#define VERSAL_RST_SDIO_1\t\t\t(0xc104030U)\n#define VERSAL_RST_I2C_PMC\t\t\t(0xc104031U)\n#define VERSAL_RST_GPIO_PMC\t\t\t(0xc104032U)\n#define VERSAL_RST_GEM_0\t\t\t(0xc104033U)\n#define VERSAL_RST_GEM_1\t\t\t(0xc104034U)\n#define VERSAL_RST_SPARE\t\t\t(0xc104035U)\n#define VERSAL_RST_USB_0\t\t\t(0xc104036U)\n#define VERSAL_RST_UART_0\t\t\t(0xc104037U)\n#define VERSAL_RST_UART_1\t\t\t(0xc104038U)\n#define VERSAL_RST_SPI_0\t\t\t(0xc104039U)\n#define VERSAL_RST_SPI_1\t\t\t(0xc10403aU)\n#define VERSAL_RST_CAN_FD_0\t\t\t(0xc10403bU)\n#define VERSAL_RST_CAN_FD_1\t\t\t(0xc10403cU)\n#define VERSAL_RST_I2C_0\t\t\t(0xc10403dU)\n#define VERSAL_RST_I2C_1\t\t\t(0xc10403eU)\n#define VERSAL_RST_GPIO_LPD\t\t\t(0xc10403fU)\n#define VERSAL_RST_TTC_0\t\t\t(0xc104040U)\n#define VERSAL_RST_TTC_1\t\t\t(0xc104041U)\n#define VERSAL_RST_TTC_2\t\t\t(0xc104042U)\n#define VERSAL_RST_TTC_3\t\t\t(0xc104043U)\n#define VERSAL_RST_SWDT_FPD\t\t\t(0xc104044U)\n#define VERSAL_RST_SWDT_LPD\t\t\t(0xc104045U)\n#define VERSAL_RST_USB\t\t\t\t(0xc104046U)\n#define VERSAL_RST_DPC\t\t\t\t(0xc208047U)\n#define VERSAL_RST_PMCDBG\t\t\t(0xc208048U)\n#define VERSAL_RST_DBG_TRACE\t\t\t(0xc208049U)\n#define VERSAL_RST_DBG_FPD\t\t\t(0xc20804aU)\n#define VERSAL_RST_DBG_TSTMP\t\t\t(0xc20804bU)\n#define VERSAL_RST_RPU0_DBG\t\t\t(0xc20804cU)\n#define VERSAL_RST_RPU1_DBG\t\t\t(0xc20804dU)\n#define VERSAL_RST_HSDP\t\t\t\t(0xc20804eU)\n#define VERSAL_RST_DBG_LPD\t\t\t(0xc20804fU)\n#define VERSAL_RST_CPM_POR\t\t\t(0xc30c050U)\n#define VERSAL_RST_CPM\t\t\t\t(0xc410051U)\n#define VERSAL_RST_CPMDBG\t\t\t(0xc208052U)\n#define VERSAL_RST_PCIE_CFG\t\t\t(0xc410053U)\n#define VERSAL_RST_PCIE_CORE0\t\t\t(0xc410054U)\n#define VERSAL_RST_PCIE_CORE1\t\t\t(0xc410055U)\n#define VERSAL_RST_PCIE_DMA\t\t\t(0xc410056U)\n#define VERSAL_RST_CMN\t\t\t\t(0xc410057U)\n#define VERSAL_RST_L2_0\t\t\t\t(0xc410058U)\n#define VERSAL_RST_L2_1\t\t\t\t(0xc410059U)\n#define VERSAL_RST_ADDR_REMAP\t\t\t(0xc41005aU)\n#define VERSAL_RST_CPI0\t\t\t\t(0xc41005bU)\n#define VERSAL_RST_CPI1\t\t\t\t(0xc41005cU)\n#define VERSAL_RST_XRAM\t\t\t\t(0xc30c05dU)\n#define VERSAL_RST_AIE_ARRAY\t\t\t(0xc10405eU)\n#define VERSAL_RST_AIE_SHIM\t\t\t(0xc10405fU)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H\n#define _DT_BINDINGS_ZYNQMP_RESETS_H\n\n#define\t\tZYNQMP_RESET_PCIE_CFG\t\t0\n#define\t\tZYNQMP_RESET_PCIE_BRIDGE\t1\n#define\t\tZYNQMP_RESET_PCIE_CTRL\t\t2\n#define\t\tZYNQMP_RESET_DP\t\t\t3\n#define\t\tZYNQMP_RESET_SWDT_CRF\t\t4\n#define\t\tZYNQMP_RESET_AFI_FM5\t\t5\n#define\t\tZYNQMP_RESET_AFI_FM4\t\t6\n#define\t\tZYNQMP_RESET_AFI_FM3\t\t7\n#define\t\tZYNQMP_RESET_AFI_FM2\t\t8\n#define\t\tZYNQMP_RESET_AFI_FM1\t\t9\n#define\t\tZYNQMP_RESET_AFI_FM0\t\t10\n#define\t\tZYNQMP_RESET_GDMA\t\t11\n#define\t\tZYNQMP_RESET_GPU_PP1\t\t12\n#define\t\tZYNQMP_RESET_GPU_PP0\t\t13\n#define\t\tZYNQMP_RESET_GPU\t\t14\n#define\t\tZYNQMP_RESET_GT\t\t\t15\n#define\t\tZYNQMP_RESET_SATA\t\t16\n#define\t\tZYNQMP_RESET_ACPU3_PWRON\t17\n#define\t\tZYNQMP_RESET_ACPU2_PWRON\t18\n#define\t\tZYNQMP_RESET_ACPU1_PWRON\t19\n#define\t\tZYNQMP_RESET_ACPU0_PWRON\t20\n#define\t\tZYNQMP_RESET_APU_L2\t\t21\n#define\t\tZYNQMP_RESET_ACPU3\t\t22\n#define\t\tZYNQMP_RESET_ACPU2\t\t23\n#define\t\tZYNQMP_RESET_ACPU1\t\t24\n#define\t\tZYNQMP_RESET_ACPU0\t\t25\n#define\t\tZYNQMP_RESET_DDR\t\t26\n#define\t\tZYNQMP_RESET_APM_FPD\t\t27\n#define\t\tZYNQMP_RESET_SOFT\t\t28\n#define\t\tZYNQMP_RESET_GEM0\t\t29\n#define\t\tZYNQMP_RESET_GEM1\t\t30\n#define\t\tZYNQMP_RESET_GEM2\t\t31\n#define\t\tZYNQMP_RESET_GEM3\t\t32\n#define\t\tZYNQMP_RESET_QSPI\t\t33\n#define\t\tZYNQMP_RESET_UART0\t\t34\n#define\t\tZYNQMP_RESET_UART1\t\t35\n#define\t\tZYNQMP_RESET_SPI0\t\t36\n#define\t\tZYNQMP_RESET_SPI1\t\t37\n#define\t\tZYNQMP_RESET_SDIO0\t\t38\n#define\t\tZYNQMP_RESET_SDIO1\t\t39\n#define\t\tZYNQMP_RESET_CAN0\t\t40\n#define\t\tZYNQMP_RESET_CAN1\t\t41\n#define\t\tZYNQMP_RESET_I2C0\t\t42\n#define\t\tZYNQMP_RESET_I2C1\t\t43\n#define\t\tZYNQMP_RESET_TTC0\t\t44\n#define\t\tZYNQMP_RESET_TTC1\t\t45\n#define\t\tZYNQMP_RESET_TTC2\t\t46\n#define\t\tZYNQMP_RESET_TTC3\t\t47\n#define\t\tZYNQMP_RESET_SWDT_CRL\t\t48\n#define\t\tZYNQMP_RESET_NAND\t\t49\n#define\t\tZYNQMP_RESET_ADMA\t\t50\n#define\t\tZYNQMP_RESET_GPIO\t\t51\n#define\t\tZYNQMP_RESET_IOU_CC\t\t52\n#define\t\tZYNQMP_RESET_TIMESTAMP\t\t53\n#define\t\tZYNQMP_RESET_RPU_R50\t\t54\n#define\t\tZYNQMP_RESET_RPU_R51\t\t55\n#define\t\tZYNQMP_RESET_RPU_AMBA\t\t56\n#define\t\tZYNQMP_RESET_OCM\t\t57\n#define\t\tZYNQMP_RESET_RPU_PGE\t\t58\n#define\t\tZYNQMP_RESET_USB0_CORERESET\t59\n#define\t\tZYNQMP_RESET_USB1_CORERESET\t60\n#define\t\tZYNQMP_RESET_USB0_HIBERRESET\t61\n#define\t\tZYNQMP_RESET_USB1_HIBERRESET\t62\n#define\t\tZYNQMP_RESET_USB0_APB\t\t63\n#define\t\tZYNQMP_RESET_USB1_APB\t\t64\n#define\t\tZYNQMP_RESET_IPI\t\t65\n#define\t\tZYNQMP_RESET_APM_LPD\t\t66\n#define\t\tZYNQMP_RESET_RTC\t\t67\n#define\t\tZYNQMP_RESET_SYSMON\t\t68\n#define\t\tZYNQMP_RESET_AFI_FM6\t\t69\n#define\t\tZYNQMP_RESET_LPD_SWDT\t\t70\n#define\t\tZYNQMP_RESET_FPD\t\t71\n#define\t\tZYNQMP_RESET_RPU_DBG1\t\t72\n#define\t\tZYNQMP_RESET_RPU_DBG0\t\t73\n#define\t\tZYNQMP_RESET_DBG_LPD\t\t74\n#define\t\tZYNQMP_RESET_DBG_FPD\t\t75\n#define\t\tZYNQMP_RESET_APLL\t\t76\n#define\t\tZYNQMP_RESET_DPLL\t\t77\n#define\t\tZYNQMP_RESET_VPLL\t\t78\n#define\t\tZYNQMP_RESET_IOPLL\t\t79\n#define\t\tZYNQMP_RESET_RPLL\t\t80\n#define\t\tZYNQMP_RESET_GPO3_PL_0\t\t81\n#define\t\tZYNQMP_RESET_GPO3_PL_1\t\t82\n#define\t\tZYNQMP_RESET_GPO3_PL_2\t\t83\n#define\t\tZYNQMP_RESET_GPO3_PL_3\t\t84\n#define\t\tZYNQMP_RESET_GPO3_PL_4\t\t85\n#define\t\tZYNQMP_RESET_GPO3_PL_5\t\t86\n#define\t\tZYNQMP_RESET_GPO3_PL_6\t\t87\n#define\t\tZYNQMP_RESET_GPO3_PL_7\t\t88\n#define\t\tZYNQMP_RESET_GPO3_PL_8\t\t89\n#define\t\tZYNQMP_RESET_GPO3_PL_9\t\t90\n#define\t\tZYNQMP_RESET_GPO3_PL_10\t\t91\n#define\t\tZYNQMP_RESET_GPO3_PL_11\t\t92\n#define\t\tZYNQMP_RESET_GPO3_PL_12\t\t93\n#define\t\tZYNQMP_RESET_GPO3_PL_13\t\t94\n#define\t\tZYNQMP_RESET_GPO3_PL_14\t\t95\n#define\t\tZYNQMP_RESET_GPO3_PL_15\t\t96\n#define\t\tZYNQMP_RESET_GPO3_PL_16\t\t97\n#define\t\tZYNQMP_RESET_GPO3_PL_17\t\t98\n#define\t\tZYNQMP_RESET_GPO3_PL_18\t\t99\n#define\t\tZYNQMP_RESET_GPO3_PL_19\t\t100\n#define\t\tZYNQMP_RESET_GPO3_PL_20\t\t101\n#define\t\tZYNQMP_RESET_GPO3_PL_21\t\t102\n#define\t\tZYNQMP_RESET_GPO3_PL_22\t\t103\n#define\t\tZYNQMP_RESET_GPO3_PL_23\t\t104\n#define\t\tZYNQMP_RESET_GPO3_PL_24\t\t105\n#define\t\tZYNQMP_RESET_GPO3_PL_25\t\t106\n#define\t\tZYNQMP_RESET_GPO3_PL_26\t\t107\n#define\t\tZYNQMP_RESET_GPO3_PL_27\t\t108\n#define\t\tZYNQMP_RESET_GPO3_PL_28\t\t109\n#define\t\tZYNQMP_RESET_GPO3_PL_29\t\t110\n#define\t\tZYNQMP_RESET_GPO3_PL_30\t\t111\n#define\t\tZYNQMP_RESET_GPO3_PL_31\t\t112\n#define\t\tZYNQMP_RESET_RPU_LS\t\t113\n#define\t\tZYNQMP_RESET_PS_ONLY\t\t114\n#define\t\tZYNQMP_RESET_PL\t\t\t115\n#define\t\tZYNQMP_RESET_PS_PL0\t\t116\n#define\t\tZYNQMP_RESET_PS_PL1\t\t117\n#define\t\tZYNQMP_RESET_PS_PL2\t\t118\n#define\t\tZYNQMP_RESET_PS_PL3\t\t119\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/versal/versal-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-versal-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-power.h\"\n#include \"include/dt-bindings/power/xlnx-versal-regnode.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-resets.h\"\n/ {\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tcan0_clk: can0_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN0_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tcan1_clk: can1_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN1_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t\tversal_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t\tversal_sec_cfg: versal-sec-cfg {\n\t\t\t\tcompatible = \"xlnx,versal-sec-cfg\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tbbram_zeroize: bbram-zeroize@4 {\n\t\t\t\t\treg = <0x04 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_key: bbram-key@10 {\n\t\t\t\t\treg = <0x10 0x20>;\n\t\t\t\t};\n\n\t\t\t\tbbram_usr: bbram-usr@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_lock: bbram-lock@48 {\n\t\t\t\t\treg = <0x48 0x4>;\n\t\t\t\t};\n\n\t\t\t\tuser_key0: user-key@110 {\n\t\t\t\t\treg = <0x110 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key1: user-key@130 {\n\t\t\t\t\treg = <0x130 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key2: user-key@150 {\n\t\t\t\t\treg = <0x150 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key3: user-key@170 {\n\t\t\t\t\treg = <0x170 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key4: user-key@190 {\n\t\t\t\t\treg = <0x190 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key5: user-key@1b0 {\n\t\t\t\t\treg = <0x1b0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key6: user-key@1d0 {\n\t\t\t\t\treg = <0x1d0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key7: user-key@1f0 {\n\t\t\t\t\treg = <0x1f0 0x20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk ACPU>;\n};\n\n&can0 {\n\tclocks = <&can0_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_0>;\n};\n\n&can1 {\n\tclocks = <&can1_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_1>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_0>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_1>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk PMC_LSBUS_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO_PMC>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk I2C0_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_0>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk I2C1_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_1>;\n};\n\n&i2c2 {\n\tclocks = <&versal_clk I2C_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_PMC>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_0>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_1>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_2>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_3>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_4>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_5>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_6>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_7>;\n};\n\n&qspi {\n\tclocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_QSPI>;\n};\n\n&ospi {\n\tclocks = <&versal_clk OSPI_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_OSPI>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware PM_DEV_RTC>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_0>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_1>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_0>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_1>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_0>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_1>;\n};\n\n&ttc0 {\n\tclocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_0>;\n};\n\n&ttc1 {\n\tclocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_1>;\n};\n\n&ttc2 {\n\tclocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_2>;\n};\n\n&ttc3 {\n\tclocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_3>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_USB_0>;\n\tresets = <&versal_reset VERSAL_RST_USB_0>;\n};\n\n&dwc3_0 {\n\tclocks = <&versal_clk USB0_BUS_REF>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SWDT_FPD>;\n};\n\n&sysmon0 {\n\txlnx,nodeid = ;\n};\n\n&sysmon1 {\n\txlnx,nodeid = ;\n};\n\n&sysmon2 {\n\txlnx,nodeid = ;\n};\n\n&sysmon3 {\n\txlnx,nodeid = ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/versal/versal-spp-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\talt_ref_clk: alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware-wip\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"alt_ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk 77>;\n};\n\n&can0 {\n\tclocks = <&versal_clk 96>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401f>;\n};\n\n&can1 {\n\tclocks = <&versal_clk 97>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224020>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x18224019>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x1822401a>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk 61>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk 98>;\n\tpower-domains = <&versal_firmware 0x1822401d>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk 99>;\n\tpower-domains = <&versal_firmware 0x1822401e>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224035>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224036>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224037>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224038>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224039>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403a>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403b>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403c>;\n};\n\n&qspi {\n\tclocks = <&versal_clk 57>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402b>;\n};\n\n&ospi {\n\tclocks = <&versal_clk 58>, <&versal_clk 82>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware 0x18224034>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk 92>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224021>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk 93>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224022>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk 59>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402e>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk 60>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402f>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk 94>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401b>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk 95>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401c>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk 91>, <&versal_clk 104>;\n\tpower-domains = <&versal_firmware 0x18224018>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk 82>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/versal/versal.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal\";\n\n\tcpus: cpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <1>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tfpga: fpga {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&versal_fpga>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tpsci: psci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 7 0x304>;\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t};\n\n\tversal_fpga: versal_fpga {\n\t\tcompatible = \"xlnx,versal-fpga\";\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t\tinterrupt-parent = <&gic>;\n\t\tu-boot,dm-pre-reloc;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\t\t\treg = <0 0xf9000000 0 0x80000>, /* GICD */\n\t\t\t <0 0xf9080000 0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\n\t\t\tgic_its: gic-its@f9020000 {\n\t\t\t\tcompatible = \"arm,gic-v3-its\";\n\t\t\t\tmsi-controller;\n\t\t\t\tmsi-cells = <1>;\n\t\t\t\treg = <0 0xf9020000 0 0x20000>;\n\t\t\t};\n\t\t};\n\n\t\tapm: performance-monitor@f0920000 {\n\t\t\tcompatible = \"xlnx,flexnoc-pm-2.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg-names = \"funnel\", \"baselpd\", \"basefpd\";\n\t\t\treg = <0x0 0xf0920000 0x0 0x1000>,\n\t\t\t <0x0 0xf0980000 0x0 0x9000>,\n\t\t\t <0x0 0xf0b80000 0x0 0x9000>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff060000 0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff070000 0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcci: cci@fd000000 {\n\t\t\tcompatible = \"arm,cci-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd000000 0 0x10000>;\n\t\t\tranges = <0 0 0xfd000000 0xa0000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcci_pmu: pmu@10000 {\n\t\t\t\tcompatible = \"arm,cci-500-pmu,r0\";\n\t\t\t\treg = <0x10000 0x90000>;\n\t\t\t\tinterrupts = <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>;\n\t\t\t};\n\t\t};\n\n\t\tlpd_dma_chan0: dma@ffa80000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa80000 0 0x1000>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa90000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa90000 0 0x1000>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffaa0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaa0000 0 0x1000>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\n\t\tlpd_dma_chan3: dma@ffab0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffab0000 0 0x1000>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffac0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffac0000 0 0x1000>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffad0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffad0000 0 0x1000>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffae0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffae0000 0 0x1000>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffaf0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaf0000 0 0x1000>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tgem0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0c0000 0 0x1000>;\n\t\t\tinterrupts = <0 56 4>, <0 56 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t/* iommus = <&smmu 0x234>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0d0000 0 0x1000>;\n\t\t\tinterrupts = <0 58 4>, <0 58 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t/* iommus = <&smmu 0x235>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tgpio0: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0b0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff020000 0 0x1000>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff030000 0 0x1000>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c2: i2c@f1000000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1000000 0 0x1000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tmc0: memory-controller@f6150000\t{\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <0>;\n\t\t};\n\n\t\tmc1: memory-controller@f62c0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <1>;\n\t\t};\n\n\t\tmc2: memory-controller@f6430000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <2>;\n\t\t};\n\n\t\tmc3: memory-controller@f65a0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <3>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tcalibration = <0x7FFF>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff000000 0 0x1000>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tserial1: serial@ff010000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff010000 0 0x1000>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd800000 0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 124 4>, <0 124 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,is-stig-pgm = <1>;\n\t\t\tcdns,trigger-address = <0xC0000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff040000 0 0x1000>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff050000 0 0x1000>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsysmon0: sysmon@f1270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\treg = <0x0 0xf1270000 0x0 0x4000>;\n\t\t\tinterrupts = <0 144 4>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\t\tsysmon1: sysmon@109270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x09270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tsysmon2: sysmon@111270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x11270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\t\tsysmon3: sysmon@119270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x19270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\t\tttc0: timer@ff0e0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff0f0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 40 4>, <0 41 4>, <0 42 4>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff100000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 46 4>, <0 47 4>, <0 48 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tusb0: usb@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff9d0000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_0: usb@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0 0xfe200000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"usb-wakeup\";\n\t\t\t\tinterrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\tsnps,mask_phy_reset;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\tcpm_pciea: pci@fca10000 {\n\t\t\t#address-cells = <3>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"xlnx,versal-cpm-host-1.00\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc_0 0>,\n\t\t\t\t\t<0 0 0 2 &pcie_intc_0 1>,\n\t\t\t\t\t<0 0 0 3 &pcie_intc_0 2>,\n\t\t\t\t\t<0 0 0 4 &pcie_intc_0 3>;\n\t\t\tinterrupt-map-mask = <0 0 0 7>;\n\t\t\tinterrupt-names = \"misc\";\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>,\n\t\t\t\t <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>;\n\t\t\tmsi-map = <0x0 &gic_its 0x0 0x10000>;\n\t\t\treg = <0x0 0xfca10000 0x0 0x1000>,\n\t\t\t <0x6 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"cpm_slcr\", \"cfg\";\n\t\t\tpcie_intc_0: pci-interrupt-controller {\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\tinterrupt-controller ;\n\t\t\t};\n\t\t};\n\n\t\twatchdog: watchdog@fd4d0000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd4d0000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 0x64 1>, <0 0x6D 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t};\n\t\txilsem_edac: edac@f2014050 {\n\t\t\tcompatible = \"xlnx,versal-xilsem-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf2014050 0x0 0xc4>;\n\t\t};\n\t};\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/versal-net/versal-net-ipp-rev1.9.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/power/xlnx-versal-net-power.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-net-ipp-1.9\", \"xlnx,versal-net-spp-5.0\", \"xlnx,versal-net-spp\", \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal NET SPP 5.0/IPP 1.9\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t};\n\t};\n\n\tmemory: memory@0 {\n\t\treg = <0 0 0 0x80000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tmmc0 = &sdhci1;\n\t\tmmc1 = &sdhci0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x01>;\n\t\t};\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t\tversal_net_reset: reset-controller {\n\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t#reset-cells = <1>;\n\t\t};\n\t};\n\n\tclk1: clk1 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <1000000>;\n\t};\n\n\tclk2_6: clk2_6 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <2670000>;\n\t};\n\n\tclk20: clk20 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <20000000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk60: clk60 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <60000000>;\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tadma0: dma-controller@ebd00000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd00000 0 0x1000>;\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tadma1: dma-controller@ebd10000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd10000 0 0x1000>;\n\t\t\tinterrupts = <0 73 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tadma2: dma-controller@ebd20000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd20000 0 0x1000>;\n\t\t\tinterrupts = <0 74 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tadma3: dma-controller@ebd30000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd30000 0 0x1000>;\n\t\t\tinterrupts = <0 75 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tadma4: dma-controller@ebd40000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd40000 0 0x1000>;\n\t\t\tinterrupts = <0 76 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tadma5: dma-controller@ebd50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd50000 0 0x1000>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tadma6: dma-controller@ebd60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd60000 0 0x1000>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tadma7: dma-controller@ebd70000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd70000 0 0x1000>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100>, <&clk100>;\n\t\t};\n\n\t\tcan0: can@f1980000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1980000 0 0x6000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&clk25>, <&clk25>;\n\t\t};\n\n\t\tcan1: can@f1990000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1990000 0 0x6000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&clk25>, <&clk25>;\n\t\t};\n\n\t\tgem0: ethernet@f19e0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19e0000 0 0x1000>;\n\t\t\tinterrupts = <0 39 4>, <0 39 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tclocks = <&clk2_6>, <&clk25>, <&clk25>, <&clk25>, <&clk25>;\n\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <11>;\n\t\t\t\tti,tx-internal-delay = <10>;\n\t\t\t\tti,fifo-depth = <1>;\n\t\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\t};\n\t\t};\n\n\t\tgem1: ethernet@f19f0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19f0000 0 0x1000>;\n\t\t\tinterrupts = <0 41 4>, <0 41 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy2>;\n\t\t\tphy-mode = \"rmii\";\n\t\t\tclocks = <&clk2_6>, <&clk25>, <&clk25>, <&clk25>, <&clk25>;\n\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t};\n\t\t};\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t};\n\n\t\tgpio0: gpio@f19d0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\treg = <0 0xf19d0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\t\ti2c0: i2c@f1940000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1940000 0 0x1000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\t\ti2c1: i2c@f1950000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1950000 0 0x1000>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\t\ti3c: i3c-master@f1948000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\treg = <0 0xf1948000 0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclocks = <&clk20>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 182 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,is-stig-pgm = <1>;\n\t\t\tcdns,trigger-address = <0xc0000000>;\n\t\t\tis-dual = <0>;\n\t\t\tis-stacked = <0>;\n\t\t\tclocks = <&clk20>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_OSPI>;\n\t\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\t\t\tmt35xu02g: flash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tcdns,read-delay = <0>;\n\t\t\t\tcdns,tshsl-ns = <0>;\n\t\t\t\tcdns,tsd2d-ns = <0>;\n\t\t\t\tcdns,tchsh-ns = <1>;\n\t\t\t\tcdns,tslch-ns = <1>;\n\t\t\t\tspi-tx-bus-width = <8>;\n\t\t\t\tspi-rx-bus-width = <8>;\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\tbroken-flash-reset;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"ospi-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"ospi-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 183 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tnum-cs = <1>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\t\t\tclocks = <&clk25>, <&clk25>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <10000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi0-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"qspi0-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupts = <0 200 4>, <0 201 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 184 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&clk20>, <&clk20>;\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 186 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&clk20>, <&clk20>;\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"arm,pl011\", \"arm,sbsa-uart\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&clk1>, <&clk1>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tsmmu: smmu@ec000000 {\n\t\t\tcompatible = \"arm,smmu-v3\";\n\t\t\treg = <0 0xec000000 0 0x40000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tinterrupt-names = \"combined\";\n\t\t\tinterrupts = <0 169 4>;\n\t\t};\n\n\t\tspi0: spi@f1960000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupts = <0 23 4>;\n\t\t\treg = <0 0xf1960000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>, <&clk25>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@f1970000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0 0xf1970000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>, <&clk25>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tttc0: timer@f1dc0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dc0000 0x0 0x1000>;\n\t\t\tclocks = <&clk1>, <&clk1>;\n\t\t};\n\n\t\tusb0: usb@f1e00000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0 0xf1e00000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tclocks = <&clk60>, <&clk60>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_0>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_0>;\n\t\t\txlnx,usb-polarity = <0>;\n\t\t\txlnx,usb-reset-mode = <0>;\n\n\t\t\tdwc3_0: dwc3@f1b00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0 0xf1b00000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 29 4>, <0 33 4>, <0 98 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,mask_phy_reset;\n\t\t\t\tdr_mode = \"peripheral\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@f1e10000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0x0 0xf1e10000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tclocks = <&clk60 &clk60>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_1>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_1>;\n\t\t\txlnx,usb-polarity = <0x00>;\n\t\t\txlnx,usb-reset-mode = <0x00>;\n\n\t\t\tdwc3_1: dwc3@f1c00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0x0 0xf1c00000 0x0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 34 4>, <0 38 4>, <0 99 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tsnps,mask_phy_reset;\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\twwdt0: watchdog@ecc10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xecc10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 139 1>, <0 140 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\t\twwdt1: watchdog@ecd10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xecd10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 143 1>, <0 144 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\t\twwdt2: watchdog@ece10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xece10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 147 1>, <0 148 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\t\twwdt3: watchdog@ecf10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xecf10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 164 1>, <0 165 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/zynq/zynq-7000.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\treplicator {\n\t\tcompatible = \"arm,coresight-static-replicator\";\n\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\tout-ports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\t/* replicator output ports */\n\t\t\tport@0 {\n\t\t\t\treg = <0>;\n\t\t\t\treplicator_out_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&tpiu_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tport@1 {\n\t\t\t\treg = <1>;\n\t\t\t\treplicator_out_port1: endpoint {\n\t\t\t\t\tremote-endpoint = <&etb_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tin-ports {\n\t\t\t/* replicator input port */\n\t\t\tport {\n\t\t\t\treplicator_in_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&funnel_out_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tamba: axi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocm: sram@fffc0000 {\n\t\t\tcompatible = \"mmio-sram\";\n\t\t\treg = <0xfffc0000 0x10000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n\t\t\tcompatible = \"xlnx,zynq-gem\", \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n\t\t\tcompatible = \"xlnx,zynq-gem\", \"cdns,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\", \"arm,primecell\";\n\t\t\treg = <0xe000e000 0x0001000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"apb_pclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */\n\t\t\t\t 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */\n\t\t\t\t 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tnfc0: nand-controller@0,0 {\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0 0 0x1000000>;\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t};\n\t\t\tnor0: flash@1,0 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <1 0 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tsdhci0: mmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: mmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n\t\tdmac_s: dmac@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t\t\"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <4>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\tetb@f8801000 {\n\t\t\tcompatible = \"arm,coresight-etb10\", \"arm,primecell\";\n\t\t\treg = <0xf8801000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\tetb_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ttpiu@f8803000 {\n\t\t\tcompatible = \"arm,coresight-tpiu\", \"arm,primecell\";\n\t\t\treg = <0xf8803000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\ttpiu_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tfunnel@f8804000 {\n\t\t\tcompatible = \"arm,coresight-static-funnel\", \"arm,primecell\";\n\t\t\treg = <0xf8804000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\t\t/* funnel output ports */\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tfunnel_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint =\n\t\t\t\t\t\t\t<&replicator_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tin-ports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\t/* funnel input ports */\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tfunnel0_in_port0: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm0_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tfunnel0_in_port1: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm1_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tfunnel0_in_port2: endpoint {\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t/* The other input ports are not connect to anything */\n\t\t\t};\n\t\t};\n\n\t\tptm@f889c000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889c000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu0>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm0_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889d000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889d000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu1>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm1_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/zynqmp/zynqmp-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-zynqmp-clk.h\"\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL0_REF>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL1_REF>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL2_REF>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL3_REF>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tdp_aclk: dp_aclk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&zynqmp_firmware {\n\tzynqmp_clk: clock-controller {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,\n\t\t\t <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\",\n\t\t\t \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t};\n};\n\n&can0 {\n\tclocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&can1 {\n\tclocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&cpu0 {\n\tclocks = <&zynqmp_clk ACPU>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gpu {\n\tclocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&nand0 {\n\tclocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gem0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>,\n\t\t <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>;\n};\n\n&gem1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>,\n\t\t <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>;\n};\n\n&gem2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>,\n\t\t <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>;\n};\n\n&gem3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>,\n\t\t <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>;\n};\n\n&gpio {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&i2c0 {\n\tclocks = <&zynqmp_clk I2C0_REF>;\n};\n\n&i2c1 {\n\tclocks = <&zynqmp_clk I2C1_REF>;\n};\n\n&perf_monitor_ocm {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&perf_monitor_ddr {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_cci {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_lpd {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&pcie {\n\tclocks = <&zynqmp_clk PCIE_REF>;\n};\n\n&qspi {\n\tclocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&sata {\n\tclocks = <&zynqmp_clk SATA_REF>;\n};\n\n&sdhci0 {\n\tclocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;\n\tassigned-clocks = <&zynqmp_clk SDIO0_REF>;\n};\n\n&sdhci1 {\n\tclocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;\n\tassigned-clocks = <&zynqmp_clk SDIO1_REF>;\n};\n\n&spi0 {\n\tclocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&spi1 {\n\tclocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart0 {\n\tclocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart1 {\n\tclocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&usb0 {\n\tclocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n\tassigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&dwc3_0 {\n\tclocks = <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&usb1 {\n\tclocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n\tassigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&dwc3_1 {\n\tclocks = <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&watchdog0 {\n\tclocks = <&zynqmp_clk WDT>;\n};\n\n&lpd_watchdog {\n\tclocks = <&zynqmp_clk LPD_WDT>;\n};\n\n&xilinx_ams {\n\tclocks = <&zynqmp_clk AMS_REF>;\n};\n\n&zynqmp_dpdma {\n\tclocks = <&zynqmp_clk DPDMA_REF>;\n\tassigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */\n};\n\n&zynqmp_dpsub {\n\tclocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>;\n\tassigned-clocks = <&zynqmp_clk DP_STC_REF>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */\n};\n\n&zynqmp_dp_snd_codec0 {\n\tclocks = <&zynqmp_clk DP_AUDIO_REF>;\n};\n\n&zynqmp_pcap {\n\tclocks = <&zynqmp_clk PCAP>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2022.2/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n#include \"include/dt-bindings/dma/xlnx-zynqmp-dpdma.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/power/xlnx-zynqmp-power.h\"\n#include \"include/dt-bindings/reset/xlnx-zynqmp-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: opp-table-cpu {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tzynqmp_ipi: zynqmp_ipi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t\txlnx,ipi-id = <0>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff990400 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\treg = <0x0 0xff9905c0 0x0 0x20>,\n\t\t\t <0x0 0xff9905e0 0x0 0x20>,\n\t\t\t <0x0 0xff990e80 0x0 0x20>,\n\t\t\t <0x0 0xff990ea0 0x0 0x20>;\n\t\t\treg-names = \"local_request_region\",\n\t\t\t\t \"local_response_region\",\n\t\t\t\t \"remote_request_region\",\n\t\t\t\t \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <4>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tzynqmp_firmware: zynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x1>;\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tnvmem_firmware {\n\t\t\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tsoc_revision: soc_revision@0 {\n\t\t\t\t\treg = <0x0 0x4>;\n\t\t\t\t};\n\t\t\t\t/* efuse access */\n\t\t\t\tefuse_dna: efuse_dna@c {\n\t\t\t\t\treg = <0xc 0xc>;\n\t\t\t\t};\n\t\t\t\tefuse_usr0: efuse_usr0@20 {\n\t\t\t\t\treg = <0x20 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr1: efuse_usr1@24 {\n\t\t\t\t\treg = <0x24 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr2: efuse_usr2@28 {\n\t\t\t\t\treg = <0x28 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr3: efuse_usr3@2c {\n\t\t\t\t\treg = <0x2c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr4: efuse_usr4@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr5: efuse_usr5@34 {\n\t\t\t\t\treg = <0x34 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr6: efuse_usr6@38 {\n\t\t\t\t\treg = <0x38 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr7: efuse_usr7@3c {\n\t\t\t\t\treg = <0x3c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_miscusr: efuse_miscusr@40 {\n\t\t\t\t\treg = <0x40 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_chash: efuse_chash@50 {\n\t\t\t\t\treg = <0x50 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_pufmisc: efuse_pufmisc@54 {\n\t\t\t\t\treg = <0x54 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_sec: efuse_sec@58 {\n\t\t\t\t\treg = <0x58 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_spkid: efuse_spkid@5c {\n\t\t\t\t\treg = <0x5c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_ppk0hash: efuse_ppk0hash@a0 {\n\t\t\t\t\treg = <0xa0 0x30>;\n\t\t\t\t};\n\t\t\t\tefuse_ppk1hash: efuse_ppk1hash@d0 {\n\t\t\t\t\treg = <0xd0 0x30>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tzynqmp_pcap: pcap {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t\t\t\tclock-names = \"ref_clk\";\n\t\t\t};\n\n\t\t\txlnx_aes: zynqmp-aes {\n\t\t\t\tcompatible = \"xlnx,zynqmp-aes\";\n\t\t\t};\n\n\t\t\tzynqmp_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\txlnx_keccak_384: sha384 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-keccak-384\";\n\t\t\t};\n\n\t\t\txlnx_rsa: zynqmp-rsa {\n\t\t\t\tcompatible = \"xlnx,zynqmp-rsa\";\n\t\t\t};\n\n\t\t\tmodepin_gpio: gpio {\n\t\t\t\tcompatible = \"xlnx,zynqmp-gpio-modepin\";\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&zynqmp_pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t};\n\n\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma-controller@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma-controller@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma-controller@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma-controller@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma-controller@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma-controller@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma-controller@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma-controller@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x0 0x10000>,\n\t\t\t <0x0 0xf9020000 0x0 0x20000>,\n\t\t\t <0x0 0xf9040000 0x0 0x20000>,\n\t\t\t <0x0 0xf9060000 0x0 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"arm,mali-400\", \"arm,mali-utgard\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"IRQGP\", \"IRQGPMMU\", \"IRQPP0\", \"IRQPPMMU0\", \"IRQPP1\", \"IRQPPMMU1\";\n\t\t\tclock-names = \"gpu\", \"gpu_pp0\", \"gpu_pp1\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPU>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma-controller@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma-controller@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma-controller@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma-controller@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma-controller@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma-controller@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma-controller@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma-controller@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand-controller@ff100000 {\n\t\t\tcompatible = \"xlnx,zynqmp-nand-controller\", \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"controller\", \"bus\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_NAND>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gem\", \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_0>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gem\", \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_1>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gem\", \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_2>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gem\", \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_3>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPIO>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tperf_monitor_ocm: perf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa00000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_ddr: perf-monitor@fd0b0000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd0b0000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <6>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <10>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_cci: perf-monitor@fd490000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd490000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_lpd: perf-monitor@ffa10000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa10000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tiommus = <&smmu 0x4d0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_PCIE>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_QSPI>;\n\t\t};\n\n\t\tpsgtr: phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\";\n\t\t\t#phy-cells = <4>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x7FFF>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SATA>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SATA>;\n\t\t/*\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;*/\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <0>;\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_0>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\txlnx,device_id = <1>;\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-uart\", \"cdns,uart-r1p12\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-uart\", \"cdns,uart-r1p12\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_1>;\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_0>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\t\t\treset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tranges;\n\n\t\t\tdwc3_0: usb@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>, <0 75 4>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-reset-on-resume;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t\t/* snps,enable-hibernation; */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb1@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_1>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\n\t\t\tranges;\n\n\t\t\tdwc3_1: usb@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>, <0 76 4>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n\t\t\t\tsnps,xhci-reset-on-resume;\n\t\t\t\tsnps,xhci-stream-quirk;\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <60>;\n\t\t\treset-on-timeout;\n\t\t};\n\n\t\tlpd_watchdog: watchdog@ff150000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 52 1>;\n\t\t\treg = <0x0 0xff150000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges;\n\n\t\t\tams_ps: ams_ps@ffa50800 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50800 0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@ffa50c00 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xffa50c00 0x0 0x400>;\n\t\t\t};\n\t\t};\n\n\t\tzynqmp_dpdma: dma-controller@fd4c0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tdma-channels = <6>;\n\t\t\tiommus = <&smmu 0xce4>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tzynqmp_dpaud_setting: dp_aud@fd4ac000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpaud-setting\", \"syscon\";\n\t\t\treg = <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t};\n\n\t\tzynqmp_dpsub: display@fd4a0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>;\n\t\t\treg-names = \"dp\", \"blend\", \"av_buf\";\n\t\t\txlnx,dpaud-reg = <&zynqmp_dpaud_setting>;\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tiommus = <&smmu 0xce3>;\n\t\t\tclock-names = \"dp_apb_clk\", \"dp_aud_clk\", \"dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_DP>;\n\t\t\tdma-names = \"vid0\", \"vid1\", \"vid2\", \"gfx0\";\n\t\t\tdmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;\n\n\t\t\t/* dummy node to to indicate there's no child i2c device */\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm0\";\n\t\t\t\tdmas = <&zynqmp_dpdma 4>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm1\";\n\t\t\t\tdmas = <&zynqmp_dpdma 5>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card0: zynqmp_dp_snd_card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,\n\t\t\t\t\t\t <&zynqmp_dp_snd_pcm1>;\n\t\t\t\txlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/ac701-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/ac701-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n i2c0 = &i2c1;\n rtc0 = &rtc;\n serial0 = &uart1;\n serial1 = &uart0;\n serial2 = &dcc;\n spi0 = &spi0;\n spi1 = &spi1;\n usb0 = &usb0;\n usb1 = &usb1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n\n\tsi5335_0: si5335_0 { /* clk0_usb - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5335_1: si5335_1 { /* clk1_dp - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 IRQ_TYPE_LEVEL_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO3\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO2\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO1\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n};\n\n&psgtr {\n\t/* usb3, dp */\n\tclocks = <&si5335_0>, <&si5335_1>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n\t/delete-property/ reset-gpios;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"super-speed\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n\treset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/kc705-full.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/kc705-lite.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/kcu105-tmr.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105-tmr.\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&tmr_0_MB1_axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/kcu105.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\ni * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/sp701-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze sp701.\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@1 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x3>;\n\t\t\tti,tx-internal-delay = <0x3>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/vcu118-rev2.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze vcu118\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-property/ pcs-handle ;\n\t/delete-property/ managed ;\n\t/delete-property/ xlnx,switch-x-sgmii ;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@3 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\tti,sgmii-ref-clock-output-enable;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\treg = <3>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-a2197-sc-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller RevA\";\n\tcompatible = \"xlnx,versal-sc-revA\", \"xlnx,versal-sc\", \"xlnx,zynqmp\";\n\n\t/* SC Bank 43\n\tFIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS\n\tSYSCTLR_GPIO0 - 5 - conneced to versal */\n\t/* cpu thermal for MAX6643 fan control */\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tdc38_led {\n\t\t\tlabel = \"ds38-green\"; /* sc AB11 500_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc37_led {\n\t\t\tlabel = \"ds37-green\"; /* sc AD10 501_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc36_led {\n\t\t\tlabel = \"ds36-green\"; /* sc AD11 502_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t};\n};\n\n/* usb - type C - pl\n and micro usb 2.0, gt\n*/\n/* Feb 28/2019 version */\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n/* TODO\nUSB0 MIO52-63\nUSB1 MIO64-75\n*/\n\n/*eth MDIO 76/77\neth reset MIO42\nmarwell m88e1512 - SGMII */\n&gem0 {\n\tphy-handle = <&phy0>;\n\t/* phy-mode = \"sgmii\"; DTG generates this properly */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: phy@21 {\n\t\treg = <21>; /* FIXME */\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5- 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 0 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\"; /* FIXME no linux driver */\n\t\t\t\treg = <0xc0>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <10000000>; /* 10 ohm */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\ti2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* FIXME connection to Samtec J212D */\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t/* FIXME connection to Samtec J53C */\n\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@5d { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@5d { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@5d { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"LPDDR4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-emu-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-emu-itr8\", \"xlnx,versal-emu\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal EMU ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:9600\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n\n\tclk0212: clk0212 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <212000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n};\n\n&timer {\n clock-frequency = <440000>;\n};\n\n&serial0 {\n status = \"okay\";\n clocks = <&clk0212 &clk0212>;\n\tcurrent-speed = <9600>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-emu-rev1.9.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tcompatible = \"xlnx,versal-net-emu-1.9\", \"xlnx,versal-net-emu\";\n\tmodel = \"Xilinx Versal NET EMU 1.9\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t};\n\t};\n\n\tmemory: memory@0 {\n\t\treg = <0 0 0 0x10000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 rdinit=/bin/sh\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tfirmware {\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tclk1: clk1 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <1000000>; /* it doesn't matter on EMU */\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&clk1>, <&clk1>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-ipp-rev1.9-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET IPP/SPP OSPI\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-net-ipp-rev1.9.dtsi\"\n\n/ {\n\tmodel = \"Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI\";\n};\n\n&ospi {\n\tstatus = \"okay\";\n};\n\n&qspi {\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-ipp-rev1.9.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/clock/xlnx-versal-net-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-net-power.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-net-ipp-1.9\", \"xlnx,versal-net-spp-5.0\", \"xlnx,versal-net-spp\", \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal NET SPP 5.0/IPP 1.9\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t};\n\t};\n\n\tmemory: memory@0 {\n\t\treg = <0 0 0 0x80000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tref_clk: ref_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x01>;\n\n\t\t\tversal_net_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-net-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupts = <0 57 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t<&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupts = <0 57 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@eb3f0440 {\n\t\t\treg = <0 0xeb3f0440 0 0x20>,\n\t\t\t <0 0xeb3f0460 0 0x20>,\n\t\t\t <0 0xeb3f0280 0 0x20>,\n\t\t\t <0 0xeb3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tadma0: dma-controller@ebd00000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd00000 0 0x1000>;\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_0>;\n\t\t};\n\n\t\tadma1: dma-controller@ebd10000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd10000 0 0x1000>;\n\t\t\tinterrupts = <0 73 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_1>;\n\t\t};\n\n\t\tadma2: dma-controller@ebd20000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd20000 0 0x1000>;\n\t\t\tinterrupts = <0 74 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_2>;\n\t\t};\n\n\t\tadma3: dma-controller@ebd30000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd30000 0 0x1000>;\n\t\t\tinterrupts = <0 75 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_3>;\n\t\t};\n\n\t\tadma4: dma-controller@ebd40000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd40000 0 0x1000>;\n\t\t\tinterrupts = <0 76 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_4>;\n\t\t};\n\n\t\tadma5: dma-controller@ebd50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd50000 0 0x1000>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_5>;\n\t\t};\n\n\t\tadma6: dma-controller@ebd60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd60000 0 0x1000>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_6>;\n\t\t};\n\n\t\tadma7: dma-controller@ebd70000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd70000 0 0x1000>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_7>;\n\t\t};\n\n\t\tcan0: can@f1980000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1980000 0 0x6000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>;\n\t\t};\n\n\t\tcan1: can@f1990000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1990000 0 0x6000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>;\n\t\t};\n\n\t\tgem0: ethernet@f19e0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19e0000 0 0x1000>;\n\t\t\tinterrupts = <0 39 4>, <0 39 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>,\n\t\t\t\t <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_0>;\n\t\t\tmdio0: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\t\t#phy-cells = <1>;\n\t\t\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t\tti,rx-internal-delay = <11>;\n\t\t\t\t\tti,tx-internal-delay = <10>;\n\t\t\t\t\tti,fifo-depth = <1>;\n\t\t\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgem1: ethernet@f19f0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19f0000 0 0x1000>;\n\t\t\tinterrupts = <0 41 4>, <0 41 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy2>;\n\t\t\tphy-mode = \"rmii\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>,\n\t\t\t\t <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_1>;\n\t\t\tmdio1: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\t\tcompatible = \"ethernet-phy-id0007.0762\"; /* Vitesse VSC8540 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t};\n\n\t\tgpio0: gpio@f19d0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\treg = <0 0xf19d0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO>;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk PMC_LSBUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>;\n\t\t};\n\n\t\ti2c0: i2c@f1940000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1940000 0 0x1000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C0_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@f1950000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1950000 0 0x1000>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C1_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n\t\t};\n\n\t\ti3c: i3c-master@f1948000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\treg = <0 0xf1948000 0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclocks = <&versal_net_clk I2C_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_PMC>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 182 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,trigger-address = <0xc0000000>;\n\t\t\tis-dual = <0>;\n\t\t\tis-stacked = <0>;\n\t\t\tclocks = <&versal_net_clk OSPI_REF>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_OSPI>;\n\t\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\t\t\tmt35xu02g: flash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tcdns,read-delay = <0>;\n\t\t\t\tcdns,tshsl-ns = <0>;\n\t\t\t\tcdns,tsd2d-ns = <0>;\n\t\t\t\tcdns,tchsh-ns = <1>;\n\t\t\t\tcdns,tslch-ns = <1>;\n\t\t\t\tspi-tx-bus-width = <8>;\n\t\t\t\tspi-rx-bus-width = <8>;\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\tbroken-flash-reset;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"ospi-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"ospi-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 183 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tnum-cs = <2>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\t\t\tclocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_QSPI>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>, <1>;\n\t\t\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <10000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi0-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"qspi0-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupts = <0 200 4>, <0 201 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 184 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_1>;\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 186 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_0>;\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_UART_0>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tsmmu: smmu@ec000000 {\n\t\t\tcompatible = \"arm,smmu-v3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xec000000 0 0x40000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tinterrupt-names = \"combined\";\n\t\t\tinterrupts = <0 169 4>;\n\t\t};\n\n\t\tspi0: spi@f1960000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupts = <0 23 4>;\n\t\t\treg = <0 0xf1960000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_0>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@f1970000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0 0xf1970000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_1>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tttc0: timer@f1dc0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dc0000 0x0 0x1000>;\n\t\t\tclocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_TTC_0>;\n\t\t};\n\n\t\tusb0: usb@f1e00000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0 0xf1e00000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t/* clocks = <&clk60>, <&clk60>; */\n\t\t\tclocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_0>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_0>;\n\n\t\t\tdwc3_0: dwc3@f1b00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0 0xf1b00000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 29 4>, <0 33 4>, <0 98 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"peripheral\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@f1e10000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0x0 0xf1e10000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tclocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_1>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_1>;\n\n\t\t\tdwc3_1: dwc3@f1c00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0x0 0xf1c00000 0x0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 34 4>, <0 38 4>, <0 99 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\twwdt0: watchdog@ecc10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xecc10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 139 1>, <0 140 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>;\n\t\t};\n\n\t\twwdt1: watchdog@ecd10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xecd10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 143 1>, <0 144 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>;\n\t\t};\n\n\t\twwdt2: watchdog@ece10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xece10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 147 1>, <0 148 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>;\n\t\t};\n\n\t\twwdt3: watchdog@ecf10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xecf10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 164 1>, <0 165 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-vn-p-b2197-00-reva-pl.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VN-P-B2197 (Tenzing2)\n *\n * (C) Copyright 2022, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n\ti2c-mux@70 {\n\t\tcompatible = \"nxp,pca9545\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x70>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tqsfp56g_0: gpio@20 { /* u118 */\n\t\t\t\tcompatible = \"ti,tca6408\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"QSFP56G_0_OC_B\", \"QSFP56G_0_PWR_EN\", /* 0, 1 */\n\t\t\t\t\t\t\"QSFP56G_0_LED_1\", \"QSFP56G_0_LED_0\", /* 2, 3 */\n\t\t\t\t\t\t\"QSFP56G_0_MODPRS_B\", \"QSFP56G_0_LPMODE\", /* 4, 5 */\n\t\t\t\t\t\t\"QSFP56G_0_RESET_B\", \"QSFP56G_0_MODSEL_B\"; /* 6, 7 */\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tqsfp56g_1: gpio@20 { /* u117 */\n\t\t\t\tcompatible = \"ti,tca6408\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"QSFP56G_1_OC_B\", \"QSFP56G_1_PWR_EN\", /* 0, 1 */\n\t\t\t\t\t\t\"QSFP56G_1_LED_1\", \"QSFP56G_1_LED_0\", /* 2, 3 */\n\t\t\t\t\t\t\"QSFP56G_1_MODPRS_B\", \"QSFP56G_1_LPMODE\", /* 4, 5 */\n\t\t\t\t\t\t\"QSFP56G_1_RESET_B\", \"QSFP56G_1_MODSEL_B\"; /* 6, 7 */\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* J48 connector */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* J47 connector */\n\t\t};\n\t};\n/*\n\tGPIO_DIP_SW0-1\n\tGPIO_LED0-1\n\tGPIO_PB0-1\n\tGPIO_SMA\n\n*/\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-vn-p-b2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2)\n *\n * (C) Copyright 2022, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"versal-net.dtsi\"\n#include \"versal-net-clk-ccf.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-net-vn-p-b2197-00-revA\",\n\t\t \"xlnx,versal-net-vn-p-b2197-00\", \"xlnx,versal-net\";\n};\n\n&i2c0 {\n\t/* Access via J70/J71 or J82/J83 */\n\tclock-frequency = <100000>;\n};\n\n&i2c1 {\n\t/* Access via J70/J71 or J82/J83 */\n\t/* By default this bus should have eeprom for board identification at 0x54 */\n\t/* SE/X-PRC card identification is also on this bus at 0x52 */\n\tclock-frequency = <100000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-spp-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-spp-itr8-cn13940875\", \"xlnx,versal-spp-itr8\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal SPP ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &ospi;\n\t\tspi2 = &spi0;\n\t\tspi3 = &spi1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tusb0 = &usb0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>;\n\t};\n\tchosen {\n\t\tbootargs = \"rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n};\n\n&timer {\n\tclock-frequency = <2720000>;\n};\n\n&serial0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tmaximum-speed = \"high-speed\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n phy0: phy@0 {\n\t\treg = <0x0>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n phy1: phy@1 {\n\t\treg = <0x1>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <0x1>;\n\treg = <0x0 0xf1030000 0x0 0x1000>;\n\tclocks = <&clk125 &clk125>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot-boot.bin\";\n\t\t\t\treg = <0x0 0x6400000>;\n\t\t\t};\n\t\t\tpartition@6400000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x6400000 0x500000>;\n\t\t\t};\n\t\t\tpartition@6900000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x6900000 0x20000>;\n\t\t\t};\n\t\t\tpartition@6920000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x6920000 0x5E0000>;\n\t\t\t};\n\t\t\tpartition@7f40000 {\n\t\t\t\tlabel = \"qspi-bootenv\";\n\t\t\t\treg = <0x7f40000 0x40000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ospi {\n\tstatus = \"disabled\";\n\tclocks = <&clk125 &clk125>;\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\tcdns,fifo-depth = <508>;\n\tcdns,fifo-width = <4>;\n\tcdns,is-dma = <1>;\n\tcdns,trigger-address = <0x00000000>;\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t};\n\t\t\tpartition@600000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t};\n\t\t\tpartition@620000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <1>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <3>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\treg = <0x0 0x84000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-v350-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal v350 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-v350-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal v350 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tspi0 = &ospi;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&serial1 {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-01 revA OSPI\";\n\n\taliases {\n\t\tspi0 = &ospi;\n\t};\n};\n\n/* Mutually exclusive */\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\treset-names = \"qspi\";\n\tresets = <&versal_reset VERSAL_RST_OSPI>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&qspi {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n compatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n \"xlnx,versal-vc-p-a2197-00\",\n \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n model = \"Xilinx Versal A2197 Processor board revA\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tgpio0 = &gpio;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-01 revA QSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-02 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem0 {\n\tphy-handle = <&phy0>; /* u9 */\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@1 { /* Marvell 88E1512; U9 */\n\t\treg = <1>;\n\t};\n};\n\n&sdhci0 {\n\txlnx,mio-bank = <1>;\n};\n\n&sdhci1 { /* U1A */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n\n&dwc3_0 { /* U4 */\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"high-speed\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* U12 Catalyst EEPROM - AT24 should be equivalent */\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U13 and U15 */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U18 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <3>;\t/* FIXME - check SPI1_SS0-2_B */\n\n\tflash@0 { /* U19 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst26vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-03 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tserial0 = &serial0;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* Must be enabled via J90/J91 */\n\teeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 64Mb */\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x800000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* J99 MIO28 - MIO33 */\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U6 - IS25LQ032B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lq032b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi\"\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tspi0 = &ospi;\n\t};\n};\n\n&qspi {\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-04 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <2>;\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tis-dual = <0>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 512MB */\n\t\treg = <0>, <1>;\n\t\tstacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x20000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n#include \"include/dt-bindings/net/mscc-phy-vsc8531.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-05 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem0 {\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 { /* 88e1510 */\n\t\treg = <1>;\n\t};\n\tphy2: phy@2 { /* VSC8531 */\n\t\treg = <2>;\n\t\tvsc8531,rx-delay = ;\n\t\tvsc8531,tx-delay = ;\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>;\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tspi-tx-bus-width = <4>;\n\tspi-rx-bus-width = <4>;\n\n\tflash@0 { /* MX25U12835 128Mbit */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 16MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <104000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x1000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc0 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n};\n\n&sdhci1 { /* connector */\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA\";\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 {\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-01-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-01-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (QSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-02-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-02-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (EMMC)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-03-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-03-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (OSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva-x-ebm-01-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-01-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (QSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva-x-ebm-02-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-02-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (EMMC)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva-x-ebm-03-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-03-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (OSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck5000-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck5000 revA\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vck5000-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck5000 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tspi0 = &ospi;\n\t};\n\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x10000000>;\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&serial1 {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vek280-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VEK280 revA\n *\n * (C) Copyright 2022, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vek280-revA\", \"xlnx,versal-vek280\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vek280 Eval board revA\";\n\n\tmemory: memory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* VADJ_FMC_EN - LPD MIO23 */\n/* FAN - LPD MIO21/22 */\n/* VCC_PL_EN - LPD MIO20 */\n/* PCIE_PERST - LPD MIO18/19 */\n/* SD_BUSPWR - PMC MIO51 */\n/* PCIE_WAKE - PMC MIO50 */\n/* VCCPSLP_EN - PMC MIO49 */\n/* I2C SYSMON - PMC MIO39 - 41 */\n/* PCIE_PWRBRK - PMC MIO38 */\n/* ZU4_TRIGGER - PMC MIO37 */\n/* VCC_AUX_1V2 - MIO11 */\n\n&ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = ;\n\t\t\tti,tx-internal-delay = ;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vek280-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VEK280 revB\n *\n * (C) Copyright 2022, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vek280-revB\", \"xlnx,versal-vek280\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vek280 Eval board revB\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* VADJ_FMC_EN - LPD MIO23 */\n/* FAN - LPD MIO21/22 */\n/* VCC_PL_EN - LPD MIO20 */\n/* PCIE_PERST - LPD MIO18/19 */\n/* SD_BUSPWR - PMC MIO51 */\n/* PCIE_WAKE - PMC MIO50 */\n/* VCCPSLP_EN - PMC MIO49 */\n/* I2C SYSMON - PMC MIO39 - 41 */\n/* PCIE_PWRBRK - PMC MIO38 */\n/* ZU4_TRIGGER - PMC MIO37 */\n/* VCC_AUX_1V2 - MIO11 */\n\n&ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@1 { /* u198 - ADI1300 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id0283.bc30\";\n\t\t\treg = <1>;\n\t\t adi,rx-internal-delay-ps = <2000>;\n\t\t\tadi,tx-internal-delay-ps = <2000>;\n\t\t\tadi,fifo-depth-bits = <8>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t\treset-assert-us = <10>;\n\t\t\treset-deassert-us = <5000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vhk158-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VHK158 revA\n *\n * (C) Copyright 2022-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vhk158-revA\", \"xlnx,versal-vhk158\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vhk158 Eval board revA\";\n\n\tmemory: memory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* ZU4_TRIGGER - PMC MIO37 */\n/* PCIE_PWRBRK - PMC MIO38 */\n/* I2C SYSMON - PMC MIO39 - 41 */\n/* VCCPSLP_EN - PMC MIO49 */\n/* PCIE_WAKE - PMC MIO50 */\n/* SOC_EN - LPD MIO13 */\n/* PSFP_EN - LPD MIO15 */\n/* AUX_1V2_EN - LPD MIO16 */\n/* HBM_EN - LPD MIO17 */\n/* PCIE_PERST - LPD MIO18/19 */\n/* VCC_PL_EN - LPD MIO20 */\n/* FAN - LPD MIO21/22 */\n/* VADJ_FMC_EN - LPD MIO23 */\n\n&ospi { /* PMC MIO0 - 12, U297 MT35XU02G */\n\tstatus = \"okay\";\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = ;\n\t\t\tti,tx-internal-delay = ;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-virt.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Venkatesh Yadav Abbarapu \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-virt\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal Virtual\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tclk2: clk2 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <2670000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t\tclock-frequency = <2720000>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */\n\t\t\t <0x0 0xf9080000 0x0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x1 0x9 4>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x2>;\n\t\tranges;\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff060000 0x0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff070000 0x0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom1: eeprom@53 {\n\t\t\t\treg = <0x53>;\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t};\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom2: eeprom@55 {\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x55>;\n\t\t\t};\n\t\t};\n\n\t\tgpio: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tethernet0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 56 4>, <0x0 56 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy0: phy@0 {\n\t\t\t\treg = <0x0>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tethernet1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 58 4>, <0x0 58 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy1: phy@1 {\n\t\t\t\treg = <0x1>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xf12a0000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tnum-cs = <0x1>;\n\t\t\treg = <0x0 0xf1030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"n25q512a\", \"micron,m25p80\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-tx-bus-width = <4>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <108000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@100000 {\n\t\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@600000 {\n\t\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@620000 {\n\t\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <1>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <3>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0x0 0x84000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\treg = <0x0 0xf1040000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\treg = <0x0 0xf1050000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\t#address-cells = <0x2>;\n\t\t\t#size-cells = <0x2>;\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tranges;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125 &clk125>;\n\n\t\t\tdwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x10000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = ðernet0;\n\t\tethernet1 = ðernet1;\n\t\tqspi = &qspi;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1 (QSPI)\";\n};\n\n&qspi {\n#include \"versal-x-ebm-01-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-02-revA\",\n\t\t \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1 (EMMC)\";\n};\n\n&sdhci1 {\n#include \"versal-x-ebm-02-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-03-revA\",\n \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board rev1.1 (OSPI)\";\n};\n\n&ospi {\n#include \"versal-x-ebm-03-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-01-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (QSPI)\";\n};\n\n&qspi {\n#include \"versal-x-ebm-01-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-02-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (EMMC)\";\n};\n\n&sdhci1 {\n#include \"versal-x-ebm-02-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-03-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (OSPI)\";\n\n aliases {\n spi0 = &ospi;\n };\n};\n\n&ospi {\n#include \"versal-x-ebm-03-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tphy2: ethernet-phy@2 { /* u134 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <2>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 49 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vp-x-a2785-00 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vp-x-a2785-00 Eval board revA\";\n\tcompatible = \"xlnx,versal-vp-x-a2785-00-revA\",\n\t\t \"xlnx,versal-vp-x-a2785-00\", \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tstatus = \"okay\"; /* u93 and u92 */\n\tnum-cs = <2>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\tstatus = \"okay\";\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk120 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk120 Eval board revA\";\n\tcompatible = \"xlnx,versal-vpk120-revA\", \"xlnx,versal-vpk120\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <2>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk120-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk120 revB\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk120 Eval board revB\";\n\tcompatible = \"xlnx,versal-vpk120-revB\", \"xlnx,versal-vpk120\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <2>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\t/* Use for storing information about board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk180 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk180 Eval board revA\";\n\tcompatible = \"xlnx,versal-vpk180-revA\", \"xlnx,versal-vpk180\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <2>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\n\t/* Use for storing information about board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tu-boot,dm-pre-reloc;\n\t};\n};\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio0 {\n\t/* FIXME Fill names when versal starts */\n};\n\n&gpio1 {\n\t/* FIXME Fill names when versal starts */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-01 revA for vck190/vmk180\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\nnum-cs = <2>;\nspi-tx-bus-width = <4>;\nspi-rx-bus-width = <4>;\n#address-cells = <1>;\n#size-cells = <0>;\nis-dual = <1>;\nflash@0 {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 256MB */\n\treg = <0>, <1>;\n\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\tspi-tx-bus-width = <4>;\n\tspi-rx-bus-width = <4>;\n\tspi-max-frequency = <150000000>;\n\tpartition@0 {\n\t\tlabel = \"spi0-flash0\";\n\t\treg = <0x0 0x10000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-02 revA for vck190/vmk180\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/* emmc MIO 0-13 - MTFC8GAKAJCN */\nnon-removable;\ndisable-wp;\nbus-width = <8>;\nxlnx,mio-bank = <0>;\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-03 revA for vck190/vmk180\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-resets.h\"\n/* U97 MT35XU02G */\ncompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\nbus-num = <2>;\nnum-cs = <1>;\n#address-cells = <1>;\n#size-cells = <0>;\nreset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\nflash@0 {\n\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\treg = <0>;\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcdns,read-delay = <0x0>;\n\tcdns,tshsl-ns = <0x0>;\n\tcdns,tsd2d-ns = <0x0>;\n\tcdns,tchsh-ns = <0x1>;\n\tcdns,tslch-ns = <0x1>;\n\tspi-tx-bus-width = <8>;\n\tspi-rx-bus-width = <8>;\n\tspi-max-frequency = <20000000>;\n\tpartition@0 {\n\t\tlabel = \"spi0-flash0\";\n\t\treg = <0x0 0x8000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n\n\t aliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n rtc0 = &rtc;\n serial0 = &uart0;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tclock_si5338_0: clk27 {\t/* u55 SI5338-GM */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tclock_si5338_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_si5338_3: clk150 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <150000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&psgtr {\n\tstatus = \"okay\";\n\t/* dp, usb3, sata */\n\tclocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem2;\n i2c0 = &i2c0;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n spi0 = &spi0;\n spi1 = &spi1;\n usb0 = &usb1;\n };\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: ethernet-phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"soft\";\n\t\tnand-ecc-algo = \"bch\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-0\";\n\t\tnand-ecc-step-size = <1024>;\n\t\tnand-ecc-strength = <24>;\n\t\tnand-on-flash-bbt;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"soft\";\n\t\tnand-ecc-algo = \"bch\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-1\";\n\t\tnand-ecc-step-size = <1024>;\n\t\tnand-ecc-strength = <24>;\n\t\tnand-on-flash-bbt;\n\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: flash@0 {\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: flash@0 {\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n serial0 = &uart1;\n spi0 = &qspi;\n mmc0 = &sdhci0;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n switch-14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n switch-13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 0>;\n\tsda-gpios = <&gpio0 51 0>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@34 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x34>;\n\t\t\t};\n\t\t\thwmon@35 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\thwmon@36 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n serial0 = &uart1;\n spi0 = &qspi;\n mmc0 = &sdhci0;\n };\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&watchdog0 {\n\treset-on-timeout;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu100-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio-bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu100-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\t aliases {\n i2c0 = &i2c1;\n rtc0 = &rtc;\n serial0 = &uart1;\n serial1 = &uart0;\n serial2 = &dcc;\n spi0 = &spi0;\n spi1 = &spi1;\n usb0 = &usb0;\n usb1 = &usb1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n led-vbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n\n\tsi5335_0: si5335_0 { /* clk0_usb - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5335_1: si5335_1 { /* clk1_dp - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 IRQ_TYPE_LEVEL_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO3\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO2\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO1\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* usb3, dp */\n\tclocks = <&si5335_0>, <&si5335_1>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n\t/delete-property/ reset-gpios;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"super-speed\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n\treset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zcu102-revb.dtsi\"\n\n/ {\n model = \"ZynqMP ZCU102 Rev1.0\";\n compatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n};\n\n&eeprom {\n #address-cells = <1>;\n #size-cells = <1>;\n\n board_sn: board-sn@0 {\n reg = <0x0 0x14>;\n };\n\n eth_mac: eth-mac@20 {\n reg = <0x20 0x6>;\n };\n\n board_name: board-name@d0 {\n reg = <0xd0 0x6>;\n };\n\n board_revision: board-revision@e0 {\n reg = <0xe0 0x3>;\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@21 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <21>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_4: out@4 {\n\t\t\t\t\t/* refclk4 for PS-GT, used for PCIE slot */\n\t\t\t\t\treg = <4>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 for PS-GT, used for PCIE */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* pcie, sata, usb3, dp */\n\tclocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\t/*\n\t * 1.0 revision has level shifter and this property should be\n\t * removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zcu102-reva.dtsi\"\n\n/ {\n model = \"ZynqMP ZCU102 RevB\";\n compatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n};\n\n&gem3 {\n phy-handle = <&phyc>;\n\tmdio: mdio {\n\t\tphyc: ethernet-phy@c {\n\t\t\t#phy-cells = <0x1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t/* Cleanup from RevA */\n\t\t/delete-node/ ethernet-phy@21;\n };\n};\n\n/* Fix collision with u61 */\n&i2c0 {\n i2c-mux@75 {\n i2c@2 {\n max15303@1b { /* u8 */\n compatible = \"maxim,max15303\";\n reg = <0x1b>;\n };\n /delete-node/ max15303@20;\n };\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* 8T49N287 - u182 */\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@20 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu104-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revC\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;\n\t};\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - IRPS5401_ALERT_B\n\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t * 2 - MAX6643_OT_B\n\t\t * 3 - MAX6643_FANFAIL_B\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t * 4, 10 - 17 - not connected\n\t\t */\n\t};\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* 8T49N287 - u182 */\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tu183: ina226@40 { /* u183 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 4, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\txlnx,mio-bank = <1>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\treg = <0xc>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\n\tina226-u67 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;\n\t};\n\tina226-u59 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n\tina226-u69 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;\n\t};\n\tina226-u66 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;\n\t};\n\tina226-u71 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u73 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tu67: ina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u67\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu59: ina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u59\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu61: ina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu60: ina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu64: ina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu69: ina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u69\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu66: ina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u66\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu63: ina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu3: ina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u3\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu71: ina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u71\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu73: ina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u73\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u57 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SI5382 - u48 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection FIXME */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, dp, usb3, sata */\n\tclocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revA\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1275-revb.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU1275 RevB\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revB\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n mmc0 = &sdhci1;\n ethernet0 = &gem1;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t* 1.0 revision has level shifter and this property should be\n\t* removed for supporting UHS mode\n\t*/\n\tno-1-8-v;\n};\n\n&gem1 {\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1285-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU1285 RevA\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1285 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1285-revA\", \"xlnx,zynqmp-zcu1285\", \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n mmc0 = &sdhci1;\n ethernet0 = &gem1; /* EMIO */\n i2c = &i2c0; /* EMIO */\n };\n\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PMBUS */\n\t\t\tmax20751@74 { /* u23 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x74>;\n\t\t\t};\n\t\t\tmax20751@70 { /* u89 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x70>;\n\t\t\t};\n\t\t\tmax15301@a { /* u28 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u48 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@d { /* u27 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\tmax15303@e { /* u11 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\tmax15303@f { /* u96 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\tmax15303@11 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\tmax15303@12 { /* u24 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u29 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u51 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u30 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u102 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15301@17 { /* u50 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u31 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* CM_I2C */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYS_EEPROM */\n\t\t\teeprom: eeprom@54 { /* u101 */\n\t\t\t\tcompatible = \"atmel,24c32\"; /* 24LC32A */\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FMC1 */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FMC2 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* ANALOG_PMBUS */\n\t\t\tu60: ina226@40 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu61: ina226@41 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu63: ina226@42 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu65: ina226@43 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu64: ina226@44 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* ANALOG_CM_I2C */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FMC3 */\n\t\t};\n\t};\n};\n\n&gem1 {\n\tmdio {\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu208-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU208\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU208 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu208-revA\", \"xlnx,zynqmp-zcu208\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu216-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU216\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU216 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu216-revA\", \"xlnx,zynqmp-zcu216\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu670-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR)\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU670 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu670-revA\", \"xlnx,zynqmp-zcu670\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\"; /* DS1 */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5381_6: si5381_6 { /* refclk_usb3 - u43 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"SFP3_TX_DISABLE\", \"SFP2_TX_DISABLE\", \"SFP1_TX_DISABLE\", /* 25 - 29 */\n\t\t \"SFP0_TX_DISABLE\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"SD_PWR_RST\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"SI5381_INT_ALM\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* Not in schematics */\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5381: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SI5381 - u43 */\n\t\t\t/*si5381: clock-generator@68 {\n\t\t\t\treg = <0x68>;\n\t\t\t};*/\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_psrefclk: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"si570_ps_ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 2Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&psgtr {\n\t/* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */\n\tclocks = <&si5381_6>;\n\tclock-names = \"ref2\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zcu670-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU670 (67DR) revB\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU670 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu670-revB\", \"xlnx,zynqmp-zcu670\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\"; /* DS1 */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5381_6: si5381_6 { /* refclk_usb3 - u43 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"SFP3_TX_DISABLE\", \"SFP2_TX_DISABLE\", \"SFP1_TX_DISABLE\", /* 25 - 29 */\n\t\t \"SFP0_TX_DISABLE\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"SD_PWR_RST\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"SI5381_INT_ALM\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* Not in schematics */\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5381: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SI5381 - u43 */\n\t\t\t/*si5381: clock-generator@68 {\n\t\t\t\treg = <0x68>;\n\t\t\t};*/\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_psrefclk: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"si570_ps_ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 2Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\txlnx,mio-bank = <1>;\n\tclk-phase-sd-hs = <120>, <60>;\n\tclk-phase-uhs-sdr25 = <132>, <60>;\n\tclk-phase-uhs-ddr50 = <153>, <48>;\n};\n\n&psgtr {\n\t/* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */\n\tclocks = <&si5381_6>;\n\tclock-names = \"ref2\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zedboard.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Naga Sureshkumar Relli \n */\n\n/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-a2197-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Versal System Controller on a2197 board RevA\";\n\tcompatible = \"xlnx,zynqmp-a2197-revA\", \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n i2c0 = &i2c0;\n nvmem0 = &eeprom1;\n nvmem1 = &eeprom0;\n serial0 = &uart0;\n };\n\n};\n\n&i2c0 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* this cover MGT board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* This cover processor board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-e-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevA\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n nvmem1 = &eeprom_ebm;\n nvmem2 = &eeprom_fmc1;\n nvmem3 = &eeprom_fmc2;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n };\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tsi570_ddrdimm1_clk: si570_ddrdimm1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tsi570_lpddr4_clk2: si570_lpddr4_clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570_lpddr4_clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk1>;\n\t};\n\n\tsi570_hsdp_clk: si570_hsdp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi570_zsfp_clk: si570_zsfp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_zsfp>;\n\t};\n\n\tsi570_user1_clk: si570_user1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_user1>;\n\t};\n\n\tsi5332_1: si5332_1 { /* u142 - GEM0 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vcc-soc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;\n\t};\n\tina226-vcc-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc-pslp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;\n\t};\n\tina226-vcc-psfp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;\n\t};\n\tina226-vccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;\n\t};\n\tina226-vccaux-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;\n\t};\n\tina226-vcco-500 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;\n\t};\n\tina226-vcco-501 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;\n\t};\n\tina226-vcco-502 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;\n\t};\n\tina226-vcco-503 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;\n\t};\n\tina226-vcc-1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;\n\t};\n\tina226-vcc-3v3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;\n\t};\n\tina226-vcc-1v2-ddr4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;\n\t};\n\tina226-vcc-1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtyavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;\n\t};\n\tina226-mgtyavtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;\n\t};\n\tina226-mgtyvccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;\n\t};\n\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n/* GEM SGMII */\n&psgtr {\n\tstatus = \"okay\";\n\t/* gem0 */\n\tclocks = <&si5332_1>;\n\tclock-names = \"ref0\";\n};\n\n&gem0 {\n\tphys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@0 { /* u131 M88E1512 */\n\t\t\treg = <0>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"ZU4_TRIGGER\", \"SYSCTLR_PB\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"\", /* 85 - 89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"PMBUS_ALERT\", \"\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ttca6416_u233: gpio@20 { /* u233 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"\", \"\", /* 0 - 3 */\n\t\t\t\t\"PMBUS2_INA226_ALERT\", \"\", \"\", \"MAX6643_FULLSPD\", /* 4 - 7 */\n\t\t\t\t\"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 10 - 13 */\n\t\t\t\t\"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* u152 IR35215 0x16/0x46 vcc_soc */\n\t\t\t/* u179 ir38164 0x19/0x49 vcco_500 */\n\t\t\t/* u181 ir38164 0x1a/0x4a vcco_501 */\n\t\t\t/* u183 ir38164 0x1b/0x4b vcco_502 */\n\t\t\t/* u185 ir38164 0x1e/0x4e vadj_fmc */\n\t\t\t/* u187 ir38164 0x1F/0x4f mgtyavcc */\n\t\t\t/* u189 ir38164 0x20/0x50 mgtyavtt */\n\t\t\t/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */\n\t\t\t/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */\n\n\t\t\tirps5401_47: irps5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* pmbus / i2c 0x17 */\n\t\t\t};\n\t\t\tirps5401_4c: irps5401@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* pmbus / i2c 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: irps5401@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* pmbus / i2c 0x1d */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <500>; /* R440 */\n\t\t\t\t/* 0.80V @ 32A 1 of 6 Phases*/\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-soc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <500>; /* R1702 */\n\t\t\t\t/* 0.80V @ 18A */\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pmc\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* R1214 */\n\t\t\t\t/* 0.78V @ 500mA */\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u162 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r1221 */\n\t\t\t\t/* 0.78V @ 4A */\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pslp\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>; /* R1216 */\n\t\t\t\t/* 0.78V @ 1A */\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-psfp\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1219 */\n\t\t\t\t/* 0.78V @ 2A */\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* u39 8T49N240 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0x6c>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* R382 */\n\t\t\t\t/* 1.5V @ 3A */\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux-pmc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>; /* R1246 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u178 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-500\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>; /* R1300 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u180 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-501\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <2000>; /* R1313 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u182 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-502\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <2000>; /* R1330 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-503\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1229 */\n\t\t\t\t/* 1.8V @ 2A */\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u173 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v8\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>; /* R400 */\n\t\t\t\t/* 1.8V @ 6A */\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-3v3\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* R1232 */\n\t\t\t\t/* 3.3V @ 500mA */\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v2-ddr4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>; /* R1275 */\n\t\t\t\t/* 1.2V @ 4A */\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>; /* R1286 */\n\t\t\t\t/* 1.1V @ 4A */\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>; /* R1350 */\n\t\t\t\t/* 1.5V @ 10A */\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavcc\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <2000>; /* R1367 */\n\t\t\t\t/* 0.88V @ 6A */\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavtt\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>; /* R1384 */\n\t\t\t\t/* 1.2V @ 10A */\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyvccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>; /* r1679 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t\ti2c@5 { /* zSFP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_zsfp: clock-generator@5d { /* u192 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_zsfp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* USER_SI570_1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_user1: clock-generator@5f { /* u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>; /* FIXME check address */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"si570_user1\";\n\t\t\t};\n\n\t\t};\n\t\ti2c@7 { /* USER_SI570_2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* 0x5c too */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* and connector J212D */\n\t\t\teeprom_ebm: eeprom@52 { /* x-ebm module */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\t\t};\n\t\tfmc1: i2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t\teeprom_fmc1: eeprom@50 {\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\tfmc2: i2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t\teeprom_fmc2: eeprom@50 {\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LPDDR4_SI570_CLK2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_lpddr4clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4clk1: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* 8A34001 - U219B and J310 connector */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n\ti2c-mux@75 { /* u214 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\ti2c@0 { /* SFP0_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* SFP0 */\n\t\t};\n\t\ti2c@1 { /* SFP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@2 { /* QSFP1_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* QSFP1 */\n\t\t};\n\t\t/* 3 - 7 unused */\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-e-a2197-00-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevB System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-e-a2197-00-reva.dtsi\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevB\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revB\", \"xlnx,zynqmp-a2197-revB\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\t/delete-node/ ina226-vcco-500;\n\t/delete-node/ ina226-vcco-501;\n\t/delete-node/ ina226-vcco-502;\n};\n\n&i2c0 {\n\ti2c-mux@74 { /* u33 */\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t/delete-node/ clock-generator@6c;\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t/delete-node/ ina226@42;\n\t\t\t/delete-node/ ina226@43;\n\t\t\t/delete-node/ ina226@44;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-g-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 MGT Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-g-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\t aliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n mmc0 = &sdhci0;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n usb0 = &usb0;\n };\n\n\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u82 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&gem0 { /* eth MDIO 76/77 */\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 */\n\t\treg = <0>;\n\t\treset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 5 - 9 */\n\t\t \"\", \"\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"\", \"\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\ti2c-mux@74 { /* u94 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* CM_I2C_SCL - Samtec */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* PMBUS - AFX_PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\ttps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\ttps544@10 { /* u73 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\ttps544@11 { /* u76 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\ttps544@12 { /* u77 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\ttps544@13 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\ttps544@14 { /* u81 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\ttps544@15 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\ttps544@16 { /* u63 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\ttps544@17 { /* u66 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\ttps544@18 { /* u67 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\ttps544@19 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\ttps544@1d { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\ttps544@1e { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\ttps544@1f { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t\ttps544@20 { /* u71 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\t\t\tu74: ina226@40 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu75: ina226@41 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\"\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@43 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu82: ina226@44 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u82\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu84: ina226@45 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\ttps53681@60 { /* u53- 0xc0 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* fmc1 via JA2G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom_fmc1: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* fmc2 via JA3G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\teeprom_fmc2: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* fmc3 via JA4G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\teeprom_fmc3: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* ddr dimm */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"high-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-01-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n spi0 = &qspi;\n };\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\tina226-vcc0v6-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc0v6_lp4: ina226@49 { /* u101 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc0v6-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@60 { /* u69 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@5d { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n status = \"disabled\"; /* not at mem board */\n};\n\n&dwc3_1 {\n /delete-property/ phy-names ;\n /delete-property/ phys ;\n maximum-speed = \"high-speed\";\n snps,dis_u2_susphy_quirk ;\n snps,dis_u3_susphy_quirk ;\n status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-02-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n spi0 = &qspi;\n };\n\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@60 { /* u69 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* C0_DDR4_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\ti2c@6 { /* C2_DDR5_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\ti2c@7 { /* C3_DDR4_UDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_RLD3 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_RLD3_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_DDR5 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_DDR5_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-03-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n spi0 = &qspi;\n };\n\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@18 { /* u3022 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@60 { /* u69 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* DDR4_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_SODIMM_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_QDRIV */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_QDRIV_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-01-revA\", \"xlnx,zynqmp-x-prc-01\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\",\"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-02-revA\", \"xlnx,zynqmp-x-prc-02\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-03-revA\", \"xlnx,zynqmp-x-prc-03\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tx_prc_si5338: clock-generator@70 { /* U9 */\n\t\t\t\tcompatible = \"silabs,si5338\";\n\t\t\t\treg = <0x70>; /* FIXME */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-04-revA\", \"xlnx,zynqmp-x-prc-04\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-05-revA\", \"xlnx,zynqmp-x-prc-05\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr_sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr_sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr_sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr_sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n };\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@60 { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* 570JAC000900DG */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@60 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP Generic System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tmodel = \"ZynqMP Generic System Controller\";\n\tcompatible = \"xlnx,zynqmp-sc-revB\", \"xlnx,zynqmp-sc\", \"xlnx,zynqmp\";\n\n\taliases {\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n spi1 = &spi0;\n spi2 = &spi1;\n usb0 = &usb0;\n usb1 = &usb1;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"sw16\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds40-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t\tds44-led {\n\t\t\tlabel = \"status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tsi5332_2: si5332_2 { /* u42 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\tpwm-fan {\n\t\tcompatible = \"pwm-fan\";\n\t\tpwms = <&ttc0 2 40000 1>;\n\t};\n\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\"QSPI_CS_B\", \"\", \"LED1\", \"LED2\", \"\", /* 5 - 9 */\n\t\t\"\", \"ZU4_TRIGGER\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\"I2C1_SDA\", \"UART0_RXD\", \"UART0_TXD\", \"\", \"\", /* 25 - 29 */\n\t\t\"\", \"\", \"\", \"\", \"I2C0_SCL\", /* 30 - 34 */\n\t\t\"I2C0_SDA\", \"UART1_TXD\", \"UART1_RXD\", \"GEM_TX_CLK\", \"GEM_TX_D0\", /* 35 - 39 */\n\t\t\"GEM_TX_D1\", \"GEM_TX_D2\", \"GEM_TX_D3\", \"GEM_TX_CTL\", \"GEM_RX_CLK\", /* 40 - 44 */\n\t\t\"GEM_RX_D0\", \"GEM_RX_D1\", \"GEM_RX_D2\", \"GEM_RX_D3\", \"GEM_RX_CTL\", /* 45 - 49 */\n\t\t\"GEM_MDC\", \"GEM_MDIO\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t\"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t\"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\"\", \"\", \"ETH_RESET_B\", /* 75 - 77, MIO end and EMIO start */\n\t\t\"\", \"\", /* 78 - 79 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem1_default>;\n\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy0: ethernet-phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = ;\n\t\t\tti,tx-internal-delay = ;\n\t\t\tti,fifo-depth = ;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t};\n\t};\n};\n\n&i2c0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\tclock-frequency = <100000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n};\n\n&i2c1 { /* i2c1 MIO 24-25 */\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <100000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t/* No reason to do pinctrl setup at u-boot stage */\n\t/* Use for storing information about SC board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tu-boot,dm-pre-reloc;\n\t};\n};\n\n/* USB 3.0 only */\n&psgtr {\n\t/* nc, nc, usb3 */\n\tclocks = <&si5332_2>;\n\tclock-names = \"ref2\";\n};\n\n&qspi { /* MIO 0-5 */\n\t/* QSPI should also have PINCTRL setup */\n\tflash@0 {\n\t\tcompatible = \"mt25qu512a\", \"m25p80\", \"jedec,spi-nor\"; /* mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x10000>; /* 256B but 64KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2250000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x2250000 0x1db0000>; /* 29.5 MB */\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&ttc0 {\n\t#pwm-cells = <3>;\n};\n\n&uart1 { /* uart0 MIO36-37 */\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 { /* required by spec */\n\tstatus = \"okay\";\n\tpinctrl_uart1_default: uart1-default {\n\t\tconf {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO37\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO36\";\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tconf {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tconf {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\t};\n\n\tpinctrl_gem1_default: gem1-default {\n\t\tconf {\n\t\t\tgroups = \"ethernet1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO44\", \"MIO46\", \"MIO48\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-bootstrap {\n\t\t\tpins = \"MIO45\", \"MIO47\", \"MIO49\";\n\t\t\tbias-disable;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO38\", \"MIO39\", \"MIO40\",\n\t\t\t\t\"MIO41\", \"MIO42\", \"MIO43\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio1\";\n\t\t\tgroups = \"mdio1_0_grp\";\n\t\t};\n\n\t\tmux {\n\t\t\tfunction = \"ethernet1\";\n\t\t\tgroups = \"ethernet1_0_grp\";\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t\"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP Generic System Controller\n *\n * Copyright (C) 2021-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sc-revb.dtsi\"\n\n/ {\n\tmodel = \"ZynqMP Generic System Controller\";\n\tcompatible = \"xlnx,zynqmp-sc-revC\", \"xlnx,zynqmp-sc\", \"xlnx,zynqmp\";\n};\n\n&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */\n\t/delete-node/ mdio;\n\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy0: ethernet-phy@1 { /* ADI1300 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id0283.bc30\";\n\t\t\treg = <1>;\n\t\t adi,rx-internal-delay-ps = <2400>;\n\t\t\tadi,tx-internal-delay-ps = <2400>;\n\t\t\tadi,fifo-depth-bits = <8>;\n\t\t\treset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;\n\t\t\treset-assert-us = <10>;\n\t\t\treset-deassert-us = <5000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-vek280-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VEK280 revA\n *\n * (C) Copyright 2022, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n\n&{/} {\n\tcompatible = \"xlnx,zynqmp-sc-vek280-revA\", \"xlnx,zynqmp-vek280-revA\",\n\t\t \"xlnx,zynqmp-vek280\", \"xlnx,zynqmp\";\n\n\tvc7_xin: vc7-xin {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <50000000>;\n\t};\n\n\tgtclk1_1: sys_clk_0 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 0>;\n\t};\n\n\tgtclk1_2: sys_clk_1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 1>;\n\t};\n\n\tgtclk1_3: sys_clk_2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 2>;\n\t};\n\n\tgtclk1_6: gtclk1_out6 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 3>;\n\t};\n\n\tgtclk1_7: gtclk1_out7 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 4>;\n\t};\n\n\tgtclk1_8: gtclk1_out8 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 5>;\n\t};\n\n\tgtclk1_10: ps_ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 6>;\n\t};\n\n\tgtclk1_11: gtclk1_out11 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 7>;\n\t};\n};\n\n&i2c0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\ttca6416_u233: gpio@20 { /* u233 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"\", \"\", \"SFP_MOD_ABS\", \"SFP_TX_DISABLE\", /* 0 - 3 */\n\t\t\t\t\"PMBUS2_INA226_ALERT\", \"\", \"\", \"\", /* 4 - 7 */\n\t\t\t\t\"FMCP1_FMC_PRSNT_M2C_B\", \"\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"\", /* 10 - 13 */\n\t\t\t\t\"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\tir35215_46: pmic@46 { /* IR35215 - u152 */\n\t\t\t\tcompatible = \"infineon,ir35215\";\n\t\t\t\treg = <0x46>; /* i2c addr - 0x16 */\n\t\t\t};\n\t\t\tirps5401_47: pmic5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* i2c addr 0x17 */\n\t\t\t};\n\t\t\tirps5401_48: pmic@48 { /* IRPS5401 - u279 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x48>; /* i2c addr 0x18 */\n\t\t\t};\n\t\t\tir38064_49: regulator@49 { /* IR38064 - u295 */\n\t\t\t\tcompatible = \"infineon,ir38064\";\n\t\t\t\treg = <0x49>; /* i2c addr 0x19 */\n\t\t\t};\n\t\t\tirps5401_4c: pmic@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: pmic@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* i2c addr 0x1d */\n\t\t\t};\n\t\t\tir38060_4e: regulator@4e { /* IR38060 - u282 */\n\t\t\t\tcompatible = \"infineon,ir38060\";\n\t\t\t\treg = <0x4e>; /* i2c addr 0x1e */\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* alerts coming to u233 and SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <500>; /* r440 */\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <500>; /* r1702 */\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* r382 */\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u355 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r2417 */\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>; /* r1830 */\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u260 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* r2386 */\n\t\t\t};\n\t\t\tvcco_hdio: ina226@46 { /* u356 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>; /* r2392 */\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpmbus2_ina226_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* alerts coming to u233 and SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* r2384 */\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>; /* r2000 */\n\t\t\t};\n\t\t\tmgtavcc: ina226@42 { /* u265 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* r1829 */\n\t\t\t};\n\t\t\tvcc1v5: ina226@43 { /* u264 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r2397 */\n\t\t\t};\n\t\t\tvcco_mio: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* r2401 */\n\t\t\t};\n\t\t\tmgtavtt: ina226@46 { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <500>; /* r1384 */\n\t\t\t};\n\t\t\tvcco_502: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* r1994 */\n\t\t\t};\n\t\t\tmgtvccaux: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>; /* r2384 */\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u306 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <500>; /* r2064 */\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u281 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>; /* r2031 */\n\t\t\t};\n\t\t\tlpdmgtyavcc: ina226@4b { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>; /* r2004 */\n\t\t\t};\n\t\t\tlpdmgtyavtt: ina226@4c { /* u309 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>; /* r1229 */\n\t\t\t};\n\t\t\tlpdmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>; /* r1679 */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\trc21008a_gtclk1: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* connector j374 */\n\t\t\t/* rc21008a at 0x9 u299 */\n\t\t\tvc7: clock-generator@9 {\n\t\t\t\tcompatible = \"renesas,rc21008a\";\n\t\t\t\treg = <0x9>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&vc7_xin>;\n\t\t\t\tclock-names = \"xin\";\n\t\t\t};\n\t\t};\n\t\tfmcp1_iic: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* to j51c */\n\t\t};\n\t\tsfp: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* sfp+ connector J376 */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-vek280-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VEK280 revB\n *\n * (C) Copyright 2022, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sc-vek280-reva.dtsi\"\n\n&{/} {\n\tcompatible = \"xlnx,zynqmp-sc-vek280-revB\", \"xlnx,zynqmp-vek280-revB\",\n\t\t \"xlnx,zynqmp-vek280\", \"xlnx,zynqmp\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sm-k24-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SM-K24 RevA\n *\n * (C) Copyright 2020 - 2021, Xilinx, Inc.\n * (C) Copyright 2022, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sm-k26-reva.dtsi\"\n\n/ {\n\tmodel = \"ZynqMP SM-K24 RevA\";\n\tcompatible = \"xlnx,zynqmp-sm-k24-revA\", \"xlnx,zynqmp-sm-k24\",\n\t\t \"xlnx,zynqmp\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sm-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SM-K26 rev1/B/A\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP SM-K26 Rev1/B/A\";\n\tcompatible = \"xlnx,zynqmp-sm-k26-rev1\", \"xlnx,zynqmp-sm-k26-revB\",\n\t\t \"xlnx,zynqmp-sm-k26-revA\", \"xlnx,zynqmp-sm-k26\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tkey-fwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36-led {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n\tpwm-fan {\n\t\tcompatible = \"pwm-fan\";\n\t\tpwms = <&ttc0 2 40000 0>;\n\t};\n};\n\n&modepin_gpio {\n\tlabel = \"modepin\";\n};\n\n&ttc0 {\n\t#pwm-cells = <3>;\n};\n\n&pinctrl0 {\n status = \"okay\";\n pinctrl_sdhci0_default: sdhci0-default {\n conf {\n groups = \"sdio0_0_grp\";\n slew-rate = ;\n power-source = ;\n bias-disable;\n };\n\n mux {\n groups = \"sdio0_0_grp\";\n function = \"sdio0\";\n };\n };\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tspi_flash: flash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Image Selector\";\n\t\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"Image Selector Golden\";\n\t\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"Persistent Register\";\n\t\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@120000 {\n\t\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@140000 {\n\t\t\t\tlabel = \"Open_1\";\n\t\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t\t};\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t\t};\n\t\t\tpartition@f00000 {\n\t\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@f80000 {\n\t\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t\t};\n\t\t\tpartition@1c80000 {\n\t\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@1d00000 {\n\t\t\t\tlabel = \"Open_2\";\n\t\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t\t};\n\t\t\tpartition@1e00000 {\n\t\t\t\tlabel = \"Recovery Image\";\n\t\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@2000000 {\n\t\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@2200000 {\n\t\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@2220000 {\n\t\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@2240000 {\n\t\t\t\tlabel = \"SHA256\";\n\t\t\t\treg = <0x2240000 0x40000>; /* 256B but 256KB sector */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@2280000 {\n\t\t\t\tlabel = \"Secure OS Storage\";\n\t\t\t\treg = <0x2280000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@22A0000 {\n\t\t\t\tlabel = \"User\";\n\t\t\t\treg = <0x22A0000 0x1db0000>; /* 29.5 MB */\n\n\t\t\t};\n\t\t};\n\t};\n};\n\n&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tassigned-clock-rates = <187498123>;\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues to be fixed in next board revision.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-smk-k24-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SMK-K24 RevA\n *\n * (C) Copyright 2020 - 2021, Xilinx, Inc.\n * (C) Copyright 2022, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sm-k24-reva.dtsi\"\n\n/ {\n\tmodel = \"ZynqMP SMK-K24 RevA\";\n\tcompatible = \"xlnx,zynqmp-smk-k24-revA\", \"xlnx,zynqmp-smk-k24\",\n\t\t \"xlnx,zynqmp\";\n};\n\n&sdhci0 {\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-smk-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sm-k26-reva.dtsi\"\n\n/ {\n model = \"ZynqMP SMK-K26 Rev1/B/A\";\n compatible = \"xlnx,zynqmp-smk-k26-rev1\", \"xlnx,zynqmp-smk-k26-revB\",\n \"xlnx,zynqmp-smk-k26-revA\", \"xlnx,zynqmp-smk-k26\",\n \"xlnx,zynqmp\";\n};\n\n&sdhci0 {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on vp-x-a2785-00 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vp-x-a2785-00-revA\",\n\t\t \"xlnx,zynqmp-vp-x-a2785-00\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n usb1 = &usb1;\n nvmem0 = &eeprom;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tj383 {\n\t\t\tlabel = \"j383\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds52 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* u285 - mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>; /* maybe 4 here */\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* sd MIO 45-51 */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 { /* u131 - M88e1512 */\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"\", \"\", \"\", \"VCCINT_FAULT_B\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\treg_vccint: tps53681@60 { /* u266 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@10 { /* u274 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@11 { /* u275 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@12 { /* u276 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc_cpm: tps544@14 { /* u272 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_util_3v3: tps544@1d { /* u278 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvcc_cpm: ina226@44 { /* u273 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpcie_smbus: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tpcie2_smbus: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\ti2c@3 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\t/* 6-7 unused */\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VPK120 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on VPK120 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vpk120-revA\",\n\t\t \"xlnx,zynqmp-vpk120\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n usb1 = &usb1;\n nvmem0 = &eeprom;\n };\n\n\tsi570_user1_fmc_clk: si570_user1_fmc_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&user_si570_1>;\n\t};\n\n\tsi570_ref_clk: si570_ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&ref_clk>;\n\t};\n\n\tsi570_lpddr4_clk3: si570_lpddr4_clk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk3>;\n\t};\n\n\tsi570_lpddr4_clk2: si570_lpddr4_clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570_lpddr4_clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk1>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw16 {\n\t\t\tlabel = \"sw16\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds40 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"\", \"\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"\", /* 85 - 89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"QSFPDD1_MODSELL\", \"QSFPDD1_MODSELL\", /* 0 - 3 */\n\t\t\t\t \"PMBUS2_INA226_ALERT\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP1_FMC_PRSNT_M2C_B\", \"\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\tir38060_41: regulator@41 { /* IR38060 - u259 */\n\t\t\t\tcompatible = \"infineon,ir38060\", \"infineon,ir38064\";\n\t\t\t\treg = <0x41>; /* i2c addr 0x11 */\n\t\t\t};\n\t\t\tir38164_43: regulator@43 { /* IR38164 - u13 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x43>; /* i2c addr 0x13 */\n\t\t\t};\n\t\t\tir35221_45: pmic@46 { /* IR35221 - u152 */\n\t\t\t\tcompatible = \"infineon,ir35221\";\n\t\t\t\treg = <0x46>; /* PMBUS - 0x16 */\n\t\t\t};\n\t\t\tirps5401_47: pmic5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* i2c addr 0x17 */\n\t\t\t};\n\t\t\tir38164_49: regulator@49 { /* IR38164 - u189 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x49>; /* i2c addr 0x19 */\n\t\t\t};\n\t\t\tirps5401_4c: pmic@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: pmic@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tir38164_4e: regulator@4e { /* IR38164 - u184 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4e>; /* i2c addr 0x1e */\n\t\t\t};\n\t\t\tir38164_4f: regulator@4f { /* IR38164 - u187 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4f>; /* i2c addr 0x1f */\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u5 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpmbus2_ina226_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@42 { /* u265 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v5: ina226@43 { /* u264 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_mio: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavtt: ina226@46 { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtvccaux: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyavcc: ina226@4b { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tlpdmgtyavtt: ina226@4c { /* u260 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tuser_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"fmc_si570\";\n\t\t\t};\n\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tref_clk_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\tfmcp1_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tlpddr4_si570_clk3_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlpddr4_clk3: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk3\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\tqsfpdd_i2c: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* J1/J2 connectors */\n\t\t};\n\t\tidt8a34001_i2c: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* Via J310 connector */\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u219B */\n\t\t\t\treg = <0x5b>; /* FIXME not in schematics */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-versal-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_VERSAL_H\n#define _DT_BINDINGS_CLK_VERSAL_H\n\n#define PMC_PLL\t\t\t\t\t1\n#define APU_PLL\t\t\t\t\t2\n#define RPU_PLL\t\t\t\t\t3\n#define CPM_PLL\t\t\t\t\t4\n#define NOC_PLL\t\t\t\t\t5\n#define PLL_MAX\t\t\t\t\t6\n#define PMC_PRESRC\t\t\t\t7\n#define PMC_POSTCLK\t\t\t\t8\n#define PMC_PLL_OUT\t\t\t\t9\n#define PPLL\t\t\t\t\t10\n#define NOC_PRESRC\t\t\t\t11\n#define NOC_POSTCLK\t\t\t\t12\n#define NOC_PLL_OUT\t\t\t\t13\n#define NPLL\t\t\t\t\t14\n#define APU_PRESRC\t\t\t\t15\n#define APU_POSTCLK\t\t\t\t16\n#define APU_PLL_OUT\t\t\t\t17\n#define APLL\t\t\t\t\t18\n#define RPU_PRESRC\t\t\t\t19\n#define RPU_POSTCLK\t\t\t\t20\n#define RPU_PLL_OUT\t\t\t\t21\n#define RPLL\t\t\t\t\t22\n#define CPM_PRESRC\t\t\t\t23\n#define CPM_POSTCLK\t\t\t\t24\n#define CPM_PLL_OUT\t\t\t\t25\n#define CPLL\t\t\t\t\t26\n#define PPLL_TO_XPD\t\t\t\t27\n#define NPLL_TO_XPD\t\t\t\t28\n#define APLL_TO_XPD\t\t\t\t29\n#define RPLL_TO_XPD\t\t\t\t30\n#define EFUSE_REF\t\t\t\t31\n#define SYSMON_REF\t\t\t\t32\n#define IRO_SUSPEND_REF\t\t\t\t33\n#define USB_SUSPEND\t\t\t\t34\n#define SWITCH_TIMEOUT\t\t\t\t35\n#define RCLK_PMC\t\t\t\t36\n#define RCLK_LPD\t\t\t\t37\n#define WDT\t\t\t\t\t38\n#define TTC0\t\t\t\t\t39\n#define TTC1\t\t\t\t\t40\n#define TTC2\t\t\t\t\t41\n#define TTC3\t\t\t\t\t42\n#define GEM_TSU\t\t\t\t\t43\n#define GEM_TSU_LB\t\t\t\t44\n#define MUXED_IRO_DIV2\t\t\t\t45\n#define MUXED_IRO_DIV4\t\t\t\t46\n#define PSM_REF\t\t\t\t\t47\n#define GEM0_RX\t\t\t\t\t48\n#define GEM0_TX\t\t\t\t\t49\n#define GEM1_RX\t\t\t\t\t50\n#define GEM1_TX\t\t\t\t\t51\n#define CPM_CORE_REF\t\t\t\t52\n#define CPM_LSBUS_REF\t\t\t\t53\n#define CPM_DBG_REF\t\t\t\t54\n#define CPM_AUX0_REF\t\t\t\t55\n#define CPM_AUX1_REF\t\t\t\t56\n#define QSPI_REF\t\t\t\t57\n#define OSPI_REF\t\t\t\t58\n#define SDIO0_REF\t\t\t\t59\n#define SDIO1_REF\t\t\t\t60\n#define PMC_LSBUS_REF\t\t\t\t61\n#define I2C_REF\t\t\t\t\t62\n#define TEST_PATTERN_REF\t\t\t63\n#define DFT_OSC_REF\t\t\t\t64\n#define PMC_PL0_REF\t\t\t\t65\n#define PMC_PL1_REF\t\t\t\t66\n#define PMC_PL2_REF\t\t\t\t67\n#define PMC_PL3_REF\t\t\t\t68\n#define CFU_REF\t\t\t\t\t69\n#define SPARE_REF\t\t\t\t70\n#define NPI_REF\t\t\t\t\t71\n#define HSM0_REF\t\t\t\t72\n#define HSM1_REF\t\t\t\t73\n#define SD_DLL_REF\t\t\t\t74\n#define FPD_TOP_SWITCH\t\t\t\t75\n#define FPD_LSBUS\t\t\t\t76\n#define ACPU\t\t\t\t\t77\n#define DBG_TRACE\t\t\t\t78\n#define DBG_FPD\t\t\t\t\t79\n#define LPD_TOP_SWITCH\t\t\t\t80\n#define ADMA\t\t\t\t\t81\n#define LPD_LSBUS\t\t\t\t82\n#define CPU_R5\t\t\t\t\t83\n#define CPU_R5_CORE\t\t\t\t84\n#define CPU_R5_OCM\t\t\t\t85\n#define CPU_R5_OCM2\t\t\t\t86\n#define IOU_SWITCH\t\t\t\t87\n#define GEM0_REF\t\t\t\t88\n#define GEM1_REF\t\t\t\t89\n#define GEM_TSU_REF\t\t\t\t90\n#define USB0_BUS_REF\t\t\t\t91\n#define UART0_REF\t\t\t\t92\n#define UART1_REF\t\t\t\t93\n#define SPI0_REF\t\t\t\t94\n#define SPI1_REF\t\t\t\t95\n#define CAN0_REF\t\t\t\t96\n#define CAN1_REF\t\t\t\t97\n#define I2C0_REF\t\t\t\t98\n#define I2C1_REF\t\t\t\t99\n#define DBG_LPD\t\t\t\t\t100\n#define TIMESTAMP_REF\t\t\t\t101\n#define DBG_TSTMP\t\t\t\t102\n#define CPM_TOPSW_REF\t\t\t\t103\n#define USB3_DUAL_REF\t\t\t\t104\n#define OUTCLK_MAX\t\t\t\t105\n#define REF_CLK\t\t\t\t\t106\n#define PL_ALT_REF_CLK\t\t\t\t107\n#define MUXED_IRO\t\t\t\t108\n#define PL_EXT\t\t\t\t\t109\n#define PL_LB\t\t\t\t\t110\n#define MIO_50_OR_51\t\t\t\t111\n#define MIO_24_OR_25\t\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-versal-net-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2022, Xilinx Inc.\n * Copyright (C) 2022, Advanced Micro Devices, Inc.\n */\n\n#ifndef _DT_BINDINGS_CLK_VERSAL_NET_H\n#define _DT_BINDINGS_CLK_VERSAL_NET_H\n\n#include \n\n#define GEM0_REF_RX\t0xA9\n#define GEM0_REF_TX\t0xA8\n#define GEM1_REF_RX\t0xA2\n#define GEM1_REF_TX\t0xA1\n#define CAN0_REF_2X\t0x9E\n#define CAN1_REF_2X\t0xAC\n#define FPD_WWDT\t0x96\n#define ACPU_0\t\t0x98\n#define ACPU_1\t\t0x9B\n#define ACPU_2\t\t0x9A\n#define ACPU_3\t\t0x99\n#define I3C0_REF\t0x9D\n#define I3C1_REF\t0x9F\n#define USB1_BUS_REF\t0xAE\n\n/* Remove Versal specific node IDs */\n#undef APU_PLL\n#undef RPU_PLL\n#undef CPM_PLL\n#undef APU_PRESRC\n#undef APU_POSTCLK\n#undef APU_PLL_OUT\n#undef APLL\n#undef RPU_PRESRC\n#undef RPU_POSTCLK\n#undef RPU_PLL_OUT\n#undef RPLL\n#undef CPM_PRESRC\n#undef CPM_POSTCLK\n#undef CPM_PLL_OUT\n#undef CPLL\n#undef APLL_TO_XPD\n#undef RPLL_TO_XPD\n#undef RCLK_PMC\n#undef RCLK_LPD\n#undef WDT\n#undef MUXED_IRO_DIV2\n#undef MUXED_IRO_DIV4\n#undef PSM_REF\n#undef CPM_CORE_REF\n#undef CPM_LSBUS_REF\n#undef CPM_DBG_REF\n#undef CPM_AUX0_REF\n#undef CPM_AUX1_REF\n#undef CPU_R5\n#undef CPU_R5_CORE\n#undef CPU_R5_OCM\n#undef CPU_R5_OCM2\n#undef CAN0_REF\n#undef CAN1_REF\n#undef I2C0_REF\n#undef I2C1_REF\n#undef CPM_TOPSW_REF\n#undef USB3_DUAL_REF\n#undef MUXED_IRO\n#undef PL_EXT\n#undef PL_LB\n#undef MIO_50_OR_51\n#undef MIO_24_OR_25\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Xilinx Zynq MPSoC Firmware layer\n *\n * Copyright (C) 2014-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_ZYNQMP_H\n#define _DT_BINDINGS_CLK_ZYNQMP_H\n\n#define IOPLL\t\t\t0\n#define RPLL\t\t\t1\n#define APLL\t\t\t2\n#define DPLL\t\t\t3\n#define VPLL\t\t\t4\n#define IOPLL_TO_FPD\t\t5\n#define RPLL_TO_FPD\t\t6\n#define APLL_TO_LPD\t\t7\n#define DPLL_TO_LPD\t\t8\n#define VPLL_TO_LPD\t\t9\n#define ACPU\t\t\t10\n#define ACPU_HALF\t\t11\n#define DBF_FPD\t\t\t12\n#define DBF_LPD\t\t\t13\n#define DBG_TRACE\t\t14\n#define DBG_TSTMP\t\t15\n#define DP_VIDEO_REF\t\t16\n#define DP_AUDIO_REF\t\t17\n#define DP_STC_REF\t\t18\n#define GDMA_REF\t\t19\n#define DPDMA_REF\t\t20\n#define DDR_REF\t\t\t21\n#define SATA_REF\t\t22\n#define PCIE_REF\t\t23\n#define GPU_REF\t\t\t24\n#define GPU_PP0_REF\t\t25\n#define GPU_PP1_REF\t\t26\n#define TOPSW_MAIN\t\t27\n#define TOPSW_LSBUS\t\t28\n#define GTGREF0_REF\t\t29\n#define LPD_SWITCH\t\t30\n#define LPD_LSBUS\t\t31\n#define USB0_BUS_REF\t\t32\n#define USB1_BUS_REF\t\t33\n#define USB3_DUAL_REF\t\t34\n#define USB0\t\t\t35\n#define USB1\t\t\t36\n#define CPU_R5\t\t\t37\n#define CPU_R5_CORE\t\t38\n#define CSU_SPB\t\t\t39\n#define CSU_PLL\t\t\t40\n#define PCAP\t\t\t41\n#define IOU_SWITCH\t\t42\n#define GEM_TSU_REF\t\t43\n#define GEM_TSU\t\t\t44\n#define GEM0_TX\t\t\t45\n#define GEM1_TX\t\t\t46\n#define GEM2_TX\t\t\t47\n#define GEM3_TX\t\t\t48\n#define GEM0_RX\t\t\t49\n#define GEM1_RX\t\t\t50\n#define GEM2_RX\t\t\t51\n#define GEM3_RX\t\t\t52\n#define QSPI_REF\t\t53\n#define SDIO0_REF\t\t54\n#define SDIO1_REF\t\t55\n#define UART0_REF\t\t56\n#define UART1_REF\t\t57\n#define SPI0_REF\t\t58\n#define SPI1_REF\t\t59\n#define NAND_REF\t\t60\n#define I2C0_REF\t\t61\n#define I2C1_REF\t\t62\n#define CAN0_REF\t\t63\n#define CAN1_REF\t\t64\n#define CAN0\t\t\t65\n#define CAN1\t\t\t66\n#define DLL_REF\t\t\t67\n#define ADMA_REF\t\t68\n#define TIMESTAMP_REF\t\t69\n#define AMS_REF\t\t\t70\n#define PL0_REF\t\t\t71\n#define PL1_REF\t\t\t72\n#define PL2_REF\t\t\t73\n#define PL3_REF\t\t\t74\n#define WDT\t\t\t75\n#define IOPLL_INT\t\t76\n#define IOPLL_PRE_SRC\t\t77\n#define IOPLL_HALF\t\t78\n#define IOPLL_INT_MUX\t\t79\n#define IOPLL_POST_SRC\t\t80\n#define RPLL_INT\t\t81\n#define RPLL_PRE_SRC\t\t82\n#define RPLL_HALF\t\t83\n#define RPLL_INT_MUX\t\t84\n#define RPLL_POST_SRC\t\t85\n#define APLL_INT\t\t86\n#define APLL_PRE_SRC\t\t87\n#define APLL_HALF\t\t88\n#define APLL_INT_MUX\t\t89\n#define APLL_POST_SRC\t\t90\n#define DPLL_INT\t\t91\n#define DPLL_PRE_SRC\t\t92\n#define DPLL_HALF\t\t93\n#define DPLL_INT_MUX\t\t94\n#define DPLL_POST_SRC\t\t95\n#define VPLL_INT\t\t96\n#define VPLL_PRE_SRC\t\t97\n#define VPLL_HALF\t\t98\n#define VPLL_INT_MUX\t\t99\n#define VPLL_POST_SRC\t\t100\n#define CAN0_MIO\t\t101\n#define CAN1_MIO\t\t102\n#define ACPU_FULL\t\t103\n#define GEM0_REF\t\t104\n#define GEM1_REF\t\t105\n#define GEM2_REF\t\t106\n#define GEM3_REF\t\t107\n#define GEM0_REF_UNG\t\t108\n#define GEM1_REF_UNG\t\t109\n#define GEM2_REF_UNG\t\t110\n#define GEM3_REF_UNG\t\t111\n#define LPD_WDT\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h", "content": "/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */\n/*\n * Copyright 2019 Laurent Pinchart \n */\n\n#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n\n#define ZYNQMP_DPDMA_VIDEO0\t\t0\n#define ZYNQMP_DPDMA_VIDEO1\t\t1\n#define ZYNQMP_DPDMA_VIDEO2\t\t2\n#define ZYNQMP_DPDMA_GRAPHICS\t\t3\n#define ZYNQMP_DPDMA_AUDIO0\t\t4\n#define ZYNQMP_DPDMA_AUDIO1\t\t5\n\n#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/gpio/gpio.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most GPIO bindings.\n *\n * Most GPIO bindings include a flags cell as part of the GPIO specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_GPIO_GPIO_H\n#define _DT_BINDINGS_GPIO_GPIO_H\n\n/* Bit 0 express polarity */\n#define GPIO_ACTIVE_HIGH 0\n#define GPIO_ACTIVE_LOW 1\n\n/* Bit 1 express single-endedness */\n#define GPIO_PUSH_PULL 0\n#define GPIO_SINGLE_ENDED 2\n\n/* Bit 2 express Open drain or open source */\n#define GPIO_LINE_OPEN_SOURCE 0\n#define GPIO_LINE_OPEN_DRAIN 4\n\n/*\n * Open Drain/Collector is the combination of single-ended open drain interface.\n * Open Source/Emitter is the combination of single-ended open source interface.\n */\n#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)\n#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)\n\n/* Bit 3 express GPIO suspend/resume and reset persistence */\n#define GPIO_PERSISTENT 0\n#define GPIO_TRANSITORY 8\n\n/* Bit 4 express pull up */\n#define GPIO_PULL_UP 16\n\n/* Bit 5 express pull down */\n#define GPIO_PULL_DOWN 32\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/input/input.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most input bindings.\n *\n * Most input bindings include key code, matrix key code format.\n * In most cases, key code and matrix key code format uses\n * the standard values/macro defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INPUT_INPUT_H\n#define _DT_BINDINGS_INPUT_INPUT_H\n\n/*\n * Device properties and quirks\n */\n\n#define INPUT_PROP_POINTER\t\t0x00\t/* needs a pointer */\n#define INPUT_PROP_DIRECT\t\t0x01\t/* direct input devices */\n#define INPUT_PROP_BUTTONPAD\t\t0x02\t/* has button(s) under pad */\n#define INPUT_PROP_SEMI_MT\t\t0x03\t/* touch rectangle only */\n#define INPUT_PROP_TOPBUTTONPAD\t\t0x04\t/* softbuttons at top of pad */\n#define INPUT_PROP_POINTING_STICK\t0x05\t/* is a pointing stick */\n#define INPUT_PROP_ACCELEROMETER\t0x06\t/* has accelerometer */\n\n#define INPUT_PROP_MAX\t\t\t0x1f\n#define INPUT_PROP_CNT\t\t\t(INPUT_PROP_MAX + 1)\n\n\n/*\n * Event types\n */\n\n#define EV_SYN\t\t\t0x00\n#define EV_KEY\t\t\t0x01\n#define EV_REL\t\t\t0x02\n#define EV_ABS\t\t\t0x03\n#define EV_MSC\t\t\t0x04\n#define EV_SW\t\t\t0x05\n#define EV_LED\t\t\t0x11\n#define EV_SND\t\t\t0x12\n#define EV_REP\t\t\t0x14\n#define EV_FF\t\t\t0x15\n#define EV_PWR\t\t\t0x16\n#define EV_FF_STATUS\t\t0x17\n#define EV_MAX\t\t\t0x1f\n#define EV_CNT\t\t\t(EV_MAX+1)\n\n/*\n * Synchronization events.\n */\n\n#define SYN_REPORT\t\t0\n#define SYN_CONFIG\t\t1\n#define SYN_MT_REPORT\t\t2\n#define SYN_DROPPED\t\t3\n#define SYN_MAX\t\t\t0xf\n#define SYN_CNT\t\t\t(SYN_MAX+1)\n\n/*\n * Keys and buttons\n *\n * Most of the keys/buttons are modeled after USB HUT 1.12\n * (see http://www.usb.org/developers/hidpage).\n * Abbreviations in the comments:\n * AC - Application Control\n * AL - Application Launch Button\n * SC - System Control\n */\n\n#define KEY_RESERVED\t\t0\n#define KEY_ESC\t\t\t1\n#define KEY_1\t\t\t2\n#define KEY_2\t\t\t3\n#define KEY_3\t\t\t4\n#define KEY_4\t\t\t5\n#define KEY_5\t\t\t6\n#define KEY_6\t\t\t7\n#define KEY_7\t\t\t8\n#define KEY_8\t\t\t9\n#define KEY_9\t\t\t10\n#define KEY_0\t\t\t11\n#define KEY_MINUS\t\t12\n#define KEY_EQUAL\t\t13\n#define KEY_BACKSPACE\t\t14\n#define KEY_TAB\t\t\t15\n#define KEY_Q\t\t\t16\n#define KEY_W\t\t\t17\n#define KEY_E\t\t\t18\n#define KEY_R\t\t\t19\n#define KEY_T\t\t\t20\n#define KEY_Y\t\t\t21\n#define KEY_U\t\t\t22\n#define KEY_I\t\t\t23\n#define KEY_O\t\t\t24\n#define KEY_P\t\t\t25\n#define KEY_LEFTBRACE\t\t26\n#define KEY_RIGHTBRACE\t\t27\n#define KEY_ENTER\t\t28\n#define KEY_LEFTCTRL\t\t29\n#define KEY_A\t\t\t30\n#define KEY_S\t\t\t31\n#define KEY_D\t\t\t32\n#define KEY_F\t\t\t33\n#define KEY_G\t\t\t34\n#define KEY_H\t\t\t35\n#define KEY_J\t\t\t36\n#define KEY_K\t\t\t37\n#define KEY_L\t\t\t38\n#define KEY_SEMICOLON\t\t39\n#define KEY_APOSTROPHE\t\t40\n#define KEY_GRAVE\t\t41\n#define KEY_LEFTSHIFT\t\t42\n#define KEY_BACKSLASH\t\t43\n#define KEY_Z\t\t\t44\n#define KEY_X\t\t\t45\n#define KEY_C\t\t\t46\n#define KEY_V\t\t\t47\n#define KEY_B\t\t\t48\n#define KEY_N\t\t\t49\n#define KEY_M\t\t\t50\n#define KEY_COMMA\t\t51\n#define KEY_DOT\t\t\t52\n#define KEY_SLASH\t\t53\n#define KEY_RIGHTSHIFT\t\t54\n#define KEY_KPASTERISK\t\t55\n#define KEY_LEFTALT\t\t56\n#define KEY_SPACE\t\t57\n#define KEY_CAPSLOCK\t\t58\n#define KEY_F1\t\t\t59\n#define KEY_F2\t\t\t60\n#define KEY_F3\t\t\t61\n#define KEY_F4\t\t\t62\n#define KEY_F5\t\t\t63\n#define KEY_F6\t\t\t64\n#define KEY_F7\t\t\t65\n#define KEY_F8\t\t\t66\n#define KEY_F9\t\t\t67\n#define KEY_F10\t\t\t68\n#define KEY_NUMLOCK\t\t69\n#define KEY_SCROLLLOCK\t\t70\n#define KEY_KP7\t\t\t71\n#define KEY_KP8\t\t\t72\n#define KEY_KP9\t\t\t73\n#define KEY_KPMINUS\t\t74\n#define KEY_KP4\t\t\t75\n#define KEY_KP5\t\t\t76\n#define KEY_KP6\t\t\t77\n#define KEY_KPPLUS\t\t78\n#define KEY_KP1\t\t\t79\n#define KEY_KP2\t\t\t80\n#define KEY_KP3\t\t\t81\n#define KEY_KP0\t\t\t82\n#define KEY_KPDOT\t\t83\n\n#define KEY_ZENKAKUHANKAKU\t85\n#define KEY_102ND\t\t86\n#define KEY_F11\t\t\t87\n#define KEY_F12\t\t\t88\n#define KEY_RO\t\t\t89\n#define KEY_KATAKANA\t\t90\n#define KEY_HIRAGANA\t\t91\n#define KEY_HENKAN\t\t92\n#define KEY_KATAKANAHIRAGANA\t93\n#define KEY_MUHENKAN\t\t94\n#define KEY_KPJPCOMMA\t\t95\n#define KEY_KPENTER\t\t96\n#define KEY_RIGHTCTRL\t\t97\n#define KEY_KPSLASH\t\t98\n#define KEY_SYSRQ\t\t99\n#define KEY_RIGHTALT\t\t100\n#define KEY_LINEFEED\t\t101\n#define KEY_HOME\t\t102\n#define KEY_UP\t\t\t103\n#define KEY_PAGEUP\t\t104\n#define KEY_LEFT\t\t105\n#define KEY_RIGHT\t\t106\n#define KEY_END\t\t\t107\n#define KEY_DOWN\t\t108\n#define KEY_PAGEDOWN\t\t109\n#define KEY_INSERT\t\t110\n#define KEY_DELETE\t\t111\n#define KEY_MACRO\t\t112\n#define KEY_MUTE\t\t113\n#define KEY_VOLUMEDOWN\t\t114\n#define KEY_VOLUMEUP\t\t115\n#define KEY_POWER\t\t116\t/* SC System Power Down */\n#define KEY_KPEQUAL\t\t117\n#define KEY_KPPLUSMINUS\t\t118\n#define KEY_PAUSE\t\t119\n#define KEY_SCALE\t\t120\t/* AL Compiz Scale (Expose) */\n\n#define KEY_KPCOMMA\t\t121\n#define KEY_HANGEUL\t\t122\n#define KEY_HANGUEL\t\tKEY_HANGEUL\n#define KEY_HANJA\t\t123\n#define KEY_YEN\t\t\t124\n#define KEY_LEFTMETA\t\t125\n#define KEY_RIGHTMETA\t\t126\n#define KEY_COMPOSE\t\t127\n#define KEY_STOP\t\t128\t/* AC Stop */\n#define KEY_AGAIN\t\t129\n#define KEY_PROPS\t\t130\t/* AC Properties */\n#define KEY_UNDO\t\t131\t/* AC Undo */\n#define KEY_FRONT\t\t132\n#define KEY_COPY\t\t133\t/* AC Copy */\n#define KEY_OPEN\t\t134\t/* AC Open */\n#define KEY_PASTE\t\t135\t/* AC Paste */\n#define KEY_FIND\t\t136\t/* AC Search */\n#define KEY_CUT\t\t\t137\t/* AC Cut */\n#define KEY_HELP\t\t138\t/* AL Integrated Help Center */\n#define KEY_MENU\t\t139\t/* Menu (show menu) */\n#define KEY_CALC\t\t140\t/* AL Calculator */\n#define KEY_SETUP\t\t141\n#define KEY_SLEEP\t\t142\t/* SC System Sleep */\n#define KEY_WAKEUP\t\t143\t/* System Wake Up */\n#define KEY_FILE\t\t144\t/* AL Local Machine Browser */\n#define KEY_SENDFILE\t\t145\n#define KEY_DELETEFILE\t\t146\n#define KEY_XFER\t\t147\n#define KEY_PROG1\t\t148\n#define KEY_PROG2\t\t149\n#define KEY_WWW\t\t\t150\t/* AL Internet Browser */\n#define KEY_MSDOS\t\t151\n#define KEY_COFFEE\t\t152\t/* AL Terminal Lock/Screensaver */\n#define KEY_SCREENLOCK\t\tKEY_COFFEE\n#define KEY_ROTATE_DISPLAY\t153\t/* Display orientation for e.g. tablets */\n#define KEY_DIRECTION\t\tKEY_ROTATE_DISPLAY\n#define KEY_CYCLEWINDOWS\t154\n#define KEY_MAIL\t\t155\n#define KEY_BOOKMARKS\t\t156\t/* AC Bookmarks */\n#define KEY_COMPUTER\t\t157\n#define KEY_BACK\t\t158\t/* AC Back */\n#define KEY_FORWARD\t\t159\t/* AC Forward */\n#define KEY_CLOSECD\t\t160\n#define KEY_EJECTCD\t\t161\n#define KEY_EJECTCLOSECD\t162\n#define KEY_NEXTSONG\t\t163\n#define KEY_PLAYPAUSE\t\t164\n#define KEY_PREVIOUSSONG\t165\n#define KEY_STOPCD\t\t166\n#define KEY_RECORD\t\t167\n#define KEY_REWIND\t\t168\n#define KEY_PHONE\t\t169\t/* Media Select Telephone */\n#define KEY_ISO\t\t\t170\n#define KEY_CONFIG\t\t171\t/* AL Consumer Control Configuration */\n#define KEY_HOMEPAGE\t\t172\t/* AC Home */\n#define KEY_REFRESH\t\t173\t/* AC Refresh */\n#define KEY_EXIT\t\t174\t/* AC Exit */\n#define KEY_MOVE\t\t175\n#define KEY_EDIT\t\t176\n#define KEY_SCROLLUP\t\t177\n#define KEY_SCROLLDOWN\t\t178\n#define KEY_KPLEFTPAREN\t\t179\n#define KEY_KPRIGHTPAREN\t180\n#define KEY_NEW\t\t\t181\t/* AC New */\n#define KEY_REDO\t\t182\t/* AC Redo/Repeat */\n\n#define KEY_F13\t\t\t183\n#define KEY_F14\t\t\t184\n#define KEY_F15\t\t\t185\n#define KEY_F16\t\t\t186\n#define KEY_F17\t\t\t187\n#define KEY_F18\t\t\t188\n#define KEY_F19\t\t\t189\n#define KEY_F20\t\t\t190\n#define KEY_F21\t\t\t191\n#define KEY_F22\t\t\t192\n#define KEY_F23\t\t\t193\n#define KEY_F24\t\t\t194\n\n#define KEY_PLAYCD\t\t200\n#define KEY_PAUSECD\t\t201\n#define KEY_PROG3\t\t202\n#define KEY_PROG4\t\t203\n#define KEY_DASHBOARD\t\t204\t/* AL Dashboard */\n#define KEY_SUSPEND\t\t205\n#define KEY_CLOSE\t\t206\t/* AC Close */\n#define KEY_PLAY\t\t207\n#define KEY_FASTFORWARD\t\t208\n#define KEY_BASSBOOST\t\t209\n#define KEY_PRINT\t\t210\t/* AC Print */\n#define KEY_HP\t\t\t211\n#define KEY_CAMERA\t\t212\n#define KEY_SOUND\t\t213\n#define KEY_QUESTION\t\t214\n#define KEY_EMAIL\t\t215\n#define KEY_CHAT\t\t216\n#define KEY_SEARCH\t\t217\n#define KEY_CONNECT\t\t218\n#define KEY_FINANCE\t\t219\t/* AL Checkbook/Finance */\n#define KEY_SPORT\t\t220\n#define KEY_SHOP\t\t221\n#define KEY_ALTERASE\t\t222\n#define KEY_CANCEL\t\t223\t/* AC Cancel */\n#define KEY_BRIGHTNESSDOWN\t224\n#define KEY_BRIGHTNESSUP\t225\n#define KEY_MEDIA\t\t226\n\n#define KEY_SWITCHVIDEOMODE\t227\t/* Cycle between available video\n\t\t\t\t\t outputs (Monitor/LCD/TV-out/etc) */\n#define KEY_KBDILLUMTOGGLE\t228\n#define KEY_KBDILLUMDOWN\t229\n#define KEY_KBDILLUMUP\t\t230\n\n#define KEY_SEND\t\t231\t/* AC Send */\n#define KEY_REPLY\t\t232\t/* AC Reply */\n#define KEY_FORWARDMAIL\t\t233\t/* AC Forward Msg */\n#define KEY_SAVE\t\t234\t/* AC Save */\n#define KEY_DOCUMENTS\t\t235\n\n#define KEY_BATTERY\t\t236\n\n#define KEY_BLUETOOTH\t\t237\n#define KEY_WLAN\t\t238\n#define KEY_UWB\t\t\t239\n\n#define KEY_UNKNOWN\t\t240\n#define KEY_VIDEO_NEXT\t\t241\t/* drive next video source */\n#define KEY_VIDEO_PREV\t\t242\t/* drive previous video source */\n#define KEY_BRIGHTNESS_CYCLE\t243\t/* brightness up, after max is min */\n#define KEY_BRIGHTNESS_AUTO\t244\t/* Set Auto Brightness: manual\n\t\t\t\t\t brightness control is off,\n\t\t\t\t\t rely on ambient */\n#define KEY_BRIGHTNESS_ZERO\tKEY_BRIGHTNESS_AUTO\n#define KEY_DISPLAY_OFF\t\t245\t/* display device to off state */\n\n#define KEY_WWAN\t\t246\t/* Wireless WAN (LTE, UMTS, GSM, etc.) */\n#define KEY_WIMAX\t\tKEY_WWAN\n#define KEY_RFKILL\t\t247\t/* Key that controls all radios */\n\n#define KEY_MICMUTE\t\t248\t/* Mute / unmute the microphone */\n\n/* Code 255 is reserved for special needs of AT keyboard driver */\n\n#define BTN_MISC\t\t0x100\n#define BTN_0\t\t\t0x100\n#define BTN_1\t\t\t0x101\n#define BTN_2\t\t\t0x102\n#define BTN_3\t\t\t0x103\n#define BTN_4\t\t\t0x104\n#define BTN_5\t\t\t0x105\n#define BTN_6\t\t\t0x106\n#define BTN_7\t\t\t0x107\n#define BTN_8\t\t\t0x108\n#define BTN_9\t\t\t0x109\n\n#define BTN_MOUSE\t\t0x110\n#define BTN_LEFT\t\t0x110\n#define BTN_RIGHT\t\t0x111\n#define BTN_MIDDLE\t\t0x112\n#define BTN_SIDE\t\t0x113\n#define BTN_EXTRA\t\t0x114\n#define BTN_FORWARD\t\t0x115\n#define BTN_BACK\t\t0x116\n#define BTN_TASK\t\t0x117\n\n#define BTN_JOYSTICK\t\t0x120\n#define BTN_TRIGGER\t\t0x120\n#define BTN_THUMB\t\t0x121\n#define BTN_THUMB2\t\t0x122\n#define BTN_TOP\t\t\t0x123\n#define BTN_TOP2\t\t0x124\n#define BTN_PINKIE\t\t0x125\n#define BTN_BASE\t\t0x126\n#define BTN_BASE2\t\t0x127\n#define BTN_BASE3\t\t0x128\n#define BTN_BASE4\t\t0x129\n#define BTN_BASE5\t\t0x12a\n#define BTN_BASE6\t\t0x12b\n#define BTN_DEAD\t\t0x12f\n\n#define BTN_GAMEPAD\t\t0x130\n#define BTN_SOUTH\t\t0x130\n#define BTN_A\t\t\tBTN_SOUTH\n#define BTN_EAST\t\t0x131\n#define BTN_B\t\t\tBTN_EAST\n#define BTN_C\t\t\t0x132\n#define BTN_NORTH\t\t0x133\n#define BTN_X\t\t\tBTN_NORTH\n#define BTN_WEST\t\t0x134\n#define BTN_Y\t\t\tBTN_WEST\n#define BTN_Z\t\t\t0x135\n#define BTN_TL\t\t\t0x136\n#define BTN_TR\t\t\t0x137\n#define BTN_TL2\t\t\t0x138\n#define BTN_TR2\t\t\t0x139\n#define BTN_SELECT\t\t0x13a\n#define BTN_START\t\t0x13b\n#define BTN_MODE\t\t0x13c\n#define BTN_THUMBL\t\t0x13d\n#define BTN_THUMBR\t\t0x13e\n\n#define BTN_DIGI\t\t0x140\n#define BTN_TOOL_PEN\t\t0x140\n#define BTN_TOOL_RUBBER\t\t0x141\n#define BTN_TOOL_BRUSH\t\t0x142\n#define BTN_TOOL_PENCIL\t\t0x143\n#define BTN_TOOL_AIRBRUSH\t0x144\n#define BTN_TOOL_FINGER\t\t0x145\n#define BTN_TOOL_MOUSE\t\t0x146\n#define BTN_TOOL_LENS\t\t0x147\n#define BTN_TOOL_QUINTTAP\t0x148\t/* Five fingers on trackpad */\n#define BTN_TOUCH\t\t0x14a\n#define BTN_STYLUS\t\t0x14b\n#define BTN_STYLUS2\t\t0x14c\n#define BTN_TOOL_DOUBLETAP\t0x14d\n#define BTN_TOOL_TRIPLETAP\t0x14e\n#define BTN_TOOL_QUADTAP\t0x14f\t/* Four fingers on trackpad */\n\n#define BTN_WHEEL\t\t0x150\n#define BTN_GEAR_DOWN\t\t0x150\n#define BTN_GEAR_UP\t\t0x151\n\n#define KEY_OK\t\t\t0x160\n#define KEY_SELECT\t\t0x161\n#define KEY_GOTO\t\t0x162\n#define KEY_CLEAR\t\t0x163\n#define KEY_POWER2\t\t0x164\n#define KEY_OPTION\t\t0x165\n#define KEY_INFO\t\t0x166\t/* AL OEM Features/Tips/Tutorial */\n#define KEY_TIME\t\t0x167\n#define KEY_VENDOR\t\t0x168\n#define KEY_ARCHIVE\t\t0x169\n#define KEY_PROGRAM\t\t0x16a\t/* Media Select Program Guide */\n#define KEY_CHANNEL\t\t0x16b\n#define KEY_FAVORITES\t\t0x16c\n#define KEY_EPG\t\t\t0x16d\n#define KEY_PVR\t\t\t0x16e\t/* Media Select Home */\n#define KEY_MHP\t\t\t0x16f\n#define KEY_LANGUAGE\t\t0x170\n#define KEY_TITLE\t\t0x171\n#define KEY_SUBTITLE\t\t0x172\n#define KEY_ANGLE\t\t0x173\n#define KEY_ZOOM\t\t0x174\n#define KEY_MODE\t\t0x175\n#define KEY_KEYBOARD\t\t0x176\n#define KEY_SCREEN\t\t0x177\n#define KEY_PC\t\t\t0x178\t/* Media Select Computer */\n#define KEY_TV\t\t\t0x179\t/* Media Select TV */\n#define KEY_TV2\t\t\t0x17a\t/* Media Select Cable */\n#define KEY_VCR\t\t\t0x17b\t/* Media Select VCR */\n#define KEY_VCR2\t\t0x17c\t/* VCR Plus */\n#define KEY_SAT\t\t\t0x17d\t/* Media Select Satellite */\n#define KEY_SAT2\t\t0x17e\n#define KEY_CD\t\t\t0x17f\t/* Media Select CD */\n#define KEY_TAPE\t\t0x180\t/* Media Select Tape */\n#define KEY_RADIO\t\t0x181\n#define KEY_TUNER\t\t0x182\t/* Media Select Tuner */\n#define KEY_PLAYER\t\t0x183\n#define KEY_TEXT\t\t0x184\n#define KEY_DVD\t\t\t0x185\t/* Media Select DVD */\n#define KEY_AUX\t\t\t0x186\n#define KEY_MP3\t\t\t0x187\n#define KEY_AUDIO\t\t0x188\t/* AL Audio Browser */\n#define KEY_VIDEO\t\t0x189\t/* AL Movie Browser */\n#define KEY_DIRECTORY\t\t0x18a\n#define KEY_LIST\t\t0x18b\n#define KEY_MEMO\t\t0x18c\t/* Media Select Messages */\n#define KEY_CALENDAR\t\t0x18d\n#define KEY_RED\t\t\t0x18e\n#define KEY_GREEN\t\t0x18f\n#define KEY_YELLOW\t\t0x190\n#define KEY_BLUE\t\t0x191\n#define KEY_CHANNELUP\t\t0x192\t/* Channel Increment */\n#define KEY_CHANNELDOWN\t\t0x193\t/* Channel Decrement */\n#define KEY_FIRST\t\t0x194\n#define KEY_LAST\t\t0x195\t/* Recall Last */\n#define KEY_AB\t\t\t0x196\n#define KEY_NEXT\t\t0x197\n#define KEY_RESTART\t\t0x198\n#define KEY_SLOW\t\t0x199\n#define KEY_SHUFFLE\t\t0x19a\n#define KEY_BREAK\t\t0x19b\n#define KEY_PREVIOUS\t\t0x19c\n#define KEY_DIGITS\t\t0x19d\n#define KEY_TEEN\t\t0x19e\n#define KEY_TWEN\t\t0x19f\n#define KEY_VIDEOPHONE\t\t0x1a0\t/* Media Select Video Phone */\n#define KEY_GAMES\t\t0x1a1\t/* Media Select Games */\n#define KEY_ZOOMIN\t\t0x1a2\t/* AC Zoom In */\n#define KEY_ZOOMOUT\t\t0x1a3\t/* AC Zoom Out */\n#define KEY_ZOOMRESET\t\t0x1a4\t/* AC Zoom */\n#define KEY_WORDPROCESSOR\t0x1a5\t/* AL Word Processor */\n#define KEY_EDITOR\t\t0x1a6\t/* AL Text Editor */\n#define KEY_SPREADSHEET\t\t0x1a7\t/* AL Spreadsheet */\n#define KEY_GRAPHICSEDITOR\t0x1a8\t/* AL Graphics Editor */\n#define KEY_PRESENTATION\t0x1a9\t/* AL Presentation App */\n#define KEY_DATABASE\t\t0x1aa\t/* AL Database App */\n#define KEY_NEWS\t\t0x1ab\t/* AL Newsreader */\n#define KEY_VOICEMAIL\t\t0x1ac\t/* AL Voicemail */\n#define KEY_ADDRESSBOOK\t\t0x1ad\t/* AL Contacts/Address Book */\n#define KEY_MESSENGER\t\t0x1ae\t/* AL Instant Messaging */\n#define KEY_DISPLAYTOGGLE\t0x1af\t/* Turn display (LCD) on and off */\n#define KEY_BRIGHTNESS_TOGGLE\tKEY_DISPLAYTOGGLE\n#define KEY_SPELLCHECK\t\t0x1b0 /* AL Spell Check */\n#define KEY_LOGOFF\t\t0x1b1 /* AL Logoff */\n\n#define KEY_DOLLAR\t\t0x1b2\n#define KEY_EURO\t\t0x1b3\n\n#define KEY_FRAMEBACK\t\t0x1b4\t/* Consumer - transport controls */\n#define KEY_FRAMEFORWARD\t0x1b5\n#define KEY_CONTEXT_MENU\t0x1b6\t/* GenDesc - system context menu */\n#define KEY_MEDIA_REPEAT\t0x1b7\t/* Consumer - transport control */\n#define KEY_10CHANNELSUP\t0x1b8\t/* 10 channels up (10+) */\n#define KEY_10CHANNELSDOWN\t0x1b9\t/* 10 channels down (10-) */\n#define KEY_IMAGES\t\t0x1ba\t/* AL Image Browser */\n\n#define KEY_DEL_EOL\t\t0x1c0\n#define KEY_DEL_EOS\t\t0x1c1\n#define KEY_INS_LINE\t\t0x1c2\n#define KEY_DEL_LINE\t\t0x1c3\n\n#define KEY_FN\t\t\t0x1d0\n#define KEY_FN_ESC\t\t0x1d1\n#define KEY_FN_F1\t\t0x1d2\n#define KEY_FN_F2\t\t0x1d3\n#define KEY_FN_F3\t\t0x1d4\n#define KEY_FN_F4\t\t0x1d5\n#define KEY_FN_F5\t\t0x1d6\n#define KEY_FN_F6\t\t0x1d7\n#define KEY_FN_F7\t\t0x1d8\n#define KEY_FN_F8\t\t0x1d9\n#define KEY_FN_F9\t\t0x1da\n#define KEY_FN_F10\t\t0x1db\n#define KEY_FN_F11\t\t0x1dc\n#define KEY_FN_F12\t\t0x1dd\n#define KEY_FN_1\t\t0x1de\n#define KEY_FN_2\t\t0x1df\n#define KEY_FN_D\t\t0x1e0\n#define KEY_FN_E\t\t0x1e1\n#define KEY_FN_F\t\t0x1e2\n#define KEY_FN_S\t\t0x1e3\n#define KEY_FN_B\t\t0x1e4\n\n#define KEY_BRL_DOT1\t\t0x1f1\n#define KEY_BRL_DOT2\t\t0x1f2\n#define KEY_BRL_DOT3\t\t0x1f3\n#define KEY_BRL_DOT4\t\t0x1f4\n#define KEY_BRL_DOT5\t\t0x1f5\n#define KEY_BRL_DOT6\t\t0x1f6\n#define KEY_BRL_DOT7\t\t0x1f7\n#define KEY_BRL_DOT8\t\t0x1f8\n#define KEY_BRL_DOT9\t\t0x1f9\n#define KEY_BRL_DOT10\t\t0x1fa\n\n#define KEY_NUMERIC_0\t\t0x200\t/* used by phones, remote controls, */\n#define KEY_NUMERIC_1\t\t0x201\t/* and other keypads */\n#define KEY_NUMERIC_2\t\t0x202\n#define KEY_NUMERIC_3\t\t0x203\n#define KEY_NUMERIC_4\t\t0x204\n#define KEY_NUMERIC_5\t\t0x205\n#define KEY_NUMERIC_6\t\t0x206\n#define KEY_NUMERIC_7\t\t0x207\n#define KEY_NUMERIC_8\t\t0x208\n#define KEY_NUMERIC_9\t\t0x209\n#define KEY_NUMERIC_STAR\t0x20a\n#define KEY_NUMERIC_POUND\t0x20b\n#define KEY_NUMERIC_A\t\t0x20c\t/* Phone key A - HUT Telephony 0xb9 */\n#define KEY_NUMERIC_B\t\t0x20d\n#define KEY_NUMERIC_C\t\t0x20e\n#define KEY_NUMERIC_D\t\t0x20f\n\n#define KEY_CAMERA_FOCUS\t0x210\n#define KEY_WPS_BUTTON\t\t0x211\t/* WiFi Protected Setup key */\n\n#define KEY_TOUCHPAD_TOGGLE\t0x212\t/* Request switch touchpad on or off */\n#define KEY_TOUCHPAD_ON\t\t0x213\n#define KEY_TOUCHPAD_OFF\t0x214\n\n#define KEY_CAMERA_ZOOMIN\t0x215\n#define KEY_CAMERA_ZOOMOUT\t0x216\n#define KEY_CAMERA_UP\t\t0x217\n#define KEY_CAMERA_DOWN\t\t0x218\n#define KEY_CAMERA_LEFT\t\t0x219\n#define KEY_CAMERA_RIGHT\t0x21a\n\n#define KEY_ATTENDANT_ON\t0x21b\n#define KEY_ATTENDANT_OFF\t0x21c\n#define KEY_ATTENDANT_TOGGLE\t0x21d\t/* Attendant call on or off */\n#define KEY_LIGHTS_TOGGLE\t0x21e\t/* Reading light on or off */\n\n#define BTN_DPAD_UP\t\t0x220\n#define BTN_DPAD_DOWN\t\t0x221\n#define BTN_DPAD_LEFT\t\t0x222\n#define BTN_DPAD_RIGHT\t\t0x223\n\n#define KEY_ALS_TOGGLE\t\t0x230\t/* Ambient light sensor */\n\n#define KEY_BUTTONCONFIG\t\t0x240\t/* AL Button Configuration */\n#define KEY_TASKMANAGER\t\t0x241\t/* AL Task/Project Manager */\n#define KEY_JOURNAL\t\t0x242\t/* AL Log/Journal/Timecard */\n#define KEY_CONTROLPANEL\t\t0x243\t/* AL Control Panel */\n#define KEY_APPSELECT\t\t0x244\t/* AL Select Task/Application */\n#define KEY_SCREENSAVER\t\t0x245\t/* AL Screen Saver */\n#define KEY_VOICECOMMAND\t\t0x246\t/* Listening Voice Command */\n\n#define KEY_BRIGHTNESS_MIN\t\t0x250\t/* Set Brightness to Minimum */\n#define KEY_BRIGHTNESS_MAX\t\t0x251\t/* Set Brightness to Maximum */\n\n#define KEY_KBDINPUTASSIST_PREV\t\t0x260\n#define KEY_KBDINPUTASSIST_NEXT\t\t0x261\n#define KEY_KBDINPUTASSIST_PREVGROUP\t\t0x262\n#define KEY_KBDINPUTASSIST_NEXTGROUP\t\t0x263\n#define KEY_KBDINPUTASSIST_ACCEPT\t\t0x264\n#define KEY_KBDINPUTASSIST_CANCEL\t\t0x265\n\n#define BTN_TRIGGER_HAPPY\t\t0x2c0\n#define BTN_TRIGGER_HAPPY1\t\t0x2c0\n#define BTN_TRIGGER_HAPPY2\t\t0x2c1\n#define BTN_TRIGGER_HAPPY3\t\t0x2c2\n#define BTN_TRIGGER_HAPPY4\t\t0x2c3\n#define BTN_TRIGGER_HAPPY5\t\t0x2c4\n#define BTN_TRIGGER_HAPPY6\t\t0x2c5\n#define BTN_TRIGGER_HAPPY7\t\t0x2c6\n#define BTN_TRIGGER_HAPPY8\t\t0x2c7\n#define BTN_TRIGGER_HAPPY9\t\t0x2c8\n#define BTN_TRIGGER_HAPPY10\t\t0x2c9\n#define BTN_TRIGGER_HAPPY11\t\t0x2ca\n#define BTN_TRIGGER_HAPPY12\t\t0x2cb\n#define BTN_TRIGGER_HAPPY13\t\t0x2cc\n#define BTN_TRIGGER_HAPPY14\t\t0x2cd\n#define BTN_TRIGGER_HAPPY15\t\t0x2ce\n#define BTN_TRIGGER_HAPPY16\t\t0x2cf\n#define BTN_TRIGGER_HAPPY17\t\t0x2d0\n#define BTN_TRIGGER_HAPPY18\t\t0x2d1\n#define BTN_TRIGGER_HAPPY19\t\t0x2d2\n#define BTN_TRIGGER_HAPPY20\t\t0x2d3\n#define BTN_TRIGGER_HAPPY21\t\t0x2d4\n#define BTN_TRIGGER_HAPPY22\t\t0x2d5\n#define BTN_TRIGGER_HAPPY23\t\t0x2d6\n#define BTN_TRIGGER_HAPPY24\t\t0x2d7\n#define BTN_TRIGGER_HAPPY25\t\t0x2d8\n#define BTN_TRIGGER_HAPPY26\t\t0x2d9\n#define BTN_TRIGGER_HAPPY27\t\t0x2da\n#define BTN_TRIGGER_HAPPY28\t\t0x2db\n#define BTN_TRIGGER_HAPPY29\t\t0x2dc\n#define BTN_TRIGGER_HAPPY30\t\t0x2dd\n#define BTN_TRIGGER_HAPPY31\t\t0x2de\n#define BTN_TRIGGER_HAPPY32\t\t0x2df\n#define BTN_TRIGGER_HAPPY33\t\t0x2e0\n#define BTN_TRIGGER_HAPPY34\t\t0x2e1\n#define BTN_TRIGGER_HAPPY35\t\t0x2e2\n#define BTN_TRIGGER_HAPPY36\t\t0x2e3\n#define BTN_TRIGGER_HAPPY37\t\t0x2e4\n#define BTN_TRIGGER_HAPPY38\t\t0x2e5\n#define BTN_TRIGGER_HAPPY39\t\t0x2e6\n#define BTN_TRIGGER_HAPPY40\t\t0x2e7\n\n/* We avoid low common keys in module aliases so they don't get huge. */\n#define KEY_MIN_INTERESTING\tKEY_MUTE\n#define KEY_MAX\t\t\t0x2ff\n#define KEY_CNT\t\t\t(KEY_MAX+1)\n\n/*\n * Relative axes\n */\n\n#define REL_X\t\t\t0x00\n#define REL_Y\t\t\t0x01\n#define REL_Z\t\t\t0x02\n#define REL_RX\t\t\t0x03\n#define REL_RY\t\t\t0x04\n#define REL_RZ\t\t\t0x05\n#define REL_HWHEEL\t\t0x06\n#define REL_DIAL\t\t0x07\n#define REL_WHEEL\t\t0x08\n#define REL_MISC\t\t0x09\n#define REL_MAX\t\t\t0x0f\n#define REL_CNT\t\t\t(REL_MAX+1)\n\n/*\n * Absolute axes\n */\n\n#define ABS_X\t\t\t0x00\n#define ABS_Y\t\t\t0x01\n#define ABS_Z\t\t\t0x02\n#define ABS_RX\t\t\t0x03\n#define ABS_RY\t\t\t0x04\n#define ABS_RZ\t\t\t0x05\n#define ABS_THROTTLE\t\t0x06\n#define ABS_RUDDER\t\t0x07\n#define ABS_WHEEL\t\t0x08\n#define ABS_GAS\t\t\t0x09\n#define ABS_BRAKE\t\t0x0a\n#define ABS_HAT0X\t\t0x10\n#define ABS_HAT0Y\t\t0x11\n#define ABS_HAT1X\t\t0x12\n#define ABS_HAT1Y\t\t0x13\n#define ABS_HAT2X\t\t0x14\n#define ABS_HAT2Y\t\t0x15\n#define ABS_HAT3X\t\t0x16\n#define ABS_HAT3Y\t\t0x17\n#define ABS_PRESSURE\t\t0x18\n#define ABS_DISTANCE\t\t0x19\n#define ABS_TILT_X\t\t0x1a\n#define ABS_TILT_Y\t\t0x1b\n#define ABS_TOOL_WIDTH\t\t0x1c\n\n#define ABS_VOLUME\t\t0x20\n\n#define ABS_MISC\t\t0x28\n\n#define ABS_MT_SLOT\t\t0x2f\t/* MT slot being modified */\n#define ABS_MT_TOUCH_MAJOR\t0x30\t/* Major axis of touching ellipse */\n#define ABS_MT_TOUCH_MINOR\t0x31\t/* Minor axis (omit if circular) */\n#define ABS_MT_WIDTH_MAJOR\t0x32\t/* Major axis of approaching ellipse */\n#define ABS_MT_WIDTH_MINOR\t0x33\t/* Minor axis (omit if circular) */\n#define ABS_MT_ORIENTATION\t0x34\t/* Ellipse orientation */\n#define ABS_MT_POSITION_X\t0x35\t/* Center X touch position */\n#define ABS_MT_POSITION_Y\t0x36\t/* Center Y touch position */\n#define ABS_MT_TOOL_TYPE\t0x37\t/* Type of touching device */\n#define ABS_MT_BLOB_ID\t\t0x38\t/* Group a set of packets as a blob */\n#define ABS_MT_TRACKING_ID\t0x39\t/* Unique ID of initiated contact */\n#define ABS_MT_PRESSURE\t\t0x3a\t/* Pressure on contact area */\n#define ABS_MT_DISTANCE\t\t0x3b\t/* Contact hover distance */\n#define ABS_MT_TOOL_X\t\t0x3c\t/* Center X tool position */\n#define ABS_MT_TOOL_Y\t\t0x3d\t/* Center Y tool position */\n\n\n#define ABS_MAX\t\t\t0x3f\n#define ABS_CNT\t\t\t(ABS_MAX+1)\n\n/*\n * Switch events\n */\n\n#define SW_LID\t\t\t0x00 /* set = lid shut */\n#define SW_TABLET_MODE\t\t0x01 /* set = tablet mode */\n#define SW_HEADPHONE_INSERT\t0x02 /* set = inserted */\n#define SW_RFKILL_ALL\t\t0x03 /* rfkill master switch, type \"any\"\n\t\t\t\t\t set = radio enabled */\n#define SW_RADIO\t\tSW_RFKILL_ALL\t/* deprecated */\n#define SW_MICROPHONE_INSERT\t0x04 /* set = inserted */\n#define SW_DOCK\t\t\t0x05 /* set = plugged into dock */\n#define SW_LINEOUT_INSERT\t0x06 /* set = inserted */\n#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */\n#define SW_VIDEOOUT_INSERT\t0x08 /* set = inserted */\n#define SW_CAMERA_LENS_COVER\t0x09 /* set = lens covered */\n#define SW_KEYPAD_SLIDE\t\t0x0a /* set = keypad slide out */\n#define SW_FRONT_PROXIMITY\t0x0b /* set = front proximity sensor active */\n#define SW_ROTATE_LOCK\t\t0x0c /* set = rotate locked/disabled */\n#define SW_LINEIN_INSERT\t0x0d /* set = inserted */\n#define SW_MUTE_DEVICE\t\t0x0e /* set = device disabled */\n#define SW_MAX\t\t\t0x0f\n#define SW_CNT\t\t\t(SW_MAX+1)\n\n/*\n * Misc events\n */\n\n#define MSC_SERIAL\t\t0x00\n#define MSC_PULSELED\t\t0x01\n#define MSC_GESTURE\t\t0x02\n#define MSC_RAW\t\t\t0x03\n#define MSC_SCAN\t\t0x04\n#define MSC_TIMESTAMP\t\t0x05\n#define MSC_MAX\t\t\t0x07\n#define MSC_CNT\t\t\t(MSC_MAX+1)\n\n/*\n * LEDs\n */\n\n#define LED_NUML\t\t0x00\n#define LED_CAPSL\t\t0x01\n#define LED_SCROLLL\t\t0x02\n#define LED_COMPOSE\t\t0x03\n#define LED_KANA\t\t0x04\n#define LED_SLEEP\t\t0x05\n#define LED_SUSPEND\t\t0x06\n#define LED_MUTE\t\t0x07\n#define LED_MISC\t\t0x08\n#define LED_MAIL\t\t0x09\n#define LED_CHARGING\t\t0x0a\n#define LED_MAX\t\t\t0x0f\n#define LED_CNT\t\t\t(LED_MAX+1)\n\n/*\n * Autorepeat values\n */\n\n#define REP_DELAY\t\t0x00\n#define REP_PERIOD\t\t0x01\n#define REP_MAX\t\t\t0x01\n#define REP_CNT\t\t\t(REP_MAX+1)\n\n/*\n * Sounds\n */\n\n#define SND_CLICK\t\t0x00\n#define SND_BELL\t\t0x01\n#define SND_TONE\t\t0x02\n#define SND_MAX\t\t\t0x07\n#define SND_CNT\t\t\t(SND_MAX+1)\n\n#define MATRIX_KEY(row, col, code)\t\\\n\t((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))\n\n#endif /* _DT_BINDINGS_INPUT_INPUT_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/interrupt-controller/irq.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most IRQ bindings.\n *\n * Most IRQ bindings include a flags cell as part of the IRQ specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n\n#define IRQ_TYPE_NONE\t\t0\n#define IRQ_TYPE_EDGE_RISING\t1\n#define IRQ_TYPE_EDGE_FALLING\t2\n#define IRQ_TYPE_EDGE_BOTH\t(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)\n#define IRQ_TYPE_LEVEL_HIGH\t4\n#define IRQ_TYPE_LEVEL_LOW\t8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/net/mscc-phy-vsc8531.h", "content": "/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */\n/*\n * Device Tree constants for Microsemi VSC8531 PHY\n *\n * Author: Nagaraju Lakkaraju\n *\n * Copyright (c) 2017 Microsemi Corporation\n */\n\n#ifndef _DT_BINDINGS_MSCC_VSC8531_H\n#define _DT_BINDINGS_MSCC_VSC8531_H\n\n/* PHY LED Modes */\n#define VSC8531_LINK_ACTIVITY\t\t\t0\n#define VSC8531_LINK_1000_ACTIVITY\t\t1\n#define VSC8531_LINK_100_ACTIVITY\t\t2\n#define VSC8531_LINK_10_ACTIVITY\t\t3\n#define VSC8531_LINK_100_1000_ACTIVITY\t\t4\n#define VSC8531_LINK_10_1000_ACTIVITY\t\t5\n#define VSC8531_LINK_10_100_ACTIVITY\t\t6\n#define VSC8584_LINK_100FX_1000X_ACTIVITY\t7\n#define VSC8531_DUPLEX_COLLISION\t\t8\n#define VSC8531_COLLISION\t\t\t9\n#define VSC8531_ACTIVITY\t\t\t10\n#define VSC8584_100FX_1000X_ACTIVITY\t\t11\n#define VSC8531_AUTONEG_FAULT\t\t\t12\n#define VSC8531_SERIAL_MODE\t\t\t13\n#define VSC8531_FORCE_LED_OFF\t\t\t14\n#define VSC8531_FORCE_LED_ON\t\t\t15\n\n#define VSC8531_RGMII_CLK_DELAY_0_2_NS\t0\n#define VSC8531_RGMII_CLK_DELAY_0_8_NS\t1\n#define VSC8531_RGMII_CLK_DELAY_1_1_NS\t2\n#define VSC8531_RGMII_CLK_DELAY_1_7_NS\t3\n#define VSC8531_RGMII_CLK_DELAY_2_0_NS\t4\n#define VSC8531_RGMII_CLK_DELAY_2_3_NS\t5\n#define VSC8531_RGMII_CLK_DELAY_2_6_NS\t6\n#define VSC8531_RGMII_CLK_DELAY_3_4_NS\t7\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/net/ti-dp83867.h", "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Device Tree constants for the Texas Instruments DP83867 PHY\n *\n * Author: Dan Murphy \n *\n * Copyright: (C) 2015 Texas Instruments, Inc.\n */\n\n#ifndef _DT_BINDINGS_TI_DP83867_H\n#define _DT_BINDINGS_TI_DP83867_H\n\n/* PHY CTRL bits */\n#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB\t0x00\n#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB\t0x01\n#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB\t0x02\n#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB\t0x03\n\n/* RGMIIDCTL internal delay for rx and tx */\n#define\tDP83867_RGMIIDCTL_250_PS\t0x0\n#define\tDP83867_RGMIIDCTL_500_PS\t0x1\n#define\tDP83867_RGMIIDCTL_750_PS\t0x2\n#define\tDP83867_RGMIIDCTL_1_NS\t\t0x3\n#define\tDP83867_RGMIIDCTL_1_25_NS\t0x4\n#define\tDP83867_RGMIIDCTL_1_50_NS\t0x5\n#define\tDP83867_RGMIIDCTL_1_75_NS\t0x6\n#define\tDP83867_RGMIIDCTL_2_00_NS\t0x7\n#define\tDP83867_RGMIIDCTL_2_25_NS\t0x8\n#define\tDP83867_RGMIIDCTL_2_50_NS\t0x9\n#define\tDP83867_RGMIIDCTL_2_75_NS\t0xa\n#define\tDP83867_RGMIIDCTL_3_00_NS\t0xb\n#define\tDP83867_RGMIIDCTL_3_25_NS\t0xc\n#define\tDP83867_RGMIIDCTL_3_50_NS\t0xd\n#define\tDP83867_RGMIIDCTL_3_75_NS\t0xe\n#define\tDP83867_RGMIIDCTL_4_00_NS\t0xf\n\n/* IO_MUX_CFG - Clock output selection */\n#define DP83867_CLK_O_SEL_CHN_A_RCLK\t\t0x0\n#define DP83867_CLK_O_SEL_CHN_B_RCLK\t\t0x1\n#define DP83867_CLK_O_SEL_CHN_C_RCLK\t\t0x2\n#define DP83867_CLK_O_SEL_CHN_D_RCLK\t\t0x3\n#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5\t0x4\n#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5\t0x5\n#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5\t0x6\n#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5\t0x7\n#define DP83867_CLK_O_SEL_CHN_A_TCLK\t\t0x8\n#define DP83867_CLK_O_SEL_CHN_B_TCLK\t\t0x9\n#define DP83867_CLK_O_SEL_CHN_C_TCLK\t\t0xA\n#define DP83867_CLK_O_SEL_CHN_D_TCLK\t\t0xB\n#define DP83867_CLK_O_SEL_REF_CLK\t\t0xC\n/* Special flag to indicate clock should be off */\n#define DP83867_CLK_O_SEL_OFF\t\t\t0xFFFFFFFF\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/phy/phy.h", "content": "/*\n *\n * This header provides constants for the phy framework\n *\n * Copyright (C) 2014 STMicroelectronics\n * Author: Gabriel Fernandez \n * License terms: GNU General Public License (GPL), version 2\n */\n\n#ifndef _DT_BINDINGS_PHY\n#define _DT_BINDINGS_PHY\n\n#define PHY_NONE\t\t0\n#define PHY_TYPE_SATA\t\t1\n#define PHY_TYPE_PCIE\t\t2\n#define PHY_TYPE_USB2\t\t3\n#define PHY_TYPE_USB3\t\t4\n#define PHY_TYPE_UFS\t\t5\n#define PHY_TYPE_DP\t\t6\n#define PHY_TYPE_XPCS\t\t7\n#define PHY_TYPE_SGMII\t\t8\n#define PHY_TYPE_QSGMII\t\t9\n\n#endif /* _DT_BINDINGS_PHY */\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * MIO pin configuration defines for Xilinx ZynqMP\n *\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H\n#define _DT_BINDINGS_PINCTRL_ZYNQMP_H\n\n/* Bit value for different voltage levels */\n#define IO_STANDARD_LVCMOS33\t0\n#define IO_STANDARD_LVCMOS18\t1\n\n/* Bit values for Slew Rates */\n#define SLEW_RATE_FAST\t\t0\n#define SLEW_RATE_SLOW\t\t1\n\n/* Bit values for Pin drive strength */\n#define DRIVE_STRENGTH_2MA\t2\n#define DRIVE_STRENGTH_4MA\t4\n#define DRIVE_STRENGTH_8MA\t8\n#define DRIVE_STRENGTH_12MA\t12\n\n#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-net-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2022-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_NET_POWER_H\n#define _DT_BINDINGS_VERSAL_NET_POWER_H\n\n#include \n\n#define PM_DEV_USB_1\t\t\t\t(0x182240D7U)\n#define PM_DEV_FPD_SWDT_0\t\t\t(0x182240DBU)\n#define PM_DEV_FPD_SWDT_1\t\t\t(0x182240DCU)\n#define PM_DEV_FPD_SWDT_2\t\t\t(0x182240DDU)\n#define PM_DEV_FPD_SWDT_3\t\t\t(0x182240DEU)\n\n/* Remove Versal specific node IDs */\n#undef PM_DEV_RPU0_0\n#undef PM_DEV_RPU0_1\n#undef PM_DEV_OCM_0\n#undef PM_DEV_OCM_1\n#undef PM_DEV_OCM_2\n#undef PM_DEV_OCM_3\n#undef PM_DEV_TCM_0_A\n#undef PM_DEV_TCM_1_A\n#undef PM_DEV_TCM_0_B\n#undef PM_DEV_TCM_1_B\n#undef PM_DEV_SWDT_FPD\n#undef PM_DEV_AI\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_POWER_H\n#define _DT_BINDINGS_VERSAL_POWER_H\n\n#define PM_DEV_USB_0\t\t\t\t(0x18224018U)\n#define PM_DEV_GEM_0\t\t\t\t(0x18224019U)\n#define PM_DEV_GEM_1\t\t\t\t(0x1822401aU)\n#define PM_DEV_SPI_0\t\t\t\t(0x1822401bU)\n#define PM_DEV_SPI_1\t\t\t\t(0x1822401cU)\n#define PM_DEV_I2C_0\t\t\t\t(0x1822401dU)\n#define PM_DEV_I2C_1\t\t\t\t(0x1822401eU)\n#define PM_DEV_I2C_PMC (0x1822402dU)\n#define PM_DEV_CAN_FD_0\t\t\t\t(0x1822401fU)\n#define PM_DEV_CAN_FD_1\t\t\t\t(0x18224020U)\n#define PM_DEV_UART_0\t\t\t\t(0x18224021U)\n#define PM_DEV_UART_1\t\t\t\t(0x18224022U)\n#define PM_DEV_GPIO\t\t\t\t(0x18224023U)\n#define PM_DEV_TTC_0\t\t\t\t(0x18224024U)\n#define PM_DEV_TTC_1\t\t\t\t(0x18224025U)\n#define PM_DEV_TTC_2\t\t\t\t(0x18224026U)\n#define PM_DEV_TTC_3\t\t\t\t(0x18224027U)\n#define PM_DEV_SWDT_FPD\t\t\t\t(0x18224029U)\n#define PM_DEV_OSPI\t\t\t\t(0x1822402aU)\n#define PM_DEV_QSPI\t\t\t\t(0x1822402bU)\n#define PM_DEV_GPIO_PMC\t\t\t\t(0x1822402cU)\n#define PM_DEV_SDIO_0\t\t\t\t(0x1822402eU)\n#define PM_DEV_SDIO_1\t\t\t\t(0x1822402fU)\n#define PM_DEV_RTC\t\t\t\t(0x18224034U)\n#define PM_DEV_ADMA_0\t\t\t\t(0x18224035U)\n#define PM_DEV_ADMA_1\t\t\t\t(0x18224036U)\n#define PM_DEV_ADMA_2\t\t\t\t(0x18224037U)\n#define PM_DEV_ADMA_3\t\t\t\t(0x18224038U)\n#define PM_DEV_ADMA_4\t\t\t\t(0x18224039U)\n#define PM_DEV_ADMA_5\t\t\t\t(0x1822403aU)\n#define PM_DEV_ADMA_6\t\t\t\t(0x1822403bU)\n#define PM_DEV_ADMA_7\t\t\t\t(0x1822403cU)\n#define PM_DEV_AI\t\t\t\t(0x18224072U)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-regnode.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2022-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_REGNODE_H\n#define _DT_BINDINGS_VERSAL_REGNODE_H\n\n#define PM_REGNODE_SYSMON_ROOT_0\t\t\t(0x18224055U)\n#define PM_REGNODE_SYSMON_ROOT_1\t\t\t(0x18225055U)\n#define PM_REGNODE_SYSMON_ROOT_2\t\t\t(0x18226055U)\n#define PM_REGNODE_SYSMON_ROOT_3\t\t\t(0x18227055U)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-zynqmp-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_POWER_H\n#define _DT_BINDINGS_ZYNQMP_POWER_H\n\n#define\t\tPD_USB_0\t22\n#define\t\tPD_USB_1\t23\n#define\t\tPD_TTC_0\t24\n#define\t\tPD_TTC_1\t25\n#define\t\tPD_TTC_2\t26\n#define\t\tPD_TTC_3\t27\n#define\t\tPD_SATA\t\t28\n#define\t\tPD_ETH_0\t29\n#define\t\tPD_ETH_1\t30\n#define\t\tPD_ETH_2\t31\n#define\t\tPD_ETH_3\t32\n#define\t\tPD_UART_0\t33\n#define\t\tPD_UART_1\t34\n#define\t\tPD_SPI_0\t35\n#define\t\tPD_SPI_1\t36\n#define\t\tPD_I2C_0\t37\n#define\t\tPD_I2C_1\t38\n#define\t\tPD_SD_0\t\t39\n#define\t\tPD_SD_1\t\t40\n#define\t\tPD_DP\t\t41\n#define\t\tPD_GDMA\t\t42\n#define\t\tPD_ADMA\t\t43\n#define\t\tPD_NAND\t\t44\n#define\t\tPD_QSPI\t\t45\n#define\t\tPD_GPIO\t\t46\n#define\t\tPD_CAN_0\t47\n#define\t\tPD_CAN_1\t48\n#define\t\tPD_GPU\t\t58\n#define\t\tPD_PCIE\t\t59\n#define\t\tPD_PL\t\t69\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-versal-net-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H\n#define _DT_BINDINGS_VERSAL_NET_RESETS_H\n\n#include \"xlnx-versal-resets.h\"\n\n#define VERSAL_RST_USB_1\t\t\t(0xC1040C6U)\n\n/* Remove Versal specific reset IDs */\n#undef VERSAL_RST_ACPU_0_POR\n#undef VERSAL_RST_ACPU_1_POR\n#undef VERSAL_RST_OCM2_POR\n#undef VERSAL_RST_APU\n#undef VERSAL_RST_ACPU_0\n#undef VERSAL_RST_ACPU_1\n#undef VERSAL_RST_ACPU_L2\n#undef VERSAL_RST_RPU_ISLAND\n#undef VERSAL_RST_RPU_AMBA\n#undef VERSAL_RST_R5_0\n#undef VERSAL_RST_R5_1\n#undef VERSAL_RST_OCM2_RST\n#undef VERSAL_RST_I2C_PMC\n#undef VERSAL_RST_I2C_0\n#undef VERSAL_RST_I2C_1\n#undef VERSAL_RST_SWDT_FPD\n#undef VERSAL_RST_SWDT_LPD\n#undef VERSAL_RST_USB\n#undef VERSAL_RST_DPC\n#undef VERSAL_RST_DBG_TRACE\n#undef VERSAL_RST_DBG_TSTMP\n#undef VERSAL_RST_RPU0_DBG\n#undef VERSAL_RST_RPU1_DBG\n#undef VERSAL_RST_HSDP\n#undef VERSAL_RST_CPMDBG\n#undef VERSAL_RST_PCIE_CFG\n#undef VERSAL_RST_PCIE_CORE0\n#undef VERSAL_RST_PCIE_CORE1\n#undef VERSAL_RST_PCIE_DMA\n#undef VERSAL_RST_L2_0\n#undef VERSAL_RST_L2_1\n#undef VERSAL_RST_ADDR_REMAP\n#undef VERSAL_RST_CPI0\n#undef VERSAL_RST_CPI1\n#undef VERSAL_RST_XRAM\n#undef VERSAL_RST_AIE_ARRAY\n#undef VERSAL_RST_AIE_SHIM\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-versal-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_RESETS_H\n#define _DT_BINDINGS_VERSAL_RESETS_H\n\n#define VERSAL_RST_PMC_POR\t\t\t(0xc30c001U)\n#define VERSAL_RST_PMC\t\t\t\t(0xc410002U)\n#define VERSAL_RST_PS_POR\t\t\t(0xc30c003U)\n#define VERSAL_RST_PL_POR\t\t\t(0xc30c004U)\n#define VERSAL_RST_NOC_POR\t\t\t(0xc30c005U)\n#define VERSAL_RST_FPD_POR\t\t\t(0xc30c006U)\n#define VERSAL_RST_ACPU_0_POR\t\t\t(0xc30c007U)\n#define VERSAL_RST_ACPU_1_POR\t\t\t(0xc30c008U)\n#define VERSAL_RST_OCM2_POR\t\t\t(0xc30c009U)\n#define VERSAL_RST_PS_SRST\t\t\t(0xc41000aU)\n#define VERSAL_RST_PL_SRST\t\t\t(0xc41000bU)\n#define VERSAL_RST_NOC\t\t\t\t(0xc41000cU)\n#define VERSAL_RST_NPI\t\t\t\t(0xc41000dU)\n#define VERSAL_RST_SYS_RST_1\t\t\t(0xc41000eU)\n#define VERSAL_RST_SYS_RST_2\t\t\t(0xc41000fU)\n#define VERSAL_RST_SYS_RST_3\t\t\t(0xc410010U)\n#define VERSAL_RST_FPD\t\t\t\t(0xc410011U)\n#define VERSAL_RST_PL0\t\t\t\t(0xc410012U)\n#define VERSAL_RST_PL1\t\t\t\t(0xc410013U)\n#define VERSAL_RST_PL2\t\t\t\t(0xc410014U)\n#define VERSAL_RST_PL3\t\t\t\t(0xc410015U)\n#define VERSAL_RST_APU\t\t\t\t(0xc410016U)\n#define VERSAL_RST_ACPU_0\t\t\t(0xc410017U)\n#define VERSAL_RST_ACPU_1\t\t\t(0xc410018U)\n#define VERSAL_RST_ACPU_L2\t\t\t(0xc410019U)\n#define VERSAL_RST_ACPU_GIC\t\t\t(0xc41001aU)\n#define VERSAL_RST_RPU_ISLAND\t\t\t(0xc41001bU)\n#define VERSAL_RST_RPU_AMBA\t\t\t(0xc41001cU)\n#define VERSAL_RST_R5_0\t\t\t\t(0xc41001dU)\n#define VERSAL_RST_R5_1\t\t\t\t(0xc41001eU)\n#define VERSAL_RST_SYSMON_PMC_SEQ_RST\t\t(0xc41001fU)\n#define VERSAL_RST_SYSMON_PMC_CFG_RST\t\t(0xc410020U)\n#define VERSAL_RST_SYSMON_FPD_CFG_RST\t\t(0xc410021U)\n#define VERSAL_RST_SYSMON_FPD_SEQ_RST\t\t(0xc410022U)\n#define VERSAL_RST_SYSMON_LPD\t\t\t(0xc410023U)\n#define VERSAL_RST_PDMA_RST1\t\t\t(0xc410024U)\n#define VERSAL_RST_PDMA_RST0\t\t\t(0xc410025U)\n#define VERSAL_RST_ADMA\t\t\t\t(0xc410026U)\n#define VERSAL_RST_TIMESTAMP\t\t\t(0xc410027U)\n#define VERSAL_RST_OCM\t\t\t\t(0xc410028U)\n#define VERSAL_RST_OCM2_RST\t\t\t(0xc410029U)\n#define VERSAL_RST_IPI\t\t\t\t(0xc41002aU)\n#define VERSAL_RST_SBI\t\t\t\t(0xc41002bU)\n#define VERSAL_RST_LPD\t\t\t\t(0xc41002cU)\n#define VERSAL_RST_QSPI\t\t\t\t(0xc10402dU)\n#define VERSAL_RST_OSPI\t\t\t\t(0xc10402eU)\n#define VERSAL_RST_SDIO_0\t\t\t(0xc10402fU)\n#define VERSAL_RST_SDIO_1\t\t\t(0xc104030U)\n#define VERSAL_RST_I2C_PMC\t\t\t(0xc104031U)\n#define VERSAL_RST_GPIO_PMC\t\t\t(0xc104032U)\n#define VERSAL_RST_GEM_0\t\t\t(0xc104033U)\n#define VERSAL_RST_GEM_1\t\t\t(0xc104034U)\n#define VERSAL_RST_SPARE\t\t\t(0xc104035U)\n#define VERSAL_RST_USB_0\t\t\t(0xc104036U)\n#define VERSAL_RST_UART_0\t\t\t(0xc104037U)\n#define VERSAL_RST_UART_1\t\t\t(0xc104038U)\n#define VERSAL_RST_SPI_0\t\t\t(0xc104039U)\n#define VERSAL_RST_SPI_1\t\t\t(0xc10403aU)\n#define VERSAL_RST_CAN_FD_0\t\t\t(0xc10403bU)\n#define VERSAL_RST_CAN_FD_1\t\t\t(0xc10403cU)\n#define VERSAL_RST_I2C_0\t\t\t(0xc10403dU)\n#define VERSAL_RST_I2C_1\t\t\t(0xc10403eU)\n#define VERSAL_RST_GPIO_LPD\t\t\t(0xc10403fU)\n#define VERSAL_RST_TTC_0\t\t\t(0xc104040U)\n#define VERSAL_RST_TTC_1\t\t\t(0xc104041U)\n#define VERSAL_RST_TTC_2\t\t\t(0xc104042U)\n#define VERSAL_RST_TTC_3\t\t\t(0xc104043U)\n#define VERSAL_RST_SWDT_FPD\t\t\t(0xc104044U)\n#define VERSAL_RST_SWDT_LPD\t\t\t(0xc104045U)\n#define VERSAL_RST_USB\t\t\t\t(0xc104046U)\n#define VERSAL_RST_DPC\t\t\t\t(0xc208047U)\n#define VERSAL_RST_PMCDBG\t\t\t(0xc208048U)\n#define VERSAL_RST_DBG_TRACE\t\t\t(0xc208049U)\n#define VERSAL_RST_DBG_FPD\t\t\t(0xc20804aU)\n#define VERSAL_RST_DBG_TSTMP\t\t\t(0xc20804bU)\n#define VERSAL_RST_RPU0_DBG\t\t\t(0xc20804cU)\n#define VERSAL_RST_RPU1_DBG\t\t\t(0xc20804dU)\n#define VERSAL_RST_HSDP\t\t\t\t(0xc20804eU)\n#define VERSAL_RST_DBG_LPD\t\t\t(0xc20804fU)\n#define VERSAL_RST_CPM_POR\t\t\t(0xc30c050U)\n#define VERSAL_RST_CPM\t\t\t\t(0xc410051U)\n#define VERSAL_RST_CPMDBG\t\t\t(0xc208052U)\n#define VERSAL_RST_PCIE_CFG\t\t\t(0xc410053U)\n#define VERSAL_RST_PCIE_CORE0\t\t\t(0xc410054U)\n#define VERSAL_RST_PCIE_CORE1\t\t\t(0xc410055U)\n#define VERSAL_RST_PCIE_DMA\t\t\t(0xc410056U)\n#define VERSAL_RST_CMN\t\t\t\t(0xc410057U)\n#define VERSAL_RST_L2_0\t\t\t\t(0xc410058U)\n#define VERSAL_RST_L2_1\t\t\t\t(0xc410059U)\n#define VERSAL_RST_ADDR_REMAP\t\t\t(0xc41005aU)\n#define VERSAL_RST_CPI0\t\t\t\t(0xc41005bU)\n#define VERSAL_RST_CPI1\t\t\t\t(0xc41005cU)\n#define VERSAL_RST_XRAM\t\t\t\t(0xc30c05dU)\n#define VERSAL_RST_AIE_ARRAY\t\t\t(0xc10405eU)\n#define VERSAL_RST_AIE_SHIM\t\t\t(0xc10405fU)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H\n#define _DT_BINDINGS_ZYNQMP_RESETS_H\n\n#define\t\tZYNQMP_RESET_PCIE_CFG\t\t0\n#define\t\tZYNQMP_RESET_PCIE_BRIDGE\t1\n#define\t\tZYNQMP_RESET_PCIE_CTRL\t\t2\n#define\t\tZYNQMP_RESET_DP\t\t\t3\n#define\t\tZYNQMP_RESET_SWDT_CRF\t\t4\n#define\t\tZYNQMP_RESET_AFI_FM5\t\t5\n#define\t\tZYNQMP_RESET_AFI_FM4\t\t6\n#define\t\tZYNQMP_RESET_AFI_FM3\t\t7\n#define\t\tZYNQMP_RESET_AFI_FM2\t\t8\n#define\t\tZYNQMP_RESET_AFI_FM1\t\t9\n#define\t\tZYNQMP_RESET_AFI_FM0\t\t10\n#define\t\tZYNQMP_RESET_GDMA\t\t11\n#define\t\tZYNQMP_RESET_GPU_PP1\t\t12\n#define\t\tZYNQMP_RESET_GPU_PP0\t\t13\n#define\t\tZYNQMP_RESET_GPU\t\t14\n#define\t\tZYNQMP_RESET_GT\t\t\t15\n#define\t\tZYNQMP_RESET_SATA\t\t16\n#define\t\tZYNQMP_RESET_ACPU3_PWRON\t17\n#define\t\tZYNQMP_RESET_ACPU2_PWRON\t18\n#define\t\tZYNQMP_RESET_ACPU1_PWRON\t19\n#define\t\tZYNQMP_RESET_ACPU0_PWRON\t20\n#define\t\tZYNQMP_RESET_APU_L2\t\t21\n#define\t\tZYNQMP_RESET_ACPU3\t\t22\n#define\t\tZYNQMP_RESET_ACPU2\t\t23\n#define\t\tZYNQMP_RESET_ACPU1\t\t24\n#define\t\tZYNQMP_RESET_ACPU0\t\t25\n#define\t\tZYNQMP_RESET_DDR\t\t26\n#define\t\tZYNQMP_RESET_APM_FPD\t\t27\n#define\t\tZYNQMP_RESET_SOFT\t\t28\n#define\t\tZYNQMP_RESET_GEM0\t\t29\n#define\t\tZYNQMP_RESET_GEM1\t\t30\n#define\t\tZYNQMP_RESET_GEM2\t\t31\n#define\t\tZYNQMP_RESET_GEM3\t\t32\n#define\t\tZYNQMP_RESET_QSPI\t\t33\n#define\t\tZYNQMP_RESET_UART0\t\t34\n#define\t\tZYNQMP_RESET_UART1\t\t35\n#define\t\tZYNQMP_RESET_SPI0\t\t36\n#define\t\tZYNQMP_RESET_SPI1\t\t37\n#define\t\tZYNQMP_RESET_SDIO0\t\t38\n#define\t\tZYNQMP_RESET_SDIO1\t\t39\n#define\t\tZYNQMP_RESET_CAN0\t\t40\n#define\t\tZYNQMP_RESET_CAN1\t\t41\n#define\t\tZYNQMP_RESET_I2C0\t\t42\n#define\t\tZYNQMP_RESET_I2C1\t\t43\n#define\t\tZYNQMP_RESET_TTC0\t\t44\n#define\t\tZYNQMP_RESET_TTC1\t\t45\n#define\t\tZYNQMP_RESET_TTC2\t\t46\n#define\t\tZYNQMP_RESET_TTC3\t\t47\n#define\t\tZYNQMP_RESET_SWDT_CRL\t\t48\n#define\t\tZYNQMP_RESET_NAND\t\t49\n#define\t\tZYNQMP_RESET_ADMA\t\t50\n#define\t\tZYNQMP_RESET_GPIO\t\t51\n#define\t\tZYNQMP_RESET_IOU_CC\t\t52\n#define\t\tZYNQMP_RESET_TIMESTAMP\t\t53\n#define\t\tZYNQMP_RESET_RPU_R50\t\t54\n#define\t\tZYNQMP_RESET_RPU_R51\t\t55\n#define\t\tZYNQMP_RESET_RPU_AMBA\t\t56\n#define\t\tZYNQMP_RESET_OCM\t\t57\n#define\t\tZYNQMP_RESET_RPU_PGE\t\t58\n#define\t\tZYNQMP_RESET_USB0_CORERESET\t59\n#define\t\tZYNQMP_RESET_USB1_CORERESET\t60\n#define\t\tZYNQMP_RESET_USB0_HIBERRESET\t61\n#define\t\tZYNQMP_RESET_USB1_HIBERRESET\t62\n#define\t\tZYNQMP_RESET_USB0_APB\t\t63\n#define\t\tZYNQMP_RESET_USB1_APB\t\t64\n#define\t\tZYNQMP_RESET_IPI\t\t65\n#define\t\tZYNQMP_RESET_APM_LPD\t\t66\n#define\t\tZYNQMP_RESET_RTC\t\t67\n#define\t\tZYNQMP_RESET_SYSMON\t\t68\n#define\t\tZYNQMP_RESET_AFI_FM6\t\t69\n#define\t\tZYNQMP_RESET_LPD_SWDT\t\t70\n#define\t\tZYNQMP_RESET_FPD\t\t71\n#define\t\tZYNQMP_RESET_RPU_DBG1\t\t72\n#define\t\tZYNQMP_RESET_RPU_DBG0\t\t73\n#define\t\tZYNQMP_RESET_DBG_LPD\t\t74\n#define\t\tZYNQMP_RESET_DBG_FPD\t\t75\n#define\t\tZYNQMP_RESET_APLL\t\t76\n#define\t\tZYNQMP_RESET_DPLL\t\t77\n#define\t\tZYNQMP_RESET_VPLL\t\t78\n#define\t\tZYNQMP_RESET_IOPLL\t\t79\n#define\t\tZYNQMP_RESET_RPLL\t\t80\n#define\t\tZYNQMP_RESET_GPO3_PL_0\t\t81\n#define\t\tZYNQMP_RESET_GPO3_PL_1\t\t82\n#define\t\tZYNQMP_RESET_GPO3_PL_2\t\t83\n#define\t\tZYNQMP_RESET_GPO3_PL_3\t\t84\n#define\t\tZYNQMP_RESET_GPO3_PL_4\t\t85\n#define\t\tZYNQMP_RESET_GPO3_PL_5\t\t86\n#define\t\tZYNQMP_RESET_GPO3_PL_6\t\t87\n#define\t\tZYNQMP_RESET_GPO3_PL_7\t\t88\n#define\t\tZYNQMP_RESET_GPO3_PL_8\t\t89\n#define\t\tZYNQMP_RESET_GPO3_PL_9\t\t90\n#define\t\tZYNQMP_RESET_GPO3_PL_10\t\t91\n#define\t\tZYNQMP_RESET_GPO3_PL_11\t\t92\n#define\t\tZYNQMP_RESET_GPO3_PL_12\t\t93\n#define\t\tZYNQMP_RESET_GPO3_PL_13\t\t94\n#define\t\tZYNQMP_RESET_GPO3_PL_14\t\t95\n#define\t\tZYNQMP_RESET_GPO3_PL_15\t\t96\n#define\t\tZYNQMP_RESET_GPO3_PL_16\t\t97\n#define\t\tZYNQMP_RESET_GPO3_PL_17\t\t98\n#define\t\tZYNQMP_RESET_GPO3_PL_18\t\t99\n#define\t\tZYNQMP_RESET_GPO3_PL_19\t\t100\n#define\t\tZYNQMP_RESET_GPO3_PL_20\t\t101\n#define\t\tZYNQMP_RESET_GPO3_PL_21\t\t102\n#define\t\tZYNQMP_RESET_GPO3_PL_22\t\t103\n#define\t\tZYNQMP_RESET_GPO3_PL_23\t\t104\n#define\t\tZYNQMP_RESET_GPO3_PL_24\t\t105\n#define\t\tZYNQMP_RESET_GPO3_PL_25\t\t106\n#define\t\tZYNQMP_RESET_GPO3_PL_26\t\t107\n#define\t\tZYNQMP_RESET_GPO3_PL_27\t\t108\n#define\t\tZYNQMP_RESET_GPO3_PL_28\t\t109\n#define\t\tZYNQMP_RESET_GPO3_PL_29\t\t110\n#define\t\tZYNQMP_RESET_GPO3_PL_30\t\t111\n#define\t\tZYNQMP_RESET_GPO3_PL_31\t\t112\n#define\t\tZYNQMP_RESET_RPU_LS\t\t113\n#define\t\tZYNQMP_RESET_PS_ONLY\t\t114\n#define\t\tZYNQMP_RESET_PL\t\t\t115\n#define\t\tZYNQMP_RESET_PS_PL0\t\t116\n#define\t\tZYNQMP_RESET_PS_PL1\t\t117\n#define\t\tZYNQMP_RESET_PS_PL2\t\t118\n#define\t\tZYNQMP_RESET_PS_PL3\t\t119\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/versal/versal-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-versal-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-power.h\"\n#include \"include/dt-bindings/power/xlnx-versal-regnode.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-resets.h\"\n/ {\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tcan0_clk: can0_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN0_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tcan1_clk: can1_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN1_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t\tversal_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,versal-pinctrl\";\n\t\t\t};\n\n\t\t\tversal_sec_cfg: versal-sec-cfg {\n\t\t\t\tcompatible = \"xlnx,versal-sec-cfg\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tbbram_zeroize: bbram-zeroize@4 {\n\t\t\t\t\treg = <0x04 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_key: bbram-key@10 {\n\t\t\t\t\treg = <0x10 0x20>;\n\t\t\t\t};\n\n\t\t\t\tbbram_usr: bbram-usr@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_lock: bbram-lock@48 {\n\t\t\t\t\treg = <0x48 0x4>;\n\t\t\t\t};\n\n\t\t\t\tuser_key0: user-key@110 {\n\t\t\t\t\treg = <0x110 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key1: user-key@130 {\n\t\t\t\t\treg = <0x130 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key2: user-key@150 {\n\t\t\t\t\treg = <0x150 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key3: user-key@170 {\n\t\t\t\t\treg = <0x170 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key4: user-key@190 {\n\t\t\t\t\treg = <0x190 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key5: user-key@1b0 {\n\t\t\t\t\treg = <0x1b0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key6: user-key@1d0 {\n\t\t\t\t\treg = <0x1d0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key7: user-key@1f0 {\n\t\t\t\t\treg = <0x1f0 0x20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk ACPU>;\n};\n\n&can0 {\n\tclocks = <&can0_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_0>;\n};\n\n&can1 {\n\tclocks = <&can1_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_1>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_0>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_1>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk PMC_LSBUS_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO_PMC>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk I2C0_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_0>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk I2C1_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_1>;\n};\n\n&i2c2 {\n\tclocks = <&versal_clk I2C_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_PMC>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_0>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_1>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_2>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_3>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_4>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_5>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_6>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_7>;\n};\n\n&qspi {\n\tclocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_QSPI>;\n};\n\n&ospi {\n\tclocks = <&versal_clk OSPI_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_OSPI>;\n\treset-names = \"qspi\";\n\tresets = <&versal_reset VERSAL_RST_OSPI>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware PM_DEV_RTC>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_0>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_1>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>,\n\t\t<&versal_clk SD_DLL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_0>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>,\n\t\t<&versal_clk SD_DLL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_1>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_0>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_1>;\n};\n\n&ttc0 {\n\tclocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_0>;\n};\n\n&ttc1 {\n\tclocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_1>;\n};\n\n&ttc2 {\n\tclocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_2>;\n};\n\n&ttc3 {\n\tclocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_3>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_USB_0>;\n\tresets = <&versal_reset VERSAL_RST_USB_0>;\n};\n\n&dwc3_0 {\n\tclocks = <&versal_clk USB0_BUS_REF>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SWDT_FPD>;\n};\n\n&sysmon0 {\n\txlnx,nodeid = ;\n};\n\n&sysmon1 {\n\txlnx,nodeid = ;\n};\n\n&sysmon2 {\n\txlnx,nodeid = ;\n};\n\n&sysmon3 {\n\txlnx,nodeid = ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/versal/versal-spp-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\talt_ref_clk: alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware-wip\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"alt_ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk 77>;\n};\n\n&can0 {\n\tclocks = <&versal_clk 96>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401f>;\n};\n\n&can1 {\n\tclocks = <&versal_clk 97>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224020>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x18224019>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x1822401a>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk 61>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk 98>;\n\tpower-domains = <&versal_firmware 0x1822401d>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk 99>;\n\tpower-domains = <&versal_firmware 0x1822401e>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224035>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224036>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224037>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224038>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224039>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403a>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403b>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403c>;\n};\n\n&qspi {\n\tclocks = <&versal_clk 57>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402b>;\n};\n\n&ospi {\n\tclocks = <&versal_clk 58>, <&versal_clk 82>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware 0x18224034>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk 92>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224021>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk 93>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224022>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk 59>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402e>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk 60>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402f>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk 94>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401b>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk 95>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401c>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk 91>, <&versal_clk 104>;\n\tpower-domains = <&versal_firmware 0x18224018>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk 82>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/versal/versal.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal\";\n\n\tcpus: cpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <1>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tfpga: fpga {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&versal_fpga>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tpsci: psci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 7 0x304>;\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t};\n\n\tversal_fpga: versal_fpga {\n\t\tcompatible = \"xlnx,versal-fpga\";\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t\tinterrupt-parent = <&gic>;\n\t\tu-boot,dm-pre-reloc;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\t\t\treg = <0 0xf9000000 0 0x80000>, /* GICD */\n\t\t\t <0 0xf9080000 0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\n\t\t\tgic_its: gic-its@f9020000 {\n\t\t\t\tcompatible = \"arm,gic-v3-its\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tmsi-controller;\n\t\t\t\tmsi-cells = <1>;\n\t\t\t\treg = <0 0xf9020000 0 0x20000>;\n\t\t\t};\n\t\t};\n\n\t\tapm: performance-monitor@f0920000 {\n\t\t\tcompatible = \"xlnx,flexnoc-pm-2.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg-names = \"funnel\", \"baselpd\", \"basefpd\";\n\t\t\treg = <0x0 0xf0920000 0x0 0x1000>,\n\t\t\t <0x0 0xf0980000 0x0 0x9000>,\n\t\t\t <0x0 0xf0b80000 0x0 0x9000>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff060000 0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff070000 0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcci: cci@fd000000 {\n\t\t\tcompatible = \"arm,cci-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd000000 0 0x10000>;\n\t\t\tranges = <0 0 0xfd000000 0xa0000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcci_pmu: pmu@10000 {\n\t\t\t\tcompatible = \"arm,cci-500-pmu,r0\";\n\t\t\t\treg = <0x10000 0x90000>;\n\t\t\t\tinterrupts = <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>;\n\t\t\t};\n\t\t};\n\n\t\tlpd_dma_chan0: dma@ffa80000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa80000 0 0x1000>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa90000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa90000 0 0x1000>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffaa0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaa0000 0 0x1000>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\n\t\tlpd_dma_chan3: dma@ffab0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffab0000 0 0x1000>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffac0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffac0000 0 0x1000>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffad0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffad0000 0 0x1000>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffae0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffae0000 0 0x1000>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffaf0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaf0000 0 0x1000>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tgem0: ethernet@ff0c0000 {\n compatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0c0000 0 0x1000>;\n\t\t\tinterrupts = <0 56 4>, <0 56 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t/* iommus = <&smmu 0x234>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0d0000 {\n compatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0d0000 0 0x1000>;\n\t\t\tinterrupts = <0 58 4>, <0 58 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t/* iommus = <&smmu 0x235>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tgpio0: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0b0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff020000 0 0x1000>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\tclock-frequency = <100000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff030000 0 0x1000>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tclock-frequency = <100000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c2: i2c@f1000000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1000000 0 0x1000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tclock-frequency = <100000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tmc0: memory-controller@f6150000\t{\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <0>;\n\t\t};\n\n\t\tmc1: memory-controller@f62c0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <1>;\n\t\t};\n\n\t\tmc2: memory-controller@f6430000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <2>;\n\t\t};\n\n\t\tmc3: memory-controller@f65a0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <3>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tcalibration = <0x7FFF>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff000000 0 0x1000>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tserial1: serial@ff010000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff010000 0 0x1000>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd800000 0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 124 4>, <0 124 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,trigger-address = <0xC0000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff040000 0 0x1000>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff050000 0 0x1000>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsysmon0: sysmon@f1270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\treg = <0x0 0xf1270000 0x0 0x4000>;\n\t\t\tinterrupts = <0 144 4>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tsysmon1: sysmon@109270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x09270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tsysmon2: sysmon@111270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x11270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tsysmon3: sysmon@119270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x19270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tttc0: timer@ff0e0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff0f0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 40 4>, <0 41 4>, <0 42 4>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff100000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 46 4>, <0 47 4>, <0 48 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tusb0: usb@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff9d0000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_0: usb@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0 0xfe200000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"usb-wakeup\";\n\t\t\t\tinterrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\tcpm_pciea: pci@fca10000 {\n\t\t\t#address-cells = <3>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"xlnx,versal-cpm-host-1.00\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc_0 0>,\n\t\t\t\t\t<0 0 0 2 &pcie_intc_0 1>,\n\t\t\t\t\t<0 0 0 3 &pcie_intc_0 2>,\n\t\t\t\t\t<0 0 0 4 &pcie_intc_0 3>;\n\t\t\tinterrupt-map-mask = <0 0 0 7>;\n\t\t\tinterrupt-names = \"misc\";\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>,\n\t\t\t\t <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>;\n\t\t\tmsi-map = <0x0 &gic_its 0x0 0x10000>;\n\t\t\treg = <0x0 0xfca10000 0x0 0x1000>,\n\t\t\t <0x6 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"cpm_slcr\", \"cfg\";\n\t\t\tpcie_intc_0: pci-interrupt-controller {\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\tinterrupt-controller ;\n\t\t\t};\n\t\t};\n\n\t\twatchdog: watchdog@fd4d0000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd4d0000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 0x64 1>, <0 0x6D 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t};\n\t\txilsem_edac: edac@f2014050 {\n\t\t\tcompatible = \"xlnx,versal-xilsem-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf2014050 0x0 0xc4>;\n\t\t};\n\t};\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/versal-net/versal-net-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * Copyright (C) 2022, Xilinx, Inc.\n * Copyright (C) 2022, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/clock/xlnx-versal-net-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-net-power.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tcan0_clk: can0-clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_net_clk CAN0_REF_2X>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tcan1_clk: can1-clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_net_clk CAN1_REF_2X>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tversal_net_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-net-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tversal_net_power: zynqmp-power { /* untested */\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 57 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tversal_sec_cfg: versal-sec-cfg { /* untested */\n\t\t\t\tcompatible = \"xlnx,versal-sec-cfg\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tbbram_zeroize: bbram-zeroize@4 {\n\t\t\t\t\treg = <0x04 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_key: bbram-key@10 {\n\t\t\t\t\treg = <0x10 0x20>;\n\t\t\t\t};\n\n\t\t\t\tbbram_usr: bbram-usr@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_lock: bbram-lock@48 {\n\t\t\t\t\treg = <0x48 0x4>;\n\t\t\t\t};\n\n\t\t\t\tuser_key0: user-key@110 {\n\t\t\t\t\treg = <0x110 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key1: user-key@130 {\n\t\t\t\t\treg = <0x130 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key2: user-key@150 {\n\t\t\t\t\treg = <0x150 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key3: user-key@170 {\n\t\t\t\t\treg = <0x170 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key4: user-key@190 {\n\t\t\t\t\treg = <0x190 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key5: user-key@1b0 {\n\t\t\t\t\treg = <0x1b0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key6: user-key@1d0 {\n\t\t\t\t\treg = <0x1d0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key7: user-key@1f0 {\n\t\t\t\t\treg = <0x1f0 0x20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 57 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@eb3f0440 {\n\t\t\treg = <0 0xeb3f0440 0 0x20>,\n\t\t\t <0 0xeb3f0460 0 0x20>,\n\t\t\t <0 0xeb3f0280 0 0x20>,\n\t\t\t <0 0xeb3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu100 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu200 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu300 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu10000 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu10100 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu10200 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu10300 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu20000 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu20100 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu20200 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu20300 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu30000 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&cpu30100 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&cpu30200 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&cpu30300 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&can0 {\n\tclocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>;\n};\n\n&can1 {\n\tclocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>;\n};\n\n&gem0 {\n\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>,\n\t\t <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GEM_0>;\n};\n\n&gem1 {\n\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>,\n\t\t <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GEM_1>;\n};\n\n&gpio0 {\n\tclocks = <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GPIO>;\n};\n\n&gpio1 {\n\tclocks = <&versal_net_clk PMC_LSBUS_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>;\n};\n\n&i2c0 {\n\tclocks = <&versal_net_clk I3C0_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n};\n\n&i2c1 {\n\tclocks = <&versal_net_clk I3C1_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n};\n\n&i3c0 {\n\tclocks = <&versal_net_clk I3C0_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n};\n\n&i3c1 {\n\tclocks = <&versal_net_clk I3C1_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n};\n\n&adma0 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_0>;\n};\n\n&adma1 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_1>;\n};\n\n&adma2 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_2>;\n};\n\n&adma3 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_3>;\n};\n\n&adma4 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_4>;\n};\n\n&adma5 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_5>;\n};\n\n&adma6 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_6>;\n};\n\n&adma7 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_7>;\n};\n\n&qspi {\n\tclocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_QSPI>;\n};\n\n&ospi {\n\tclocks = <&versal_net_clk OSPI_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_OSPI>;\n\tresets = <&versal_net_reset VERSAL_RST_OSPI>;\n};\n\n&rtc {\n\tpower-domains = <&versal_net_firmware PM_DEV_RTC>;\n};\n\n&serial0 {\n\tclocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_UART_0>;\n};\n\n&serial1 {\n\tclocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_UART_1>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>,\n\t\t<&versal_net_clk SD_DLL_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_0>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>,\n\t\t<&versal_net_clk SD_DLL_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_1>;\n};\n\n&spi0 {\n\tclocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SPI_0>;\n};\n\n&spi1 {\n\tclocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SPI_1>;\n};\n\n&ttc0 {\n\tclocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_0>;\n};\n\n&ttc1 {\n\tclocks = <&versal_net_clk TTC1>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_1>;\n};\n\n&ttc2 {\n\tclocks = <&versal_net_clk TTC2>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_2>;\n};\n\n&ttc3 {\n\tclocks = <&versal_net_clk TTC3>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_3>;\n};\n\n&usb0 {\n\tclocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_USB_0>;\n\tresets = <&versal_net_reset VERSAL_RST_USB_0>;\n};\n\n&dwc3_0 {\n\tclocks = <&versal_net_clk USB0_BUS_REF>;\n};\n\n&usb1 {\n\tclocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_USB_1>;\n\tresets = <&versal_net_reset VERSAL_RST_USB_1>;\n};\n\n&dwc3_1 {\n\tclocks = <&versal_net_clk USB1_BUS_REF>;\n};\n\n&wwdt0 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>;\n};\n\n&wwdt1 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>;\n};\n\n&wwdt2 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>;\n};\n\n&wwdt3 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/versal-net/versal-net-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET fixed clock\n *\n * (C) Copyright 2022, Xilinx, Inc.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tclk60: clk60 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <60000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk150: clk150 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <150000000>;\n\t};\n\n\tclk160: clk160 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <160000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk450: clk450 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <450000000>;\n\t};\n\n\tclk1200: clk1200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <1200000000>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&adma0 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma1 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma2 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma3 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma4 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma5 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma6 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma7 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&can0 {\n\tclocks = <&clk160>, <&clk160>;\n};\n\n&can1 {\n\tclocks = <&clk160>, <&clk160>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;\n};\n\n\n&gpio0 {\n\tclocks = <&clk100>;\n};\n\n&gpio1 {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&i3c0 {\n\tclocks = <&clk100>;\n};\n\n&i3c1 {\n\tclocks = <&clk100>;\n};\n\n&ospi {\n\tclocks = <&clk200>;\n\tresets = <&versal_net_reset VERSAL_RST_OSPI>;\n};\n\n&qspi {\n\tclocks = <&clk300>, <&clk300>;\n};\n\n&rtc {\n\t/* Nothing */\n};\n\n&sdhci0 {\n\tclocks = <&clk200>, <&clk200>, <&clk1200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200>, <&clk200>, <&clk1200>;\n};\n\n&serial0 {\n\tclocks = <&clk100>, <&clk100>;\n\tclock = <1000000>;\n};\n\n&serial1 {\n\tclocks = <&clk100>, <&clk100>;\n\tclock = <100000000>;\n};\n\n&spi0 {\n\tclocks = <&clk200>, <&clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200>, <&clk200>;\n};\n\n&ttc0 {\n\tclocks = <&clk150>;\n};\n\n&usb0 {\n\tclocks = <&clk60>, <&clk60>;\n};\n\n&dwc3_0 {\n\t/* Nothing */\n};\n\n&usb1 {\n\tclocks = <&clk60>, <&clk60>;\n};\n\n&dwc3_1 {\n\t/* Nothing */\n};\n\n&wwdt0 {\n\tclocks = <&clk150>;\n};\n\n&wwdt1 {\n\tclocks = <&clk150>;\n};\n\n&wwdt2 {\n\tclocks = <&clk150>;\n};\n\n&wwdt3 {\n\tclocks = <&clk150>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/versal-net/versal-net-ipp-rev1.9.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/clock/xlnx-versal-net-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-net-power.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-net-ipp-1.9\", \"xlnx,versal-net-spp-5.0\", \"xlnx,versal-net-spp\", \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal NET SPP 5.0/IPP 1.9\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t};\n\t};\n\n\tmemory: memory@0 {\n\t\treg = <0 0 0 0x80000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tref_clk: ref_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x01>;\n\n\t\t\tversal_net_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-net-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupts = <0 57 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t<&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupts = <0 57 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@eb3f0440 {\n\t\t\treg = <0 0xeb3f0440 0 0x20>,\n\t\t\t <0 0xeb3f0460 0 0x20>,\n\t\t\t <0 0xeb3f0280 0 0x20>,\n\t\t\t <0 0xeb3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tadma0: dma-controller@ebd00000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd00000 0 0x1000>;\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_0>;\n\t\t};\n\n\t\tadma1: dma-controller@ebd10000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd10000 0 0x1000>;\n\t\t\tinterrupts = <0 73 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_1>;\n\t\t};\n\n\t\tadma2: dma-controller@ebd20000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd20000 0 0x1000>;\n\t\t\tinterrupts = <0 74 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_2>;\n\t\t};\n\n\t\tadma3: dma-controller@ebd30000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd30000 0 0x1000>;\n\t\t\tinterrupts = <0 75 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_3>;\n\t\t};\n\n\t\tadma4: dma-controller@ebd40000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd40000 0 0x1000>;\n\t\t\tinterrupts = <0 76 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_4>;\n\t\t};\n\n\t\tadma5: dma-controller@ebd50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd50000 0 0x1000>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_5>;\n\t\t};\n\n\t\tadma6: dma-controller@ebd60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd60000 0 0x1000>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_6>;\n\t\t};\n\n\t\tadma7: dma-controller@ebd70000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd70000 0 0x1000>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_7>;\n\t\t};\n\n\t\tcan0: can@f1980000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1980000 0 0x6000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>;\n\t\t};\n\n\t\tcan1: can@f1990000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1990000 0 0x6000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>;\n\t\t};\n\n\t\tgem0: ethernet@f19e0000 {\n compatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19e0000 0 0x1000>;\n\t\t\tinterrupts = <0 39 4>, <0 39 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>,\n\t\t\t\t <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_0>;\n\t\t\tmdio0: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\t\t#phy-cells = <1>;\n\t\t\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t\tti,rx-internal-delay = <11>;\n\t\t\t\t\tti,tx-internal-delay = <10>;\n\t\t\t\t\tti,fifo-depth = <1>;\n\t\t\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgem1: ethernet@f19f0000 {\n compatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19f0000 0 0x1000>;\n\t\t\tinterrupts = <0 41 4>, <0 41 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy2>;\n\t\t\tphy-mode = \"rmii\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>,\n\t\t\t\t <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_1>;\n\t\t\tmdio1: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\t\tcompatible = \"ethernet-phy-id0007.0762\"; /* Vitesse VSC8540 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t};\n\n\t\tgpio0: gpio@f19d0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\treg = <0 0xf19d0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO>;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk PMC_LSBUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>;\n\t\t};\n\n\t\ti2c0: i2c@f1940000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1940000 0 0x1000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C0_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@f1950000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1950000 0 0x1000>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C1_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n\t\t};\n\n\t\ti3c: i3c-master@f1948000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\treg = <0 0xf1948000 0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclocks = <&versal_net_clk I2C_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_PMC>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 182 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,trigger-address = <0xc0000000>;\n\t\t\tis-dual = <0>;\n\t\t\tis-stacked = <0>;\n\t\t\tclocks = <&versal_net_clk OSPI_REF>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_OSPI>;\n\t\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\t\t\tmt35xu02g: flash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tcdns,read-delay = <0>;\n\t\t\t\tcdns,tshsl-ns = <0>;\n\t\t\t\tcdns,tsd2d-ns = <0>;\n\t\t\t\tcdns,tchsh-ns = <1>;\n\t\t\t\tcdns,tslch-ns = <1>;\n\t\t\t\tspi-tx-bus-width = <8>;\n\t\t\t\tspi-rx-bus-width = <8>;\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\tbroken-flash-reset;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"ospi-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"ospi-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 183 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tnum-cs = <1>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\t\t\tclocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_QSPI>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <10000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi0-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"qspi0-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupts = <0 200 4>, <0 201 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 184 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_0>;\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 186 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_1>;\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_UART_0>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tsmmu: smmu@ec000000 {\n\t\t\tcompatible = \"arm,smmu-v3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xec000000 0 0x40000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tinterrupt-names = \"combined\";\n\t\t\tinterrupts = <0 169 4>;\n\t\t};\n\n\t\tspi0: spi@f1960000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupts = <0 23 4>;\n\t\t\treg = <0 0xf1960000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_0>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@f1970000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0 0xf1970000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_1>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tttc0: timer@f1dc0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dc0000 0x0 0x1000>;\n\t\t\tclocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_TTC_0>;\n\t\t};\n\n\t\tusb0: usb@f1e00000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0 0xf1e00000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t/* clocks = <&clk60>, <&clk60>; */\n\t\t\tclocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_0>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_0>;\n\n\t\t\tdwc3_0: dwc3@f1b00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0 0xf1b00000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 29 4>, <0 33 4>, <0 98 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tdr_mode = \"peripheral\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@f1e10000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0x0 0xf1e10000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tclocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_1>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_1>;\n\n\t\t\tdwc3_1: dwc3@f1c00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0x0 0xf1c00000 0x0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 34 4>, <0 38 4>, <0 99 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tsnps,refclk_fladj;\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\twwdt0: watchdog@ecc10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xecc10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 139 1>, <0 140 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>;\n\t\t};\n\n\t\twwdt1: watchdog@ecd10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xecd10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 143 1>, <0 144 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>;\n\t\t};\n\n\t\twwdt2: watchdog@ece10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xece10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 147 1>, <0 148 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>;\n\t\t};\n\n\t\twwdt3: watchdog@ecf10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\treg = <0 0xecf10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 164 1>, <0 165 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/versal-net/versal-net.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * Copyright (C) 2022, Xilinx, Inc.\n * Copyright (C) 2022, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal NET\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tcluster2 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu20000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu20100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu20200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu20300>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tcluster3 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu30000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu30100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu30200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu30300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t\tcpu20000: cpu@20000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20000>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t\tcpu20100: cpu@20100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20100>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t\tcpu20200: cpu@20200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20200>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t\tcpu20300: cpu@20300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20300>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t\tcpu30000: cpu@30000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30000>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t\tcpu30100: cpu@30100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30100>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t\tcpu30200: cpu@30200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30200>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t\tcpu30300: cpu@30300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30300>;\n operating-points-v2 = <&cpu_opp_table>;\n\t\t};\n\t};\n\n\tcpu_opp_table: opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-1066000000 {\n\t\t\topp-hz = /bits/ 64 <1066000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-1866000000 {\n\t\t\topp-hz = /bits/ 64 <1866000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-1900000000 {\n\t\t\topp-hz = /bits/ 64 <1900000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-1999000000 {\n\t\t\topp-hz = /bits/ 64 <1999000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2050000000 {\n\t\t\topp-hz = /bits/ 64 <2050000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2100000000 {\n\t\t\topp-hz = /bits/ 64 <2100000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2200000000 {\n\t\t\topp-hz = /bits/ 64 <2200000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2400000000 {\n\t\t\topp-hz = /bits/ 64 <2400000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n };\n };\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tserial2 = &dcc;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\trtc = &rtc;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t\tspi0 = &ospi;\n\t\tspi1 = &qspi;\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tfirmware {\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tadma0: dma-controller@ebd00000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd00000 0 0x1000>;\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma1: dma-controller@ebd10000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd10000 0 0x1000>;\n\t\t\tinterrupts = <0 73 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma2: dma-controller@ebd20000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd20000 0 0x1000>;\n\t\t\tinterrupts = <0 74 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma3: dma-controller@ebd30000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd30000 0 0x1000>;\n\t\t\tinterrupts = <0 75 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma4: dma-controller@ebd40000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd40000 0 0x1000>;\n\t\t\tinterrupts = <0 76 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma5: dma-controller@ebd50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd50000 0 0x1000>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma6: dma-controller@ebd60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd60000 0 0x1000>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma7: dma-controller@ebd70000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd70000 0 0x1000>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tcan0: can@f1980000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1980000 0 0x6000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t};\n\n\t\tcan1: can@f1990000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1990000 0 0x6000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t};\n\n\t\tgem0: ethernet@f19e0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf19e0000 0 0x1000>;\n\t\t\tinterrupts = <0 39 4>, <0 39 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\",\n\t\t\t \"tsu_clk\";\n\t\t};\n\n\t\tgem1: ethernet@f19f0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf19f0000 0 0x1000>;\n\t\t\tinterrupts = <0 41 4>, <0 41 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\",\n\t\t\t\t \"tsu_clk\";\n\t\t};\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>,\n\t\t\t <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\t\t\tits: gic-its@e2040000 {\n\t\t\t\tcompatible = \"arm,gic-v3-its\";\n\t\t\t\tmsi-controller;\n\t\t\t\t#msi-cells = <1>;\n\t\t\t\treg = <0 0xe2040000 0 0x20000>;\n\t\t\t};\n\t\t};\n\n\t\tgpio0: gpio@f19d0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf19d0000 0 0x1000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 180 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\ti2c0: i2c@f1940000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1940000 0 0x1000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@f1950000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1950000 0 0x1000>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti3c0: i3c-master@f1948000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1948000 0 0x1000>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t};\n\n\t\ti3c1: i3c-master@f1958000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1958000 0 0x1000>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000>,\n\t\t\t <0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 182 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>; /* u-boot specific */\n\t\t\t/* cdns,is-stig-pgm = <1>; - unused - checking with Sai */\n\t\t\tcdns,trigger-address = <0xc0000000>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1030000 0 0x1000>; /* missing one more reg range - checking with Sai */\n\t\t\tinterrupts = <0 183 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupts = <0 200 4>, <0 201 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 184 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-net-5.1-emmc\",\n\t\t\t\t \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 186 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tserial1: serial@f1930000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1930000 0 0x1000>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tsmmu: iommu@ec000000 {\n\t\t\tcompatible = \"arm,smmu-v3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xec000000 0 0x40000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tinterrupt-names = \"combined\";\n\t\t\tinterrupts = <0 169 4>;\n\t\t\tdma-coherent;\n\t\t};\n\n\t\tspi0: spi@f1960000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 23 4>;\n\t\t\treg = <0 0xf1960000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t};\n\n\t\tspi1: spi@f1970000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0 0xf1970000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t};\n\n\t\tttc0: timer@f1dc0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dc0000 0x0 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f1dd0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 46 4>, <0 47 4>, <0 48 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dd0000 0x0 0x1000>;\n\t\t};\n\n\t\tttc2: timer@f1de0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 49 4>, <0 50 4>, <0 51 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1de0000 0x0 0x1000>;\n\t\t};\n\n\t\tttc3: timer@f1df0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 52 4>, <0 53 4>, <0 54 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1df0000 0x0 0x1000>;\n\t\t};\n\n\t\tusb0: usb@f1e00000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1e00000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_0: usb@f1b00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0 0xf1b00000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"usb-wakeup\";\n\t\t\t\tinterrupts = <0 29 4>, <0 33 4>, <0 98 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"peripheral\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\t/*phy-names = \"usb3-phy\";- checking with Pyiush */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@f1e10000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf1e10000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_1: usb@f1c00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xf1c00000 0x0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 34 4>, <0 38 4>, <0 99 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\t/* phy-names = \"usb3-phy\"; - checking with Pyiush */\n\t\t\t};\n\t\t};\n\n\t\twwdt0: watchdog@ecc10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xecc10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 139 1>, <0 140 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t};\n\n\t\twwdt1: watchdog@ecd10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xecd10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 143 1>, <0 144 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t};\n\n\t\twwdt2: watchdog@ece10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xece10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 147 1>, <0 148 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t};\n\n\t\twwdt3: watchdog@ecf10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xecf10000 0 0x10000>;\n\t\t\tinterrupt-names = \"wdt\", \"wwdt_reset_pending\";\n\t\t\tinterrupts = <0 164 1>, <0 165 1>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tpretimeout-sec = <25>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/zynq/skeleton.dtsi", "content": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/zynq/zynq-7000.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\treplicator {\n\t\tcompatible = \"arm,coresight-static-replicator\";\n\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\tout-ports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\t/* replicator output ports */\n\t\t\tport@0 {\n\t\t\t\treg = <0>;\n\t\t\t\treplicator_out_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&tpiu_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tport@1 {\n\t\t\t\treg = <1>;\n\t\t\t\treplicator_out_port1: endpoint {\n\t\t\t\t\tremote-endpoint = <&etb_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tin-ports {\n\t\t\t/* replicator input port */\n\t\t\tport {\n\t\t\t\treplicator_in_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&funnel_out_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tamba: axi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocm: sram@fffc0000 {\n\t\t\tcompatible = \"mmio-sram\";\n\t\t\treg = <0xfffc0000 0x10000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n compatible = \"xlnx,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n compatible = \"xlnx,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\", \"arm,primecell\";\n\t\t\treg = <0xe000e000 0x0001000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"apb_pclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */\n\t\t\t\t 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */\n\t\t\t\t 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tnfc0: nand-controller@0,0 {\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0 0 0x1000000>;\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t};\n\t\t\tnor0: flash@1,0 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <1 0 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tsdhci0: mmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: mmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n dmac_s: dma-controller@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n /*\n\t\t\t * interrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t * \"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\t */\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\tetb@f8801000 {\n\t\t\tcompatible = \"arm,coresight-etb10\", \"arm,primecell\";\n\t\t\treg = <0xf8801000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\tetb_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ttpiu@f8803000 {\n\t\t\tcompatible = \"arm,coresight-tpiu\", \"arm,primecell\";\n\t\t\treg = <0xf8803000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\ttpiu_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tfunnel@f8804000 {\n\t\t\tcompatible = \"arm,coresight-static-funnel\", \"arm,primecell\";\n\t\t\treg = <0xf8804000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\t\t/* funnel output ports */\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tfunnel_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint =\n\t\t\t\t\t\t\t<&replicator_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tin-ports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\t/* funnel input ports */\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tfunnel0_in_port0: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm0_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tfunnel0_in_port1: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm1_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tfunnel0_in_port2: endpoint {\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t/* The other input ports are not connect to anything */\n\t\t\t};\n\t\t};\n\n\t\tptm@f889c000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889c000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu0>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm0_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889d000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889d000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu1>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm1_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/zynqmp/zynqmp-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-zynqmp-clk.h\"\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL0_REF>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL1_REF>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL2_REF>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL3_REF>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tdp_aclk: dp_aclk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n};\n\n&zynqmp_firmware {\n\tzynqmp_clk: clock-controller {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,\n\t\t\t <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\",\n\t\t\t \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t};\n};\n\n&can0 {\n\tclocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&can1 {\n\tclocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&cpu0 {\n\tclocks = <&zynqmp_clk ACPU>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gpu {\n\tclocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&nand0 {\n\tclocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gem0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>,\n\t\t <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>;\n};\n\n&gem1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>,\n\t\t <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>;\n};\n\n&gem2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>,\n\t\t <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>;\n};\n\n&gem3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>,\n\t\t <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>;\n};\n\n&gpio {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&i2c0 {\n\tclocks = <&zynqmp_clk I2C0_REF>;\n};\n\n&i2c1 {\n\tclocks = <&zynqmp_clk I2C1_REF>;\n};\n\n&perf_monitor_ocm {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&perf_monitor_ddr {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_cci {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_lpd {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&pcie {\n\tclocks = <&zynqmp_clk PCIE_REF>;\n};\n\n&qspi {\n\tclocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&sata {\n\tclocks = <&zynqmp_clk SATA_REF>;\n};\n\n&sdhci0 {\n\tclocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;\n\tassigned-clocks = <&zynqmp_clk SDIO0_REF>;\n};\n\n&sdhci1 {\n\tclocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;\n\tassigned-clocks = <&zynqmp_clk SDIO1_REF>;\n};\n\n&spi0 {\n\tclocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&spi1 {\n\tclocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart0 {\n\tclocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart1 {\n\tclocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&usb0 {\n\tclocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n\tassigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&dwc3_0 {\n\tclocks = <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&usb1 {\n\tclocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n\tassigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&dwc3_1 {\n\tclocks = <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&watchdog0 {\n\tclocks = <&zynqmp_clk WDT>;\n};\n\n&lpd_watchdog {\n\tclocks = <&zynqmp_clk LPD_WDT>;\n};\n\n&xilinx_ams {\n\tclocks = <&zynqmp_clk AMS_REF>;\n};\n\n&zynqmp_pcap {\n\tclocks = <&zynqmp_clk PCAP>;\n};\n\n&zynqmp_dpdma {\n\tclocks = <&zynqmp_clk DPDMA_REF>;\n\tassigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */\n};\n\n&zynqmp_dpsub {\n\tclocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>;\n\tassigned-clocks = <&zynqmp_clk DP_STC_REF>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */\n};\n\n&zynqmp_dp_snd_codec0 {\n\tclocks = <&zynqmp_clk DP_AUDIO_REF>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/2023.1/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n#include \"include/dt-bindings/dma/xlnx-zynqmp-dpdma.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/power/xlnx-zynqmp-power.h\"\n#include \"include/dt-bindings/reset/xlnx-zynqmp-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tL2: l2-cache {\n\t\t\tcompatible = \"cache\";\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: opp-table-cpu {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tzynqmp_ipi: zynqmp_ipi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t\txlnx,ipi-id = <0>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff9905c0 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\treg = <0x0 0xff9905c0 0x0 0x20>,\n\t\t\t <0x0 0xff9905e0 0x0 0x20>,\n\t\t\t <0x0 0xff990e80 0x0 0x20>,\n\t\t\t <0x0 0xff990ea0 0x0 0x20>;\n\t\t\treg-names = \"local_request_region\",\n\t\t\t\t \"local_response_region\",\n\t\t\t\t \"remote_request_region\",\n\t\t\t\t \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <4>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t\tinterrupt-affinity = <&cpu0>,\n\t\t\t\t <&cpu1>,\n\t\t\t\t <&cpu2>,\n\t\t\t\t <&cpu3>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tzynqmp_firmware: zynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x1>;\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tnvmem_firmware {\n\t\t\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tsoc_revision: soc_revision@0 {\n\t\t\t\t\treg = <0x0 0x4>;\n\t\t\t\t};\n\t\t\t\t/* efuse access */\n\t\t\t\tefuse_dna: efuse_dna@c {\n\t\t\t\t\treg = <0xc 0xc>;\n\t\t\t\t};\n\t\t\t\tefuse_usr0: efuse_usr0@20 {\n\t\t\t\t\treg = <0x20 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr1: efuse_usr1@24 {\n\t\t\t\t\treg = <0x24 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr2: efuse_usr2@28 {\n\t\t\t\t\treg = <0x28 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr3: efuse_usr3@2c {\n\t\t\t\t\treg = <0x2c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr4: efuse_usr4@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr5: efuse_usr5@34 {\n\t\t\t\t\treg = <0x34 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr6: efuse_usr6@38 {\n\t\t\t\t\treg = <0x38 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr7: efuse_usr7@3c {\n\t\t\t\t\treg = <0x3c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_miscusr: efuse_miscusr@40 {\n\t\t\t\t\treg = <0x40 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_chash: efuse_chash@50 {\n\t\t\t\t\treg = <0x50 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_pufmisc: efuse_pufmisc@54 {\n\t\t\t\t\treg = <0x54 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_sec: efuse_sec@58 {\n\t\t\t\t\treg = <0x58 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_spkid: efuse_spkid@5c {\n\t\t\t\t\treg = <0x5c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_ppk0hash: efuse_ppk0hash@a0 {\n\t\t\t\t\treg = <0xa0 0x30>;\n\t\t\t\t};\n\t\t\t\tefuse_ppk1hash: efuse_ppk1hash@d0 {\n\t\t\t\t\treg = <0xd0 0x30>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tzynqmp_pcap: pcap {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t\t\t\tclock-names = \"ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\tmodepin_gpio: gpio {\n\t\t\t\tcompatible = \"xlnx,zynqmp-gpio-modepin\";\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&zynqmp_pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t};\n\n\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma-controller@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma-controller@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma-controller@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma-controller@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma-controller@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma-controller@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma-controller@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma-controller@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x0 0x10000>,\n\t\t\t <0x0 0xf9020000 0x0 0x20000>,\n\t\t\t <0x0 0xf9040000 0x0 0x20000>,\n\t\t\t <0x0 0xf9060000 0x0 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-mali\", \"arm,mali-400\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"gp\", \"gpmmu\", \"pp0\", \"ppmmu0\", \"pp1\", \"ppmmu1\";\n\t\t\tclock-names = \"bus\", \"core\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPU>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma-controller@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma-controller@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma-controller@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma-controller@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma-controller@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma-controller@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma-controller@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma-controller@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand-controller@ff100000 {\n\t\t\tcompatible = \"xlnx,zynqmp-nand-controller\", \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"controller\", \"bus\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_NAND>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_0>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;\n\t\t\treset-names = \"gem0_rst\";\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_1>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;\n\t\t\treset-names = \"gem1_rst\";\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_2>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;\n\t\t\treset-names = \"gem2_rst\";\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_3>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;\n\t\t\treset-names = \"gem3_rst\";\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPIO>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tperf_monitor_ocm: perf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa00000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_ddr: perf-monitor@fd0b0000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd0b0000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <6>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <10>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_cci: perf-monitor@fd490000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd490000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_lpd: perf-monitor@ffa10000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa10000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tiommus = <&smmu 0x4d0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_PCIE>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_QSPI>;\n\t\t};\n\n\t\tpsgtr: phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\";\n\t\t\t#phy-cells = <4>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x7FFF>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SATA>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SATA>;\n\t\t/*\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;*/\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_0>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-uart\", \"cdns,uart-r1p12\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-uart\", \"cdns,uart-r1p12\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_1>;\n\t\t};\n\n\t\tusb0: usb@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_0>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\t\t\treset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tranges;\n\n\t\t\tdwc3_0: usb@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>, <0 75 4>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n snps,resume-hs-terminations;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_1>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\n\t\t\tranges;\n\n\t\t\tdwc3_1: usb@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>, <0 76 4>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\tsnps,enable_guctl1_resume_quirk;\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n snps,resume-hs-terminations;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <60>;\n\t\t\treset-on-timeout;\n\t\t};\n\n\t\tlpd_watchdog: watchdog@ff150000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 52 1>;\n\t\t\treg = <0x0 0xff150000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\tinterrupt-names = \"ams-irq\";\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\treg-names = \"ams-base\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges = <0 0 0xffa50800 0x800>;\n\n\t\t\tams_ps: ams_ps@0 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams_pl@400 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x400 0x400>;\n\t\t\t};\n\t\t};\n\n\t\tzynqmp_dpdma: dma-controller@fd4c0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tdma-channels = <6>;\n\t\t\tiommus = <&smmu 0xce4>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tzynqmp_dpaud_setting: dp_aud@fd4ac000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpaud-setting\", \"syscon\";\n\t\t\treg = <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t};\n\n\t\tzynqmp_dpsub: display@fd4a0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>;\n\t\t\treg-names = \"dp\", \"blend\", \"av_buf\";\n\t\t\txlnx,dpaud-reg = <&zynqmp_dpaud_setting>;\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tiommus = <&smmu 0xce3>;\n\t\t\tclock-names = \"dp_apb_clk\", \"dp_aud_clk\", \"dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_DP>;\n\t\t\tdma-names = \"vid0\", \"vid1\", \"vid2\", \"gfx0\";\n\t\t\tdmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;\n\n\t\t\t/* dummy node to to indicate there's no child i2c device */\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm0\";\n\t\t\t\tdmas = <&zynqmp_dpdma 4>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm1\";\n\t\t\t\tdmas = <&zynqmp_dpdma 5>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card0: zynqmp_dp_snd_card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,\n\t\t\t\t\t\t <&zynqmp_dp_snd_pcm1>;\n\t\t\t\txlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/ac701-full.dtsi", "content": "&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/ac701-lite.dtsi", "content": "&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n i2c0 = &i2c1;\n rtc0 = &rtc;\n serial0 = &uart1;\n serial1 = &uart0;\n serial2 = &dcc;\n spi0 = &spi0;\n spi1 = &spi1;\n usb0 = &usb0;\n usb1 = &usb1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n\n\tsi5335_0: si5335_0 { /* clk0_usb - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5335_1: si5335_1 { /* clk1_dp - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 IRQ_TYPE_LEVEL_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO3\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO2\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO1\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n};\n\n&psgtr {\n\t/* usb3, dp */\n\tclocks = <&si5335_0>, <&si5335_1>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n\t/delete-property/ reset-gpios;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"super-speed\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n\treset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/kc705-full.dtsi", "content": "&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/kc705-lite.dtsi", "content": "&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/kcu105-tmr.dtsi", "content": "&tmr_0_MB1_axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/kcu105.dtsi", "content": "&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/sp701-rev1.0.dtsi", "content": "&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@1 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x3>;\n\t\t\tti,tx-internal-delay = <0x3>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/vcu118-rev2.0.dtsi", "content": "&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-property/ pcs-handle ;\n\t/delete-property/ managed ;\n\t/delete-property/ xlnx,switch-x-sgmii ;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@3 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\tti,sgmii-ref-clock-output-enable;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\treg = <3>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-a2197-sc-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller RevA\";\n\tcompatible = \"xlnx,versal-sc-revA\", \"xlnx,versal-sc\", \"xlnx,zynqmp\";\n\n\t/* SC Bank 43\n\tFIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS\n\tSYSCTLR_GPIO0 - 5 - conneced to versal */\n\t/* cpu thermal for MAX6643 fan control */\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tdc38_led {\n\t\t\tlabel = \"ds38-green\"; /* sc AB11 500_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc37_led {\n\t\t\tlabel = \"ds37-green\"; /* sc AD10 501_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc36_led {\n\t\t\tlabel = \"ds36-green\"; /* sc AD11 502_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t};\n};\n\n/* usb - type C - pl\n and micro usb 2.0, gt\n*/\n/* Feb 28/2019 version */\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tu-boot,dm-pre-reloc;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n/* TODO\nUSB0 MIO52-63\nUSB1 MIO64-75\n*/\n\n/*eth MDIO 76/77\neth reset MIO42\nmarwell m88e1512 - SGMII */\n&gem0 {\n\tphy-handle = <&phy0>;\n\t/* phy-mode = \"sgmii\"; DTG generates this properly */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: phy@21 {\n\t\treg = <21>; /* FIXME */\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5- 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 0 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\"; /* FIXME no linux driver */\n\t\t\t\treg = <0xc0>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <10000000>; /* 10 ohm */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\ti2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* FIXME connection to Samtec J212D */\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t/* FIXME connection to Samtec J53C */\n\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@5d { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@5d { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@5d { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"LPDDR4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-emu-itr8-cn13940875.dtsi", "content": "/ {\n\tcompatible = \"xlnx,versal-emu-itr8\", \"xlnx,versal-emu\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal EMU ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:9600\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n\n\tclk0212: clk0212 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <212000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n};\n\n&timer {\n clock-frequency = <440000>;\n};\n\n&serial0 {\n status = \"okay\";\n clocks = <&clk0212 &clk0212>;\n\tcurrent-speed = <9600>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-emu-rev1.9.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tcompatible = \"xlnx,versal-net-emu-1.9\", \"xlnx,versal-net-emu\";\n\tmodel = \"Xilinx Versal NET EMU 1.9\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t};\n\t};\n\n\tmemory: memory@0 {\n\t\treg = <0 0 0 0x10000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 rdinit=/bin/sh\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tfirmware {\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tclk1: clk1 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <1000000>; /* it doesn't matter on EMU */\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&clk1>, <&clk1>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET IPP/SPP OSPI\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-net-ipp-rev1.9.dtsi\"\n\n/ {\n\tmodel = \"Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI\";\n};\n\n&ospi {\n\tstatus = \"okay\";\n};\n\n&qspi {\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-ipp-rev1.9.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/clock/xlnx-versal-net-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-net-power.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-net-ipp-1.9\", \"xlnx,versal-net-spp-5.0\", \"xlnx,versal-net-spp\", \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal NET SPP 5.0/IPP 1.9\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t};\n\t};\n\n\tmemory: memory@0 {\n\t\treg = <0 0 0 0x80000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tref_clk: ref-clk {\n\t\tcompatible = \"fixed-clock\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x01>;\n\n\t\t\tversal_net_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-net-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupts = <0 57 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t<&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tzynqmp-ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupts = <0 57 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@eb3f0440 {\n\t\t\treg = <0 0xeb3f0440 0 0x20>,\n\t\t\t <0 0xeb3f0460 0 0x20>,\n\t\t\t <0 0xeb3f0280 0 0x20>,\n\t\t\t <0 0xeb3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tadma0: dma-controller@ebd00000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd00000 0 0x1000>;\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_0>;\n\t\t};\n\n\t\tadma1: dma-controller@ebd10000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd10000 0 0x1000>;\n\t\t\tinterrupts = <0 73 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_1>;\n\t\t};\n\n\t\tadma2: dma-controller@ebd20000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd20000 0 0x1000>;\n\t\t\tinterrupts = <0 74 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_2>;\n\t\t};\n\n\t\tadma3: dma-controller@ebd30000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd30000 0 0x1000>;\n\t\t\tinterrupts = <0 75 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_3>;\n\t\t};\n\n\t\tadma4: dma-controller@ebd40000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd40000 0 0x1000>;\n\t\t\tinterrupts = <0 76 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_4>;\n\t\t};\n\n\t\tadma5: dma-controller@ebd50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd50000 0 0x1000>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_5>;\n\t\t};\n\n\t\tadma6: dma-controller@ebd60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd60000 0 0x1000>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_6>;\n\t\t};\n\n\t\tadma7: dma-controller@ebd70000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd70000 0 0x1000>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_7>;\n\t\t};\n\n\t\tcan0: can@f1980000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1980000 0 0x6000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>;\n\t\t};\n\n\t\tcan1: can@f1990000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1990000 0 0x6000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>;\n\t\t};\n\n\t\tgem0: ethernet@f19e0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19e0000 0 0x1000>;\n\t\t\tinterrupts = <0 39 4>, <0 39 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>,\n\t\t\t\t <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_0>;\n\t\t\tmdio0: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\t\t#phy-cells = <1>;\n\t\t\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t\tti,rx-internal-delay = <11>;\n\t\t\t\t\tti,tx-internal-delay = <10>;\n\t\t\t\t\tti,fifo-depth = <1>;\n\t\t\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgem1: ethernet@f19f0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19f0000 0 0x1000>;\n\t\t\tinterrupts = <0 41 4>, <0 41 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy2>;\n\t\t\tphy-mode = \"rmii\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>,\n\t\t\t\t <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_1>;\n\t\t\tmdio1: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\t\tcompatible = \"ethernet-phy-id0007.0762\"; /* Vitesse VSC8540 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t};\n\n\t\tgpio0: gpio@f19d0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\treg = <0 0xf19d0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO>;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk PMC_LSBUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>;\n\t\t};\n\n\t\ti2c0: i2c@f1940000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1940000 0 0x1000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C0_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@f1950000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1950000 0 0x1000>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C1_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n\t\t};\n\n\t\ti3c: i3c-master@f1948000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\treg = <0 0xf1948000 0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclocks = <&versal_net_clk I2C_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_PMC>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 182 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,trigger-address = <0xc0000000>;\n\t\t\tis-dual = <0>;\n\t\t\tis-stacked = <0>;\n\t\t\tclocks = <&versal_net_clk OSPI_REF>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_OSPI>;\n\t\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\t\t\tmt35xu02g: flash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tcdns,read-delay = <0>;\n\t\t\t\tcdns,tshsl-ns = <0>;\n\t\t\t\tcdns,tsd2d-ns = <0>;\n\t\t\t\tcdns,tchsh-ns = <1>;\n\t\t\t\tcdns,tslch-ns = <1>;\n\t\t\t\tspi-tx-bus-width = <8>;\n\t\t\t\tspi-rx-bus-width = <8>;\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\tbroken-flash-reset;\n\t\t\t\tno-wp;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"ospi-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"ospi-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 183 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tnum-cs = <2>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\t\t\tclocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_QSPI>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>, <1>;\n\t\t\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <10000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi0-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"qspi0-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupts = <0 200 4>, <0 201 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 184 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_1>;\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 186 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_0>;\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_UART_0>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tserial1: serial@f1930000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1930000 0 0x1000>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_UART_1>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tsmmu: smmu@ec000000 {\n\t\t\tcompatible = \"arm,smmu-v3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xec000000 0 0x40000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tinterrupt-names = \"combined\";\n\t\t\tinterrupts = <0 169 4>;\n\t\t};\n\n\t\tspi0: spi@f1960000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupts = <0 23 4>;\n\t\t\treg = <0 0xf1960000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_0>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@f1970000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0 0xf1970000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_1>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tttc0: timer@f1dc0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dc0000 0x0 0x1000>;\n\t\t\tclocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_TTC_0>;\n\t\t};\n\n\t\tusb0: usb@f1e00000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0 0xf1e00000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t/* clocks = <&clk60>, <&clk60>; */\n\t\t\tclocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_0>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_0>;\n\n\t\t\tdwc3_0: dwc3@f1b00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0 0xf1b00000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 29 4>, <0 33 4>, <0 98 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"peripheral\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@f1e10000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0x0 0xf1e10000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tclocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_1>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_1>;\n\n\t\t\tdwc3_1: dwc3@f1c00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0x0 0xf1c00000 0x0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 34 4>, <0 38 4>, <0 99 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\twwdt0: watchdog@ecc10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecc10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>;\n\t\t};\n\n\t\twwdt1: watchdog@ecd10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecd10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>;\n\t\t};\n\n\t\twwdt2: watchdog@ece10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xece10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>;\n\t\t};\n\n\t\twwdt3: watchdog@ecf10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecf10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-vn-p-b2197-00-reva-pl.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VN-P-B2197 (Tenzing2)\n *\n * (C) Copyright 2022, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n\ti2c-mux@70 {\n\t\tcompatible = \"nxp,pca9545\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x70>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tqsfp56g_0: gpio@20 { /* u118 */\n\t\t\t\tcompatible = \"ti,tca6408\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"QSFP56G_0_OC_B\", \"QSFP56G_0_PWR_EN\", /* 0, 1 */\n\t\t\t\t\t\t\"QSFP56G_0_LED_1\", \"QSFP56G_0_LED_0\", /* 2, 3 */\n\t\t\t\t\t\t\"QSFP56G_0_MODPRS_B\", \"QSFP56G_0_LPMODE\", /* 4, 5 */\n\t\t\t\t\t\t\"QSFP56G_0_RESET_B\", \"QSFP56G_0_MODSEL_B\"; /* 6, 7 */\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tqsfp56g_1: gpio@20 { /* u117 */\n\t\t\t\tcompatible = \"ti,tca6408\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"QSFP56G_1_OC_B\", \"QSFP56G_1_PWR_EN\", /* 0, 1 */\n\t\t\t\t\t\t\"QSFP56G_1_LED_1\", \"QSFP56G_1_LED_0\", /* 2, 3 */\n\t\t\t\t\t\t\"QSFP56G_1_MODPRS_B\", \"QSFP56G_1_LPMODE\", /* 4, 5 */\n\t\t\t\t\t\t\"QSFP56G_1_RESET_B\", \"QSFP56G_1_MODSEL_B\"; /* 6, 7 */\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* J48 connector */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* J47 connector */\n\t\t};\n\t};\n/*\n\tGPIO_DIP_SW0-1\n\tGPIO_LED0-1\n\tGPIO_PB0-1\n\tGPIO_SMA\n\n*/\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-vn-p-b2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2)\n *\n * (C) Copyright 2022, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n\n/ {\n\tcompatible = \"xlnx,versal-net-vn-p-b2197-00-revA\",\n\t\t \"xlnx,versal-net-vn-p-b2197-00\", \"xlnx,versal-net\";\n};\n\n&i2c0 {\n\t/* Access via J70/J71 or J82/J83 */\n\tclock-frequency = <100000>;\n};\n\n&i2c1 {\n\t/* Access via J70/J71 or J82/J83 */\n\t/* By default this bus should have eeprom for board identification at 0x54 */\n\t/* SE/X-PRC card identification is also on this bus at 0x52 */\n\tclock-frequency = <100000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-vn-x-b2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal Net VNX board\n *\n * (C) Copyright 2022, Xilinx, Inc.\n * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-net-vn-x-b2197-00-revA\",\n\t\t \"xlnx,versal-net-vn-x-b2197-00\", \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal Net VNX\";\n\n\taliases {\n\t\tnvmem0 = &eeprom0;\n\t};\n};\n\n&adma0 {\n\tstatus = \"okay\";\n};\n\n&adma1 {\n\tstatus = \"okay\";\n};\n\n&adma2 {\n\tstatus = \"okay\";\n};\n\n&adma3 {\n\tstatus = \"okay\";\n};\n\n&adma4 {\n\tstatus = \"okay\";\n};\n\n&adma5 {\n\tstatus = \"okay\";\n};\n\n&adma6 {\n\tstatus = \"okay\";\n};\n\n&adma7 {\n\tstatus = \"okay\";\n};\n\n&lpd_wwdt0 {\n\tstatus = \"okay\";\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tphy-handle = <&phy>;\n\tphy-mode = \"rmii\";\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy: ethernet-phy {\n\t\t\treg = <4>;\n\t\t};\n\t};\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\teeprom0: eeprom@51 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t\tu-boot,dm-pre-reloc;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\teeprom1: eeprom@55 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x55>;\n\t\tu-boot,dm-pre-reloc;\n\t};\n};\n\n&ospi {\n\tstatus = \"okay\";\n\tis-dual = <0>;\n\tis-stacked = <1>;\n\treset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n\treset-names = \"qspi\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tmt35xu02g: flash@0 {\n\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <5000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"ospi-flash0\";\n\t\t\t\treg = <0 0x8000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\tno-1-8-v;\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&serial1 {\n\tstatus = \"okay\";\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tnum-cs = <3>;\n};\n\n&usb1 {\n\tstatus = \"okay\";\n};\n\n&dwc3_1 {\n\tstatus = \"okay\";\n\tsnps,refclk_fladj;\n\tsnps,mask_phy_reset;\n\tphy-names = \"usb3-phy\";\n};\n\n&wwdt0 {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-spp-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-spp-itr8-cn13940875\", \"xlnx,versal-spp-itr8\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal SPP ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &ospi;\n\t\tspi2 = &spi0;\n\t\tspi3 = &spi1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tusb0 = &usb0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>;\n\t};\n\tchosen {\n\t\tbootargs = \"rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n};\n\n&timer {\n\tclock-frequency = <2720000>;\n};\n\n&serial0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tmaximum-speed = \"high-speed\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n phy0: phy@0 {\n\t\treg = <0x0>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n phy1: phy@1 {\n\t\treg = <0x1>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <0x1>;\n\treg = <0x0 0xf1030000 0x0 0x1000>;\n\tclocks = <&clk125 &clk125>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot-boot.bin\";\n\t\t\t\treg = <0x0 0x6400000>;\n\t\t\t};\n\t\t\tpartition@6400000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x6400000 0x500000>;\n\t\t\t};\n\t\t\tpartition@6900000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x6900000 0x20000>;\n\t\t\t};\n\t\t\tpartition@6920000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x6920000 0x5E0000>;\n\t\t\t};\n\t\t\tpartition@7f40000 {\n\t\t\t\tlabel = \"qspi-bootenv\";\n\t\t\t\treg = <0x7f40000 0x40000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ospi {\n\tstatus = \"disabled\";\n\tclocks = <&clk125 &clk125>;\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\tcdns,fifo-depth = <508>;\n\tcdns,fifo-width = <4>;\n\tcdns,is-dma = <1>;\n\tcdns,trigger-address = <0x00000000>;\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t};\n\t\t\tpartition@600000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t};\n\t\t\tpartition@620000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <1>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <3>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\treg = <0x0 0x84000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-v350-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal v350 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-v350-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal v350 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &ospi;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&serial1 {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-01 revA OSPI\";\n\n\taliases {\n\t\tspi0 = &ospi;\n\t};\n};\n\n/* Mutually exclusive */\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\treset-names = \"qspi\";\n\tresets = <&versal_reset VERSAL_RST_OSPI>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&qspi {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n compatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n \"xlnx,versal-vc-p-a2197-00\",\n \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n model = \"Xilinx Versal A2197 Processor board revA\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tgpio0 = &gpio;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-01 revA QSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-02 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem0 {\n\tphy-handle = <&phy0>; /* u9 */\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@1 { /* Marvell 88E1512; U9 */\n\t\treg = <1>;\n\t};\n};\n\n&sdhci0 {\n\txlnx,mio-bank = <1>;\n};\n\n&sdhci1 { /* U1A */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n\n&dwc3_0 { /* U4 */\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"high-speed\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* U12 Catalyst EEPROM - AT24 should be equivalent */\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U13 and U15 */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U18 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <3>;\t/* FIXME - check SPI1_SS0-2_B */\n\n\tflash@0 { /* U19 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst26vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-03 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tserial0 = &serial0;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* Must be enabled via J90/J91 */\n\teeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 64Mb */\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x800000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* J99 MIO28 - MIO33 */\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U6 - IS25LQ032B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lq032b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi\"\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tspi0 = &ospi;\n\t};\n};\n\n&qspi {\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-04 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tphy1: phy@1 {\n\t\treg = <2>;\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tis-dual = <0>;\n\tis-stacked = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 512MB */\n\t\treg = <0>, <1>;\n\t\tstacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x20000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n#include \"include/dt-bindings/net/mscc-phy-vsc8531.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-05 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem0 {\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 { /* 88e1510 */\n\t\treg = <1>;\n\t};\n\tphy2: phy@2 { /* VSC8531 */\n\t\treg = <2>;\n\t\tvsc8531,rx-delay = ;\n\t\tvsc8531,tx-delay = ;\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>;\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tspi-tx-bus-width = <4>;\n\tspi-rx-bus-width = <4>;\n\n\tflash@0 { /* MX25U12835 128Mbit */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 16MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <104000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x1000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc0 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n};\n\n&sdhci1 { /* connector */\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA\";\n\n\taliases {\n\t\tserial2 = &dcc;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 {\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-01-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-01-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (QSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-02-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-02-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (EMMC)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-03-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-03-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (OSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva-x-ebm-01-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-01-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (QSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva-x-ebm-02-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-02-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (EMMC)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva-x-ebm-03-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-03-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (OSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck5000-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck5000 revA\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vck5000-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck5000 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &ospi;\n\t};\n\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x10000000>;\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&serial1 {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vek280-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VEK280 revA\n *\n * (C) Copyright 2022, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vek280-revA\", \"xlnx,versal-vek280\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vek280 Eval board revA\";\n\n\tmemory: memory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* VADJ_FMC_EN - LPD MIO23 */\n/* FAN - LPD MIO21/22 */\n/* VCC_PL_EN - LPD MIO20 */\n/* PCIE_PERST - LPD MIO18/19 */\n/* SD_BUSPWR - PMC MIO51 */\n/* PCIE_WAKE - PMC MIO50 */\n/* VCCPSLP_EN - PMC MIO49 */\n/* I2C SYSMON - PMC MIO39 - 41 */\n/* PCIE_PWRBRK - PMC MIO38 */\n/* ZU4_TRIGGER - PMC MIO37 */\n/* VCC_AUX_1V2 - MIO11 */\n\n&ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = ;\n\t\t\tti,tx-internal-delay = ;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vek280-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VEK280 revB\n *\n * (C) Copyright 2022, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vek280-revB\", \"xlnx,versal-vek280\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vek280 Eval board revB\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* VADJ_FMC_EN - LPD MIO23 */\n/* FAN - LPD MIO21/22 */\n/* VCC_PL_EN - LPD MIO20 */\n/* PCIE_PERST - LPD MIO18/19 */\n/* SD_BUSPWR - PMC MIO51 */\n/* PCIE_WAKE - PMC MIO50 */\n/* VCCPSLP_EN - PMC MIO49 */\n/* I2C SYSMON - PMC MIO39 - 41 */\n/* PCIE_PWRBRK - PMC MIO38 */\n/* ZU4_TRIGGER - PMC MIO37 */\n/* VCC_AUX_1V2 - MIO11 */\n\n&ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@1 { /* u198 - ADI1300 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id0283.bc30\";\n\t\t\treg = <1>;\n\t\t adi,rx-internal-delay-ps = <2000>;\n\t\t\tadi,tx-internal-delay-ps = <2000>;\n\t\t\tadi,fifo-depth-bits = <8>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t\treset-assert-us = <10>;\n\t\t\treset-deassert-us = <5000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vhk158-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VHK158 revA\n *\n * (C) Copyright 2022-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vhk158-revA\", \"xlnx,versal-vhk158\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vhk158 Eval board revA\";\n\n\tmemory: memory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* ZU4_TRIGGER - PMC MIO37 */\n/* PCIE_PWRBRK - PMC MIO38 */\n/* I2C SYSMON - PMC MIO39 - 41 */\n/* VCCPSLP_EN - PMC MIO49 */\n/* PCIE_WAKE - PMC MIO50 */\n/* SOC_EN - LPD MIO13 */\n/* PSFP_EN - LPD MIO15 */\n/* AUX_1V2_EN - LPD MIO16 */\n/* HBM_EN - LPD MIO17 */\n/* PCIE_PERST - LPD MIO18/19 */\n/* VCC_PL_EN - LPD MIO20 */\n/* FAN - LPD MIO21/22 */\n/* VADJ_FMC_EN - LPD MIO23 */\n\n&ospi { /* PMC MIO0 - 12, U297 MT35XU02G */\n\tstatus = \"okay\";\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = ;\n\t\t\tti,tx-internal-delay = ;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-virt.dtsi", "content": "#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-virt\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal Virtual\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tclk2: clk2 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <2670000>;\n\t};\n\n\tclk25: clk25 {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t\tclock-frequency = <2720000>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */\n\t\t\t <0x0 0xf9080000 0x0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x1 0x9 4>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x2>;\n\t\tranges;\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff060000 0x0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff070000 0x0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom1: eeprom@53 {\n\t\t\t\treg = <0x53>;\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t};\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom2: eeprom@55 {\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x55>;\n\t\t\t};\n\t\t};\n\n\t\tgpio: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tethernet0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 56 4>, <0x0 56 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy0: phy@0 {\n\t\t\t\treg = <0x0>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tethernet1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 58 4>, <0x0 58 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy1: phy@1 {\n\t\t\t\treg = <0x1>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xf12a0000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tnum-cs = <0x1>;\n\t\t\treg = <0x0 0xf1030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"n25q512a\", \"micron,m25p80\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-tx-bus-width = <4>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <108000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@100000 {\n\t\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@600000 {\n\t\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@620000 {\n\t\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <1>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <3>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0x0 0x84000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\treg = <0x0 0xf1040000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\treg = <0x0 0xf1050000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\t#address-cells = <0x2>;\n\t\t\t#size-cells = <0x2>;\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tranges;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125 &clk125>;\n\n\t\t\tdwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x10000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = ðernet0;\n\t\tethernet1 = ðernet1;\n\t\tqspi = &qspi;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1 (QSPI)\";\n};\n\n&qspi {\n#include \"versal-x-ebm-01-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-02-revA\",\n\t\t \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1 (EMMC)\";\n};\n\n&sdhci1 {\n#include \"versal-x-ebm-02-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-03-revA\",\n \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board rev1.1 (OSPI)\";\n};\n\n&ospi {\n#include \"versal-x-ebm-03-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-01-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (QSPI)\";\n};\n\n&qspi {\n#include \"versal-x-ebm-01-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-02-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (EMMC)\";\n};\n\n&sdhci1 {\n#include \"versal-x-ebm-02-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-03-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (OSPI)\";\n\n aliases {\n spi0 = &ospi;\n };\n};\n\n&ospi {\n#include \"versal-x-ebm-03-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tphy2: ethernet-phy@2 { /* u134 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <2>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 49 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vp-x-a2785-00 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vp-x-a2785-00 Eval board revA\";\n\tcompatible = \"xlnx,versal-vp-x-a2785-00-revA\",\n\t\t \"xlnx,versal-vp-x-a2785-00\", \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tstatus = \"okay\"; /* u93 and u92 */\n\tnum-cs = <2>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\tstatus = \"okay\";\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk120 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk120 Eval board revA\";\n\tcompatible = \"xlnx,versal-vpk120-revA\", \"xlnx,versal-vpk120\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <2>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vpk120-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk120 revB\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk120 Eval board revB\";\n\tcompatible = \"xlnx,versal-vpk120-revB\", \"xlnx,versal-vpk120\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <2>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\t/* Use for storing information about board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vpk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk180 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk180 Eval board revA\";\n\tcompatible = \"xlnx,versal-vpk180-revA\", \"xlnx,versal-vpk180\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <2>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\n\t/* Use for storing information about board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tu-boot,dm-pre-reloc;\n\t};\n};\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gpio0 {\n\t/* FIXME Fill names when versal starts */\n};\n\n&gpio1 {\n\t/* FIXME Fill names when versal starts */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-01 revA for vck190/vmk180\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\nnum-cs = <2>;\nspi-tx-bus-width = <4>;\nspi-rx-bus-width = <4>;\n#address-cells = <1>;\n#size-cells = <0>;\nis-dual = <1>;\nflash@0 {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 256MB */\n\treg = <0>, <1>;\n\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\tspi-tx-bus-width = <4>;\n\tspi-rx-bus-width = <4>;\n\tspi-max-frequency = <150000000>;\n\tpartition@0 {\n\t\tlabel = \"spi0-flash0\";\n\t\treg = <0x0 0x10000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-02 revA for vck190/vmk180\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/* emmc MIO 0-13 - MTFC8GAKAJCN */\nnon-removable;\ndisable-wp;\nbus-width = <8>;\nxlnx,mio-bank = <0>;\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/versal-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-03 revA for vck190/vmk180\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-resets.h\"\n/* U97 MT35XU02G */\ncompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\nbus-num = <2>;\nnum-cs = <1>;\n#address-cells = <1>;\n#size-cells = <0>;\nreset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\nflash@0 {\n\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\treg = <0>;\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcdns,read-delay = <0x0>;\n\tcdns,tshsl-ns = <0x0>;\n\tcdns,tsd2d-ns = <0x0>;\n\tcdns,tchsh-ns = <0x1>;\n\tcdns,tslch-ns = <0x1>;\n\tspi-tx-bus-width = <8>;\n\tspi-rx-bus-width = <8>;\n\tspi-max-frequency = <20000000>;\n\tno-wp;\n\tpartition@0 {\n\t\tlabel = \"spi0-flash0\";\n\t\treg = <0x0 0x8000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n\n\t aliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n rtc0 = &rtc;\n serial0 = &uart0;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tclock_si5338_0: clk27 {\t/* u55 SI5338-GM */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tclock_si5338_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_si5338_3: clk150 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <150000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&psgtr {\n\tstatus = \"okay\";\n\t/* dp, usb3, sata */\n\tclocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem2;\n i2c0 = &i2c0;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n spi0 = &spi0;\n spi1 = &spi1;\n usb0 = &usb1;\n };\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: ethernet-phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"hw\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-0\";\n\t\tnand-ecc-step-size = <1024>;\n\t\tnand-ecc-strength = <24>;\n\t\tnand-on-flash-bbt;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"hw\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-1\";\n\t\tnand-ecc-step-size = <1024>;\n\t\tnand-ecc-strength = <24>;\n\t\tnand-on-flash-bbt;\n\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: flash@0 {\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: flash@0 {\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n#include \n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n serial0 = &uart1;\n spi0 = &qspi;\n mmc0 = &sdhci0;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n switch-14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n switch-13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@34 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x34>;\n\t\t\t};\n\t\t\thwmon@35 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\thwmon@36 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n serial0 = &uart1;\n spi0 = &qspi;\n mmc0 = &sdhci0;\n };\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&watchdog0 {\n\treset-on-timeout;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu100-reva.dtsi", "content": "/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio-bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu100-revb.dtsi", "content": "/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\t aliases {\n i2c0 = &i2c1;\n rtc0 = &rtc;\n serial0 = &uart1;\n serial1 = &uart0;\n serial2 = &dcc;\n spi0 = &spi0;\n spi1 = &spi1;\n usb0 = &usb0;\n usb1 = &usb1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n led-vbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n\n\tsi5335_0: si5335_0 { /* clk0_usb - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5335_1: si5335_1 { /* clk1_dp - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 IRQ_TYPE_LEVEL_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO3\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO2\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO1\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* usb3, dp */\n\tclocks = <&si5335_0>, <&si5335_1>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n\t/delete-property/ reset-gpios;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"super-speed\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n\treset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zcu102-revb.dtsi\"\n\n/ {\n model = \"ZynqMP ZCU102 Rev1.0\";\n compatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n};\n\n&eeprom {\n #address-cells = <1>;\n #size-cells = <1>;\n\n board_sn: board-sn@0 {\n reg = <0x0 0x14>;\n };\n\n eth_mac: eth-mac@20 {\n reg = <0x20 0x6>;\n };\n\n board_name: board-name@d0 {\n reg = <0xd0 0x6>;\n };\n\n board_revision: board-revision@e0 {\n reg = <0xe0 0x3>;\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@21 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <21>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_4: out@4 {\n\t\t\t\t\t/* refclk4 for PS-GT, used for PCIE slot */\n\t\t\t\t\treg = <4>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 for PS-GT, used for PCIE */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* pcie, sata, usb3, dp */\n\tclocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\t/*\n\t * 1.0 revision has level shifter and this property should be\n\t * removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zcu102-reva.dtsi\"\n\n/ {\n model = \"ZynqMP ZCU102 RevB\";\n compatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n};\n\n&gem3 {\n phy-handle = <&phyc>;\n\tmdio: mdio {\n\t\tphyc: ethernet-phy@c {\n\t\t\t#phy-cells = <0x1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t/* Cleanup from RevA */\n\t\t/delete-node/ ethernet-phy@21;\n };\n};\n\n/* Fix collision with u61 */\n&i2c0 {\n i2c-mux@75 {\n i2c@2 {\n max15303@1b { /* u8 */\n compatible = \"maxim,max15303\";\n reg = <0x1b>;\n };\n /delete-node/ max15303@20;\n };\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* 8T49N287 - u182 */\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@20 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu104-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revC\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;\n\t};\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - IRPS5401_ALERT_B\n\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t * 2 - MAX6643_OT_B\n\t\t * 3 - MAX6643_FANFAIL_B\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t * 4, 10 - 17 - not connected\n\t\t */\n\t};\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* 8T49N287 - u182 */\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tu183: ina226@40 { /* u183 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 4, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\txlnx,mio-bank = <1>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\treg = <0xc>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\n\tina226-u67 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;\n\t};\n\tina226-u59 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n\tina226-u69 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;\n\t};\n\tina226-u66 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;\n\t};\n\tina226-u71 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u73 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tu67: ina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u67\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu59: ina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u59\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu61: ina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu60: ina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu64: ina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu69: ina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u69\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu66: ina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u66\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu63: ina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu3: ina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u3\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu71: ina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u71\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu73: ina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u73\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u57 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SI5382 - u48 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection FIXME */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, dp, usb3, sata */\n\tclocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revA\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu1275-revb.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU1275 RevB\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revB\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n mmc0 = &sdhci1;\n ethernet0 = &gem1;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t* 1.0 revision has level shifter and this property should be\n\t* removed for supporting UHS mode\n\t*/\n\tno-1-8-v;\n};\n\n&gem1 {\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu1285-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU1285 RevA\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1285 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1285-revA\", \"xlnx,zynqmp-zcu1285\", \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n mmc0 = &sdhci1;\n ethernet0 = &gem1; /* EMIO */\n i2c = &i2c0; /* EMIO */\n };\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n};\n\n&gem1 {\n\tmdio {\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu208-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU208\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU208 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu208-revA\", \"xlnx,zynqmp-zcu208\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu216-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU216\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU216 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu216-revA\", \"xlnx,zynqmp-zcu216\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu670-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR)\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU670 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu670-revA\", \"xlnx,zynqmp-zcu670\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\"; /* DS1 */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5381_6: si5381_6 { /* refclk_usb3 - u43 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"SFP3_TX_DISABLE\", \"SFP2_TX_DISABLE\", \"SFP1_TX_DISABLE\", /* 25 - 29 */\n\t\t \"SFP0_TX_DISABLE\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"SD_PWR_RST\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"SI5381_INT_ALM\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* Not in schematics */\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5381: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SI5381 - u43 */\n\t\t\t/*si5381: clock-generator@68 {\n\t\t\t\treg = <0x68>;\n\t\t\t};*/\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_psrefclk: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"si570_ps_ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 2Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&psgtr {\n\t/* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */\n\tclocks = <&si5381_6>;\n\tclock-names = \"ref2\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zcu670-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU670 (67DR) revB\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU670 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu670-revB\", \"xlnx,zynqmp-zcu670\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\"; /* DS1 */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5381_6: si5381_6 { /* refclk_usb3 - u43 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"SFP3_TX_DISABLE\", \"SFP2_TX_DISABLE\", \"SFP1_TX_DISABLE\", /* 25 - 29 */\n\t\t \"SFP0_TX_DISABLE\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"SD_PWR_RST\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"SI5381_INT_ALM\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* Not in schematics */\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5381: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SI5381 - u43 */\n\t\t\t/*si5381: clock-generator@68 {\n\t\t\t\treg = <0x68>;\n\t\t\t};*/\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_psrefclk: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"si570_ps_ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 2Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\txlnx,mio-bank = <1>;\n\tclk-phase-sd-hs = <120>, <60>;\n\tclk-phase-uhs-sdr25 = <132>, <60>;\n\tclk-phase-uhs-ddr50 = <153>, <48>;\n};\n\n&psgtr {\n\t/* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */\n\tclocks = <&si5381_6>;\n\tclock-names = \"ref2\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zedboard.dtsi", "content": "/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tu-boot,dm-pre-reloc;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tu-boot,dm-pre-reloc;\n};\n\n&uart1 {\n\tu-boot,dm-pre-reloc;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-a2197-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Versal System Controller on a2197 board RevA\";\n\tcompatible = \"xlnx,zynqmp-a2197-revA\", \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n i2c0 = &i2c0;\n nvmem0 = &eeprom1;\n nvmem1 = &eeprom0;\n serial0 = &uart0;\n };\n\n};\n\n&i2c0 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* this cover MGT board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* This cover processor board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tu-boot,dm-pre-reloc;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-e-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevA\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n nvmem1 = &eeprom_ebm;\n nvmem2 = &eeprom_fmc1;\n nvmem3 = &eeprom_fmc2;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n };\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tsi570_ddrdimm1_clk: si570_ddrdimm1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tsi570_lpddr4_clk2: si570_lpddr4_clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570_lpddr4_clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk1>;\n\t};\n\n\tsi570_hsdp_clk: si570_hsdp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi570_zsfp_clk: si570_zsfp_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_zsfp>;\n\t};\n\n\tsi570_user1_clk: si570_user1_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_user1>;\n\t};\n\n\tsi5332_1: si5332_1 { /* u142 - GEM0 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vcc-soc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;\n\t};\n\tina226-vcc-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc-pslp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;\n\t};\n\tina226-vcc-psfp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;\n\t};\n\tina226-vccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;\n\t};\n\tina226-vccaux-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;\n\t};\n\tina226-vcco-500 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;\n\t};\n\tina226-vcco-501 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;\n\t};\n\tina226-vcco-502 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;\n\t};\n\tina226-vcco-503 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;\n\t};\n\tina226-vcc-1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;\n\t};\n\tina226-vcc-3v3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;\n\t};\n\tina226-vcc-1v2-ddr4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;\n\t};\n\tina226-vcc-1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtyavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;\n\t};\n\tina226-mgtyavtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;\n\t};\n\tina226-mgtyvccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;\n\t};\n\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n/* GEM SGMII */\n&psgtr {\n\tstatus = \"okay\";\n\t/* gem0 */\n\tclocks = <&si5332_1>;\n\tclock-names = \"ref0\";\n};\n\n&gem0 {\n\tphys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@0 { /* u131 M88E1512 */\n\t\t\treg = <0>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"ZU4_TRIGGER\", \"SYSCTLR_PB\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"\", /* 85 - 89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"PMBUS_ALERT\", \"\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ttca6416_u233: gpio@20 { /* u233 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"\", \"\", /* 0 - 3 */\n\t\t\t\t\"PMBUS2_INA226_ALERT\", \"\", \"\", \"MAX6643_FULLSPD\", /* 4 - 7 */\n\t\t\t\t\"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 10 - 13 */\n\t\t\t\t\"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* u152 IR35215 0x16/0x46 vcc_soc */\n\t\t\t/* u179 ir38164 0x19/0x49 vcco_500 */\n\t\t\t/* u181 ir38164 0x1a/0x4a vcco_501 */\n\t\t\t/* u183 ir38164 0x1b/0x4b vcco_502 */\n\t\t\t/* u185 ir38164 0x1e/0x4e vadj_fmc */\n\t\t\t/* u187 ir38164 0x1F/0x4f mgtyavcc */\n\t\t\t/* u189 ir38164 0x20/0x50 mgtyavtt */\n\t\t\t/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */\n\t\t\t/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */\n\n\t\t\tirps5401_47: irps5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* pmbus / i2c 0x17 */\n\t\t\t};\n\t\t\tirps5401_4c: irps5401@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* pmbus / i2c 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: irps5401@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* pmbus / i2c 0x1d */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <500>; /* R440 */\n\t\t\t\t/* 0.80V @ 32A 1 of 6 Phases*/\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-soc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <500>; /* R1702 */\n\t\t\t\t/* 0.80V @ 18A */\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pmc\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* R1214 */\n\t\t\t\t/* 0.78V @ 500mA */\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u162 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r1221 */\n\t\t\t\t/* 0.78V @ 4A */\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pslp\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>; /* R1216 */\n\t\t\t\t/* 0.78V @ 1A */\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-psfp\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1219 */\n\t\t\t\t/* 0.78V @ 2A */\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* u39 8T49N240 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0x6c>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* R382 */\n\t\t\t\t/* 1.5V @ 3A */\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux-pmc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>; /* R1246 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u178 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-500\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>; /* R1300 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u180 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-501\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <2000>; /* R1313 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u182 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-502\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <2000>; /* R1330 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-503\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1229 */\n\t\t\t\t/* 1.8V @ 2A */\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u173 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v8\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>; /* R400 */\n\t\t\t\t/* 1.8V @ 6A */\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-3v3\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* R1232 */\n\t\t\t\t/* 3.3V @ 500mA */\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v2-ddr4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>; /* R1275 */\n\t\t\t\t/* 1.2V @ 4A */\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>; /* R1286 */\n\t\t\t\t/* 1.1V @ 4A */\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>; /* R1350 */\n\t\t\t\t/* 1.5V @ 10A */\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavcc\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <2000>; /* R1367 */\n\t\t\t\t/* 0.88V @ 6A */\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavtt\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>; /* R1384 */\n\t\t\t\t/* 1.2V @ 10A */\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyvccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>; /* r1679 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t\ti2c@5 { /* zSFP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_zsfp: clock-generator@5d { /* u192 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_zsfp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* USER_SI570_1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_user1: clock-generator@5f { /* u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>; /* FIXME check address */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"si570_user1\";\n\t\t\t};\n\n\t\t};\n\t\ti2c@7 { /* USER_SI570_2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* 0x5c too */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* and connector J212D */\n\t\t\teeprom_ebm: eeprom@52 { /* x-ebm module */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\t\t};\n\t\tfmc1: i2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t\teeprom_fmc1: eeprom@50 {\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\tfmc2: i2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t\teeprom_fmc2: eeprom@50 {\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LPDDR4_SI570_CLK2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_lpddr4clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4clk1: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* 8A34001 - U219B and J310 connector */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n\ti2c-mux@75 { /* u214 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\ti2c@0 { /* SFP0_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* SFP0 */\n\t\t};\n\t\ti2c@1 { /* SFP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@2 { /* QSFP1_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* QSFP1 */\n\t\t};\n\t\t/* 3 - 7 unused */\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-e-a2197-00-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevB System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-e-a2197-00-reva.dtsi\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevB\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revB\", \"xlnx,zynqmp-a2197-revB\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\t/delete-node/ ina226-vcco-500;\n\t/delete-node/ ina226-vcco-501;\n\t/delete-node/ ina226-vcco-502;\n};\n\n&i2c0 {\n\ti2c-mux@74 { /* u33 */\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t/delete-node/ clock-generator@6c;\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t/delete-node/ ina226@42;\n\t\t\t/delete-node/ ina226@43;\n\t\t\t/delete-node/ ina226@44;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-g-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 MGT Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-g-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\t aliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n mmc0 = &sdhci0;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n usb0 = &usb0;\n };\n\n\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u82 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&gem0 { /* eth MDIO 76/77 */\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 */\n\t\treg = <0>;\n\t\treset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 5 - 9 */\n\t\t \"\", \"\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"\", \"\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\ti2c-mux@74 { /* u94 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* CM_I2C_SCL - Samtec */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* PMBUS - AFX_PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\ttps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\ttps544@10 { /* u73 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\ttps544@11 { /* u76 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\ttps544@12 { /* u77 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\ttps544@13 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\ttps544@14 { /* u81 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\ttps544@15 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\ttps544@16 { /* u63 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\ttps544@17 { /* u66 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\ttps544@18 { /* u67 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\ttps544@19 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\ttps544@1d { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\ttps544@1e { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\ttps544@1f { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t\ttps544@20 { /* u71 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\t\t\tu74: ina226@40 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu75: ina226@41 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\"\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@43 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu82: ina226@44 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u82\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu84: ina226@45 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\ttps53681@60 { /* u53- 0xc0 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* fmc1 via JA2G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom_fmc1: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* fmc2 via JA3G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\teeprom_fmc2: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* fmc3 via JA4G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\teeprom_fmc3: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* ddr dimm */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"high-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-m-a2197-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-01-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n spi0 = &qspi;\n };\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\tina226-vcc0v6-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc0v6_lp4: ina226@49 { /* u101 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc0v6-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@60 { /* u69 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@5d { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n status = \"disabled\"; /* not at mem board */\n};\n\n&dwc3_1 {\n /delete-property/ phy-names ;\n /delete-property/ phys ;\n maximum-speed = \"high-speed\";\n snps,dis_u2_susphy_quirk ;\n snps,dis_u3_susphy_quirk ;\n status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-m-a2197-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-02-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n spi0 = &qspi;\n };\n\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@60 { /* u69 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* C0_DDR4_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\ti2c@6 { /* C2_DDR5_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\ti2c@7 { /* C3_DDR4_UDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_RLD3 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_RLD3_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_DDR5 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_DDR5_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-m-a2197-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-03-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n spi0 = &qspi;\n };\n\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n};\n\n&qspi {\n\tis-dual = <1>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@18 { /* u3022 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@60 { /* u69 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* DDR4_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_SODIMM_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_QDRIV */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_QDRIV_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-01-revA\", \"xlnx,zynqmp-x-prc-01\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\",\"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-02-revA\", \"xlnx,zynqmp-x-prc-02\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-03-revA\", \"xlnx,zynqmp-x-prc-03\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tx_prc_si5338: clock-generator@70 { /* U9 */\n\t\t\t\tcompatible = \"silabs,si5338\";\n\t\t\t\treg = <0x70>; /* FIXME */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-04-revA\", \"xlnx,zynqmp-x-prc-04\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-05-revA\", \"xlnx,zynqmp-x-prc-05\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n };\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@60 { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* 570JAC000900DG */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@60 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sc-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP Generic System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tmodel = \"ZynqMP Generic System Controller\";\n\tcompatible = \"xlnx,zynqmp-sc-revB\", \"xlnx,zynqmp-sc\", \"xlnx,zynqmp\";\n\n\taliases {\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n spi1 = &spi0;\n spi2 = &spi1;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tfwuen {\n\t\t\tlabel = \"sw16\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds40-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t\tds44-led {\n\t\t\tlabel = \"status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tsi5332_2: si5332_2 { /* u42 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\tpwm-fan {\n\t\tcompatible = \"pwm-fan\";\n\t\tpwms = <&ttc0 2 40000 1>;\n\t};\n\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\"QSPI_CS_B\", \"\", \"LED1\", \"LED2\", \"\", /* 5 - 9 */\n\t\t\"\", \"ZU4_TRIGGER\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\"I2C1_SDA\", \"UART0_RXD\", \"UART0_TXD\", \"\", \"\", /* 25 - 29 */\n\t\t\"\", \"\", \"\", \"\", \"I2C0_SCL\", /* 30 - 34 */\n\t\t\"I2C0_SDA\", \"UART1_TXD\", \"UART1_RXD\", \"GEM_TX_CLK\", \"GEM_TX_D0\", /* 35 - 39 */\n\t\t\"GEM_TX_D1\", \"GEM_TX_D2\", \"GEM_TX_D3\", \"GEM_TX_CTL\", \"GEM_RX_CLK\", /* 40 - 44 */\n\t\t\"GEM_RX_D0\", \"GEM_RX_D1\", \"GEM_RX_D2\", \"GEM_RX_D3\", \"GEM_RX_CTL\", /* 45 - 49 */\n\t\t\"GEM_MDC\", \"GEM_MDIO\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t\"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t\"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\"\", \"\", \"ETH_RESET_B\", /* 75 - 77, MIO end and EMIO start */\n\t\t\"\", \"\", /* 78 - 79 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem1_default>;\n\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy0: ethernet-phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = ;\n\t\t\tti,tx-internal-delay = ;\n\t\t\tti,fifo-depth = ;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t};\n\t};\n};\n\n&i2c0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\tclock-frequency = <100000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n};\n\n&i2c1 { /* i2c1 MIO 24-25 */\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <100000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t/* No reason to do pinctrl setup at u-boot stage */\n\t/* Use for storing information about SC board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tu-boot,dm-pre-reloc;\n\t};\n};\n\n/* USB 3.0 only */\n&psgtr {\n\t/* nc, nc, usb3 */\n\tclocks = <&si5332_2>;\n\tclock-names = \"ref2\";\n};\n\n&qspi { /* MIO 0-5 */\n\t/* QSPI should also have PINCTRL setup */\n\tflash@0 {\n\t\tcompatible = \"mt25qu512a\", \"m25p80\", \"jedec,spi-nor\"; /* mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x40000>; /* 256B but 256KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2280000 {\n\t\t\tlabel = \"Secure OS Storage\";\n\t\t\treg = <0x2280000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@22A0000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x22A0000 0x1d60000>; /* 29.375 MB */\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&ttc0 {\n\t#pwm-cells = <3>;\n};\n\n&uart1 { /* uart0 MIO36-37 */\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&pinctrl0 { /* required by spec */\n\tstatus = \"okay\";\n\tpinctrl_uart1_default: uart1-default {\n\t\tconf {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO37\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO36\";\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tconf {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tconf {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\t};\n\n\tpinctrl_gem1_default: gem1-default {\n\t\tconf {\n\t\t\tgroups = \"ethernet1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO44\", \"MIO46\", \"MIO48\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-bootstrap {\n\t\t\tpins = \"MIO45\", \"MIO47\", \"MIO49\";\n\t\t\tbias-disable;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO38\", \"MIO39\", \"MIO40\",\n\t\t\t\t\"MIO41\", \"MIO42\", \"MIO43\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio1\";\n\t\t\tgroups = \"mdio1_0_grp\";\n\t\t};\n\n\t\tmux {\n\t\t\tfunction = \"ethernet1\";\n\t\t\tgroups = \"ethernet1_0_grp\";\n\t\t};\n\t};\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sc-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP Generic System Controller\n *\n * Copyright (C) 2021-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sc-revb.dtsi\"\n\n/ {\n\tmodel = \"ZynqMP Generic System Controller\";\n\tcompatible = \"xlnx,zynqmp-sc-revC\", \"xlnx,zynqmp-sc\", \"xlnx,zynqmp\";\n};\n\n&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */\n\t/delete-node/ mdio;\n\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy0: ethernet-phy@1 { /* ADI1300 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id0283.bc30\";\n\t\t\treg = <1>;\n\t\t adi,rx-internal-delay-ps = <2400>;\n\t\t\tadi,tx-internal-delay-ps = <2400>;\n\t\t\tadi,fifo-depth-bits = <8>;\n\t\t\treset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;\n\t\t\treset-assert-us = <10>;\n\t\t\treset-deassert-us = <5000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sc-vek280-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VEK280 revA\n *\n * (C) Copyright 2022, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n\n&{/} {\n\tcompatible = \"xlnx,zynqmp-sc-vek280-revA\", \"xlnx,zynqmp-vek280-revA\",\n\t\t \"xlnx,zynqmp-vek280\", \"xlnx,zynqmp\";\n\n\tvc7_xin: vc7-xin {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <50000000>;\n\t};\n\n\tgtclk1_1: sys_clk_0 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 0>;\n\t};\n\n\tgtclk1_2: sys_clk_1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 1>;\n\t};\n\n\tgtclk1_3: sys_clk_2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 2>;\n\t};\n\n\tgtclk1_6: gtclk1_out6 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 3>;\n\t};\n\n\tgtclk1_7: gtclk1_out7 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 4>;\n\t};\n\n\tgtclk1_8: gtclk1_out8 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 5>;\n\t};\n\n\tgtclk1_10: ps_ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 6>;\n\t};\n\n\tgtclk1_11: gtclk1_out11 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 7>;\n\t};\n};\n\n&i2c0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\ttca6416_u233: gpio@20 { /* u233 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"\", \"\", \"SFP_MOD_ABS\", \"SFP_TX_DISABLE\", /* 0 - 3 */\n\t\t\t\t\"PMBUS2_INA226_ALERT\", \"\", \"\", \"\", /* 4 - 7 */\n\t\t\t\t\"FMCP1_FMC_PRSNT_M2C_B\", \"\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"\", /* 10 - 13 */\n\t\t\t\t\"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\tir35215_46: pmic@46 { /* IR35215 - u152 */\n\t\t\t\tcompatible = \"infineon,ir35215\";\n\t\t\t\treg = <0x46>; /* i2c addr - 0x16 */\n\t\t\t};\n\t\t\tirps5401_47: pmic5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* i2c addr 0x17 */\n\t\t\t};\n\t\t\tirps5401_48: pmic@48 { /* IRPS5401 - u279 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x48>; /* i2c addr 0x18 */\n\t\t\t};\n\t\t\tir38064_49: regulator@49 { /* IR38064 - u295 */\n\t\t\t\tcompatible = \"infineon,ir38064\";\n\t\t\t\treg = <0x49>; /* i2c addr 0x19 */\n\t\t\t};\n\t\t\tirps5401_4c: pmic@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: pmic@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* i2c addr 0x1d */\n\t\t\t};\n\t\t\tir38060_4e: regulator@4e { /* IR38060 - u282 */\n\t\t\t\tcompatible = \"infineon,ir38060\";\n\t\t\t\treg = <0x4e>; /* i2c addr 0x1e */\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* alerts coming to u233 and SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <500>; /* r440 */\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <500>; /* r1702 */\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* r382 */\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u355 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r2417 */\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>; /* r1830 */\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u260 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* r2386 */\n\t\t\t};\n\t\t\tvcco_hdio: ina226@46 { /* u356 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>; /* r2392 */\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpmbus2_ina226_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* alerts coming to u233 and SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* r2384 */\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>; /* r2000 */\n\t\t\t};\n\t\t\tmgtavcc: ina226@42 { /* u265 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* r1829 */\n\t\t\t};\n\t\t\tvcc1v5: ina226@43 { /* u264 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r2397 */\n\t\t\t};\n\t\t\tvcco_mio: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* r2401 */\n\t\t\t};\n\t\t\tmgtavtt: ina226@46 { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <500>; /* r1384 */\n\t\t\t};\n\t\t\tvcco_502: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* r1994 */\n\t\t\t};\n\t\t\tmgtvccaux: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>; /* r2384 */\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u306 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <500>; /* r2064 */\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u281 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>; /* r2031 */\n\t\t\t};\n\t\t\tlpdmgtyavcc: ina226@4b { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>; /* r2004 */\n\t\t\t};\n\t\t\tlpdmgtyavtt: ina226@4c { /* u309 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>; /* r1229 */\n\t\t\t};\n\t\t\tlpdmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>; /* r1679 */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\trc21008a_gtclk1: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* connector j374 */\n\t\t\t/* rc21008a at 0x9 u299 */\n\t\t\tvc7: clock-generator@9 {\n\t\t\t\tcompatible = \"renesas,rc21008a\";\n\t\t\t\treg = <0x9>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&vc7_xin>;\n\t\t\t\tclock-names = \"xin\";\n\t\t\t};\n\t\t};\n\t\tfmcp1_iic: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* to j51c */\n\t\t};\n\t\tsfp: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* sfp+ connector J376 */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sc-vek280-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VEK280 revB\n *\n * (C) Copyright 2022, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sc-vek280-reva.dtsi\"\n\n&{/} {\n\tcompatible = \"xlnx,zynqmp-sc-vek280-revB\", \"xlnx,zynqmp-vek280-revB\",\n\t\t \"xlnx,zynqmp-vek280\", \"xlnx,zynqmp\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sm-k24-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SM-K24 RevA\n *\n * (C) Copyright 2020 - 2021, Xilinx, Inc.\n * (C) Copyright 2022, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sm-k26-reva.dtsi\"\n\n/ {\n\tmodel = \"ZynqMP SM-K24 RevA/B/1\";\n\tcompatible = \"xlnx,zynqmp-sm-k24-rev1\", \"xlnx,zynqmp-sm-k24-revB\",\n\t\t \"xlnx,zynqmp-sm-k24-revA\", \"xlnx,zynqmp-sm-k24\",\n\t\t \"xlnx,zynqmp\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sm-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SM-K26 rev1/B/A\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP SM-K26 Rev1/B/A\";\n\tcompatible = \"xlnx,zynqmp-sm-k26-rev1\", \"xlnx,zynqmp-sm-k26-revB\",\n\t\t \"xlnx,zynqmp-sm-k26-revA\", \"xlnx,zynqmp-sm-k26\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\treserved-memory {\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tpmu_region: pmu@7ff00000 {\n\t\t\treg = <0x0 0x7ff00000 0x0 0x100000>;\n\t\t\tno-map;\n\t\t};\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tkey-fwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36-led {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n\tpwm-fan {\n\t\tcompatible = \"pwm-fan\";\n\t\tpwms = <&ttc0 2 40000 0>;\n\t};\n};\n\n&modepin_gpio {\n\tlabel = \"modepin\";\n};\n\n&ttc0 {\n\t#pwm-cells = <3>;\n};\n\n&pinctrl0 {\n status = \"okay\";\n pinctrl_sdhci0_default: sdhci0-default {\n conf {\n groups = \"sdio0_0_grp\";\n slew-rate = ;\n power-source = ;\n bias-disable;\n };\n\n mux {\n groups = \"sdio0_0_grp\";\n function = \"sdio0\";\n };\n };\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tspi_flash: flash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Image Selector\";\n\t\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"Image Selector Golden\";\n\t\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"Persistent Register\";\n\t\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@120000 {\n\t\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@140000 {\n\t\t\t\tlabel = \"Open_1\";\n\t\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t\t};\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t\t};\n\t\t\tpartition@f00000 {\n\t\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@f80000 {\n\t\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t\t};\n\t\t\tpartition@1c80000 {\n\t\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@1d00000 {\n\t\t\t\tlabel = \"Open_2\";\n\t\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t\t};\n\t\t\tpartition@1e00000 {\n\t\t\t\tlabel = \"Recovery Image\";\n\t\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@2000000 {\n\t\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@2200000 {\n\t\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@2220000 {\n\t\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@2240000 {\n\t\t\t\tlabel = \"SHA256\";\n\t\t\t\treg = <0x2240000 0x40000>; /* 256B but 256KB sector */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@2280000 {\n\t\t\t\tlabel = \"Secure OS Storage\";\n\t\t\t\treg = <0x2280000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@22A0000 {\n\t\t\t\tlabel = \"User\";\n\t\t\t\treg = <0x22A0000 0x1d60000>; /* 29.375 MB */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tassigned-clock-rates = <187498123>;\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tu-boot,dm-pre-reloc;\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues to be fixed in next board revision.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-smk-k24-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SMK-K24 RevA\n *\n * (C) Copyright 2020 - 2021, Xilinx, Inc.\n * (C) Copyright 2022, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sm-k24-reva.dtsi\"\n\n/ {\n\tmodel = \"ZynqMP SMK-K24 RevA\";\n\tcompatible = \"xlnx,zynqmp-smk-k24-revA\", \"xlnx,zynqmp-smk-k24\",\n\t\t \"xlnx,zynqmp\";\n};\n\n&sdhci0 {\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-smk-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sm-k26-reva.dtsi\"\n\n/ {\n model = \"ZynqMP SMK-K26 Rev1/B/A\";\n compatible = \"xlnx,zynqmp-smk-k26-rev1\", \"xlnx,zynqmp-smk-k26-revB\",\n \"xlnx,zynqmp-smk-k26-revA\", \"xlnx,zynqmp-smk-k26\",\n \"xlnx,zynqmp\";\n};\n\n&sdhci0 {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on vp-x-a2785-00 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vp-x-a2785-00-revA\",\n\t\t \"xlnx,zynqmp-vp-x-a2785-00\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n usb1 = &usb1;\n nvmem0 = &eeprom;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tj383 {\n\t\t\tlabel = \"j383\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds52 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* u285 - mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>; /* maybe 4 here */\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* sd MIO 45-51 */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 { /* u131 - M88e1512 */\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"\", \"\", \"\", \"VCCINT_FAULT_B\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\treg_vccint: tps53681@60 { /* u266 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@10 { /* u274 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@11 { /* u275 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@12 { /* u276 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc_cpm: tps544@14 { /* u272 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_util_3v3: tps544@1d { /* u278 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvcc_cpm: ina226@44 { /* u273 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpcie_smbus: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tpcie2_smbus: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\ti2c@3 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\t/* 6-7 unused */\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VPK120 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on VPK120 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vpk120-revA\",\n\t\t \"xlnx,zynqmp-vpk120\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n usb1 = &usb1;\n nvmem0 = &eeprom;\n };\n\n\tsi570_user1_fmc_clk: si570_user1_fmc_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&user_si570_1>;\n\t};\n\n\tsi570_ref_clk: si570_ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&ref_clk>;\n\t};\n\n\tsi570_lpddr4_clk3: si570_lpddr4_clk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk3>;\n\t};\n\n\tsi570_lpddr4_clk2: si570_lpddr4_clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570_lpddr4_clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk1>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw16 {\n\t\t\tlabel = \"sw16\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds40 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tu-boot,dm-pre-reloc;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"\", \"\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"\", /* 85 - 89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"QSFPDD1_MODSELL\", \"QSFPDD1_MODSELL\", /* 0 - 3 */\n\t\t\t\t \"PMBUS2_INA226_ALERT\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP1_FMC_PRSNT_M2C_B\", \"\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\tir38060_41: regulator@41 { /* IR38060 - u259 */\n\t\t\t\tcompatible = \"infineon,ir38060\", \"infineon,ir38064\";\n\t\t\t\treg = <0x41>; /* i2c addr 0x11 */\n\t\t\t};\n\t\t\tir38164_43: regulator@43 { /* IR38164 - u13 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x43>; /* i2c addr 0x13 */\n\t\t\t};\n\t\t\tir35221_45: pmic@46 { /* IR35221 - u152 */\n\t\t\t\tcompatible = \"infineon,ir35221\";\n\t\t\t\treg = <0x46>; /* PMBUS - 0x16 */\n\t\t\t};\n\t\t\tirps5401_47: pmic5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* i2c addr 0x17 */\n\t\t\t};\n\t\t\tir38164_49: regulator@49 { /* IR38164 - u189 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x49>; /* i2c addr 0x19 */\n\t\t\t};\n\t\t\tirps5401_4c: pmic@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: pmic@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tir38164_4e: regulator@4e { /* IR38164 - u184 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4e>; /* i2c addr 0x1e */\n\t\t\t};\n\t\t\tir38164_4f: regulator@4f { /* IR38164 - u187 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4f>; /* i2c addr 0x1f */\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u5 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpmbus2_ina226_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@42 { /* u265 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v5: ina226@43 { /* u264 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_mio: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavtt: ina226@46 { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtvccaux: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyavcc: ina226@4b { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tlpdmgtyavtt: ina226@4c { /* u260 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tuser_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"fmc_si570\";\n\t\t\t};\n\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tref_clk_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\tfmcp1_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tlpddr4_si570_clk3_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlpddr4_clk3: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk3\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\tqsfpdd_i2c: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* J1/J2 connectors */\n\t\t};\n\t\tidt8a34001_i2c: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* Via J310 connector */\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u219B */\n\t\t\t\treg = <0x5b>; /* FIXME not in schematics */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/clock/xlnx-versal-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_VERSAL_H\n#define _DT_BINDINGS_CLK_VERSAL_H\n\n#define PMC_PLL\t\t\t\t\t1\n#define APU_PLL\t\t\t\t\t2\n#define RPU_PLL\t\t\t\t\t3\n#define CPM_PLL\t\t\t\t\t4\n#define NOC_PLL\t\t\t\t\t5\n#define PLL_MAX\t\t\t\t\t6\n#define PMC_PRESRC\t\t\t\t7\n#define PMC_POSTCLK\t\t\t\t8\n#define PMC_PLL_OUT\t\t\t\t9\n#define PPLL\t\t\t\t\t10\n#define NOC_PRESRC\t\t\t\t11\n#define NOC_POSTCLK\t\t\t\t12\n#define NOC_PLL_OUT\t\t\t\t13\n#define NPLL\t\t\t\t\t14\n#define APU_PRESRC\t\t\t\t15\n#define APU_POSTCLK\t\t\t\t16\n#define APU_PLL_OUT\t\t\t\t17\n#define APLL\t\t\t\t\t18\n#define RPU_PRESRC\t\t\t\t19\n#define RPU_POSTCLK\t\t\t\t20\n#define RPU_PLL_OUT\t\t\t\t21\n#define RPLL\t\t\t\t\t22\n#define CPM_PRESRC\t\t\t\t23\n#define CPM_POSTCLK\t\t\t\t24\n#define CPM_PLL_OUT\t\t\t\t25\n#define CPLL\t\t\t\t\t26\n#define PPLL_TO_XPD\t\t\t\t27\n#define NPLL_TO_XPD\t\t\t\t28\n#define APLL_TO_XPD\t\t\t\t29\n#define RPLL_TO_XPD\t\t\t\t30\n#define EFUSE_REF\t\t\t\t31\n#define SYSMON_REF\t\t\t\t32\n#define IRO_SUSPEND_REF\t\t\t\t33\n#define USB_SUSPEND\t\t\t\t34\n#define SWITCH_TIMEOUT\t\t\t\t35\n#define RCLK_PMC\t\t\t\t36\n#define RCLK_LPD\t\t\t\t37\n#define WDT\t\t\t\t\t38\n#define TTC0\t\t\t\t\t39\n#define TTC1\t\t\t\t\t40\n#define TTC2\t\t\t\t\t41\n#define TTC3\t\t\t\t\t42\n#define GEM_TSU\t\t\t\t\t43\n#define GEM_TSU_LB\t\t\t\t44\n#define MUXED_IRO_DIV2\t\t\t\t45\n#define MUXED_IRO_DIV4\t\t\t\t46\n#define PSM_REF\t\t\t\t\t47\n#define GEM0_RX\t\t\t\t\t48\n#define GEM0_TX\t\t\t\t\t49\n#define GEM1_RX\t\t\t\t\t50\n#define GEM1_TX\t\t\t\t\t51\n#define CPM_CORE_REF\t\t\t\t52\n#define CPM_LSBUS_REF\t\t\t\t53\n#define CPM_DBG_REF\t\t\t\t54\n#define CPM_AUX0_REF\t\t\t\t55\n#define CPM_AUX1_REF\t\t\t\t56\n#define QSPI_REF\t\t\t\t57\n#define OSPI_REF\t\t\t\t58\n#define SDIO0_REF\t\t\t\t59\n#define SDIO1_REF\t\t\t\t60\n#define PMC_LSBUS_REF\t\t\t\t61\n#define I2C_REF\t\t\t\t\t62\n#define TEST_PATTERN_REF\t\t\t63\n#define DFT_OSC_REF\t\t\t\t64\n#define PMC_PL0_REF\t\t\t\t65\n#define PMC_PL1_REF\t\t\t\t66\n#define PMC_PL2_REF\t\t\t\t67\n#define PMC_PL3_REF\t\t\t\t68\n#define CFU_REF\t\t\t\t\t69\n#define SPARE_REF\t\t\t\t70\n#define NPI_REF\t\t\t\t\t71\n#define HSM0_REF\t\t\t\t72\n#define HSM1_REF\t\t\t\t73\n#define SD_DLL_REF\t\t\t\t74\n#define FPD_TOP_SWITCH\t\t\t\t75\n#define FPD_LSBUS\t\t\t\t76\n#define ACPU\t\t\t\t\t77\n#define DBG_TRACE\t\t\t\t78\n#define DBG_FPD\t\t\t\t\t79\n#define LPD_TOP_SWITCH\t\t\t\t80\n#define ADMA\t\t\t\t\t81\n#define LPD_LSBUS\t\t\t\t82\n#define CPU_R5\t\t\t\t\t83\n#define CPU_R5_CORE\t\t\t\t84\n#define CPU_R5_OCM\t\t\t\t85\n#define CPU_R5_OCM2\t\t\t\t86\n#define IOU_SWITCH\t\t\t\t87\n#define GEM0_REF\t\t\t\t88\n#define GEM1_REF\t\t\t\t89\n#define GEM_TSU_REF\t\t\t\t90\n#define USB0_BUS_REF\t\t\t\t91\n#define UART0_REF\t\t\t\t92\n#define UART1_REF\t\t\t\t93\n#define SPI0_REF\t\t\t\t94\n#define SPI1_REF\t\t\t\t95\n#define CAN0_REF\t\t\t\t96\n#define CAN1_REF\t\t\t\t97\n#define I2C0_REF\t\t\t\t98\n#define I2C1_REF\t\t\t\t99\n#define DBG_LPD\t\t\t\t\t100\n#define TIMESTAMP_REF\t\t\t\t101\n#define DBG_TSTMP\t\t\t\t102\n#define CPM_TOPSW_REF\t\t\t\t103\n#define USB3_DUAL_REF\t\t\t\t104\n#define OUTCLK_MAX\t\t\t\t105\n#define REF_CLK\t\t\t\t\t106\n#define PL_ALT_REF_CLK\t\t\t\t107\n#define MUXED_IRO\t\t\t\t108\n#define PL_EXT\t\t\t\t\t109\n#define PL_LB\t\t\t\t\t110\n#define MIO_50_OR_51\t\t\t\t111\n#define MIO_24_OR_25\t\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/clock/xlnx-versal-net-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2022, Xilinx Inc.\n * Copyright (C) 2022, Advanced Micro Devices, Inc.\n */\n\n#ifndef _DT_BINDINGS_CLK_VERSAL_NET_H\n#define _DT_BINDINGS_CLK_VERSAL_NET_H\n\n#include \n\n#define GEM0_REF_RX\t0xA9\n#define GEM0_REF_TX\t0xA8\n#define GEM1_REF_RX\t0xA2\n#define GEM1_REF_TX\t0xA1\n#define CAN0_REF_2X\t0x9E\n#define CAN1_REF_2X\t0xAC\n#define FPD_WWDT\t0x96\n#define ACPU_0\t\t0x98\n#define ACPU_1\t\t0x9B\n#define ACPU_2\t\t0x9A\n#define ACPU_3\t\t0x99\n#define I3C0_REF\t0x9D\n#define I3C1_REF\t0x9F\n#define USB1_BUS_REF\t0xAE\n#define LPD_WWDT\t0xAD\n\n/* Remove Versal specific node IDs */\n#undef APU_PLL\n#undef RPU_PLL\n#undef CPM_PLL\n#undef APU_PRESRC\n#undef APU_POSTCLK\n#undef APU_PLL_OUT\n#undef APLL\n#undef RPU_PRESRC\n#undef RPU_POSTCLK\n#undef RPU_PLL_OUT\n#undef RPLL\n#undef CPM_PRESRC\n#undef CPM_POSTCLK\n#undef CPM_PLL_OUT\n#undef CPLL\n#undef APLL_TO_XPD\n#undef RPLL_TO_XPD\n#undef RCLK_PMC\n#undef RCLK_LPD\n#undef WDT\n#undef MUXED_IRO_DIV2\n#undef MUXED_IRO_DIV4\n#undef PSM_REF\n#undef CPM_CORE_REF\n#undef CPM_LSBUS_REF\n#undef CPM_DBG_REF\n#undef CPM_AUX0_REF\n#undef CPM_AUX1_REF\n#undef CPU_R5\n#undef CPU_R5_CORE\n#undef CPU_R5_OCM\n#undef CPU_R5_OCM2\n#undef CAN0_REF\n#undef CAN1_REF\n#undef I2C0_REF\n#undef I2C1_REF\n#undef CPM_TOPSW_REF\n#undef USB3_DUAL_REF\n#undef MUXED_IRO\n#undef PL_EXT\n#undef PL_LB\n#undef MIO_50_OR_51\n#undef MIO_24_OR_25\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Xilinx Zynq MPSoC Firmware layer\n *\n * Copyright (C) 2014-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_ZYNQMP_H\n#define _DT_BINDINGS_CLK_ZYNQMP_H\n\n#define IOPLL\t\t\t0\n#define RPLL\t\t\t1\n#define APLL\t\t\t2\n#define DPLL\t\t\t3\n#define VPLL\t\t\t4\n#define IOPLL_TO_FPD\t\t5\n#define RPLL_TO_FPD\t\t6\n#define APLL_TO_LPD\t\t7\n#define DPLL_TO_LPD\t\t8\n#define VPLL_TO_LPD\t\t9\n#define ACPU\t\t\t10\n#define ACPU_HALF\t\t11\n#define DBF_FPD\t\t\t12\n#define DBF_LPD\t\t\t13\n#define DBG_TRACE\t\t14\n#define DBG_TSTMP\t\t15\n#define DP_VIDEO_REF\t\t16\n#define DP_AUDIO_REF\t\t17\n#define DP_STC_REF\t\t18\n#define GDMA_REF\t\t19\n#define DPDMA_REF\t\t20\n#define DDR_REF\t\t\t21\n#define SATA_REF\t\t22\n#define PCIE_REF\t\t23\n#define GPU_REF\t\t\t24\n#define GPU_PP0_REF\t\t25\n#define GPU_PP1_REF\t\t26\n#define TOPSW_MAIN\t\t27\n#define TOPSW_LSBUS\t\t28\n#define GTGREF0_REF\t\t29\n#define LPD_SWITCH\t\t30\n#define LPD_LSBUS\t\t31\n#define USB0_BUS_REF\t\t32\n#define USB1_BUS_REF\t\t33\n#define USB3_DUAL_REF\t\t34\n#define USB0\t\t\t35\n#define USB1\t\t\t36\n#define CPU_R5\t\t\t37\n#define CPU_R5_CORE\t\t38\n#define CSU_SPB\t\t\t39\n#define CSU_PLL\t\t\t40\n#define PCAP\t\t\t41\n#define IOU_SWITCH\t\t42\n#define GEM_TSU_REF\t\t43\n#define GEM_TSU\t\t\t44\n#define GEM0_TX\t\t\t45\n#define GEM1_TX\t\t\t46\n#define GEM2_TX\t\t\t47\n#define GEM3_TX\t\t\t48\n#define GEM0_RX\t\t\t49\n#define GEM1_RX\t\t\t50\n#define GEM2_RX\t\t\t51\n#define GEM3_RX\t\t\t52\n#define QSPI_REF\t\t53\n#define SDIO0_REF\t\t54\n#define SDIO1_REF\t\t55\n#define UART0_REF\t\t56\n#define UART1_REF\t\t57\n#define SPI0_REF\t\t58\n#define SPI1_REF\t\t59\n#define NAND_REF\t\t60\n#define I2C0_REF\t\t61\n#define I2C1_REF\t\t62\n#define CAN0_REF\t\t63\n#define CAN1_REF\t\t64\n#define CAN0\t\t\t65\n#define CAN1\t\t\t66\n#define DLL_REF\t\t\t67\n#define ADMA_REF\t\t68\n#define TIMESTAMP_REF\t\t69\n#define AMS_REF\t\t\t70\n#define PL0_REF\t\t\t71\n#define PL1_REF\t\t\t72\n#define PL2_REF\t\t\t73\n#define PL3_REF\t\t\t74\n#define WDT\t\t\t75\n#define IOPLL_INT\t\t76\n#define IOPLL_PRE_SRC\t\t77\n#define IOPLL_HALF\t\t78\n#define IOPLL_INT_MUX\t\t79\n#define IOPLL_POST_SRC\t\t80\n#define RPLL_INT\t\t81\n#define RPLL_PRE_SRC\t\t82\n#define RPLL_HALF\t\t83\n#define RPLL_INT_MUX\t\t84\n#define RPLL_POST_SRC\t\t85\n#define APLL_INT\t\t86\n#define APLL_PRE_SRC\t\t87\n#define APLL_HALF\t\t88\n#define APLL_INT_MUX\t\t89\n#define APLL_POST_SRC\t\t90\n#define DPLL_INT\t\t91\n#define DPLL_PRE_SRC\t\t92\n#define DPLL_HALF\t\t93\n#define DPLL_INT_MUX\t\t94\n#define DPLL_POST_SRC\t\t95\n#define VPLL_INT\t\t96\n#define VPLL_PRE_SRC\t\t97\n#define VPLL_HALF\t\t98\n#define VPLL_INT_MUX\t\t99\n#define VPLL_POST_SRC\t\t100\n#define CAN0_MIO\t\t101\n#define CAN1_MIO\t\t102\n#define ACPU_FULL\t\t103\n#define GEM0_REF\t\t104\n#define GEM1_REF\t\t105\n#define GEM2_REF\t\t106\n#define GEM3_REF\t\t107\n#define GEM0_REF_UNG\t\t108\n#define GEM1_REF_UNG\t\t109\n#define GEM2_REF_UNG\t\t110\n#define GEM3_REF_UNG\t\t111\n#define LPD_WDT\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h", "content": "/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */\n/*\n * Copyright 2019 Laurent Pinchart \n */\n\n#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n\n#define ZYNQMP_DPDMA_VIDEO0\t\t0\n#define ZYNQMP_DPDMA_VIDEO1\t\t1\n#define ZYNQMP_DPDMA_VIDEO2\t\t2\n#define ZYNQMP_DPDMA_GRAPHICS\t\t3\n#define ZYNQMP_DPDMA_AUDIO0\t\t4\n#define ZYNQMP_DPDMA_AUDIO1\t\t5\n\n#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/gpio/gpio.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most GPIO bindings.\n *\n * Most GPIO bindings include a flags cell as part of the GPIO specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_GPIO_GPIO_H\n#define _DT_BINDINGS_GPIO_GPIO_H\n\n/* Bit 0 express polarity */\n#define GPIO_ACTIVE_HIGH 0\n#define GPIO_ACTIVE_LOW 1\n\n/* Bit 1 express single-endedness */\n#define GPIO_PUSH_PULL 0\n#define GPIO_SINGLE_ENDED 2\n\n/* Bit 2 express Open drain or open source */\n#define GPIO_LINE_OPEN_SOURCE 0\n#define GPIO_LINE_OPEN_DRAIN 4\n\n/*\n * Open Drain/Collector is the combination of single-ended open drain interface.\n * Open Source/Emitter is the combination of single-ended open source interface.\n */\n#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)\n#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)\n\n/* Bit 3 express GPIO suspend/resume and reset persistence */\n#define GPIO_PERSISTENT 0\n#define GPIO_TRANSITORY 8\n\n/* Bit 4 express pull up */\n#define GPIO_PULL_UP 16\n\n/* Bit 5 express pull down */\n#define GPIO_PULL_DOWN 32\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/input/input.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most input bindings.\n *\n * Most input bindings include key code, matrix key code format.\n * In most cases, key code and matrix key code format uses\n * the standard values/macro defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INPUT_INPUT_H\n#define _DT_BINDINGS_INPUT_INPUT_H\n\n/*\n * Device properties and quirks\n */\n\n#define INPUT_PROP_POINTER\t\t0x00\t/* needs a pointer */\n#define INPUT_PROP_DIRECT\t\t0x01\t/* direct input devices */\n#define INPUT_PROP_BUTTONPAD\t\t0x02\t/* has button(s) under pad */\n#define INPUT_PROP_SEMI_MT\t\t0x03\t/* touch rectangle only */\n#define INPUT_PROP_TOPBUTTONPAD\t\t0x04\t/* softbuttons at top of pad */\n#define INPUT_PROP_POINTING_STICK\t0x05\t/* is a pointing stick */\n#define INPUT_PROP_ACCELEROMETER\t0x06\t/* has accelerometer */\n\n#define INPUT_PROP_MAX\t\t\t0x1f\n#define INPUT_PROP_CNT\t\t\t(INPUT_PROP_MAX + 1)\n\n\n/*\n * Event types\n */\n\n#define EV_SYN\t\t\t0x00\n#define EV_KEY\t\t\t0x01\n#define EV_REL\t\t\t0x02\n#define EV_ABS\t\t\t0x03\n#define EV_MSC\t\t\t0x04\n#define EV_SW\t\t\t0x05\n#define EV_LED\t\t\t0x11\n#define EV_SND\t\t\t0x12\n#define EV_REP\t\t\t0x14\n#define EV_FF\t\t\t0x15\n#define EV_PWR\t\t\t0x16\n#define EV_FF_STATUS\t\t0x17\n#define EV_MAX\t\t\t0x1f\n#define EV_CNT\t\t\t(EV_MAX+1)\n\n/*\n * Synchronization events.\n */\n\n#define SYN_REPORT\t\t0\n#define SYN_CONFIG\t\t1\n#define SYN_MT_REPORT\t\t2\n#define SYN_DROPPED\t\t3\n#define SYN_MAX\t\t\t0xf\n#define SYN_CNT\t\t\t(SYN_MAX+1)\n\n/*\n * Keys and buttons\n *\n * Most of the keys/buttons are modeled after USB HUT 1.12\n * (see http://www.usb.org/developers/hidpage).\n * Abbreviations in the comments:\n * AC - Application Control\n * AL - Application Launch Button\n * SC - System Control\n */\n\n#define KEY_RESERVED\t\t0\n#define KEY_ESC\t\t\t1\n#define KEY_1\t\t\t2\n#define KEY_2\t\t\t3\n#define KEY_3\t\t\t4\n#define KEY_4\t\t\t5\n#define KEY_5\t\t\t6\n#define KEY_6\t\t\t7\n#define KEY_7\t\t\t8\n#define KEY_8\t\t\t9\n#define KEY_9\t\t\t10\n#define KEY_0\t\t\t11\n#define KEY_MINUS\t\t12\n#define KEY_EQUAL\t\t13\n#define KEY_BACKSPACE\t\t14\n#define KEY_TAB\t\t\t15\n#define KEY_Q\t\t\t16\n#define KEY_W\t\t\t17\n#define KEY_E\t\t\t18\n#define KEY_R\t\t\t19\n#define KEY_T\t\t\t20\n#define KEY_Y\t\t\t21\n#define KEY_U\t\t\t22\n#define KEY_I\t\t\t23\n#define KEY_O\t\t\t24\n#define KEY_P\t\t\t25\n#define KEY_LEFTBRACE\t\t26\n#define KEY_RIGHTBRACE\t\t27\n#define KEY_ENTER\t\t28\n#define KEY_LEFTCTRL\t\t29\n#define KEY_A\t\t\t30\n#define KEY_S\t\t\t31\n#define KEY_D\t\t\t32\n#define KEY_F\t\t\t33\n#define KEY_G\t\t\t34\n#define KEY_H\t\t\t35\n#define KEY_J\t\t\t36\n#define KEY_K\t\t\t37\n#define KEY_L\t\t\t38\n#define KEY_SEMICOLON\t\t39\n#define KEY_APOSTROPHE\t\t40\n#define KEY_GRAVE\t\t41\n#define KEY_LEFTSHIFT\t\t42\n#define KEY_BACKSLASH\t\t43\n#define KEY_Z\t\t\t44\n#define KEY_X\t\t\t45\n#define KEY_C\t\t\t46\n#define KEY_V\t\t\t47\n#define KEY_B\t\t\t48\n#define KEY_N\t\t\t49\n#define KEY_M\t\t\t50\n#define KEY_COMMA\t\t51\n#define KEY_DOT\t\t\t52\n#define KEY_SLASH\t\t53\n#define KEY_RIGHTSHIFT\t\t54\n#define KEY_KPASTERISK\t\t55\n#define KEY_LEFTALT\t\t56\n#define KEY_SPACE\t\t57\n#define KEY_CAPSLOCK\t\t58\n#define KEY_F1\t\t\t59\n#define KEY_F2\t\t\t60\n#define KEY_F3\t\t\t61\n#define KEY_F4\t\t\t62\n#define KEY_F5\t\t\t63\n#define KEY_F6\t\t\t64\n#define KEY_F7\t\t\t65\n#define KEY_F8\t\t\t66\n#define KEY_F9\t\t\t67\n#define KEY_F10\t\t\t68\n#define KEY_NUMLOCK\t\t69\n#define KEY_SCROLLLOCK\t\t70\n#define KEY_KP7\t\t\t71\n#define KEY_KP8\t\t\t72\n#define KEY_KP9\t\t\t73\n#define KEY_KPMINUS\t\t74\n#define KEY_KP4\t\t\t75\n#define KEY_KP5\t\t\t76\n#define KEY_KP6\t\t\t77\n#define KEY_KPPLUS\t\t78\n#define KEY_KP1\t\t\t79\n#define KEY_KP2\t\t\t80\n#define KEY_KP3\t\t\t81\n#define KEY_KP0\t\t\t82\n#define KEY_KPDOT\t\t83\n\n#define KEY_ZENKAKUHANKAKU\t85\n#define KEY_102ND\t\t86\n#define KEY_F11\t\t\t87\n#define KEY_F12\t\t\t88\n#define KEY_RO\t\t\t89\n#define KEY_KATAKANA\t\t90\n#define KEY_HIRAGANA\t\t91\n#define KEY_HENKAN\t\t92\n#define KEY_KATAKANAHIRAGANA\t93\n#define KEY_MUHENKAN\t\t94\n#define KEY_KPJPCOMMA\t\t95\n#define KEY_KPENTER\t\t96\n#define KEY_RIGHTCTRL\t\t97\n#define KEY_KPSLASH\t\t98\n#define KEY_SYSRQ\t\t99\n#define KEY_RIGHTALT\t\t100\n#define KEY_LINEFEED\t\t101\n#define KEY_HOME\t\t102\n#define KEY_UP\t\t\t103\n#define KEY_PAGEUP\t\t104\n#define KEY_LEFT\t\t105\n#define KEY_RIGHT\t\t106\n#define KEY_END\t\t\t107\n#define KEY_DOWN\t\t108\n#define KEY_PAGEDOWN\t\t109\n#define KEY_INSERT\t\t110\n#define KEY_DELETE\t\t111\n#define KEY_MACRO\t\t112\n#define KEY_MUTE\t\t113\n#define KEY_VOLUMEDOWN\t\t114\n#define KEY_VOLUMEUP\t\t115\n#define KEY_POWER\t\t116\t/* SC System Power Down */\n#define KEY_KPEQUAL\t\t117\n#define KEY_KPPLUSMINUS\t\t118\n#define KEY_PAUSE\t\t119\n#define KEY_SCALE\t\t120\t/* AL Compiz Scale (Expose) */\n\n#define KEY_KPCOMMA\t\t121\n#define KEY_HANGEUL\t\t122\n#define KEY_HANGUEL\t\tKEY_HANGEUL\n#define KEY_HANJA\t\t123\n#define KEY_YEN\t\t\t124\n#define KEY_LEFTMETA\t\t125\n#define KEY_RIGHTMETA\t\t126\n#define KEY_COMPOSE\t\t127\n#define KEY_STOP\t\t128\t/* AC Stop */\n#define KEY_AGAIN\t\t129\n#define KEY_PROPS\t\t130\t/* AC Properties */\n#define KEY_UNDO\t\t131\t/* AC Undo */\n#define KEY_FRONT\t\t132\n#define KEY_COPY\t\t133\t/* AC Copy */\n#define KEY_OPEN\t\t134\t/* AC Open */\n#define KEY_PASTE\t\t135\t/* AC Paste */\n#define KEY_FIND\t\t136\t/* AC Search */\n#define KEY_CUT\t\t\t137\t/* AC Cut */\n#define KEY_HELP\t\t138\t/* AL Integrated Help Center */\n#define KEY_MENU\t\t139\t/* Menu (show menu) */\n#define KEY_CALC\t\t140\t/* AL Calculator */\n#define KEY_SETUP\t\t141\n#define KEY_SLEEP\t\t142\t/* SC System Sleep */\n#define KEY_WAKEUP\t\t143\t/* System Wake Up */\n#define KEY_FILE\t\t144\t/* AL Local Machine Browser */\n#define KEY_SENDFILE\t\t145\n#define KEY_DELETEFILE\t\t146\n#define KEY_XFER\t\t147\n#define KEY_PROG1\t\t148\n#define KEY_PROG2\t\t149\n#define KEY_WWW\t\t\t150\t/* AL Internet Browser */\n#define KEY_MSDOS\t\t151\n#define KEY_COFFEE\t\t152\t/* AL Terminal Lock/Screensaver */\n#define KEY_SCREENLOCK\t\tKEY_COFFEE\n#define KEY_ROTATE_DISPLAY\t153\t/* Display orientation for e.g. tablets */\n#define KEY_DIRECTION\t\tKEY_ROTATE_DISPLAY\n#define KEY_CYCLEWINDOWS\t154\n#define KEY_MAIL\t\t155\n#define KEY_BOOKMARKS\t\t156\t/* AC Bookmarks */\n#define KEY_COMPUTER\t\t157\n#define KEY_BACK\t\t158\t/* AC Back */\n#define KEY_FORWARD\t\t159\t/* AC Forward */\n#define KEY_CLOSECD\t\t160\n#define KEY_EJECTCD\t\t161\n#define KEY_EJECTCLOSECD\t162\n#define KEY_NEXTSONG\t\t163\n#define KEY_PLAYPAUSE\t\t164\n#define KEY_PREVIOUSSONG\t165\n#define KEY_STOPCD\t\t166\n#define KEY_RECORD\t\t167\n#define KEY_REWIND\t\t168\n#define KEY_PHONE\t\t169\t/* Media Select Telephone */\n#define KEY_ISO\t\t\t170\n#define KEY_CONFIG\t\t171\t/* AL Consumer Control Configuration */\n#define KEY_HOMEPAGE\t\t172\t/* AC Home */\n#define KEY_REFRESH\t\t173\t/* AC Refresh */\n#define KEY_EXIT\t\t174\t/* AC Exit */\n#define KEY_MOVE\t\t175\n#define KEY_EDIT\t\t176\n#define KEY_SCROLLUP\t\t177\n#define KEY_SCROLLDOWN\t\t178\n#define KEY_KPLEFTPAREN\t\t179\n#define KEY_KPRIGHTPAREN\t180\n#define KEY_NEW\t\t\t181\t/* AC New */\n#define KEY_REDO\t\t182\t/* AC Redo/Repeat */\n\n#define KEY_F13\t\t\t183\n#define KEY_F14\t\t\t184\n#define KEY_F15\t\t\t185\n#define KEY_F16\t\t\t186\n#define KEY_F17\t\t\t187\n#define KEY_F18\t\t\t188\n#define KEY_F19\t\t\t189\n#define KEY_F20\t\t\t190\n#define KEY_F21\t\t\t191\n#define KEY_F22\t\t\t192\n#define KEY_F23\t\t\t193\n#define KEY_F24\t\t\t194\n\n#define KEY_PLAYCD\t\t200\n#define KEY_PAUSECD\t\t201\n#define KEY_PROG3\t\t202\n#define KEY_PROG4\t\t203\n#define KEY_DASHBOARD\t\t204\t/* AL Dashboard */\n#define KEY_SUSPEND\t\t205\n#define KEY_CLOSE\t\t206\t/* AC Close */\n#define KEY_PLAY\t\t207\n#define KEY_FASTFORWARD\t\t208\n#define KEY_BASSBOOST\t\t209\n#define KEY_PRINT\t\t210\t/* AC Print */\n#define KEY_HP\t\t\t211\n#define KEY_CAMERA\t\t212\n#define KEY_SOUND\t\t213\n#define KEY_QUESTION\t\t214\n#define KEY_EMAIL\t\t215\n#define KEY_CHAT\t\t216\n#define KEY_SEARCH\t\t217\n#define KEY_CONNECT\t\t218\n#define KEY_FINANCE\t\t219\t/* AL Checkbook/Finance */\n#define KEY_SPORT\t\t220\n#define KEY_SHOP\t\t221\n#define KEY_ALTERASE\t\t222\n#define KEY_CANCEL\t\t223\t/* AC Cancel */\n#define KEY_BRIGHTNESSDOWN\t224\n#define KEY_BRIGHTNESSUP\t225\n#define KEY_MEDIA\t\t226\n\n#define KEY_SWITCHVIDEOMODE\t227\t/* Cycle between available video\n\t\t\t\t\t outputs (Monitor/LCD/TV-out/etc) */\n#define KEY_KBDILLUMTOGGLE\t228\n#define KEY_KBDILLUMDOWN\t229\n#define KEY_KBDILLUMUP\t\t230\n\n#define KEY_SEND\t\t231\t/* AC Send */\n#define KEY_REPLY\t\t232\t/* AC Reply */\n#define KEY_FORWARDMAIL\t\t233\t/* AC Forward Msg */\n#define KEY_SAVE\t\t234\t/* AC Save */\n#define KEY_DOCUMENTS\t\t235\n\n#define KEY_BATTERY\t\t236\n\n#define KEY_BLUETOOTH\t\t237\n#define KEY_WLAN\t\t238\n#define KEY_UWB\t\t\t239\n\n#define KEY_UNKNOWN\t\t240\n#define KEY_VIDEO_NEXT\t\t241\t/* drive next video source */\n#define KEY_VIDEO_PREV\t\t242\t/* drive previous video source */\n#define KEY_BRIGHTNESS_CYCLE\t243\t/* brightness up, after max is min */\n#define KEY_BRIGHTNESS_AUTO\t244\t/* Set Auto Brightness: manual\n\t\t\t\t\t brightness control is off,\n\t\t\t\t\t rely on ambient */\n#define KEY_BRIGHTNESS_ZERO\tKEY_BRIGHTNESS_AUTO\n#define KEY_DISPLAY_OFF\t\t245\t/* display device to off state */\n\n#define KEY_WWAN\t\t246\t/* Wireless WAN (LTE, UMTS, GSM, etc.) */\n#define KEY_WIMAX\t\tKEY_WWAN\n#define KEY_RFKILL\t\t247\t/* Key that controls all radios */\n\n#define KEY_MICMUTE\t\t248\t/* Mute / unmute the microphone */\n\n/* Code 255 is reserved for special needs of AT keyboard driver */\n\n#define BTN_MISC\t\t0x100\n#define BTN_0\t\t\t0x100\n#define BTN_1\t\t\t0x101\n#define BTN_2\t\t\t0x102\n#define BTN_3\t\t\t0x103\n#define BTN_4\t\t\t0x104\n#define BTN_5\t\t\t0x105\n#define BTN_6\t\t\t0x106\n#define BTN_7\t\t\t0x107\n#define BTN_8\t\t\t0x108\n#define BTN_9\t\t\t0x109\n\n#define BTN_MOUSE\t\t0x110\n#define BTN_LEFT\t\t0x110\n#define BTN_RIGHT\t\t0x111\n#define BTN_MIDDLE\t\t0x112\n#define BTN_SIDE\t\t0x113\n#define BTN_EXTRA\t\t0x114\n#define BTN_FORWARD\t\t0x115\n#define BTN_BACK\t\t0x116\n#define BTN_TASK\t\t0x117\n\n#define BTN_JOYSTICK\t\t0x120\n#define BTN_TRIGGER\t\t0x120\n#define BTN_THUMB\t\t0x121\n#define BTN_THUMB2\t\t0x122\n#define BTN_TOP\t\t\t0x123\n#define BTN_TOP2\t\t0x124\n#define BTN_PINKIE\t\t0x125\n#define BTN_BASE\t\t0x126\n#define BTN_BASE2\t\t0x127\n#define BTN_BASE3\t\t0x128\n#define BTN_BASE4\t\t0x129\n#define BTN_BASE5\t\t0x12a\n#define BTN_BASE6\t\t0x12b\n#define BTN_DEAD\t\t0x12f\n\n#define BTN_GAMEPAD\t\t0x130\n#define BTN_SOUTH\t\t0x130\n#define BTN_A\t\t\tBTN_SOUTH\n#define BTN_EAST\t\t0x131\n#define BTN_B\t\t\tBTN_EAST\n#define BTN_C\t\t\t0x132\n#define BTN_NORTH\t\t0x133\n#define BTN_X\t\t\tBTN_NORTH\n#define BTN_WEST\t\t0x134\n#define BTN_Y\t\t\tBTN_WEST\n#define BTN_Z\t\t\t0x135\n#define BTN_TL\t\t\t0x136\n#define BTN_TR\t\t\t0x137\n#define BTN_TL2\t\t\t0x138\n#define BTN_TR2\t\t\t0x139\n#define BTN_SELECT\t\t0x13a\n#define BTN_START\t\t0x13b\n#define BTN_MODE\t\t0x13c\n#define BTN_THUMBL\t\t0x13d\n#define BTN_THUMBR\t\t0x13e\n\n#define BTN_DIGI\t\t0x140\n#define BTN_TOOL_PEN\t\t0x140\n#define BTN_TOOL_RUBBER\t\t0x141\n#define BTN_TOOL_BRUSH\t\t0x142\n#define BTN_TOOL_PENCIL\t\t0x143\n#define BTN_TOOL_AIRBRUSH\t0x144\n#define BTN_TOOL_FINGER\t\t0x145\n#define BTN_TOOL_MOUSE\t\t0x146\n#define BTN_TOOL_LENS\t\t0x147\n#define BTN_TOOL_QUINTTAP\t0x148\t/* Five fingers on trackpad */\n#define BTN_TOUCH\t\t0x14a\n#define BTN_STYLUS\t\t0x14b\n#define BTN_STYLUS2\t\t0x14c\n#define BTN_TOOL_DOUBLETAP\t0x14d\n#define BTN_TOOL_TRIPLETAP\t0x14e\n#define BTN_TOOL_QUADTAP\t0x14f\t/* Four fingers on trackpad */\n\n#define BTN_WHEEL\t\t0x150\n#define BTN_GEAR_DOWN\t\t0x150\n#define BTN_GEAR_UP\t\t0x151\n\n#define KEY_OK\t\t\t0x160\n#define KEY_SELECT\t\t0x161\n#define KEY_GOTO\t\t0x162\n#define KEY_CLEAR\t\t0x163\n#define KEY_POWER2\t\t0x164\n#define KEY_OPTION\t\t0x165\n#define KEY_INFO\t\t0x166\t/* AL OEM Features/Tips/Tutorial */\n#define KEY_TIME\t\t0x167\n#define KEY_VENDOR\t\t0x168\n#define KEY_ARCHIVE\t\t0x169\n#define KEY_PROGRAM\t\t0x16a\t/* Media Select Program Guide */\n#define KEY_CHANNEL\t\t0x16b\n#define KEY_FAVORITES\t\t0x16c\n#define KEY_EPG\t\t\t0x16d\n#define KEY_PVR\t\t\t0x16e\t/* Media Select Home */\n#define KEY_MHP\t\t\t0x16f\n#define KEY_LANGUAGE\t\t0x170\n#define KEY_TITLE\t\t0x171\n#define KEY_SUBTITLE\t\t0x172\n#define KEY_ANGLE\t\t0x173\n#define KEY_ZOOM\t\t0x174\n#define KEY_MODE\t\t0x175\n#define KEY_KEYBOARD\t\t0x176\n#define KEY_SCREEN\t\t0x177\n#define KEY_PC\t\t\t0x178\t/* Media Select Computer */\n#define KEY_TV\t\t\t0x179\t/* Media Select TV */\n#define KEY_TV2\t\t\t0x17a\t/* Media Select Cable */\n#define KEY_VCR\t\t\t0x17b\t/* Media Select VCR */\n#define KEY_VCR2\t\t0x17c\t/* VCR Plus */\n#define KEY_SAT\t\t\t0x17d\t/* Media Select Satellite */\n#define KEY_SAT2\t\t0x17e\n#define KEY_CD\t\t\t0x17f\t/* Media Select CD */\n#define KEY_TAPE\t\t0x180\t/* Media Select Tape */\n#define KEY_RADIO\t\t0x181\n#define KEY_TUNER\t\t0x182\t/* Media Select Tuner */\n#define KEY_PLAYER\t\t0x183\n#define KEY_TEXT\t\t0x184\n#define KEY_DVD\t\t\t0x185\t/* Media Select DVD */\n#define KEY_AUX\t\t\t0x186\n#define KEY_MP3\t\t\t0x187\n#define KEY_AUDIO\t\t0x188\t/* AL Audio Browser */\n#define KEY_VIDEO\t\t0x189\t/* AL Movie Browser */\n#define KEY_DIRECTORY\t\t0x18a\n#define KEY_LIST\t\t0x18b\n#define KEY_MEMO\t\t0x18c\t/* Media Select Messages */\n#define KEY_CALENDAR\t\t0x18d\n#define KEY_RED\t\t\t0x18e\n#define KEY_GREEN\t\t0x18f\n#define KEY_YELLOW\t\t0x190\n#define KEY_BLUE\t\t0x191\n#define KEY_CHANNELUP\t\t0x192\t/* Channel Increment */\n#define KEY_CHANNELDOWN\t\t0x193\t/* Channel Decrement */\n#define KEY_FIRST\t\t0x194\n#define KEY_LAST\t\t0x195\t/* Recall Last */\n#define KEY_AB\t\t\t0x196\n#define KEY_NEXT\t\t0x197\n#define KEY_RESTART\t\t0x198\n#define KEY_SLOW\t\t0x199\n#define KEY_SHUFFLE\t\t0x19a\n#define KEY_BREAK\t\t0x19b\n#define KEY_PREVIOUS\t\t0x19c\n#define KEY_DIGITS\t\t0x19d\n#define KEY_TEEN\t\t0x19e\n#define KEY_TWEN\t\t0x19f\n#define KEY_VIDEOPHONE\t\t0x1a0\t/* Media Select Video Phone */\n#define KEY_GAMES\t\t0x1a1\t/* Media Select Games */\n#define KEY_ZOOMIN\t\t0x1a2\t/* AC Zoom In */\n#define KEY_ZOOMOUT\t\t0x1a3\t/* AC Zoom Out */\n#define KEY_ZOOMRESET\t\t0x1a4\t/* AC Zoom */\n#define KEY_WORDPROCESSOR\t0x1a5\t/* AL Word Processor */\n#define KEY_EDITOR\t\t0x1a6\t/* AL Text Editor */\n#define KEY_SPREADSHEET\t\t0x1a7\t/* AL Spreadsheet */\n#define KEY_GRAPHICSEDITOR\t0x1a8\t/* AL Graphics Editor */\n#define KEY_PRESENTATION\t0x1a9\t/* AL Presentation App */\n#define KEY_DATABASE\t\t0x1aa\t/* AL Database App */\n#define KEY_NEWS\t\t0x1ab\t/* AL Newsreader */\n#define KEY_VOICEMAIL\t\t0x1ac\t/* AL Voicemail */\n#define KEY_ADDRESSBOOK\t\t0x1ad\t/* AL Contacts/Address Book */\n#define KEY_MESSENGER\t\t0x1ae\t/* AL Instant Messaging */\n#define KEY_DISPLAYTOGGLE\t0x1af\t/* Turn display (LCD) on and off */\n#define KEY_BRIGHTNESS_TOGGLE\tKEY_DISPLAYTOGGLE\n#define KEY_SPELLCHECK\t\t0x1b0 /* AL Spell Check */\n#define KEY_LOGOFF\t\t0x1b1 /* AL Logoff */\n\n#define KEY_DOLLAR\t\t0x1b2\n#define KEY_EURO\t\t0x1b3\n\n#define KEY_FRAMEBACK\t\t0x1b4\t/* Consumer - transport controls */\n#define KEY_FRAMEFORWARD\t0x1b5\n#define KEY_CONTEXT_MENU\t0x1b6\t/* GenDesc - system context menu */\n#define KEY_MEDIA_REPEAT\t0x1b7\t/* Consumer - transport control */\n#define KEY_10CHANNELSUP\t0x1b8\t/* 10 channels up (10+) */\n#define KEY_10CHANNELSDOWN\t0x1b9\t/* 10 channels down (10-) */\n#define KEY_IMAGES\t\t0x1ba\t/* AL Image Browser */\n\n#define KEY_DEL_EOL\t\t0x1c0\n#define KEY_DEL_EOS\t\t0x1c1\n#define KEY_INS_LINE\t\t0x1c2\n#define KEY_DEL_LINE\t\t0x1c3\n\n#define KEY_FN\t\t\t0x1d0\n#define KEY_FN_ESC\t\t0x1d1\n#define KEY_FN_F1\t\t0x1d2\n#define KEY_FN_F2\t\t0x1d3\n#define KEY_FN_F3\t\t0x1d4\n#define KEY_FN_F4\t\t0x1d5\n#define KEY_FN_F5\t\t0x1d6\n#define KEY_FN_F6\t\t0x1d7\n#define KEY_FN_F7\t\t0x1d8\n#define KEY_FN_F8\t\t0x1d9\n#define KEY_FN_F9\t\t0x1da\n#define KEY_FN_F10\t\t0x1db\n#define KEY_FN_F11\t\t0x1dc\n#define KEY_FN_F12\t\t0x1dd\n#define KEY_FN_1\t\t0x1de\n#define KEY_FN_2\t\t0x1df\n#define KEY_FN_D\t\t0x1e0\n#define KEY_FN_E\t\t0x1e1\n#define KEY_FN_F\t\t0x1e2\n#define KEY_FN_S\t\t0x1e3\n#define KEY_FN_B\t\t0x1e4\n\n#define KEY_BRL_DOT1\t\t0x1f1\n#define KEY_BRL_DOT2\t\t0x1f2\n#define KEY_BRL_DOT3\t\t0x1f3\n#define KEY_BRL_DOT4\t\t0x1f4\n#define KEY_BRL_DOT5\t\t0x1f5\n#define KEY_BRL_DOT6\t\t0x1f6\n#define KEY_BRL_DOT7\t\t0x1f7\n#define KEY_BRL_DOT8\t\t0x1f8\n#define KEY_BRL_DOT9\t\t0x1f9\n#define KEY_BRL_DOT10\t\t0x1fa\n\n#define KEY_NUMERIC_0\t\t0x200\t/* used by phones, remote controls, */\n#define KEY_NUMERIC_1\t\t0x201\t/* and other keypads */\n#define KEY_NUMERIC_2\t\t0x202\n#define KEY_NUMERIC_3\t\t0x203\n#define KEY_NUMERIC_4\t\t0x204\n#define KEY_NUMERIC_5\t\t0x205\n#define KEY_NUMERIC_6\t\t0x206\n#define KEY_NUMERIC_7\t\t0x207\n#define KEY_NUMERIC_8\t\t0x208\n#define KEY_NUMERIC_9\t\t0x209\n#define KEY_NUMERIC_STAR\t0x20a\n#define KEY_NUMERIC_POUND\t0x20b\n#define KEY_NUMERIC_A\t\t0x20c\t/* Phone key A - HUT Telephony 0xb9 */\n#define KEY_NUMERIC_B\t\t0x20d\n#define KEY_NUMERIC_C\t\t0x20e\n#define KEY_NUMERIC_D\t\t0x20f\n\n#define KEY_CAMERA_FOCUS\t0x210\n#define KEY_WPS_BUTTON\t\t0x211\t/* WiFi Protected Setup key */\n\n#define KEY_TOUCHPAD_TOGGLE\t0x212\t/* Request switch touchpad on or off */\n#define KEY_TOUCHPAD_ON\t\t0x213\n#define KEY_TOUCHPAD_OFF\t0x214\n\n#define KEY_CAMERA_ZOOMIN\t0x215\n#define KEY_CAMERA_ZOOMOUT\t0x216\n#define KEY_CAMERA_UP\t\t0x217\n#define KEY_CAMERA_DOWN\t\t0x218\n#define KEY_CAMERA_LEFT\t\t0x219\n#define KEY_CAMERA_RIGHT\t0x21a\n\n#define KEY_ATTENDANT_ON\t0x21b\n#define KEY_ATTENDANT_OFF\t0x21c\n#define KEY_ATTENDANT_TOGGLE\t0x21d\t/* Attendant call on or off */\n#define KEY_LIGHTS_TOGGLE\t0x21e\t/* Reading light on or off */\n\n#define BTN_DPAD_UP\t\t0x220\n#define BTN_DPAD_DOWN\t\t0x221\n#define BTN_DPAD_LEFT\t\t0x222\n#define BTN_DPAD_RIGHT\t\t0x223\n\n#define KEY_ALS_TOGGLE\t\t0x230\t/* Ambient light sensor */\n\n#define KEY_BUTTONCONFIG\t\t0x240\t/* AL Button Configuration */\n#define KEY_TASKMANAGER\t\t0x241\t/* AL Task/Project Manager */\n#define KEY_JOURNAL\t\t0x242\t/* AL Log/Journal/Timecard */\n#define KEY_CONTROLPANEL\t\t0x243\t/* AL Control Panel */\n#define KEY_APPSELECT\t\t0x244\t/* AL Select Task/Application */\n#define KEY_SCREENSAVER\t\t0x245\t/* AL Screen Saver */\n#define KEY_VOICECOMMAND\t\t0x246\t/* Listening Voice Command */\n\n#define KEY_BRIGHTNESS_MIN\t\t0x250\t/* Set Brightness to Minimum */\n#define KEY_BRIGHTNESS_MAX\t\t0x251\t/* Set Brightness to Maximum */\n\n#define KEY_KBDINPUTASSIST_PREV\t\t0x260\n#define KEY_KBDINPUTASSIST_NEXT\t\t0x261\n#define KEY_KBDINPUTASSIST_PREVGROUP\t\t0x262\n#define KEY_KBDINPUTASSIST_NEXTGROUP\t\t0x263\n#define KEY_KBDINPUTASSIST_ACCEPT\t\t0x264\n#define KEY_KBDINPUTASSIST_CANCEL\t\t0x265\n\n#define BTN_TRIGGER_HAPPY\t\t0x2c0\n#define BTN_TRIGGER_HAPPY1\t\t0x2c0\n#define BTN_TRIGGER_HAPPY2\t\t0x2c1\n#define BTN_TRIGGER_HAPPY3\t\t0x2c2\n#define BTN_TRIGGER_HAPPY4\t\t0x2c3\n#define BTN_TRIGGER_HAPPY5\t\t0x2c4\n#define BTN_TRIGGER_HAPPY6\t\t0x2c5\n#define BTN_TRIGGER_HAPPY7\t\t0x2c6\n#define BTN_TRIGGER_HAPPY8\t\t0x2c7\n#define BTN_TRIGGER_HAPPY9\t\t0x2c8\n#define BTN_TRIGGER_HAPPY10\t\t0x2c9\n#define BTN_TRIGGER_HAPPY11\t\t0x2ca\n#define BTN_TRIGGER_HAPPY12\t\t0x2cb\n#define BTN_TRIGGER_HAPPY13\t\t0x2cc\n#define BTN_TRIGGER_HAPPY14\t\t0x2cd\n#define BTN_TRIGGER_HAPPY15\t\t0x2ce\n#define BTN_TRIGGER_HAPPY16\t\t0x2cf\n#define BTN_TRIGGER_HAPPY17\t\t0x2d0\n#define BTN_TRIGGER_HAPPY18\t\t0x2d1\n#define BTN_TRIGGER_HAPPY19\t\t0x2d2\n#define BTN_TRIGGER_HAPPY20\t\t0x2d3\n#define BTN_TRIGGER_HAPPY21\t\t0x2d4\n#define BTN_TRIGGER_HAPPY22\t\t0x2d5\n#define BTN_TRIGGER_HAPPY23\t\t0x2d6\n#define BTN_TRIGGER_HAPPY24\t\t0x2d7\n#define BTN_TRIGGER_HAPPY25\t\t0x2d8\n#define BTN_TRIGGER_HAPPY26\t\t0x2d9\n#define BTN_TRIGGER_HAPPY27\t\t0x2da\n#define BTN_TRIGGER_HAPPY28\t\t0x2db\n#define BTN_TRIGGER_HAPPY29\t\t0x2dc\n#define BTN_TRIGGER_HAPPY30\t\t0x2dd\n#define BTN_TRIGGER_HAPPY31\t\t0x2de\n#define BTN_TRIGGER_HAPPY32\t\t0x2df\n#define BTN_TRIGGER_HAPPY33\t\t0x2e0\n#define BTN_TRIGGER_HAPPY34\t\t0x2e1\n#define BTN_TRIGGER_HAPPY35\t\t0x2e2\n#define BTN_TRIGGER_HAPPY36\t\t0x2e3\n#define BTN_TRIGGER_HAPPY37\t\t0x2e4\n#define BTN_TRIGGER_HAPPY38\t\t0x2e5\n#define BTN_TRIGGER_HAPPY39\t\t0x2e6\n#define BTN_TRIGGER_HAPPY40\t\t0x2e7\n\n/* We avoid low common keys in module aliases so they don't get huge. */\n#define KEY_MIN_INTERESTING\tKEY_MUTE\n#define KEY_MAX\t\t\t0x2ff\n#define KEY_CNT\t\t\t(KEY_MAX+1)\n\n/*\n * Relative axes\n */\n\n#define REL_X\t\t\t0x00\n#define REL_Y\t\t\t0x01\n#define REL_Z\t\t\t0x02\n#define REL_RX\t\t\t0x03\n#define REL_RY\t\t\t0x04\n#define REL_RZ\t\t\t0x05\n#define REL_HWHEEL\t\t0x06\n#define REL_DIAL\t\t0x07\n#define REL_WHEEL\t\t0x08\n#define REL_MISC\t\t0x09\n#define REL_MAX\t\t\t0x0f\n#define REL_CNT\t\t\t(REL_MAX+1)\n\n/*\n * Absolute axes\n */\n\n#define ABS_X\t\t\t0x00\n#define ABS_Y\t\t\t0x01\n#define ABS_Z\t\t\t0x02\n#define ABS_RX\t\t\t0x03\n#define ABS_RY\t\t\t0x04\n#define ABS_RZ\t\t\t0x05\n#define ABS_THROTTLE\t\t0x06\n#define ABS_RUDDER\t\t0x07\n#define ABS_WHEEL\t\t0x08\n#define ABS_GAS\t\t\t0x09\n#define ABS_BRAKE\t\t0x0a\n#define ABS_HAT0X\t\t0x10\n#define ABS_HAT0Y\t\t0x11\n#define ABS_HAT1X\t\t0x12\n#define ABS_HAT1Y\t\t0x13\n#define ABS_HAT2X\t\t0x14\n#define ABS_HAT2Y\t\t0x15\n#define ABS_HAT3X\t\t0x16\n#define ABS_HAT3Y\t\t0x17\n#define ABS_PRESSURE\t\t0x18\n#define ABS_DISTANCE\t\t0x19\n#define ABS_TILT_X\t\t0x1a\n#define ABS_TILT_Y\t\t0x1b\n#define ABS_TOOL_WIDTH\t\t0x1c\n\n#define ABS_VOLUME\t\t0x20\n\n#define ABS_MISC\t\t0x28\n\n#define ABS_MT_SLOT\t\t0x2f\t/* MT slot being modified */\n#define ABS_MT_TOUCH_MAJOR\t0x30\t/* Major axis of touching ellipse */\n#define ABS_MT_TOUCH_MINOR\t0x31\t/* Minor axis (omit if circular) */\n#define ABS_MT_WIDTH_MAJOR\t0x32\t/* Major axis of approaching ellipse */\n#define ABS_MT_WIDTH_MINOR\t0x33\t/* Minor axis (omit if circular) */\n#define ABS_MT_ORIENTATION\t0x34\t/* Ellipse orientation */\n#define ABS_MT_POSITION_X\t0x35\t/* Center X touch position */\n#define ABS_MT_POSITION_Y\t0x36\t/* Center Y touch position */\n#define ABS_MT_TOOL_TYPE\t0x37\t/* Type of touching device */\n#define ABS_MT_BLOB_ID\t\t0x38\t/* Group a set of packets as a blob */\n#define ABS_MT_TRACKING_ID\t0x39\t/* Unique ID of initiated contact */\n#define ABS_MT_PRESSURE\t\t0x3a\t/* Pressure on contact area */\n#define ABS_MT_DISTANCE\t\t0x3b\t/* Contact hover distance */\n#define ABS_MT_TOOL_X\t\t0x3c\t/* Center X tool position */\n#define ABS_MT_TOOL_Y\t\t0x3d\t/* Center Y tool position */\n\n\n#define ABS_MAX\t\t\t0x3f\n#define ABS_CNT\t\t\t(ABS_MAX+1)\n\n/*\n * Switch events\n */\n\n#define SW_LID\t\t\t0x00 /* set = lid shut */\n#define SW_TABLET_MODE\t\t0x01 /* set = tablet mode */\n#define SW_HEADPHONE_INSERT\t0x02 /* set = inserted */\n#define SW_RFKILL_ALL\t\t0x03 /* rfkill master switch, type \"any\"\n\t\t\t\t\t set = radio enabled */\n#define SW_RADIO\t\tSW_RFKILL_ALL\t/* deprecated */\n#define SW_MICROPHONE_INSERT\t0x04 /* set = inserted */\n#define SW_DOCK\t\t\t0x05 /* set = plugged into dock */\n#define SW_LINEOUT_INSERT\t0x06 /* set = inserted */\n#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */\n#define SW_VIDEOOUT_INSERT\t0x08 /* set = inserted */\n#define SW_CAMERA_LENS_COVER\t0x09 /* set = lens covered */\n#define SW_KEYPAD_SLIDE\t\t0x0a /* set = keypad slide out */\n#define SW_FRONT_PROXIMITY\t0x0b /* set = front proximity sensor active */\n#define SW_ROTATE_LOCK\t\t0x0c /* set = rotate locked/disabled */\n#define SW_LINEIN_INSERT\t0x0d /* set = inserted */\n#define SW_MUTE_DEVICE\t\t0x0e /* set = device disabled */\n#define SW_MAX\t\t\t0x0f\n#define SW_CNT\t\t\t(SW_MAX+1)\n\n/*\n * Misc events\n */\n\n#define MSC_SERIAL\t\t0x00\n#define MSC_PULSELED\t\t0x01\n#define MSC_GESTURE\t\t0x02\n#define MSC_RAW\t\t\t0x03\n#define MSC_SCAN\t\t0x04\n#define MSC_TIMESTAMP\t\t0x05\n#define MSC_MAX\t\t\t0x07\n#define MSC_CNT\t\t\t(MSC_MAX+1)\n\n/*\n * LEDs\n */\n\n#define LED_NUML\t\t0x00\n#define LED_CAPSL\t\t0x01\n#define LED_SCROLLL\t\t0x02\n#define LED_COMPOSE\t\t0x03\n#define LED_KANA\t\t0x04\n#define LED_SLEEP\t\t0x05\n#define LED_SUSPEND\t\t0x06\n#define LED_MUTE\t\t0x07\n#define LED_MISC\t\t0x08\n#define LED_MAIL\t\t0x09\n#define LED_CHARGING\t\t0x0a\n#define LED_MAX\t\t\t0x0f\n#define LED_CNT\t\t\t(LED_MAX+1)\n\n/*\n * Autorepeat values\n */\n\n#define REP_DELAY\t\t0x00\n#define REP_PERIOD\t\t0x01\n#define REP_MAX\t\t\t0x01\n#define REP_CNT\t\t\t(REP_MAX+1)\n\n/*\n * Sounds\n */\n\n#define SND_CLICK\t\t0x00\n#define SND_BELL\t\t0x01\n#define SND_TONE\t\t0x02\n#define SND_MAX\t\t\t0x07\n#define SND_CNT\t\t\t(SND_MAX+1)\n\n#define MATRIX_KEY(row, col, code)\t\\\n\t((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))\n\n#endif /* _DT_BINDINGS_INPUT_INPUT_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/interrupt-controller/irq.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most IRQ bindings.\n *\n * Most IRQ bindings include a flags cell as part of the IRQ specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n\n#define IRQ_TYPE_NONE\t\t0\n#define IRQ_TYPE_EDGE_RISING\t1\n#define IRQ_TYPE_EDGE_FALLING\t2\n#define IRQ_TYPE_EDGE_BOTH\t(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)\n#define IRQ_TYPE_LEVEL_HIGH\t4\n#define IRQ_TYPE_LEVEL_LOW\t8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/net/mscc-phy-vsc8531.h", "content": "/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */\n/*\n * Device Tree constants for Microsemi VSC8531 PHY\n *\n * Author: Nagaraju Lakkaraju\n *\n * Copyright (c) 2017 Microsemi Corporation\n */\n\n#ifndef _DT_BINDINGS_MSCC_VSC8531_H\n#define _DT_BINDINGS_MSCC_VSC8531_H\n\n/* PHY LED Modes */\n#define VSC8531_LINK_ACTIVITY\t\t\t0\n#define VSC8531_LINK_1000_ACTIVITY\t\t1\n#define VSC8531_LINK_100_ACTIVITY\t\t2\n#define VSC8531_LINK_10_ACTIVITY\t\t3\n#define VSC8531_LINK_100_1000_ACTIVITY\t\t4\n#define VSC8531_LINK_10_1000_ACTIVITY\t\t5\n#define VSC8531_LINK_10_100_ACTIVITY\t\t6\n#define VSC8584_LINK_100FX_1000X_ACTIVITY\t7\n#define VSC8531_DUPLEX_COLLISION\t\t8\n#define VSC8531_COLLISION\t\t\t9\n#define VSC8531_ACTIVITY\t\t\t10\n#define VSC8584_100FX_1000X_ACTIVITY\t\t11\n#define VSC8531_AUTONEG_FAULT\t\t\t12\n#define VSC8531_SERIAL_MODE\t\t\t13\n#define VSC8531_FORCE_LED_OFF\t\t\t14\n#define VSC8531_FORCE_LED_ON\t\t\t15\n\n#define VSC8531_RGMII_CLK_DELAY_0_2_NS\t0\n#define VSC8531_RGMII_CLK_DELAY_0_8_NS\t1\n#define VSC8531_RGMII_CLK_DELAY_1_1_NS\t2\n#define VSC8531_RGMII_CLK_DELAY_1_7_NS\t3\n#define VSC8531_RGMII_CLK_DELAY_2_0_NS\t4\n#define VSC8531_RGMII_CLK_DELAY_2_3_NS\t5\n#define VSC8531_RGMII_CLK_DELAY_2_6_NS\t6\n#define VSC8531_RGMII_CLK_DELAY_3_4_NS\t7\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/net/ti-dp83867.h", "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Device Tree constants for the Texas Instruments DP83867 PHY\n *\n * Author: Dan Murphy \n *\n * Copyright: (C) 2015 Texas Instruments, Inc.\n */\n\n#ifndef _DT_BINDINGS_TI_DP83867_H\n#define _DT_BINDINGS_TI_DP83867_H\n\n/* PHY CTRL bits */\n#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB\t0x00\n#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB\t0x01\n#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB\t0x02\n#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB\t0x03\n\n/* RGMIIDCTL internal delay for rx and tx */\n#define\tDP83867_RGMIIDCTL_250_PS\t0x0\n#define\tDP83867_RGMIIDCTL_500_PS\t0x1\n#define\tDP83867_RGMIIDCTL_750_PS\t0x2\n#define\tDP83867_RGMIIDCTL_1_NS\t\t0x3\n#define\tDP83867_RGMIIDCTL_1_25_NS\t0x4\n#define\tDP83867_RGMIIDCTL_1_50_NS\t0x5\n#define\tDP83867_RGMIIDCTL_1_75_NS\t0x6\n#define\tDP83867_RGMIIDCTL_2_00_NS\t0x7\n#define\tDP83867_RGMIIDCTL_2_25_NS\t0x8\n#define\tDP83867_RGMIIDCTL_2_50_NS\t0x9\n#define\tDP83867_RGMIIDCTL_2_75_NS\t0xa\n#define\tDP83867_RGMIIDCTL_3_00_NS\t0xb\n#define\tDP83867_RGMIIDCTL_3_25_NS\t0xc\n#define\tDP83867_RGMIIDCTL_3_50_NS\t0xd\n#define\tDP83867_RGMIIDCTL_3_75_NS\t0xe\n#define\tDP83867_RGMIIDCTL_4_00_NS\t0xf\n\n/* IO_MUX_CFG - Clock output selection */\n#define DP83867_CLK_O_SEL_CHN_A_RCLK\t\t0x0\n#define DP83867_CLK_O_SEL_CHN_B_RCLK\t\t0x1\n#define DP83867_CLK_O_SEL_CHN_C_RCLK\t\t0x2\n#define DP83867_CLK_O_SEL_CHN_D_RCLK\t\t0x3\n#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5\t0x4\n#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5\t0x5\n#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5\t0x6\n#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5\t0x7\n#define DP83867_CLK_O_SEL_CHN_A_TCLK\t\t0x8\n#define DP83867_CLK_O_SEL_CHN_B_TCLK\t\t0x9\n#define DP83867_CLK_O_SEL_CHN_C_TCLK\t\t0xA\n#define DP83867_CLK_O_SEL_CHN_D_TCLK\t\t0xB\n#define DP83867_CLK_O_SEL_REF_CLK\t\t0xC\n/* Special flag to indicate clock should be off */\n#define DP83867_CLK_O_SEL_OFF\t\t\t0xFFFFFFFF\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/phy/phy.h", "content": "/*\n *\n * This header provides constants for the phy framework\n *\n * Copyright (C) 2014 STMicroelectronics\n * Author: Gabriel Fernandez \n * License terms: GNU General Public License (GPL), version 2\n */\n\n#ifndef _DT_BINDINGS_PHY\n#define _DT_BINDINGS_PHY\n\n#define PHY_NONE\t\t0\n#define PHY_TYPE_SATA\t\t1\n#define PHY_TYPE_PCIE\t\t2\n#define PHY_TYPE_USB2\t\t3\n#define PHY_TYPE_USB3\t\t4\n#define PHY_TYPE_UFS\t\t5\n#define PHY_TYPE_DP\t\t6\n#define PHY_TYPE_XPCS\t\t7\n#define PHY_TYPE_SGMII\t\t8\n#define PHY_TYPE_QSGMII\t\t9\n\n#endif /* _DT_BINDINGS_PHY */\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * MIO pin configuration defines for Xilinx ZynqMP\n *\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H\n#define _DT_BINDINGS_PINCTRL_ZYNQMP_H\n\n/* Bit value for different voltage levels */\n#define IO_STANDARD_LVCMOS33\t0\n#define IO_STANDARD_LVCMOS18\t1\n\n/* Bit values for Slew Rates */\n#define SLEW_RATE_FAST\t\t0\n#define SLEW_RATE_SLOW\t\t1\n\n/* Bit values for Pin drive strength */\n#define DRIVE_STRENGTH_2MA\t2\n#define DRIVE_STRENGTH_4MA\t4\n#define DRIVE_STRENGTH_8MA\t8\n#define DRIVE_STRENGTH_12MA\t12\n\n#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/power/xlnx-versal-net-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2022, Xilinx, Inc.\n * Copyright (C) 2022, Advanced Micro Devices, Inc.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_NET_POWER_H\n#define _DT_BINDINGS_VERSAL_NET_POWER_H\n\n#include \n\n#define PM_DEV_USB_1\t\t\t\t(0x182240D7U)\n#define PM_DEV_FPD_SWDT_0\t\t\t(0x182240DBU)\n#define PM_DEV_FPD_SWDT_1\t\t\t(0x182240DCU)\n#define PM_DEV_FPD_SWDT_2\t\t\t(0x182240DDU)\n#define PM_DEV_FPD_SWDT_3\t\t\t(0x182240DEU)\n#define PM_DEV_TCM_A_0A\t\t\t\t(0x183180CBU)\n#define PM_DEV_TCM_A_0B\t\t\t\t(0x183180CCU)\n#define PM_DEV_TCM_A_0C\t\t\t\t(0x183180CDU)\n#define PM_DEV_RPU_A_0\t\t\t\t(0x181100BFU)\n#define PM_DEV_LPD_SWDT_0\t\t\t(0x182240D9U)\n#define PM_DEV_LPD_SWDT_1\t\t\t(0x182240DAU)\n\n/* Remove Versal specific node IDs */\n#undef PM_DEV_RPU0_0\n#undef PM_DEV_RPU0_1\n#undef PM_DEV_OCM_0\n#undef PM_DEV_OCM_1\n#undef PM_DEV_OCM_2\n#undef PM_DEV_OCM_3\n#undef PM_DEV_TCM_0_A\n#undef PM_DEV_TCM_1_A\n#undef PM_DEV_TCM_0_B\n#undef PM_DEV_TCM_1_B\n#undef PM_DEV_SWDT_FPD\n#undef PM_DEV_AI\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/power/xlnx-versal-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_POWER_H\n#define _DT_BINDINGS_VERSAL_POWER_H\n\n#define PM_DEV_USB_0\t\t\t\t(0x18224018U)\n#define PM_DEV_GEM_0\t\t\t\t(0x18224019U)\n#define PM_DEV_GEM_1\t\t\t\t(0x1822401aU)\n#define PM_DEV_SPI_0\t\t\t\t(0x1822401bU)\n#define PM_DEV_SPI_1\t\t\t\t(0x1822401cU)\n#define PM_DEV_I2C_0\t\t\t\t(0x1822401dU)\n#define PM_DEV_I2C_1\t\t\t\t(0x1822401eU)\n#define PM_DEV_I2C_PMC (0x1822402dU)\n#define PM_DEV_CAN_FD_0\t\t\t\t(0x1822401fU)\n#define PM_DEV_CAN_FD_1\t\t\t\t(0x18224020U)\n#define PM_DEV_UART_0\t\t\t\t(0x18224021U)\n#define PM_DEV_UART_1\t\t\t\t(0x18224022U)\n#define PM_DEV_GPIO\t\t\t\t(0x18224023U)\n#define PM_DEV_TTC_0\t\t\t\t(0x18224024U)\n#define PM_DEV_TTC_1\t\t\t\t(0x18224025U)\n#define PM_DEV_TTC_2\t\t\t\t(0x18224026U)\n#define PM_DEV_TTC_3\t\t\t\t(0x18224027U)\n#define PM_DEV_SWDT_FPD\t\t\t\t(0x18224029U)\n#define PM_DEV_OSPI\t\t\t\t(0x1822402aU)\n#define PM_DEV_QSPI\t\t\t\t(0x1822402bU)\n#define PM_DEV_GPIO_PMC\t\t\t\t(0x1822402cU)\n#define PM_DEV_SDIO_0\t\t\t\t(0x1822402eU)\n#define PM_DEV_SDIO_1\t\t\t\t(0x1822402fU)\n#define PM_DEV_RTC\t\t\t\t(0x18224034U)\n#define PM_DEV_ADMA_0\t\t\t\t(0x18224035U)\n#define PM_DEV_ADMA_1\t\t\t\t(0x18224036U)\n#define PM_DEV_ADMA_2\t\t\t\t(0x18224037U)\n#define PM_DEV_ADMA_3\t\t\t\t(0x18224038U)\n#define PM_DEV_ADMA_4\t\t\t\t(0x18224039U)\n#define PM_DEV_ADMA_5\t\t\t\t(0x1822403aU)\n#define PM_DEV_ADMA_6\t\t\t\t(0x1822403bU)\n#define PM_DEV_ADMA_7\t\t\t\t(0x1822403cU)\n#define PM_DEV_AI\t\t\t\t(0x18224072U)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/power/xlnx-versal-regnode.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2022-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_REGNODE_H\n#define _DT_BINDINGS_VERSAL_REGNODE_H\n\n#define PM_REGNODE_SYSMON_ROOT_0\t\t\t(0x18224055U)\n#define PM_REGNODE_SYSMON_ROOT_1\t\t\t(0x18225055U)\n#define PM_REGNODE_SYSMON_ROOT_2\t\t\t(0x18226055U)\n#define PM_REGNODE_SYSMON_ROOT_3\t\t\t(0x18227055U)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/power/xlnx-zynqmp-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_POWER_H\n#define _DT_BINDINGS_ZYNQMP_POWER_H\n\n#define\t\tPD_USB_0\t22\n#define\t\tPD_USB_1\t23\n#define\t\tPD_TTC_0\t24\n#define\t\tPD_TTC_1\t25\n#define\t\tPD_TTC_2\t26\n#define\t\tPD_TTC_3\t27\n#define\t\tPD_SATA\t\t28\n#define\t\tPD_ETH_0\t29\n#define\t\tPD_ETH_1\t30\n#define\t\tPD_ETH_2\t31\n#define\t\tPD_ETH_3\t32\n#define\t\tPD_UART_0\t33\n#define\t\tPD_UART_1\t34\n#define\t\tPD_SPI_0\t35\n#define\t\tPD_SPI_1\t36\n#define\t\tPD_I2C_0\t37\n#define\t\tPD_I2C_1\t38\n#define\t\tPD_SD_0\t\t39\n#define\t\tPD_SD_1\t\t40\n#define\t\tPD_DP\t\t41\n#define\t\tPD_GDMA\t\t42\n#define\t\tPD_ADMA\t\t43\n#define\t\tPD_NAND\t\t44\n#define\t\tPD_QSPI\t\t45\n#define\t\tPD_GPIO\t\t46\n#define\t\tPD_CAN_0\t47\n#define\t\tPD_CAN_1\t48\n#define\t\tPD_GPU\t\t58\n#define\t\tPD_PCIE\t\t59\n#define\t\tPD_PL\t\t69\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/reset/xlnx-versal-net-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H\n#define _DT_BINDINGS_VERSAL_NET_RESETS_H\n\n#include \"xlnx-versal-resets.h\"\n\n#define VERSAL_RST_USB_1\t\t\t(0xC1040C6U)\n\n/* Remove Versal specific reset IDs */\n#undef VERSAL_RST_ACPU_0_POR\n#undef VERSAL_RST_ACPU_1_POR\n#undef VERSAL_RST_OCM2_POR\n#undef VERSAL_RST_APU\n#undef VERSAL_RST_ACPU_0\n#undef VERSAL_RST_ACPU_1\n#undef VERSAL_RST_ACPU_L2\n#undef VERSAL_RST_RPU_ISLAND\n#undef VERSAL_RST_RPU_AMBA\n#undef VERSAL_RST_R5_0\n#undef VERSAL_RST_R5_1\n#undef VERSAL_RST_OCM2_RST\n#undef VERSAL_RST_I2C_PMC\n#undef VERSAL_RST_I2C_0\n#undef VERSAL_RST_I2C_1\n#undef VERSAL_RST_SWDT_FPD\n#undef VERSAL_RST_SWDT_LPD\n#undef VERSAL_RST_USB\n#undef VERSAL_RST_DPC\n#undef VERSAL_RST_DBG_TRACE\n#undef VERSAL_RST_DBG_TSTMP\n#undef VERSAL_RST_RPU0_DBG\n#undef VERSAL_RST_RPU1_DBG\n#undef VERSAL_RST_HSDP\n#undef VERSAL_RST_CPMDBG\n#undef VERSAL_RST_PCIE_CFG\n#undef VERSAL_RST_PCIE_CORE0\n#undef VERSAL_RST_PCIE_CORE1\n#undef VERSAL_RST_PCIE_DMA\n#undef VERSAL_RST_L2_0\n#undef VERSAL_RST_L2_1\n#undef VERSAL_RST_ADDR_REMAP\n#undef VERSAL_RST_CPI0\n#undef VERSAL_RST_CPI1\n#undef VERSAL_RST_XRAM\n#undef VERSAL_RST_AIE_ARRAY\n#undef VERSAL_RST_AIE_SHIM\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/reset/xlnx-versal-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_RESETS_H\n#define _DT_BINDINGS_VERSAL_RESETS_H\n\n#define VERSAL_RST_PMC_POR\t\t\t(0xc30c001U)\n#define VERSAL_RST_PMC\t\t\t\t(0xc410002U)\n#define VERSAL_RST_PS_POR\t\t\t(0xc30c003U)\n#define VERSAL_RST_PL_POR\t\t\t(0xc30c004U)\n#define VERSAL_RST_NOC_POR\t\t\t(0xc30c005U)\n#define VERSAL_RST_FPD_POR\t\t\t(0xc30c006U)\n#define VERSAL_RST_ACPU_0_POR\t\t\t(0xc30c007U)\n#define VERSAL_RST_ACPU_1_POR\t\t\t(0xc30c008U)\n#define VERSAL_RST_OCM2_POR\t\t\t(0xc30c009U)\n#define VERSAL_RST_PS_SRST\t\t\t(0xc41000aU)\n#define VERSAL_RST_PL_SRST\t\t\t(0xc41000bU)\n#define VERSAL_RST_NOC\t\t\t\t(0xc41000cU)\n#define VERSAL_RST_NPI\t\t\t\t(0xc41000dU)\n#define VERSAL_RST_SYS_RST_1\t\t\t(0xc41000eU)\n#define VERSAL_RST_SYS_RST_2\t\t\t(0xc41000fU)\n#define VERSAL_RST_SYS_RST_3\t\t\t(0xc410010U)\n#define VERSAL_RST_FPD\t\t\t\t(0xc410011U)\n#define VERSAL_RST_PL0\t\t\t\t(0xc410012U)\n#define VERSAL_RST_PL1\t\t\t\t(0xc410013U)\n#define VERSAL_RST_PL2\t\t\t\t(0xc410014U)\n#define VERSAL_RST_PL3\t\t\t\t(0xc410015U)\n#define VERSAL_RST_APU\t\t\t\t(0xc410016U)\n#define VERSAL_RST_ACPU_0\t\t\t(0xc410017U)\n#define VERSAL_RST_ACPU_1\t\t\t(0xc410018U)\n#define VERSAL_RST_ACPU_L2\t\t\t(0xc410019U)\n#define VERSAL_RST_ACPU_GIC\t\t\t(0xc41001aU)\n#define VERSAL_RST_RPU_ISLAND\t\t\t(0xc41001bU)\n#define VERSAL_RST_RPU_AMBA\t\t\t(0xc41001cU)\n#define VERSAL_RST_R5_0\t\t\t\t(0xc41001dU)\n#define VERSAL_RST_R5_1\t\t\t\t(0xc41001eU)\n#define VERSAL_RST_SYSMON_PMC_SEQ_RST\t\t(0xc41001fU)\n#define VERSAL_RST_SYSMON_PMC_CFG_RST\t\t(0xc410020U)\n#define VERSAL_RST_SYSMON_FPD_CFG_RST\t\t(0xc410021U)\n#define VERSAL_RST_SYSMON_FPD_SEQ_RST\t\t(0xc410022U)\n#define VERSAL_RST_SYSMON_LPD\t\t\t(0xc410023U)\n#define VERSAL_RST_PDMA_RST1\t\t\t(0xc410024U)\n#define VERSAL_RST_PDMA_RST0\t\t\t(0xc410025U)\n#define VERSAL_RST_ADMA\t\t\t\t(0xc410026U)\n#define VERSAL_RST_TIMESTAMP\t\t\t(0xc410027U)\n#define VERSAL_RST_OCM\t\t\t\t(0xc410028U)\n#define VERSAL_RST_OCM2_RST\t\t\t(0xc410029U)\n#define VERSAL_RST_IPI\t\t\t\t(0xc41002aU)\n#define VERSAL_RST_SBI\t\t\t\t(0xc41002bU)\n#define VERSAL_RST_LPD\t\t\t\t(0xc41002cU)\n#define VERSAL_RST_QSPI\t\t\t\t(0xc10402dU)\n#define VERSAL_RST_OSPI\t\t\t\t(0xc10402eU)\n#define VERSAL_RST_SDIO_0\t\t\t(0xc10402fU)\n#define VERSAL_RST_SDIO_1\t\t\t(0xc104030U)\n#define VERSAL_RST_I2C_PMC\t\t\t(0xc104031U)\n#define VERSAL_RST_GPIO_PMC\t\t\t(0xc104032U)\n#define VERSAL_RST_GEM_0\t\t\t(0xc104033U)\n#define VERSAL_RST_GEM_1\t\t\t(0xc104034U)\n#define VERSAL_RST_SPARE\t\t\t(0xc104035U)\n#define VERSAL_RST_USB_0\t\t\t(0xc104036U)\n#define VERSAL_RST_UART_0\t\t\t(0xc104037U)\n#define VERSAL_RST_UART_1\t\t\t(0xc104038U)\n#define VERSAL_RST_SPI_0\t\t\t(0xc104039U)\n#define VERSAL_RST_SPI_1\t\t\t(0xc10403aU)\n#define VERSAL_RST_CAN_FD_0\t\t\t(0xc10403bU)\n#define VERSAL_RST_CAN_FD_1\t\t\t(0xc10403cU)\n#define VERSAL_RST_I2C_0\t\t\t(0xc10403dU)\n#define VERSAL_RST_I2C_1\t\t\t(0xc10403eU)\n#define VERSAL_RST_GPIO_LPD\t\t\t(0xc10403fU)\n#define VERSAL_RST_TTC_0\t\t\t(0xc104040U)\n#define VERSAL_RST_TTC_1\t\t\t(0xc104041U)\n#define VERSAL_RST_TTC_2\t\t\t(0xc104042U)\n#define VERSAL_RST_TTC_3\t\t\t(0xc104043U)\n#define VERSAL_RST_SWDT_FPD\t\t\t(0xc104044U)\n#define VERSAL_RST_SWDT_LPD\t\t\t(0xc104045U)\n#define VERSAL_RST_USB\t\t\t\t(0xc104046U)\n#define VERSAL_RST_DPC\t\t\t\t(0xc208047U)\n#define VERSAL_RST_PMCDBG\t\t\t(0xc208048U)\n#define VERSAL_RST_DBG_TRACE\t\t\t(0xc208049U)\n#define VERSAL_RST_DBG_FPD\t\t\t(0xc20804aU)\n#define VERSAL_RST_DBG_TSTMP\t\t\t(0xc20804bU)\n#define VERSAL_RST_RPU0_DBG\t\t\t(0xc20804cU)\n#define VERSAL_RST_RPU1_DBG\t\t\t(0xc20804dU)\n#define VERSAL_RST_HSDP\t\t\t\t(0xc20804eU)\n#define VERSAL_RST_DBG_LPD\t\t\t(0xc20804fU)\n#define VERSAL_RST_CPM_POR\t\t\t(0xc30c050U)\n#define VERSAL_RST_CPM\t\t\t\t(0xc410051U)\n#define VERSAL_RST_CPMDBG\t\t\t(0xc208052U)\n#define VERSAL_RST_PCIE_CFG\t\t\t(0xc410053U)\n#define VERSAL_RST_PCIE_CORE0\t\t\t(0xc410054U)\n#define VERSAL_RST_PCIE_CORE1\t\t\t(0xc410055U)\n#define VERSAL_RST_PCIE_DMA\t\t\t(0xc410056U)\n#define VERSAL_RST_CMN\t\t\t\t(0xc410057U)\n#define VERSAL_RST_L2_0\t\t\t\t(0xc410058U)\n#define VERSAL_RST_L2_1\t\t\t\t(0xc410059U)\n#define VERSAL_RST_ADDR_REMAP\t\t\t(0xc41005aU)\n#define VERSAL_RST_CPI0\t\t\t\t(0xc41005bU)\n#define VERSAL_RST_CPI1\t\t\t\t(0xc41005cU)\n#define VERSAL_RST_XRAM\t\t\t\t(0xc30c05dU)\n#define VERSAL_RST_AIE_ARRAY\t\t\t(0xc10405eU)\n#define VERSAL_RST_AIE_SHIM\t\t\t(0xc10405fU)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H\n#define _DT_BINDINGS_ZYNQMP_RESETS_H\n\n#define\t\tZYNQMP_RESET_PCIE_CFG\t\t0\n#define\t\tZYNQMP_RESET_PCIE_BRIDGE\t1\n#define\t\tZYNQMP_RESET_PCIE_CTRL\t\t2\n#define\t\tZYNQMP_RESET_DP\t\t\t3\n#define\t\tZYNQMP_RESET_SWDT_CRF\t\t4\n#define\t\tZYNQMP_RESET_AFI_FM5\t\t5\n#define\t\tZYNQMP_RESET_AFI_FM4\t\t6\n#define\t\tZYNQMP_RESET_AFI_FM3\t\t7\n#define\t\tZYNQMP_RESET_AFI_FM2\t\t8\n#define\t\tZYNQMP_RESET_AFI_FM1\t\t9\n#define\t\tZYNQMP_RESET_AFI_FM0\t\t10\n#define\t\tZYNQMP_RESET_GDMA\t\t11\n#define\t\tZYNQMP_RESET_GPU_PP1\t\t12\n#define\t\tZYNQMP_RESET_GPU_PP0\t\t13\n#define\t\tZYNQMP_RESET_GPU\t\t14\n#define\t\tZYNQMP_RESET_GT\t\t\t15\n#define\t\tZYNQMP_RESET_SATA\t\t16\n#define\t\tZYNQMP_RESET_ACPU3_PWRON\t17\n#define\t\tZYNQMP_RESET_ACPU2_PWRON\t18\n#define\t\tZYNQMP_RESET_ACPU1_PWRON\t19\n#define\t\tZYNQMP_RESET_ACPU0_PWRON\t20\n#define\t\tZYNQMP_RESET_APU_L2\t\t21\n#define\t\tZYNQMP_RESET_ACPU3\t\t22\n#define\t\tZYNQMP_RESET_ACPU2\t\t23\n#define\t\tZYNQMP_RESET_ACPU1\t\t24\n#define\t\tZYNQMP_RESET_ACPU0\t\t25\n#define\t\tZYNQMP_RESET_DDR\t\t26\n#define\t\tZYNQMP_RESET_APM_FPD\t\t27\n#define\t\tZYNQMP_RESET_SOFT\t\t28\n#define\t\tZYNQMP_RESET_GEM0\t\t29\n#define\t\tZYNQMP_RESET_GEM1\t\t30\n#define\t\tZYNQMP_RESET_GEM2\t\t31\n#define\t\tZYNQMP_RESET_GEM3\t\t32\n#define\t\tZYNQMP_RESET_QSPI\t\t33\n#define\t\tZYNQMP_RESET_UART0\t\t34\n#define\t\tZYNQMP_RESET_UART1\t\t35\n#define\t\tZYNQMP_RESET_SPI0\t\t36\n#define\t\tZYNQMP_RESET_SPI1\t\t37\n#define\t\tZYNQMP_RESET_SDIO0\t\t38\n#define\t\tZYNQMP_RESET_SDIO1\t\t39\n#define\t\tZYNQMP_RESET_CAN0\t\t40\n#define\t\tZYNQMP_RESET_CAN1\t\t41\n#define\t\tZYNQMP_RESET_I2C0\t\t42\n#define\t\tZYNQMP_RESET_I2C1\t\t43\n#define\t\tZYNQMP_RESET_TTC0\t\t44\n#define\t\tZYNQMP_RESET_TTC1\t\t45\n#define\t\tZYNQMP_RESET_TTC2\t\t46\n#define\t\tZYNQMP_RESET_TTC3\t\t47\n#define\t\tZYNQMP_RESET_SWDT_CRL\t\t48\n#define\t\tZYNQMP_RESET_NAND\t\t49\n#define\t\tZYNQMP_RESET_ADMA\t\t50\n#define\t\tZYNQMP_RESET_GPIO\t\t51\n#define\t\tZYNQMP_RESET_IOU_CC\t\t52\n#define\t\tZYNQMP_RESET_TIMESTAMP\t\t53\n#define\t\tZYNQMP_RESET_RPU_R50\t\t54\n#define\t\tZYNQMP_RESET_RPU_R51\t\t55\n#define\t\tZYNQMP_RESET_RPU_AMBA\t\t56\n#define\t\tZYNQMP_RESET_OCM\t\t57\n#define\t\tZYNQMP_RESET_RPU_PGE\t\t58\n#define\t\tZYNQMP_RESET_USB0_CORERESET\t59\n#define\t\tZYNQMP_RESET_USB1_CORERESET\t60\n#define\t\tZYNQMP_RESET_USB0_HIBERRESET\t61\n#define\t\tZYNQMP_RESET_USB1_HIBERRESET\t62\n#define\t\tZYNQMP_RESET_USB0_APB\t\t63\n#define\t\tZYNQMP_RESET_USB1_APB\t\t64\n#define\t\tZYNQMP_RESET_IPI\t\t65\n#define\t\tZYNQMP_RESET_APM_LPD\t\t66\n#define\t\tZYNQMP_RESET_RTC\t\t67\n#define\t\tZYNQMP_RESET_SYSMON\t\t68\n#define\t\tZYNQMP_RESET_AFI_FM6\t\t69\n#define\t\tZYNQMP_RESET_LPD_SWDT\t\t70\n#define\t\tZYNQMP_RESET_FPD\t\t71\n#define\t\tZYNQMP_RESET_RPU_DBG1\t\t72\n#define\t\tZYNQMP_RESET_RPU_DBG0\t\t73\n#define\t\tZYNQMP_RESET_DBG_LPD\t\t74\n#define\t\tZYNQMP_RESET_DBG_FPD\t\t75\n#define\t\tZYNQMP_RESET_APLL\t\t76\n#define\t\tZYNQMP_RESET_DPLL\t\t77\n#define\t\tZYNQMP_RESET_VPLL\t\t78\n#define\t\tZYNQMP_RESET_IOPLL\t\t79\n#define\t\tZYNQMP_RESET_RPLL\t\t80\n#define\t\tZYNQMP_RESET_GPO3_PL_0\t\t81\n#define\t\tZYNQMP_RESET_GPO3_PL_1\t\t82\n#define\t\tZYNQMP_RESET_GPO3_PL_2\t\t83\n#define\t\tZYNQMP_RESET_GPO3_PL_3\t\t84\n#define\t\tZYNQMP_RESET_GPO3_PL_4\t\t85\n#define\t\tZYNQMP_RESET_GPO3_PL_5\t\t86\n#define\t\tZYNQMP_RESET_GPO3_PL_6\t\t87\n#define\t\tZYNQMP_RESET_GPO3_PL_7\t\t88\n#define\t\tZYNQMP_RESET_GPO3_PL_8\t\t89\n#define\t\tZYNQMP_RESET_GPO3_PL_9\t\t90\n#define\t\tZYNQMP_RESET_GPO3_PL_10\t\t91\n#define\t\tZYNQMP_RESET_GPO3_PL_11\t\t92\n#define\t\tZYNQMP_RESET_GPO3_PL_12\t\t93\n#define\t\tZYNQMP_RESET_GPO3_PL_13\t\t94\n#define\t\tZYNQMP_RESET_GPO3_PL_14\t\t95\n#define\t\tZYNQMP_RESET_GPO3_PL_15\t\t96\n#define\t\tZYNQMP_RESET_GPO3_PL_16\t\t97\n#define\t\tZYNQMP_RESET_GPO3_PL_17\t\t98\n#define\t\tZYNQMP_RESET_GPO3_PL_18\t\t99\n#define\t\tZYNQMP_RESET_GPO3_PL_19\t\t100\n#define\t\tZYNQMP_RESET_GPO3_PL_20\t\t101\n#define\t\tZYNQMP_RESET_GPO3_PL_21\t\t102\n#define\t\tZYNQMP_RESET_GPO3_PL_22\t\t103\n#define\t\tZYNQMP_RESET_GPO3_PL_23\t\t104\n#define\t\tZYNQMP_RESET_GPO3_PL_24\t\t105\n#define\t\tZYNQMP_RESET_GPO3_PL_25\t\t106\n#define\t\tZYNQMP_RESET_GPO3_PL_26\t\t107\n#define\t\tZYNQMP_RESET_GPO3_PL_27\t\t108\n#define\t\tZYNQMP_RESET_GPO3_PL_28\t\t109\n#define\t\tZYNQMP_RESET_GPO3_PL_29\t\t110\n#define\t\tZYNQMP_RESET_GPO3_PL_30\t\t111\n#define\t\tZYNQMP_RESET_GPO3_PL_31\t\t112\n#define\t\tZYNQMP_RESET_RPU_LS\t\t113\n#define\t\tZYNQMP_RESET_PS_ONLY\t\t114\n#define\t\tZYNQMP_RESET_PL\t\t\t115\n#define\t\tZYNQMP_RESET_PS_PL0\t\t116\n#define\t\tZYNQMP_RESET_PS_PL1\t\t117\n#define\t\tZYNQMP_RESET_PS_PL2\t\t118\n#define\t\tZYNQMP_RESET_PS_PL3\t\t119\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/versal/versal-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-versal-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-power.h\"\n#include \"include/dt-bindings/power/xlnx-versal-regnode.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-resets.h\"\n/ {\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tcan0_clk: can0_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN0_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tcan1_clk: can1_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN1_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t};\n\t\t\tversal_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,versal-pinctrl\";\n\t\t\t};\n\n\t\t\tversal_sec_cfg: versal-sec-cfg {\n\t\t\t\tcompatible = \"xlnx,versal-sec-cfg\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tbbram_zeroize: bbram-zeroize@4 {\n\t\t\t\t\treg = <0x04 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_key: bbram-key@10 {\n\t\t\t\t\treg = <0x10 0x20>;\n\t\t\t\t};\n\n\t\t\t\tbbram_usr: bbram-usr@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_lock: bbram-lock@48 {\n\t\t\t\t\treg = <0x48 0x4>;\n\t\t\t\t};\n\n\t\t\t\tuser_key0: user-key@110 {\n\t\t\t\t\treg = <0x110 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key1: user-key@130 {\n\t\t\t\t\treg = <0x130 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key2: user-key@150 {\n\t\t\t\t\treg = <0x150 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key3: user-key@170 {\n\t\t\t\t\treg = <0x170 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key4: user-key@190 {\n\t\t\t\t\treg = <0x190 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key5: user-key@1b0 {\n\t\t\t\t\treg = <0x1b0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key6: user-key@1d0 {\n\t\t\t\t\treg = <0x1d0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key7: user-key@1f0 {\n\t\t\t\t\treg = <0x1f0 0x20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk ACPU>;\n};\n\n&can0 {\n\tclocks = <&can0_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_0>;\n};\n\n&can1 {\n\tclocks = <&can1_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_1>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_0>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_1>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk PMC_LSBUS_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO_PMC>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk I2C0_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_0>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk I2C1_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_1>;\n};\n\n&i2c2 {\n\tclocks = <&versal_clk I2C_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_PMC>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_0>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_1>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_2>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_3>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_4>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_5>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_6>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_7>;\n};\n\n&qspi {\n\tclocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_QSPI>;\n};\n\n&ospi {\n\tclocks = <&versal_clk OSPI_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_OSPI>;\n\treset-names = \"qspi\";\n\tresets = <&versal_reset VERSAL_RST_OSPI>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware PM_DEV_RTC>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_0>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_1>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>,\n\t\t<&versal_clk SD_DLL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_0>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>,\n\t\t<&versal_clk SD_DLL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_1>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_0>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_1>;\n};\n\n&ttc0 {\n\tclocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_0>;\n};\n\n&ttc1 {\n\tclocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_1>;\n};\n\n&ttc2 {\n\tclocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_2>;\n};\n\n&ttc3 {\n\tclocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_3>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_USB_0>;\n\tresets = <&versal_reset VERSAL_RST_USB_0>;\n};\n\n&dwc3_0 {\n\tclocks = <&versal_clk USB0_BUS_REF>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SWDT_FPD>;\n};\n\n&sysmon0 {\n\txlnx,nodeid = ;\n};\n\n&sysmon1 {\n\txlnx,nodeid = ;\n};\n\n&sysmon2 {\n\txlnx,nodeid = ;\n};\n\n&sysmon3 {\n\txlnx,nodeid = ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/versal/versal-spp-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\talt_ref_clk: alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware-wip\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"alt_ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk 77>;\n};\n\n&can0 {\n\tclocks = <&versal_clk 96>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401f>;\n};\n\n&can1 {\n\tclocks = <&versal_clk 97>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224020>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x18224019>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x1822401a>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk 61>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk 98>;\n\tpower-domains = <&versal_firmware 0x1822401d>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk 99>;\n\tpower-domains = <&versal_firmware 0x1822401e>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224035>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224036>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224037>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224038>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224039>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403a>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403b>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403c>;\n};\n\n&qspi {\n\tclocks = <&versal_clk 57>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402b>;\n};\n\n&ospi {\n\tclocks = <&versal_clk 58>, <&versal_clk 82>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware 0x18224034>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk 92>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224021>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk 93>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224022>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk 59>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402e>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk 60>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402f>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk 94>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401b>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk 95>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401c>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk 91>, <&versal_clk 104>;\n\tpower-domains = <&versal_firmware 0x18224018>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk 82>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/versal/versal.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal\";\n\n\tcpus: cpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <1>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu-opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tfpga: fpga {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&versal_fpga>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tpsci: psci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 7 0x304>;\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t};\n\n\tversal_fpga: versal-fpga {\n\t\tcompatible = \"xlnx,versal-fpga\";\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t\tinterrupt-parent = <&gic>;\n\t\tu-boot,dm-pre-reloc;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\t\t\treg = <0 0xf9000000 0 0x80000>, /* GICD */\n\t\t\t <0 0xf9080000 0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\n\t\t\tgic_its: gic-its@f9020000 {\n\t\t\t\tcompatible = \"arm,gic-v3-its\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tmsi-controller;\n\t\t\t\tmsi-cells = <1>;\n\t\t\t\treg = <0 0xf9020000 0 0x20000>;\n\t\t\t};\n\t\t};\n\n\t\tapm: performance-monitor@f0920000 {\n\t\t\tcompatible = \"xlnx,flexnoc-pm-2.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg-names = \"funnel\", \"baselpd\", \"basefpd\";\n\t\t\treg = <0x0 0xf0920000 0x0 0x1000>,\n\t\t\t <0x0 0xf0980000 0x0 0x9000>,\n\t\t\t <0x0 0xf0b80000 0x0 0x9000>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff060000 0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff070000 0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcci: cci@fd000000 {\n\t\t\tcompatible = \"arm,cci-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd000000 0 0x10000>;\n\t\t\tranges = <0 0 0xfd000000 0xa0000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcci_pmu: pmu@10000 {\n\t\t\t\tcompatible = \"arm,cci-500-pmu,r0\";\n\t\t\t\treg = <0x10000 0x90000>;\n\t\t\t\tinterrupts = <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>;\n\t\t\t};\n\t\t};\n\n\t\tlpd_dma_chan0: dma@ffa80000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa80000 0 0x1000>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa90000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa90000 0 0x1000>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffaa0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaa0000 0 0x1000>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\n\t\tlpd_dma_chan3: dma@ffab0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffab0000 0 0x1000>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffac0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffac0000 0 0x1000>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffad0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffad0000 0 0x1000>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffae0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffae0000 0 0x1000>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffaf0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaf0000 0 0x1000>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tgem0: ethernet@ff0c0000 {\n compatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0c0000 0 0x1000>;\n\t\t\tinterrupts = <0 56 4>, <0 56 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t/* iommus = <&smmu 0x234>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0d0000 {\n compatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0d0000 0 0x1000>;\n\t\t\tinterrupts = <0 58 4>, <0 58 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t/* iommus = <&smmu 0x235>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tgpio0: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0b0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff020000 0 0x1000>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\tclock-frequency = <100000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff030000 0 0x1000>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tclock-frequency = <100000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c2: i2c@f1000000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1000000 0 0x1000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tclock-frequency = <100000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tmc0: memory-controller@f6150000\t{\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <0>;\n\t\t};\n\n\t\tmc1: memory-controller@f62c0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <1>;\n\t\t};\n\n\t\tmc2: memory-controller@f6430000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <2>;\n\t\t};\n\n\t\tmc3: memory-controller@f65a0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>;\n\t\t\treg-names = \"ddrmc_base\", \"ddrmc_noc_base\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t\txlnx,mc-id = <3>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tcalibration = <0x7FFF>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff000000 0 0x1000>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tserial1: serial@ff010000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff010000 0 0x1000>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd800000 0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 124 4>, <0 124 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,trigger-address = <0xC0000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff040000 0 0x1000>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff050000 0 0x1000>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsysmon0: sysmon@f1270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\treg = <0x0 0xf1270000 0x0 0x4000>;\n\t\t\tinterrupts = <0 144 4>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tsysmon1: sysmon@109270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x09270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tsysmon2: sysmon@111270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x11270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tsysmon3: sysmon@119270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x19270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tttc0: timer@ff0e0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff0f0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 40 4>, <0 41 4>, <0 42 4>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff100000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 46 4>, <0 47 4>, <0 48 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tusb0: usb@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff9d0000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_0: usb@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0 0xfe200000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"usb-wakeup\";\n\t\t\t\tinterrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\tcpm_pciea: pci@fca10000 {\n\t\t\tdevice_type = \"pci\";\n\t\t\t#address-cells = <3>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"xlnx,versal-cpm-host-1.00\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc_0 0>,\n\t\t\t\t\t<0 0 0 2 &pcie_intc_0 1>,\n\t\t\t\t\t<0 0 0 3 &pcie_intc_0 2>,\n\t\t\t\t\t<0 0 0 4 &pcie_intc_0 3>;\n\t\t\tinterrupt-map-mask = <0 0 0 7>;\n\t\t\tinterrupt-names = \"misc\";\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>,\n\t\t\t\t <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>;\n\t\t\tmsi-map = <0x0 &gic_its 0x0 0x10000>;\n\t\t\treg = <0x0 0xfca10000 0x0 0x1000>,\n\t\t\t <0x6 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"cpm_slcr\", \"cfg\";\n\t\t\tpcie_intc_0: interrupt-controller {\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\tinterrupt-controller ;\n\t\t\t};\n\t\t};\n\n\t\tcpm5_pcie: pcie@fcdd0000 {\n\t\t\tdevice_type = \"pci\";\n\t\t\t#address-cells = <3>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"xlnx,versal-cpm5-host\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc_1 0>,\n\t\t\t\t\t<0 0 0 2 &pcie_intc_1 1>,\n\t\t\t\t\t<0 0 0 3 &pcie_intc_1 2>,\n\t\t\t\t\t<0 0 0 4 &pcie_intc_1 3>;\n\t\t\tinterrupt-map-mask = <0 0 0 7>;\n\t\t\tinterrupt-names = \"misc\";\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,\n\t\t\t\t <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;\n\t\t\tmsi-map = <0x0 &gic_its 0x0 0x10000>;\n\t\t\treg = <0x00 0xfcdd0000 0x00 0x1000>,\n\t\t\t <0x06 0x00000000 0x00 0x1000000>,\n\t\t\t <0x00 0xfce20000 0x00 0x1000000>;\n\t\t\treg-names = \"cpm_slcr\", \"cfg\", \"cpm_csr\";\n\t\t\tpcie_intc_1: interrupt-controller {\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\tinterrupt-controller;\n\t\t\t};\n\t\t};\n\n\t\twatchdog: watchdog@fd4d0000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd4d0000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\t\txilsem_edac: edac@f2014050 {\n\t\t\tcompatible = \"xlnx,versal-xilsem-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf2014050 0x0 0xc4>;\n\t\t};\n\t};\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/versal-net/versal-net-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * Copyright (C) 2022, Xilinx, Inc.\n * Copyright (C) 2022, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/clock/xlnx-versal-net-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-net-power.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tref_clk: ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tcan0_clk: can0-clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_net_clk CAN0_REF_2X>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tcan1_clk: can1-clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_net_clk CAN1_REF_2X>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tversal_net_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-net-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tversal_net_power: zynqmp-power { /* untested */\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 57 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tversal_sec_cfg: versal-sec-cfg { /* untested */\n\t\t\t\tcompatible = \"xlnx,versal-sec-cfg\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tbbram_zeroize: bbram-zeroize@4 {\n\t\t\t\t\treg = <0x04 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_key: bbram-key@10 {\n\t\t\t\t\treg = <0x10 0x20>;\n\t\t\t\t};\n\n\t\t\t\tbbram_usr: bbram-usr@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_lock: bbram-lock@48 {\n\t\t\t\t\treg = <0x48 0x4>;\n\t\t\t\t};\n\n\t\t\t\tuser_key0: user-key@110 {\n\t\t\t\t\treg = <0x110 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key1: user-key@130 {\n\t\t\t\t\treg = <0x130 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key2: user-key@150 {\n\t\t\t\t\treg = <0x150 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key3: user-key@170 {\n\t\t\t\t\treg = <0x170 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key4: user-key@190 {\n\t\t\t\t\treg = <0x190 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key5: user-key@1b0 {\n\t\t\t\t\treg = <0x1b0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key6: user-key@1d0 {\n\t\t\t\t\treg = <0x1d0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key7: user-key@1f0 {\n\t\t\t\t\treg = <0x1f0 0x20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp-ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 57 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@eb3f0440 {\n\t\t\treg = <0 0xeb3f0440 0 0x20>,\n\t\t\t <0 0xeb3f0460 0 0x20>,\n\t\t\t <0 0xeb3f0280 0 0x20>,\n\t\t\t <0 0xeb3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu100 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu200 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu300 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu10000 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu10100 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu10200 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu10300 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu20000 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu20100 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu20200 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu20300 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu30000 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&cpu30100 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&cpu30200 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&cpu30300 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&can0 {\n\tclocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>;\n};\n\n&can1 {\n\tclocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>;\n};\n\n&gem0 {\n\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>,\n\t\t <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GEM_0>;\n};\n\n&gem1 {\n\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>,\n\t\t <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GEM_1>;\n};\n\n&gpio0 {\n\tclocks = <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GPIO>;\n};\n\n&gpio1 {\n\tclocks = <&versal_net_clk PMC_LSBUS_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>;\n};\n\n&i2c0 {\n\tclocks = <&versal_net_clk I3C0_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n};\n\n&i2c1 {\n\tclocks = <&versal_net_clk I3C1_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n};\n\n&i3c0 {\n\tclocks = <&versal_net_clk I3C0_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n};\n\n&i3c1 {\n\tclocks = <&versal_net_clk I3C1_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n};\n\n&adma0 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_0>;\n};\n\n&adma1 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_1>;\n};\n\n&adma2 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_2>;\n};\n\n&adma3 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_3>;\n};\n\n&adma4 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_4>;\n};\n\n&adma5 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_5>;\n};\n\n&adma6 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_6>;\n};\n\n&adma7 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_7>;\n};\n\n&qspi {\n\tclocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_QSPI>;\n};\n\n&ospi {\n\tclocks = <&versal_net_clk OSPI_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_OSPI>;\n\tresets = <&versal_net_reset VERSAL_RST_OSPI>;\n};\n\n&rtc {\n\tpower-domains = <&versal_net_firmware PM_DEV_RTC>;\n};\n\n&serial0 {\n\tclocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_UART_0>;\n};\n\n&serial1 {\n\tclocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_UART_1>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>,\n\t\t<&versal_net_clk SD_DLL_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_0>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>,\n\t\t<&versal_net_clk SD_DLL_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_1>;\n};\n\n&spi0 {\n\tclocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SPI_0>;\n};\n\n&spi1 {\n\tclocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SPI_1>;\n};\n\n&ttc0 {\n\tclocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_0>;\n};\n\n&ttc1 {\n\tclocks = <&versal_net_clk TTC1>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_1>;\n};\n\n&ttc2 {\n\tclocks = <&versal_net_clk TTC2>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_2>;\n};\n\n&ttc3 {\n\tclocks = <&versal_net_clk TTC3>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_3>;\n};\n\n&usb0 {\n\tclocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_USB_0>;\n\tresets = <&versal_net_reset VERSAL_RST_USB_0>;\n};\n\n&dwc3_0 {\n\tclocks = <&versal_net_clk USB0_BUS_REF>;\n};\n\n&usb1 {\n\tclocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_USB_1>;\n\tresets = <&versal_net_reset VERSAL_RST_USB_1>;\n};\n\n&dwc3_1 {\n\tclocks = <&versal_net_clk USB1_BUS_REF>;\n};\n\n&wwdt0 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>;\n};\n\n&wwdt1 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>;\n};\n\n&wwdt2 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>;\n};\n\n&wwdt3 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>;\n};\n\n&lpd_wwdt0 {\n\tclocks = <&versal_net_clk LPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_0>;\n};\n\n&lpd_wwdt1 {\n\tclocks = <&versal_net_clk LPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_1>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/versal-net/versal-net-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET fixed clock\n *\n * (C) Copyright 2022, Xilinx, Inc.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tclk60: clk60 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <60000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk150: clk150 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <150000000>;\n\t};\n\n\tclk160: clk160 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <160000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk450: clk450 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <450000000>;\n\t};\n\n\tclk1200: clk1200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <1200000000>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&adma0 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma1 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma2 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma3 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma4 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma5 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma6 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma7 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&can0 {\n\tclocks = <&clk160>, <&clk160>;\n};\n\n&can1 {\n\tclocks = <&clk160>, <&clk160>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;\n};\n\n\n&gpio0 {\n\tclocks = <&clk100>;\n};\n\n&gpio1 {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&i3c0 {\n\tclocks = <&clk100>;\n};\n\n&i3c1 {\n\tclocks = <&clk100>;\n};\n\n&ospi {\n\tclocks = <&clk200>;\n\tresets = <&versal_net_reset VERSAL_RST_OSPI>;\n};\n\n&qspi {\n\tclocks = <&clk300>, <&clk300>;\n};\n\n&rtc {\n\t/* Nothing */\n};\n\n&sdhci0 {\n\tclocks = <&clk200>, <&clk200>, <&clk1200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200>, <&clk200>, <&clk1200>;\n};\n\n&serial0 {\n\tclocks = <&clk100>, <&clk100>;\n\tclock = <1000000>;\n};\n\n&serial1 {\n\tclocks = <&clk100>, <&clk100>;\n\tclock = <100000000>;\n};\n\n&spi0 {\n\tclocks = <&clk200>, <&clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200>, <&clk200>;\n};\n\n&ttc0 {\n\tclocks = <&clk150>;\n};\n\n&usb0 {\n\tclocks = <&clk60>, <&clk60>;\n};\n\n&dwc3_0 {\n\t/* Nothing */\n};\n\n&usb1 {\n\tclocks = <&clk60>, <&clk60>;\n};\n\n&dwc3_1 {\n\t/* Nothing */\n};\n\n&wwdt0 {\n\tclocks = <&clk150>;\n};\n\n&wwdt1 {\n\tclocks = <&clk150>;\n};\n\n&wwdt2 {\n\tclocks = <&clk150>;\n};\n\n&wwdt3 {\n\tclocks = <&clk150>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/versal-net/versal-net-ipp-rev1.9.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/clock/xlnx-versal-net-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-net-power.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-net-ipp-1.9\", \"xlnx,versal-net-spp-5.0\", \"xlnx,versal-net-spp\", \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal NET SPP 5.0/IPP 1.9\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t};\n\t};\n\n\tmemory: memory@0 {\n\t\treg = <0 0 0 0x80000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tref_clk: ref_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x01>;\n\n\t\t\tversal_net_clk: clock-controller {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-net-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupts = <0 57 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t<&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tzynqmp-ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupts = <0 57 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@eb3f0440 {\n\t\t\treg = <0 0xeb3f0440 0 0x20>,\n\t\t\t <0 0xeb3f0460 0 0x20>,\n\t\t\t <0 0xeb3f0280 0 0x20>,\n\t\t\t <0 0xeb3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tadma0: dma-controller@ebd00000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd00000 0 0x1000>;\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_0>;\n\t\t};\n\n\t\tadma1: dma-controller@ebd10000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd10000 0 0x1000>;\n\t\t\tinterrupts = <0 73 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_1>;\n\t\t};\n\n\t\tadma2: dma-controller@ebd20000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd20000 0 0x1000>;\n\t\t\tinterrupts = <0 74 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_2>;\n\t\t};\n\n\t\tadma3: dma-controller@ebd30000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd30000 0 0x1000>;\n\t\t\tinterrupts = <0 75 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_3>;\n\t\t};\n\n\t\tadma4: dma-controller@ebd40000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd40000 0 0x1000>;\n\t\t\tinterrupts = <0 76 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_4>;\n\t\t};\n\n\t\tadma5: dma-controller@ebd50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd50000 0 0x1000>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_5>;\n\t\t};\n\n\t\tadma6: dma-controller@ebd60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd60000 0 0x1000>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_6>;\n\t\t};\n\n\t\tadma7: dma-controller@ebd70000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd70000 0 0x1000>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_7>;\n\t\t};\n\n\t\tcan0: can@f1980000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1980000 0 0x6000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>;\n\t\t};\n\n\t\tcan1: can@f1990000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1990000 0 0x6000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>;\n\t\t};\n\n\t\tgem0: ethernet@f19e0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19e0000 0 0x1000>;\n\t\t\tinterrupts = <0 39 4>, <0 39 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>,\n\t\t\t\t <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_0>;\n\t\t\tmdio0: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\t\t#phy-cells = <1>;\n\t\t\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t\tti,rx-internal-delay = <11>;\n\t\t\t\t\tti,tx-internal-delay = <10>;\n\t\t\t\t\tti,fifo-depth = <1>;\n\t\t\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgem1: ethernet@f19f0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19f0000 0 0x1000>;\n\t\t\tinterrupts = <0 41 4>, <0 41 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy2>;\n\t\t\tphy-mode = \"rmii\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>,\n\t\t\t\t <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_1>;\n\t\t\tmdio1: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\t\tcompatible = \"ethernet-phy-id0007.0762\"; /* Vitesse VSC8540 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t};\n\n\t\tgpio0: gpio@f19d0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\treg = <0 0xf19d0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO>;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk PMC_LSBUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>;\n\t\t};\n\n\t\ti2c0: i2c@f1940000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1940000 0 0x1000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C0_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@f1950000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1950000 0 0x1000>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C1_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n\t\t};\n\n\t\ti3c: i3c-master@f1948000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\treg = <0 0xf1948000 0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclocks = <&versal_net_clk I2C_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_PMC>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 182 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,trigger-address = <0xc0000000>;\n\t\t\tis-dual = <0>;\n\t\t\tis-stacked = <0>;\n\t\t\tclocks = <&versal_net_clk OSPI_REF>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_OSPI>;\n\t\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\t\t\tmt35xu02g: flash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tcdns,read-delay = <0>;\n\t\t\t\tcdns,tshsl-ns = <0>;\n\t\t\t\tcdns,tsd2d-ns = <0>;\n\t\t\t\tcdns,tchsh-ns = <1>;\n\t\t\t\tcdns,tslch-ns = <1>;\n\t\t\t\tspi-tx-bus-width = <8>;\n\t\t\t\tspi-rx-bus-width = <8>;\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\tbroken-flash-reset;\n\t\t\t\tno-wp;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"ospi-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"ospi-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 183 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tnum-cs = <2>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\t\t\tclocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_QSPI>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>, <1>;\n\t\t\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <10000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi0-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"qspi0-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupts = <0 200 4>, <0 201 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 184 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_1>;\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 186 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_0>;\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_UART_0>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tserial1: serial@f1930000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1930000 0 0x1000>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_UART_1>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tsmmu: smmu@ec000000 {\n\t\t\tcompatible = \"arm,smmu-v3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xec000000 0 0x40000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tinterrupt-names = \"combined\";\n\t\t\tinterrupts = <0 169 4>;\n\t\t};\n\n\t\tspi0: spi@f1960000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupts = <0 23 4>;\n\t\t\treg = <0 0xf1960000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_0>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@f1970000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0 0xf1970000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_1>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tttc0: timer@f1dc0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dc0000 0x0 0x1000>;\n\t\t\tclocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_TTC_0>;\n\t\t};\n\n\t\tusb0: usb@f1e00000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0 0xf1e00000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t/* clocks = <&clk60>, <&clk60>; */\n\t\t\tclocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_0>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_0>;\n\n\t\t\tdwc3_0: dwc3@f1b00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0 0xf1b00000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 29 4>, <0 33 4>, <0 98 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"peripheral\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@f1e10000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0x0 0xf1e10000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tclocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_1>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_1>;\n\n\t\t\tdwc3_1: dwc3@f1c00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0x0 0xf1c00000 0x0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 34 4>, <0 38 4>, <0 99 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\twwdt0: watchdog@ecc10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecc10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>;\n\t\t};\n\n\t\twwdt1: watchdog@ecd10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecd10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>;\n\t\t};\n\n\t\twwdt2: watchdog@ece10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xece10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>;\n\t\t};\n\n\t\twwdt3: watchdog@ecf10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecf10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/versal-net/versal-net.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * Copyright (C) 2022, Xilinx, Inc.\n * Copyright (C) 2022, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal NET\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tcluster2 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu20000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu20100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu20200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu20300>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tcluster3 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu30000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu30100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu30200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu30300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu20000: cpu@20000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20000>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu20100: cpu@20100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20100>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu20200: cpu@20200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20200>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu20300: cpu@20300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20300>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu30000: cpu@30000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30000>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu30100: cpu@30100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30100>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu30200: cpu@30200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30200>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu30300: cpu@30300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30300>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-1066000000 {\n\t\t\topp-hz = /bits/ 64 <1066000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-1866000000 {\n\t\t\topp-hz = /bits/ 64 <1866000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-1900000000 {\n\t\t\topp-hz = /bits/ 64 <1900000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-1999000000 {\n\t\t\topp-hz = /bits/ 64 <1999000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2050000000 {\n\t\t\topp-hz = /bits/ 64 <2050000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2100000000 {\n\t\t\topp-hz = /bits/ 64 <2100000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2200000000 {\n\t\t\topp-hz = /bits/ 64 <2200000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2400000000 {\n\t\t\topp-hz = /bits/ 64 <2400000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n };\n };\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tserial2 = &dcc;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\trtc = &rtc;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t\tspi0 = &ospi;\n\t\tspi1 = &qspi;\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tfirmware {\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tfpga: fpga {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&versal_fpga>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tversal_fpga: versal-fpga {\n\t\tcompatible = \"xlnx,versal-fpga\";\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tadma0: dma-controller@ebd00000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd00000 0 0x1000>;\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma1: dma-controller@ebd10000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd10000 0 0x1000>;\n\t\t\tinterrupts = <0 73 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma2: dma-controller@ebd20000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd20000 0 0x1000>;\n\t\t\tinterrupts = <0 74 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma3: dma-controller@ebd30000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd30000 0 0x1000>;\n\t\t\tinterrupts = <0 75 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma4: dma-controller@ebd40000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd40000 0 0x1000>;\n\t\t\tinterrupts = <0 76 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma5: dma-controller@ebd50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd50000 0 0x1000>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma6: dma-controller@ebd60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd60000 0 0x1000>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma7: dma-controller@ebd70000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd70000 0 0x1000>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tcan0: can@f1980000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1980000 0 0x6000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t};\n\n\t\tcan1: can@f1990000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1990000 0 0x6000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t};\n\n\t\tgem0: ethernet@f19e0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf19e0000 0 0x1000>;\n\t\t\tinterrupts = <0 39 4>, <0 39 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\",\n\t\t\t \"tsu_clk\";\n\t\t};\n\n\t\tgem1: ethernet@f19f0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf19f0000 0 0x1000>;\n\t\t\tinterrupts = <0 41 4>, <0 41 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\",\n\t\t\t\t \"tsu_clk\";\n\t\t};\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>,\n\t\t\t <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\t\t\tits: msi-controller@e2040000 {\n\t\t\t\tcompatible = \"arm,gic-v3-its\";\n\t\t\t\tmsi-controller;\n\t\t\t\t#msi-cells = <1>;\n\t\t\t\treg = <0 0xe2040000 0 0x20000>;\n\t\t\t};\n\t\t};\n\n\t\tgpio0: gpio@f19d0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf19d0000 0 0x1000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 180 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\ti2c0: i2c@f1940000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1940000 0 0x1000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@f1950000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1950000 0 0x1000>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti3c0: i3c-master@f1948000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1948000 0 0x1000>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t};\n\n\t\ti3c1: i3c-master@f1958000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1958000 0 0x1000>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000>,\n\t\t\t <0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 182 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>; /* u-boot specific */\n\t\t\t/* cdns,is-stig-pgm = <1>; - unused - checking with Sai */\n\t\t\tcdns,trigger-address = <0xc0000000>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1030000 0 0x1000>; /* missing one more reg range - checking with Sai */\n\t\t\tinterrupts = <0 183 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupts = <0 200 4>, <0 201 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 184 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-net-emmc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 186 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tserial1: serial@f1930000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1930000 0 0x1000>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tsmmu: iommu@ec000000 {\n\t\t\tcompatible = \"arm,smmu-v3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xec000000 0 0x40000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tinterrupt-names = \"combined\";\n\t\t\tinterrupts = <0 169 4>;\n\t\t\tdma-coherent;\n\t\t};\n\n\t\tspi0: spi@f1960000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 23 4>;\n\t\t\treg = <0 0xf1960000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t};\n\n\t\tspi1: spi@f1970000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0 0xf1970000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t};\n\n\t\tsysmon0: sysmon@f1270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf1270000 0x0 0x4000>;\n\t\t\tinterrupts = <0 202 4>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tttc0: timer@f1dc0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dc0000 0x0 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f1dd0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 46 4>, <0 47 4>, <0 48 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dd0000 0x0 0x1000>;\n\t\t};\n\n\t\tttc2: timer@f1de0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 49 4>, <0 50 4>, <0 51 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1de0000 0x0 0x1000>;\n\t\t};\n\n\t\tttc3: timer@f1df0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 52 4>, <0 53 4>, <0 54 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1df0000 0x0 0x1000>;\n\t\t};\n\n\t\tusb0: usb@f1e00000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1e00000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_0: usb@f1b00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0 0xf1b00000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"usb-wakeup\";\n\t\t\t\tinterrupts = <0 29 4>, <0 33 4>, <0 98 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"peripheral\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\t/*phy-names = \"usb3-phy\";- checking with Pyiush */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@f1e10000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf1e10000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\tinterrupt-names = \"usb-wakeup\";\n\t\t\tinterrupts = <0 99 4>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_1: usb@f1c00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xf1c00000 0x0 0x10000>;\n\t\t\t\tinterrupt-names = \"host\", \"peripheral\", \"otg\", \"wakeup\";\n\t\t\t\tinterrupts = <0 34 4>, <0 34 4>, <0 38 4>, <0 99 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\t/* phy-names = \"usb3-phy\"; - checking with Pyiush */\n\t\t\t};\n\t\t};\n\n\t\twwdt0: watchdog@ecc10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xecc10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\twwdt1: watchdog@ecd10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xecd10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\twwdt2: watchdog@ece10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xece10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\twwdt3: watchdog@ecf10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xecf10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\tlpd_wwdt0: watchdog@ea420000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xea420000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\tlpd_wwdt1: watchdog@ea430000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xea430000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/zynq/skeleton.dtsi", "content": "/*\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/zynq/zynq-7000.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\treplicator {\n\t\tcompatible = \"arm,coresight-static-replicator\";\n\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\tout-ports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\t/* replicator output ports */\n\t\t\tport@0 {\n\t\t\t\treg = <0>;\n\t\t\t\treplicator_out_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&tpiu_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tport@1 {\n\t\t\t\treg = <1>;\n\t\t\t\treplicator_out_port1: endpoint {\n\t\t\t\t\tremote-endpoint = <&etb_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tin-ports {\n\t\t\t/* replicator input port */\n\t\t\tport {\n\t\t\t\treplicator_in_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&funnel_out_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tamba: axi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocm: sram@fffc0000 {\n\t\t\tcompatible = \"mmio-sram\";\n\t\t\treg = <0xfffc0000 0x10000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n compatible = \"xlnx,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n compatible = \"xlnx,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\", \"arm,primecell\";\n\t\t\treg = <0xe000e000 0x0001000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"apb_pclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */\n\t\t\t\t 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */\n\t\t\t\t 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tnfc0: nand-controller@0,0 {\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0 0 0x1000000>;\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t};\n\t\t\tnor0: flash@1,0 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <1 0 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tsdhci0: mmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: mmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n dmac_s: dma-controller@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n /*\n\t\t\t * interrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t * \"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\t */\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\tetb@f8801000 {\n\t\t\tcompatible = \"arm,coresight-etb10\", \"arm,primecell\";\n\t\t\treg = <0xf8801000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\tetb_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ttpiu@f8803000 {\n\t\t\tcompatible = \"arm,coresight-tpiu\", \"arm,primecell\";\n\t\t\treg = <0xf8803000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\ttpiu_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tfunnel@f8804000 {\n\t\t\tcompatible = \"arm,coresight-static-funnel\", \"arm,primecell\";\n\t\t\treg = <0xf8804000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\t\t/* funnel output ports */\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tfunnel_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint =\n\t\t\t\t\t\t\t<&replicator_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tin-ports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\t/* funnel input ports */\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tfunnel0_in_port0: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm0_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tfunnel0_in_port1: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm1_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tfunnel0_in_port2: endpoint {\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t/* The other input ports are not connect to anything */\n\t\t\t};\n\t\t};\n\n\t\tptm@f889c000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889c000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu0>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm0_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889d000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889d000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu1>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm1_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/zynqmp/zynqmp-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-zynqmp-clk.h\"\n\n/ {\n\tfclk0: fclk0 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL0_REF>;\n\t};\n\n\tfclk1: fclk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL1_REF>;\n\t};\n\n\tfclk2: fclk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL2_REF>;\n\t};\n\n\tfclk3: fclk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&zynqmp_clk PL3_REF>;\n\t};\n\n\tpss_ref_clk: pss_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&zynqmp_firmware {\n\tzynqmp_clk: clock-controller {\n\t\tu-boot,dm-pre-reloc;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,\n\t\t\t <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\",\n\t\t\t \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t};\n};\n\n&can0 {\n\tclocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&can1 {\n\tclocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&cpu0 {\n\tclocks = <&zynqmp_clk ACPU>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gpu {\n\tclocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&nand0 {\n\tclocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gem0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>,\n\t\t <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>;\n\tassigned-clocks = <&zynqmp_clk GEM_TSU>;\n};\n\n&gem1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>,\n\t\t <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>;\n\tassigned-clocks = <&zynqmp_clk GEM_TSU>;\n};\n\n&gem2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>,\n\t\t <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>;\n\tassigned-clocks = <&zynqmp_clk GEM_TSU>;\n};\n\n&gem3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>,\n\t\t <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>;\n\tassigned-clocks = <&zynqmp_clk GEM_TSU>;\n};\n\n&gpio {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&i2c0 {\n\tclocks = <&zynqmp_clk I2C0_REF>;\n};\n\n&i2c1 {\n\tclocks = <&zynqmp_clk I2C1_REF>;\n};\n\n&perf_monitor_ocm {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&perf_monitor_ddr {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_cci {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_lpd {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&pcie {\n\tclocks = <&zynqmp_clk PCIE_REF>;\n};\n\n&qspi {\n\tclocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&sata {\n\tclocks = <&zynqmp_clk SATA_REF>;\n};\n\n&sdhci0 {\n\tclocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;\n\tassigned-clocks = <&zynqmp_clk SDIO0_REF>;\n};\n\n&sdhci1 {\n\tclocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;\n\tassigned-clocks = <&zynqmp_clk SDIO1_REF>;\n};\n\n&spi0 {\n\tclocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&spi1 {\n\tclocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart0 {\n\tclocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart1 {\n\tclocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&usb0 {\n\tclocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n\tassigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&dwc3_0 {\n\tclocks = <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&usb1 {\n\tclocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n\tassigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&dwc3_1 {\n\tclocks = <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&watchdog0 {\n\tclocks = <&zynqmp_clk WDT>;\n};\n\n&lpd_watchdog {\n\tclocks = <&zynqmp_clk LPD_WDT>;\n};\n\n&xilinx_ams {\n\tclocks = <&zynqmp_clk AMS_REF>;\n};\n\n&zynqmp_dpdma {\n\tclocks = <&zynqmp_clk DPDMA_REF>;\n\tassigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */\n};\n\n&zynqmp_dpsub {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>,\n\t\t<&zynqmp_clk DP_AUDIO_REF>,\n\t\t<&zynqmp_clk DP_VIDEO_REF>;\n\tassigned-clocks = <&zynqmp_clk DP_STC_REF>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */\n};\n\n&zynqmp_dp_snd_codec0 {\n\tclocks = <&zynqmp_clk DP_AUDIO_REF>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2023.2/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n#include \"include/dt-bindings/dma/xlnx-zynqmp-dpdma.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/power/xlnx-zynqmp-power.h\"\n#include \"include/dt-bindings/reset/xlnx-zynqmp-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tL2: l2-cache {\n\t\t\tcompatible = \"cache\";\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: opp-table-cpu {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tzynqmp_ipi: zynqmp-ipi {\n\t\tu-boot,dm-pre-reloc;\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t\txlnx,ipi-id = <0>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff9905c0 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\treg = <0x0 0xff9905c0 0x0 0x20>,\n\t\t\t <0x0 0xff9905e0 0x0 0x20>,\n\t\t\t <0x0 0xff990e80 0x0 0x20>,\n\t\t\t <0x0 0xff990ea0 0x0 0x20>;\n\t\t\treg-names = \"local_request_region\",\n\t\t\t\t \"local_response_region\",\n\t\t\t\t \"remote_request_region\",\n\t\t\t\t \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <4>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tu-boot,dm-pre-reloc;\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t\tinterrupt-affinity = <&cpu0>,\n\t\t\t\t <&cpu1>,\n\t\t\t\t <&cpu2>,\n\t\t\t\t <&cpu3>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tzynqmp_firmware: zynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x1>;\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tu-boot,dm-pre-reloc;\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tnvmem-firmware {\n\t\t\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tsoc_revision: soc-revision@0 {\n\t\t\t\t\treg = <0x0 0x4>;\n\t\t\t\t};\n\t\t\t\t/* efuse access */\n\t\t\t\tefuse_dna: efuse-dna@c {\n\t\t\t\t\treg = <0xc 0xc>;\n\t\t\t\t};\n\t\t\t\tefuse_usr0: efuse-usr0@20 {\n\t\t\t\t\treg = <0x20 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr1: efuse-usr1@24 {\n\t\t\t\t\treg = <0x24 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr2: efuse-usr2@28 {\n\t\t\t\t\treg = <0x28 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr3: efuse-usr3@2c {\n\t\t\t\t\treg = <0x2c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr4: efuse-usr4@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr5: efuse-usr5@34 {\n\t\t\t\t\treg = <0x34 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr6: efuse-usr6@38 {\n\t\t\t\t\treg = <0x38 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_usr7: efuse-usr7@3c {\n\t\t\t\t\treg = <0x3c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_miscusr: efuse-miscusr@40 {\n\t\t\t\t\treg = <0x40 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_chash: efuse-chash@50 {\n\t\t\t\t\treg = <0x50 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_pufmisc: efuse-pufmisc@54 {\n\t\t\t\t\treg = <0x54 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_sec: efuse-sec@58 {\n\t\t\t\t\treg = <0x58 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_spkid: efuse-spkid@5c {\n\t\t\t\t\treg = <0x5c 0x4>;\n\t\t\t\t};\n\t\t\t\tefuse_ppk0hash: efuse-ppk0hash@a0 {\n\t\t\t\t\treg = <0xa0 0x30>;\n\t\t\t\t};\n\t\t\t\tefuse_ppk1hash: efuse-ppk1hash@d0 {\n\t\t\t\t\treg = <0xd0 0x30>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tzynqmp_pcap: pcap {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t\t\t};\n\n\t\t\tzynqmp_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\tmodepin_gpio: gpio {\n\t\t\t\tcompatible = \"xlnx,zynqmp-gpio-modepin\";\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tedac {\n\t\tcompatible = \"arm,cortex-a53-edac\";\n\t};\n\n\tfpga_full: fpga-full {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&zynqmp_pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t};\n\n\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tu-boot,dm-pre-reloc;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_CAN0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_CAN1>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma-controller@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma-controller@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma-controller@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma-controller@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma-controller@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma-controller@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma-controller@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma-controller@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x0 0x10000>,\n\t\t\t <0x0 0xf9020000 0x0 0x20000>,\n\t\t\t <0x0 0xf9040000 0x0 0x20000>,\n\t\t\t <0x0 0xf9060000 0x0 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-mali\", \"arm,mali-400\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"gp\", \"gpmmu\", \"pp0\", \"ppmmu0\", \"pp1\", \"ppmmu1\";\n\t\t\tclock-names = \"bus\", \"core\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPU>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma-controller@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma-controller@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma-controller@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma-controller@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma-controller@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma-controller@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma-controller@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma-controller@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand-controller@ff100000 {\n\t\t\tcompatible = \"xlnx,zynqmp-nand-controller\", \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"controller\", \"bus\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_NAND>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_0>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;\n\t\t\treset-names = \"gem0_rst\";\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_1>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;\n\t\t\treset-names = \"gem1_rst\";\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_2>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;\n\t\t\treset-names = \"gem2_rst\";\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_3>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;\n\t\t\treset-names = \"gem3_rst\";\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPIO>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tperf_monitor_ocm: perf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa00000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_ddr: perf-monitor@fd0b0000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd0b0000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <6>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <10>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_cci: perf-monitor@fd490000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd490000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_lpd: perf-monitor@ffa10000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa10000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x10000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tiommus = <&smmu 0x4d0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_PCIE>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_QSPI>;\n\t\t};\n\n\t\tpsgtr: phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\";\n\t\t\t#phy-cells = <4>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x7FFF>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SATA>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SATA>;\n\t\t/*\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;*/\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_0>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-uart\", \"cdns,uart-r1p12\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-uart\", \"cdns,uart-r1p12\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_1>;\n\t\t};\n\n\t\tusb0: usb@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_0>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\t\t\treset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tranges;\n\n\t\t\tdwc3_0: usb@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 65 4>, <0 69 4>, <0 75 4>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n snps,resume-hs-terminations;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_1>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\n\t\t\tranges;\n\n\t\t\tdwc3_1: usb@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\", \"otg\", \"hiber\";\n\t\t\t\tinterrupts = <0 70 4>, <0 74 4>, <0 76 4>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\tsnps,enable_guctl1_ipd_quirk;\n snps,resume-hs-terminations;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <60>;\n\t\t\treset-on-timeout;\n\t\t};\n\n\t\tlpd_watchdog: watchdog@ff150000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 52 1>;\n\t\t\treg = <0x0 0xff150000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges = <0 0 0xffa50800 0x800>;\n\n\t\t\tams_ps: ams-ps@0 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams-pl@400 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x400 0x400>;\n\t\t\t};\n\t\t};\n\n\t\tzynqmp_dpdma: dma-controller@fd4c0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tdma-channels = <6>;\n\t\t\tiommus = <&smmu 0xce4>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tzynqmp_dpaud_setting: dp-aud@fd4ac000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpaud-setting\", \"syscon\";\n\t\t\treg = <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t};\n\n\t\tzynqmp_dpsub: display@fd4a0000 {\n\t\t\tu-boot,dm-pre-reloc;\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>;\n\t\t\treg-names = \"dp\", \"blend\", \"av_buf\";\n\t\t\txlnx,dpaud-reg = <&zynqmp_dpaud_setting>;\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tiommus = <&smmu 0xce3>;\n\t\t\tclock-names = \"dp_apb_clk\", \"dp_aud_clk\", \"dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_DP>;\n\t\t\tdma-names = \"vid0\", \"vid1\", \"vid2\", \"gfx0\";\n\t\t\tdmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;\n\n\t\t\t/* dummy node to to indicate there's no child i2c device */\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0: zynqmp-dp-snd-codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0: zynqmp-dp-snd-pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm0\";\n\t\t\t\tdmas = <&zynqmp_dpdma 4>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1: zynqmp-dp-snd-pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm1\";\n\t\t\t\tdmas = <&zynqmp_dpdma 5>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card0: zynqmp-dp-snd-card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,\n\t\t\t\t\t\t <&zynqmp_dp_snd_pcm1>;\n\t\t\t\txlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/ac701-full.dtsi", "content": "&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/ac701-lite.dtsi", "content": "&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n i2c0 = &i2c1;\n rtc0 = &rtc;\n serial0 = &uart1;\n serial1 = &uart0;\n serial2 = &dcc;\n spi0 = &spi0;\n spi1 = &spi1;\n usb0 = &usb0;\n usb1 = &usb1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n\n\tsi5335_0: si5335_0 { /* clk0_usb - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5335_1: si5335_1 { /* clk1_dp - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 IRQ_TYPE_LEVEL_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO3\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO2\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO1\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n};\n\n&psgtr {\n\t/* usb3, dp */\n\tclocks = <&si5335_0>, <&si5335_1>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n\t/delete-property/ reset-gpios;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"super-speed\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n\treset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/kc705-full.dtsi", "content": "&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/kc705-lite.dtsi", "content": "&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/kcu105-tmr.dtsi", "content": "&tmr_0_MB1_axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/kcu105.dtsi", "content": "&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/sp701-rev1.0.dtsi", "content": "&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@1 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x3>;\n\t\t\tti,tx-internal-delay = <0x3>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/vcu118-rev2.0.dtsi", "content": "&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-property/ pcs-handle ;\n\t/delete-property/ managed ;\n\t/delete-property/ xlnx,switch-x-sgmii ;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@3 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\tti,sgmii-ref-clock-output-enable;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\treg = <3>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-a2197-sc-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller RevA\";\n\tcompatible = \"xlnx,versal-sc-revA\", \"xlnx,versal-sc\", \"xlnx,zynqmp\";\n\n\t/* SC Bank 43\n\tFIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS\n\tSYSCTLR_GPIO0 - 5 - conneced to versal */\n\t/* cpu thermal for MAX6643 fan control */\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tdc38_led {\n\t\t\tlabel = \"ds38-green\"; /* sc AB11 500_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc37_led {\n\t\t\tlabel = \"ds37-green\"; /* sc AD10 501_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc36_led {\n\t\t\tlabel = \"ds36-green\"; /* sc AD11 502_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t};\n};\n\n/* usb - type C - pl\n and micro usb 2.0, gt\n*/\n/* Feb 28/2019 version */\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tbootph-all;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tbootph-all;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n/* TODO\nUSB0 MIO52-63\nUSB1 MIO64-75\n*/\n\n/*eth MDIO 76/77\neth reset MIO42\nmarwell m88e1512 - SGMII */\n&gem0 {\n\tphy-handle = <&phy0>;\n\t/* phy-mode = \"sgmii\"; DTG generates this properly */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: phy@21 {\n\t\treg = <21>; /* FIXME */\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5- 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 0 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\"; /* FIXME no linux driver */\n\t\t\t\treg = <0xc0>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <10000000>; /* 10 ohm */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\ti2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* FIXME connection to Samtec J212D */\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t/* FIXME connection to Samtec J53C */\n\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@5d { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@5d { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@5d { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"LPDDR4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-emb-plus-ve2302-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal Embedded+ VE2302 revA\n *\n * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-emb-plus-ve2302-revA\",\n\t\t \"xlnx,versal-emb-plus-ve2302\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal Embedded+ VE2302 revA\";\n\n\tchosen {\n\t\tbootargs = \"earlycon clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\ti2c0 = &i2c0;\n\t};\n\n\t/* For extension board */\n\tonewire {\n\t\tcompatible = \"w1-gpio\";\n\t\tgpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&gpio0 {\n\tgpio-line-names = \"GPIO_LED2\", \"GPIO_LED3\", \"GPIO_LED4\", \"\", \"1WIRE\", /* 0 - 4 */\n\t\t\t\"\", \"FUSA\", \"\", \"EGPIO\", \"AGPIO\", /* 5 - 9 */\n\t\t\t\"I2C0_SCL\", \"I2C0_SDA\", \"\", \"\", \"\", /* 10 - 14 */\n\t\t\t\"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t\t\"\", \"\", \"\", \"\", \"3V3_MON_N\", /* 20 - 24 */\n\t\t\t\"3V3_MON_P\", /* 25, MIO end and EMIO start */\n\t\t\t\"\", \"\", \"\", /* 26 - 29 */\n\t\t\t\"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t\"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t\"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t\"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t\"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t\"\", \"\", \"\"; /* 55 - 57 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-emu-itr8-cn13940875.dtsi", "content": "/ {\n\tcompatible = \"xlnx,versal-emu-itr8\", \"xlnx,versal-emu\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal EMU ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:9600\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n\n\tclk0212: clk0212 {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <212000>;\n\t};\n\n\tclk25: clk25 {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n};\n\n&timer {\n clock-frequency = <440000>;\n};\n\n&serial0 {\n status = \"okay\";\n clocks = <&clk0212 &clk0212>;\n\tcurrent-speed = <9600>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-emu-rev1.9.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tcompatible = \"xlnx,versal-net-emu-1.9\", \"xlnx,versal-net-emu\";\n\tmodel = \"Xilinx Versal NET EMU 1.9\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t};\n\t};\n\n\tmemory: memory@0 {\n\t\treg = <0 0 0 0x10000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 rdinit=/bin/sh\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tfirmware {\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tclk1: clk1 {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <1000000>; /* it doesn't matter on EMU */\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tbootph-all;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&clk1>, <&clk1>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-ipp-rev1.9-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET IPP/SPP OSPI\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-net-ipp-rev1.9.dtsi\"\n\n/ {\n\tmodel = \"Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI\";\n};\n\n&ospi {\n\tstatus = \"okay\";\n};\n\n&qspi {\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-ipp-rev1.9.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/clock/xlnx-versal-net-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-net-power.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-net-ipp-1.9\", \"xlnx,versal-net-spp-5.0\", \"xlnx,versal-net-spp\", \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal NET SPP 5.0/IPP 1.9\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t};\n\t};\n\n\tmemory: memory@0 {\n\t\treg = <0 0 0 0x80000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tserail2 = &dcc;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tbootph-all;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tref_clk: ref_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\tbootph-all;\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\", \"xlnx,versal-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tbootph-all;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x01>;\n\n\t\t\tversal_net_clk: clock-controller {\n\t\t\t\tbootph-all;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-net-clk\", \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupts = <0 57 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t<&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tzynqmp-ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupts = <0 57 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@eb3f0440 {\n\t\t\treg = <0 0xeb3f0440 0 0x20>,\n\t\t\t <0 0xeb3f0460 0 0x20>,\n\t\t\t <0 0xeb3f0280 0 0x20>,\n\t\t\t <0 0xeb3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tbootph-all;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tadma0: dma-controller@ebd00000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd00000 0 0x1000>;\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_0>;\n\t\t};\n\n\t\tadma1: dma-controller@ebd10000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd10000 0 0x1000>;\n\t\t\tinterrupts = <0 73 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_1>;\n\t\t};\n\n\t\tadma2: dma-controller@ebd20000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd20000 0 0x1000>;\n\t\t\tinterrupts = <0 74 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_2>;\n\t\t};\n\n\t\tadma3: dma-controller@ebd30000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd30000 0 0x1000>;\n\t\t\tinterrupts = <0 75 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_3>;\n\t\t};\n\n\t\tadma4: dma-controller@ebd40000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd40000 0 0x1000>;\n\t\t\tinterrupts = <0 76 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_4>;\n\t\t};\n\n\t\tadma5: dma-controller@ebd50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd50000 0 0x1000>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_5>;\n\t\t};\n\n\t\tadma6: dma-controller@ebd60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd60000 0 0x1000>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_6>;\n\t\t};\n\n\t\tadma7: dma-controller@ebd70000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd70000 0 0x1000>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_7>;\n\t\t};\n\n\t\tcan0: can@f1980000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1980000 0 0x6000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>;\n\t\t};\n\n\t\tcan1: can@f1990000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1990000 0 0x6000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>;\n\t\t};\n\n\t\tgem0: ethernet@f19e0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19e0000 0 0x1000>;\n\t\t\tinterrupts = <0 39 4>, <0 39 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>,\n\t\t\t\t <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_0>;\n\t\t\tmdio0: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\t\t#phy-cells = <1>;\n\t\t\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t\tti,rx-internal-delay = <11>;\n\t\t\t\t\tti,tx-internal-delay = <10>;\n\t\t\t\t\tti,fifo-depth = <1>;\n\t\t\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgem1: ethernet@f19f0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19f0000 0 0x1000>;\n\t\t\tinterrupts = <0 41 4>, <0 41 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy2>;\n\t\t\tphy-mode = \"rmii\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>,\n\t\t\t\t <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_1>;\n\t\t\tmdio1: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\t\tcompatible = \"ethernet-phy-id0007.0762\"; /* Vitesse VSC8540 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t};\n\n\t\tgpio0: gpio@f19d0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\treg = <0 0xf19d0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO>;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk PMC_LSBUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>;\n\t\t};\n\n\t\ti2c0: i2c@f1940000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1940000 0 0x1000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C0_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@f1950000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1950000 0 0x1000>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C1_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n\t\t};\n\n\t\ti3c: i3c-master@f1948000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\treg = <0 0xf1948000 0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclocks = <&versal_net_clk I2C_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_PMC>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 182 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,trigger-address = <0xc0000000>;\n\t\t\tclocks = <&versal_net_clk OSPI_REF>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_OSPI>;\n\n\t\t\tmt35xu02g: flash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tcdns,read-delay = <0>;\n\t\t\t\tcdns,tshsl-ns = <0>;\n\t\t\t\tcdns,tsd2d-ns = <0>;\n\t\t\t\tcdns,tchsh-ns = <1>;\n\t\t\t\tcdns,tslch-ns = <1>;\n\t\t\t\tspi-tx-bus-width = <8>;\n\t\t\t\tspi-rx-bus-width = <8>;\n\t\t\t\tspi-max-frequency = <20000000>;\n\t\t\t\tbroken-flash-reset;\n\t\t\t\tno-wp;\n\t\t\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"ospi-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"ospi-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 183 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tnum-cs = <2>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\t\t\tclocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_QSPI>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>, <1>;\n\t\t\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <10000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi0-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"qspi0-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupts = <0 200 4>, <0 201 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 184 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_1>;\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 186 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_0>;\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_UART_0>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tserial1: serial@f1930000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1930000 0 0x1000>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_UART_1>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tsmmu: smmu@ec000000 {\n\t\t\tcompatible = \"arm,smmu-v3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xec000000 0 0x40000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tinterrupt-names = \"combined\";\n\t\t\tinterrupts = <0 169 4>;\n\t\t};\n\n\t\tspi0: spi@f1960000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupts = <0 23 4>;\n\t\t\treg = <0 0xf1960000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_0>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@f1970000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0 0xf1970000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_1>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tttc0: timer@f1dc0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dc0000 0x0 0x1000>;\n\t\t\tclocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_TTC_0>;\n\t\t};\n\n\t\tusb0: usb@f1e00000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0 0xf1e00000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t/* clocks = <&clk60>, <&clk60>; */\n\t\t\tclocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_0>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_0>;\n\n\t\t\tdwc3_0: usb@f1b00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0 0xf1b00000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"host\", \"peripheral\", \"otg\", \"wakeup\";\n\t\t\t\tinterrupts = <0 29 4>, <0 29 4>, <0 33 4>, <0 98 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"peripheral\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@f1e10000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0x0 0xf1e10000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tclocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_1>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_1>;\n\n\t\t\tdwc3_1: usb@f1c00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0x0 0xf1c00000 0x0 0x10000>;\n\t\t\t\tinterrupt-names = \"host\", \"peripheral\", \"otg\", \"wakeup\";\n\t\t\t\tinterrupts = <0 34 4>, <0 34 4>, <0 38 4>, <0 99 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\twwdt0: watchdog@ecc10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecc10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>;\n\t\t};\n\n\t\twwdt1: watchdog@ecd10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecd10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>;\n\t\t};\n\n\t\twwdt2: watchdog@ece10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xece10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>;\n\t\t};\n\n\t\twwdt3: watchdog@ecf10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecf10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-vn-p-b2197-00-reva-pl.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VN-P-B2197 (Tenzing2)\n *\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n\ti2c-mux@70 {\n\t\tcompatible = \"nxp,pca9545\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x70>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tqsfp56g_0: gpio@20 { /* u118 */\n\t\t\t\tcompatible = \"ti,tca6408\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"QSFP56G_0_OC_B\", \"QSFP56G_0_PWR_EN\", /* 0, 1 */\n\t\t\t\t\t\t\"QSFP56G_0_LED_1\", \"QSFP56G_0_LED_0\", /* 2, 3 */\n\t\t\t\t\t\t\"QSFP56G_0_MODPRS_B\", \"QSFP56G_0_LPMODE\", /* 4, 5 */\n\t\t\t\t\t\t\"QSFP56G_0_RESET_B\", \"QSFP56G_0_MODSEL_B\"; /* 6, 7 */\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tqsfp56g_1: gpio@20 { /* u117 */\n\t\t\t\tcompatible = \"ti,tca6408\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"QSFP56G_1_OC_B\", \"QSFP56G_1_PWR_EN\", /* 0, 1 */\n\t\t\t\t\t\t\"QSFP56G_1_LED_1\", \"QSFP56G_1_LED_0\", /* 2, 3 */\n\t\t\t\t\t\t\"QSFP56G_1_MODPRS_B\", \"QSFP56G_1_LPMODE\", /* 4, 5 */\n\t\t\t\t\t\t\"QSFP56G_1_RESET_B\", \"QSFP56G_1_MODSEL_B\"; /* 6, 7 */\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* J48 connector */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* J47 connector */\n\t\t};\n\t};\n/*\n\tGPIO_DIP_SW0-1\n\tGPIO_LED0-1\n\tGPIO_PB0-1\n\tGPIO_SMA\n\n*/\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-vn-p-b2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2)\n *\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n\n/ {\n\tcompatible = \"xlnx,versal-net-vn-p-b2197-00-revA\",\n\t\t \"xlnx,versal-net-vn-p-b2197-00\", \"xlnx,versal-net\";\n};\n\n&i2c0 {\n\t/* Access via J70/J71 or J82/J83 */\n\tclock-frequency = <100000>;\n};\n\n&i2c1 {\n\t/* Access via J70/J71 or J82/J83 */\n\t/* By default this bus should have eeprom for board identification at 0x54 */\n\t/* SE/X-PRC card identification is also on this bus at 0x52 */\n\tclock-frequency = <100000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-vn-x-b2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal Net VNX board\n *\n * (C) Copyright 2022, Xilinx, Inc.\n * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-net-vn-x-b2197-00-revA\",\n\t\t \"xlnx,versal-net-vn-x-b2197-00\", \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal Net VNX\";\n\n\taliases {\n\t\tnvmem0 = &eeprom0;\n\t};\n};\n\n&adma0 {\n\tstatus = \"okay\";\n};\n\n&adma1 {\n\tstatus = \"okay\";\n};\n\n&adma2 {\n\tstatus = \"okay\";\n};\n\n&adma3 {\n\tstatus = \"okay\";\n};\n\n&adma4 {\n\tstatus = \"okay\";\n};\n\n&adma5 {\n\tstatus = \"okay\";\n};\n\n&adma6 {\n\tstatus = \"okay\";\n};\n\n&adma7 {\n\tstatus = \"okay\";\n};\n\n&lpd_wwdt0 {\n\tstatus = \"okay\";\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tphy-handle = <&phy>;\n\tphy-mode = \"rmii\";\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy: ethernet-phy {\n\t\t\treg = <4>;\n\t\t};\n\t};\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\teeprom0: eeprom@51 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t\tbootph-all;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\teeprom1: eeprom@55 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x55>;\n\t\tbootph-all;\n\t};\n};\n\n&ospi {\n\tstatus = \"okay\";\n\tis-dual = <0>;\n\tis-stacked = <1>;\n\treset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n\treset-names = \"qspi\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tmt35xu02g: flash@0 {\n\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <5000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"ospi-flash0\";\n\t\t\t\treg = <0 0x8000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\tno-1-8-v;\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&serial1 {\n\tstatus = \"okay\";\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tnum-cs = <3>;\n};\n\n&usb1 {\n\tstatus = \"okay\";\n};\n\n&dwc3_1 {\n\tstatus = \"okay\";\n\tsnps,refclk_fladj;\n\tsnps,mask_phy_reset;\n\tphy-names = \"usb3-phy\";\n};\n\n&wwdt0 {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-spp-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-spp-itr8-cn13940875\", \"xlnx,versal-spp-itr8\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal SPP ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &ospi;\n\t\tspi2 = &spi0;\n\t\tspi3 = &spi1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tusb0 = &usb0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>;\n\t};\n\tchosen {\n\t\tbootargs = \"rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tclk25: clk25 {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n};\n\n&timer {\n\tclock-frequency = <2720000>;\n};\n\n&serial0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tmaximum-speed = \"high-speed\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n phy0: phy@0 {\n\t\treg = <0x0>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n phy1: phy@1 {\n\t\treg = <0x1>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <0x1>;\n\treg = <0x0 0xf1030000 0x0 0x1000>;\n\tclocks = <&clk125 &clk125>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot-boot.bin\";\n\t\t\t\treg = <0x0 0x6400000>;\n\t\t\t};\n\t\t\tpartition@6400000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x6400000 0x500000>;\n\t\t\t};\n\t\t\tpartition@6900000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x6900000 0x20000>;\n\t\t\t};\n\t\t\tpartition@6920000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x6920000 0x5E0000>;\n\t\t\t};\n\t\t\tpartition@7f40000 {\n\t\t\t\tlabel = \"qspi-bootenv\";\n\t\t\t\treg = <0x7f40000 0x40000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ospi {\n\tstatus = \"disabled\";\n\tclocks = <&clk125 &clk125>;\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\tcdns,fifo-depth = <508>;\n\tcdns,fifo-width = <4>;\n\tcdns,is-dma = <1>;\n\tcdns,trigger-address = <0x00000000>;\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t};\n\t\t\tpartition@600000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t};\n\t\t\tpartition@620000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <1>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <3>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\treg = <0x0 0x84000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-v350-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal v350 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-v350-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal v350 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &ospi;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&serial1 {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-01 revA OSPI\";\n\n\taliases {\n\t\tspi0 = &ospi;\n\t};\n};\n\n/* Mutually exclusive */\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-names = \"qspi\";\n\tresets = <&versal_reset VERSAL_RST_OSPI>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&qspi {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n compatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n \"xlnx,versal-vc-p-a2197-00\",\n \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n model = \"Xilinx Versal A2197 Processor board revA\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tgpio0 = &gpio;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-01 revA QSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t\tphy2: phy@2 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <2>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-02 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem0 {\n\tphy-handle = <&phy0>; /* u9 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@1 { /* Marvell 88E1512; U9 */\n\t\t\treg = <1>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\txlnx,mio-bank = <1>;\n};\n\n&sdhci1 { /* U1A */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n\n&dwc3_0 { /* U4 */\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"high-speed\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* U12 Catalyst EEPROM - AT24 should be equivalent */\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U13 and U15 */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U18 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <3>;\t/* FIXME - check SPI1_SS0-2_B */\n\n\tflash@0 { /* U19 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst26vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-03 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tserial0 = &serial0;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* Must be enabled via J90/J91 */\n\teeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 64Mb */\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x800000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* J99 MIO28 - MIO33 */\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U6 - IS25LQ032B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lq032b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi\"\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tspi0 = &ospi;\n\t};\n};\n\n&qspi {\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-04 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: phy@1 {\n\t\t\treg = <2>;\n\t\t};\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 512MB */\n\t\treg = <0>, <1>;\n\t\tstacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x20000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n#include \"include/dt-bindings/net/mscc-phy-vsc8531.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-05 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem0 {\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: phy@1 { /* 88e1510 */\n\t\t\treg = <1>;\n\t\t};\n\t\tphy2: phy@2 { /* VSC8531 */\n\t\t\treg = <2>;\n\t\t\trx-internal-delay-ps = <2600>;\n\t\t\ttx-internal-delay-ps = <2600>;\n\t\t};\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>;\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tspi-tx-bus-width = <4>;\n\tspi-rx-bus-width = <4>;\n\n\tflash@0 { /* MX25U12835 128Mbit */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 16MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <104000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x1000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc0 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n};\n\n&sdhci1 { /* connector */\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA\";\n\n\taliases {\n\t\tserial2 = &dcc;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 {\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-01-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-01-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (QSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-02-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-02-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (EMMC)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-03-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-03-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (OSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva-x-ebm-01-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-01-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (QSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva-x-ebm-02-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-02-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (EMMC)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva-x-ebm-03-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-03-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (OSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck5000-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck5000 revA\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vck5000-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck5000 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &ospi;\n\t};\n\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x10000000>;\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&serial1 {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vek280-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VEK280 revA\n *\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vek280-revA\", \"xlnx,versal-vek280\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vek280 Eval board revA\";\n\n\tmemory: memory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* VADJ_FMC_EN - LPD MIO23 */\n/* FAN - LPD MIO21/22 */\n/* VCC_PL_EN - LPD MIO20 */\n/* PCIE_PERST - LPD MIO18/19 */\n/* SD_BUSPWR - PMC MIO51 */\n/* PCIE_WAKE - PMC MIO50 */\n/* VCCPSLP_EN - PMC MIO49 */\n/* I2C SYSMON - PMC MIO39 - 41 */\n/* PCIE_PWRBRK - PMC MIO38 */\n/* ZU4_TRIGGER - PMC MIO37 */\n/* VCC_AUX_1V2 - MIO11 */\n\n&ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\treset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = ;\n\t\t\tti,tx-internal-delay = ;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vek280-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VEK280 revB\n *\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vek280-revB\", \"xlnx,versal-vek280\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vek280 Eval board revB\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* VADJ_FMC_EN - LPD MIO23 */\n/* FAN - LPD MIO21/22 */\n/* VCC_PL_EN - LPD MIO20 */\n/* PCIE_PERST - LPD MIO18/19 */\n/* SD_BUSPWR - PMC MIO51 */\n/* PCIE_WAKE - PMC MIO50 */\n/* VCCPSLP_EN - PMC MIO49 */\n/* I2C SYSMON - PMC MIO39 - 41 */\n/* PCIE_PWRBRK - PMC MIO38 */\n/* ZU4_TRIGGER - PMC MIO37 */\n/* VCC_AUX_1V2 - MIO11 */\n\n&ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\treset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@1 { /* u198 - ADI1300 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id0283.bc30\";\n\t\t\treg = <1>;\n\t\t adi,rx-internal-delay-ps = <2000>;\n\t\t\tadi,tx-internal-delay-ps = <2000>;\n\t\t\tadi,fifo-depth-bits = <8>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t\treset-assert-us = <10>;\n\t\t\treset-deassert-us = <5000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vhk158-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VHK158 revA\n *\n * (C) Copyright 2022-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vhk158-revA\", \"xlnx,versal-vhk158\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vhk158 Eval board revA\";\n\n\tmemory: memory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* ZU4_TRIGGER - PMC MIO37 */\n/* PCIE_PWRBRK - PMC MIO38 */\n/* I2C SYSMON - PMC MIO39 - 41 */\n/* VCCPSLP_EN - PMC MIO49 */\n/* PCIE_WAKE - PMC MIO50 */\n/* SOC_EN - LPD MIO13 */\n/* PSFP_EN - LPD MIO15 */\n/* AUX_1V2_EN - LPD MIO16 */\n/* HBM_EN - LPD MIO17 */\n/* PCIE_PERST - LPD MIO18/19 */\n/* VCC_PL_EN - LPD MIO20 */\n/* FAN - LPD MIO21/22 */\n/* VADJ_FMC_EN - LPD MIO23 */\n\n&ospi { /* PMC MIO0 - 12, U297 MT35XU02G */\n\tstatus = \"okay\";\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\treset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = ;\n\t\t\tti,tx-internal-delay = ;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-virt.dtsi", "content": "#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-virt\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal Virtual\";\n\n\toptions {\n\t\tu-boot {\n\t\t\tcompatible = \"u-boot,config\";\n\t\t\tbootscr-address = /bits/ 64 <0x20000000>;\n\t\t};\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tclk2: clk2 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <2670000>;\n\t};\n\n\tclk25: clk25 {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t\tclock-frequency = <2720000>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */\n\t\t\t <0x0 0xf9080000 0x0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x1 0x9 4>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tbootph-all;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x2>;\n\t\tranges;\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff060000 0x0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff070000 0x0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom1: eeprom@53 {\n\t\t\t\treg = <0x53>;\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t};\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom2: eeprom@55 {\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x55>;\n\t\t\t};\n\t\t};\n\n\t\tgpio: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tethernet0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 56 4>, <0x0 56 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy0: phy@0 {\n\t\t\t\treg = <0x0>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tethernet1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 58 4>, <0x0 58 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy1: phy@1 {\n\t\t\t\treg = <0x1>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xf12a0000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tnum-cs = <0x1>;\n\t\t\treg = <0x0 0xf1030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"n25q512a\", \"micron,m25p80\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-tx-bus-width = <4>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <108000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@100000 {\n\t\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@600000 {\n\t\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@620000 {\n\t\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <1>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <3>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0x0 0x84000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\treg = <0x0 0xf1040000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\treg = <0x0 0xf1050000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\t#address-cells = <0x2>;\n\t\t\t#size-cells = <0x2>;\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tranges;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125 &clk125>;\n\n\t\t\tdwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x10000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = ðernet0;\n\t\tethernet1 = ðernet1;\n\t\tqspi = &qspi;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1 (QSPI)\";\n};\n\n&qspi {\n#include \"versal-x-ebm-01-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-02-revA\",\n\t\t \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1 (EMMC)\";\n};\n\n&sdhci1 {\n#include \"versal-x-ebm-02-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-03-revA\",\n \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board rev1.1 (OSPI)\";\n};\n\n&ospi {\n#include \"versal-x-ebm-03-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-01-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (QSPI)\";\n};\n\n&qspi {\n#include \"versal-x-ebm-01-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-02-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (EMMC)\";\n};\n\n&sdhci1 {\n#include \"versal-x-ebm-02-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-03-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (OSPI)\";\n\n aliases {\n spi0 = &ospi;\n };\n};\n\n&ospi {\n#include \"versal-x-ebm-03-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tphy2: ethernet-phy@2 { /* u134 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <2>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 49 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vp-x-a2785-00 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vp-x-a2785-00 Eval board revA\";\n\tcompatible = \"xlnx,versal-vp-x-a2785-00-revA\",\n\t\t \"xlnx,versal-vp-x-a2785-00\", \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tstatus = \"okay\"; /* u93 and u92 */\n\tnum-cs = <2>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\tstatus = \"okay\";\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk120 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk120 Eval board revA\";\n\tcompatible = \"xlnx,versal-vpk120-revA\", \"xlnx,versal-vpk120\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <2>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vpk120-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk120 revB\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk120 Eval board revB\";\n\tcompatible = \"xlnx,versal-vpk120-revB\", \"xlnx,versal-vpk120\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <2>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\t/* Use for storing information about board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tbootph-all;\n\t};\n\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vpk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk180 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk180 Eval board revA\";\n\tcompatible = \"xlnx,versal-vpk180-revA\", \"xlnx,versal-vpk180\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <2>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\n\t/* Use for storing information about board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tbootph-all;\n\t};\n};\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n\n&gpio0 {\n\t/* FIXME Fill names when versal starts */\n};\n\n&gpio1 {\n\t/* FIXME Fill names when versal starts */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-01 revA for vck190/vmk180\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\nnum-cs = <2>;\nspi-tx-bus-width = <4>;\nspi-rx-bus-width = <4>;\n#address-cells = <1>;\n#size-cells = <0>;\nflash@0 {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 256MB */\n\treg = <0>, <1>;\n\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\tspi-tx-bus-width = <4>;\n\tspi-rx-bus-width = <4>;\n\tspi-max-frequency = <150000000>;\n\tpartition@0 {\n\t\tlabel = \"spi0-flash0\";\n\t\treg = <0x0 0x10000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-02 revA for vck190/vmk180\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/* emmc MIO 0-13 - MTFC8GAKAJCN */\nnon-removable;\ndisable-wp;\nbus-width = <8>;\nxlnx,mio-bank = <0>;\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/versal-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-03 revA for vck190/vmk180\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-resets.h\"\n/* U97 MT35XU02G */\ncompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\nbus-num = <2>;\nnum-cs = <1>;\n#address-cells = <1>;\n#size-cells = <0>;\n\nflash@0 {\n\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\treg = <0>;\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcdns,read-delay = <0x0>;\n\tcdns,tshsl-ns = <0x0>;\n\tcdns,tsd2d-ns = <0x0>;\n\tcdns,tchsh-ns = <0x1>;\n\tcdns,tslch-ns = <0x1>;\n\tspi-tx-bus-width = <8>;\n\tspi-rx-bus-width = <8>;\n\tspi-max-frequency = <20000000>;\n\tno-wp;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>;\n\tpartition@0 {\n\t\tlabel = \"spi0-flash0\";\n\t\treg = <0x0 0x8000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n\n\t aliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n rtc0 = &rtc;\n serial0 = &uart0;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tclock_si5338_0: clk27 {\t/* u55 SI5338-GM */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tclock_si5338_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_si5338_3: clk150 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <150000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&psgtr {\n\tstatus = \"okay\";\n\t/* dp, usb3, sata */\n\tclocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem2;\n i2c0 = &i2c0;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n spi0 = &spi0;\n spi1 = &spi1;\n usb0 = &usb1;\n };\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: ethernet-phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"hw\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-0\";\n\t\tnand-ecc-step-size = <1024>;\n\t\tnand-ecc-strength = <24>;\n\t\tnand-on-flash-bbt;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"hw\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-1\";\n\t\tnand-ecc-step-size = <1024>;\n\t\tnand-ecc-strength = <24>;\n\t\tnand-on-flash-bbt;\n\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: flash@0 {\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: flash@0 {\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n#include \n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n serial0 = &uart1;\n spi0 = &qspi;\n mmc0 = &sdhci0;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n switch-14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n switch-13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@34 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x34>;\n\t\t\t};\n\t\t\thwmon@35 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\thwmon@36 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tbootph-all;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tbootph-all;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tbootph-all;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n serial0 = &uart1;\n spi0 = &qspi;\n mmc0 = &sdhci0;\n };\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tbootph-all;\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tbootph-all;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tbootph-all;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&watchdog0 {\n\treset-on-timeout;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu100-reva.dtsi", "content": "/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio-bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu100-revb.dtsi", "content": "/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\t aliases {\n i2c0 = &i2c1;\n rtc0 = &rtc;\n serial0 = &uart1;\n serial1 = &uart0;\n serial2 = &dcc;\n spi0 = &spi0;\n spi1 = &spi1;\n usb0 = &usb0;\n usb1 = &usb1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n led-vbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n\n\tsi5335_0: si5335_0 { /* clk0_usb - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5335_1: si5335_1 { /* clk1_dp - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 IRQ_TYPE_LEVEL_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO3\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO2\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO1\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* usb3, dp */\n\tclocks = <&si5335_0>, <&si5335_1>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n\t/delete-property/ reset-gpios;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"super-speed\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n\treset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zcu102-revb.dtsi\"\n\n/ {\n model = \"ZynqMP ZCU102 Rev1.0\";\n compatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n};\n\n&eeprom {\n #address-cells = <1>;\n #size-cells = <1>;\n\n board_sn: board-sn@0 {\n reg = <0x0 0x14>;\n };\n\n eth_mac: eth-mac@20 {\n reg = <0x20 0x6>;\n };\n\n board_name: board-name@d0 {\n reg = <0xd0 0x6>;\n };\n\n board_revision: board-revision@e0 {\n reg = <0xe0 0x3>;\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@21 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <21>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_4: out@4 {\n\t\t\t\t\t/* refclk4 for PS-GT, used for PCIE slot */\n\t\t\t\t\treg = <4>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 for PS-GT, used for PCIE */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* pcie, sata, usb3, dp */\n\tclocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\t/*\n\t * 1.0 revision has level shifter and this property should be\n\t * removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zcu102-reva.dtsi\"\n\n/ {\n model = \"ZynqMP ZCU102 RevB\";\n compatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n};\n\n&gem3 {\n phy-handle = <&phyc>;\n\tmdio: mdio {\n\t\tphyc: ethernet-phy@c {\n\t\t\t#phy-cells = <0x1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t/* Cleanup from RevA */\n\t\t/delete-node/ ethernet-phy@21;\n };\n};\n\n/* Fix collision with u61 */\n&i2c0 {\n i2c-mux@75 {\n i2c@2 {\n max15303@1b { /* u8 */\n compatible = \"maxim,max15303\";\n reg = <0x1b>;\n };\n /delete-node/ max15303@20;\n };\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* 8T49N287 - u182 */\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@20 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu104-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revC\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;\n\t};\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - IRPS5401_ALERT_B\n\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t * 2 - MAX6643_OT_B\n\t\t * 3 - MAX6643_FANFAIL_B\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t * 4, 10 - 17 - not connected\n\t\t */\n\t};\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* 8T49N287 - u182 */\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tu183: ina226@40 { /* u183 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 4, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\txlnx,mio-bank = <1>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\treg = <0xc>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\n\tina226-u67 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;\n\t};\n\tina226-u59 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n\tina226-u69 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;\n\t};\n\tina226-u66 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;\n\t};\n\tina226-u71 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u73 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tu67: ina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u67\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu59: ina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u59\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu61: ina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu60: ina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu64: ina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu69: ina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u69\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu66: ina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u66\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu63: ina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu3: ina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u3\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu71: ina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u71\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu73: ina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u73\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u57 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SI5382 - u48 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection FIXME */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, dp, usb3, sata */\n\tclocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revA\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu1275-revb.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU1275 RevB\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revB\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n mmc0 = &sdhci1;\n ethernet0 = &gem1;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t* 1.0 revision has level shifter and this property should be\n\t* removed for supporting UHS mode\n\t*/\n\tno-1-8-v;\n};\n\n&gem1 {\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu1285-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU1285 RevA\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1285 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1285-revA\", \"xlnx,zynqmp-zcu1285\", \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n mmc0 = &sdhci1;\n ethernet0 = &gem1; /* EMIO */\n i2c = &i2c0; /* EMIO */\n };\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n};\n\n&gem1 {\n\tmdio {\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu208-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU208\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU208 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu208-revA\", \"xlnx,zynqmp-zcu208\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu216-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU216\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU216 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu216-revA\", \"xlnx,zynqmp-zcu216\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu670-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR)\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU670 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu670-revA\", \"xlnx,zynqmp-zcu670\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\"; /* DS1 */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5381_6: si5381_6 { /* refclk_usb3 - u43 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"SFP3_TX_DISABLE\", \"SFP2_TX_DISABLE\", \"SFP1_TX_DISABLE\", /* 25 - 29 */\n\t\t \"SFP0_TX_DISABLE\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"SD_PWR_RST\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"SI5381_INT_ALM\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* Not in schematics */\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5381: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SI5381 - u43 */\n\t\t\t/*si5381: clock-generator@68 {\n\t\t\t\treg = <0x68>;\n\t\t\t};*/\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_psrefclk: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"si570_ps_ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 2Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&psgtr {\n\t/* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */\n\tclocks = <&si5381_6>;\n\tclock-names = \"ref2\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zcu670-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU670 (67DR) revB\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU670 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu670-revB\", \"xlnx,zynqmp-zcu670\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\"; /* DS1 */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5381_6: si5381_6 { /* refclk_usb3 - u43 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"SFP3_TX_DISABLE\", \"SFP2_TX_DISABLE\", \"SFP1_TX_DISABLE\", /* 25 - 29 */\n\t\t \"SFP0_TX_DISABLE\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"SD_PWR_RST\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"SI5381_INT_ALM\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* Not in schematics */\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5381: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SI5381 - u43 */\n\t\t\t/*si5381: clock-generator@68 {\n\t\t\t\treg = <0x68>;\n\t\t\t};*/\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_psrefclk: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"si570_ps_ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 2Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\txlnx,mio-bank = <1>;\n\tclk-phase-sd-hs = <120>, <60>;\n\tclk-phase-uhs-sdr25 = <132>, <60>;\n\tclk-phase-uhs-ddr50 = <153>, <48>;\n};\n\n&psgtr {\n\t/* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */\n\tclocks = <&si5381_6>;\n\tclock-names = \"ref2\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zedboard.dtsi", "content": "/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tbootph-all;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tbootph-all;\n};\n\n&uart1 {\n\tbootph-all;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-a2197-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Versal System Controller on a2197 board RevA\";\n\tcompatible = \"xlnx,zynqmp-a2197-revA\", \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n i2c0 = &i2c0;\n nvmem0 = &eeprom1;\n nvmem1 = &eeprom0;\n serial0 = &uart0;\n };\n\n};\n\n&i2c0 {\n\tbootph-all;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* this cover MGT board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tbootph-all;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tbootph-all;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tbootph-all;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* This cover processor board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tbootph-all;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tbootph-all;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-e-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevA\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n nvmem1 = &eeprom_ebm;\n nvmem2 = &eeprom_fmc1;\n nvmem3 = &eeprom_fmc2;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n };\n\n\n\tref_clk: ref-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tsi570_ddrdimm1_clk: si570-ddrdimm1-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tsi570_lpddr4_clk2: si570-lpddr4-clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570-lpddr4-clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk1>;\n\t};\n\n\tsi570_hsdp_clk: si570-hsdp-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi570_zsfp_clk: si570-zsfp-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_zsfp>;\n\t};\n\n\tsi570_user1_clk: si570-user1-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_user1>;\n\t};\n\n\tsi5332_1: si5332_1 { /* u142 - GEM0 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vcc-soc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;\n\t};\n\tina226-vcc-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc-pslp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;\n\t};\n\tina226-vcc-psfp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;\n\t};\n\tina226-vccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;\n\t};\n\tina226-vccaux-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;\n\t};\n\tina226-vcco-500 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;\n\t};\n\tina226-vcco-501 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;\n\t};\n\tina226-vcco-502 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;\n\t};\n\tina226-vcco-503 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;\n\t};\n\tina226-vcc-1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;\n\t};\n\tina226-vcc-3v3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;\n\t};\n\tina226-vcc-1v2-ddr4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;\n\t};\n\tina226-vcc-1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtyavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;\n\t};\n\tina226-mgtyavtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;\n\t};\n\tina226-mgtyvccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;\n\t};\n\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n/* GEM SGMII */\n&psgtr {\n\tstatus = \"okay\";\n\t/* gem0 */\n\tclocks = <&si5332_1>;\n\tclock-names = \"ref0\";\n};\n\n&gem0 {\n\tphys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@0 { /* u131 M88E1512 */\n\t\t\treg = <0>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"ZU4_TRIGGER\", \"SYSCTLR_PB\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"\", /* 85 - 89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"PMBUS_ALERT\", \"\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ttca6416_u233: gpio@20 { /* u233 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"\", \"\", /* 0 - 3 */\n\t\t\t\t\"PMBUS2_INA226_ALERT\", \"\", \"\", \"MAX6643_FULLSPD\", /* 4 - 7 */\n\t\t\t\t\"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 10 - 13 */\n\t\t\t\t\"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* u152 IR35215 0x16/0x46 vcc_soc */\n\t\t\t/* u179 ir38164 0x19/0x49 vcco_500 */\n\t\t\t/* u181 ir38164 0x1a/0x4a vcco_501 */\n\t\t\t/* u183 ir38164 0x1b/0x4b vcco_502 */\n\t\t\t/* u185 ir38164 0x1e/0x4e vadj_fmc */\n\t\t\t/* u187 ir38164 0x1F/0x4f mgtyavcc */\n\t\t\t/* u189 ir38164 0x20/0x50 mgtyavtt */\n\t\t\t/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */\n\t\t\t/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */\n\n\t\t\tirps5401_47: irps5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* pmbus / i2c 0x17 */\n\t\t\t};\n\t\t\tirps5401_4c: irps5401@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* pmbus / i2c 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: irps5401@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* pmbus / i2c 0x1d */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <500>; /* R440 */\n\t\t\t\t/* 0.80V @ 32A 1 of 6 Phases*/\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-soc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <500>; /* R1702 */\n\t\t\t\t/* 0.80V @ 18A */\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pmc\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* R1214 */\n\t\t\t\t/* 0.78V @ 500mA */\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u162 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r1221 */\n\t\t\t\t/* 0.78V @ 4A */\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pslp\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>; /* R1216 */\n\t\t\t\t/* 0.78V @ 1A */\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-psfp\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1219 */\n\t\t\t\t/* 0.78V @ 2A */\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u39 8T49N240 */\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* R382 */\n\t\t\t\t/* 1.5V @ 3A */\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux-pmc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>; /* R1246 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u178 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-500\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>; /* R1300 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u180 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-501\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <2000>; /* R1313 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u182 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-502\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <2000>; /* R1330 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-503\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1229 */\n\t\t\t\t/* 1.8V @ 2A */\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u173 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v8\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>; /* R400 */\n\t\t\t\t/* 1.8V @ 6A */\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-3v3\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* R1232 */\n\t\t\t\t/* 3.3V @ 500mA */\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v2-ddr4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>; /* R1275 */\n\t\t\t\t/* 1.2V @ 4A */\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>; /* R1286 */\n\t\t\t\t/* 1.1V @ 4A */\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>; /* R1350 */\n\t\t\t\t/* 1.5V @ 10A */\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavcc\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <2000>; /* R1367 */\n\t\t\t\t/* 0.88V @ 6A */\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavtt\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>; /* R1384 */\n\t\t\t\t/* 1.2V @ 10A */\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyvccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>; /* r1679 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t\ti2c@5 { /* zSFP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_zsfp: clock-generator@5d { /* u192 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_zsfp_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* USER_SI570_1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_user1: clock-generator@5f { /* u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>; /* FIXME check address */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"si570_user1\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\n\t\t};\n\t\ti2c@7 { /* USER_SI570_2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* 0x5c too */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* and connector J212D */\n\t\t\teeprom_ebm: eeprom@52 { /* x-ebm module */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\t\t};\n\t\tfmc1: i2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t\teeprom_fmc1: eeprom@50 {\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\tfmc2: i2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t\teeprom_fmc2: eeprom@50 {\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LPDDR4_SI570_CLK2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_lpddr4clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk2\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4clk1: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk1\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* 8A34001 - U219B and J310 connector */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n\ti2c-mux@75 { /* u214 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\ti2c@0 { /* SFP0_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* SFP0 */\n\t\t};\n\t\ti2c@1 { /* SFP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@2 { /* QSFP1_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* QSFP1 */\n\t\t};\n\t\t/* 3 - 7 unused */\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-e-a2197-00-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevB System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-e-a2197-00-reva.dtsi\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevB\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revB\", \"xlnx,zynqmp-a2197-revB\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\t/delete-node/ ina226-vcco-500;\n\t/delete-node/ ina226-vcco-501;\n\t/delete-node/ ina226-vcco-502;\n};\n\n&i2c0 {\n\ti2c-mux@74 { /* u33 */\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t/delete-node/ clock-generator@6c;\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t/delete-node/ ina226@42;\n\t\t\t/delete-node/ ina226@43;\n\t\t\t/delete-node/ ina226@44;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-g-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 MGT Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-g-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\t aliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n mmc0 = &sdhci0;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n usb0 = &usb0;\n };\n\n\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u82 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&gem0 { /* eth MDIO 76/77 */\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 */\n\t\treg = <0>;\n\t\treset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 5 - 9 */\n\t\t \"\", \"\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"\", \"\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\ti2c-mux@74 { /* u94 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* CM_I2C_SCL - Samtec */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* PMBUS - AFX_PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\ttps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\ttps544@10 { /* u73 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\ttps544@11 { /* u76 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\ttps544@12 { /* u77 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\ttps544@13 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\ttps544@14 { /* u81 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\ttps544@15 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\ttps544@16 { /* u63 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\ttps544@17 { /* u66 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\ttps544@18 { /* u67 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\ttps544@19 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\ttps544@1d { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\ttps544@1e { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\ttps544@1f { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t\ttps544@20 { /* u71 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\t\t\tu74: ina226@40 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu75: ina226@41 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\"\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@43 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu82: ina226@44 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u82\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu84: ina226@45 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\ttps53681@60 { /* u53- 0xc0 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* fmc1 via JA2G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom_fmc1: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* fmc2 via JA3G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\teeprom_fmc2: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* fmc3 via JA4G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\teeprom_fmc3: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* ddr dimm */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"high-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-m-a2197-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-01-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n spi0 = &qspi;\n };\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\tina226-vcc0v6-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc0v6_lp4: ina226@49 { /* u101 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc0v6-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@60 { /* u69 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@5d { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n status = \"disabled\"; /* not at mem board */\n};\n\n&dwc3_1 {\n /delete-property/ phy-names ;\n /delete-property/ phys ;\n maximum-speed = \"high-speed\";\n snps,dis_u2_susphy_quirk ;\n snps,dis_u3_susphy_quirk ;\n status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-m-a2197-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-02-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n spi0 = &qspi;\n };\n\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@60 { /* u69 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* C0_DDR4_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\ti2c@6 { /* C2_DDR5_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\ti2c@7 { /* C3_DDR4_UDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_RLD3 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_RLD3_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_DDR5 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_DDR5_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-m-a2197-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-03-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n spi0 = &qspi;\n };\n\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@18 { /* u3022 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@60 { /* u69 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* DDR4_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_SODIMM_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_QDRIV */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_QDRIV_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-01-revA\", \"xlnx,zynqmp-x-prc-01\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\",\"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-02-revA\", \"xlnx,zynqmp-x-prc-02\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-03-revA\", \"xlnx,zynqmp-x-prc-03\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tx_prc_si5338: clock-generator@70 { /* U9 */\n\t\t\t\tcompatible = \"silabs,si5338\";\n\t\t\t\treg = <0x70>; /* FIXME */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-04-revA\", \"xlnx,zynqmp-x-prc-04\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-05-revA\", \"xlnx,zynqmp-x-prc-05\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n };\n\n\n\tref_clk: ref-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4-dimm1-si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4-dimm2-si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4-si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp-si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@60 { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* 570JAC000900DG */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u39 8T49N240 - pcie clocking 3 */\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sc-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP Generic System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tmodel = \"ZynqMP Generic System Controller\";\n\tcompatible = \"xlnx,zynqmp-sc-revB\", \"xlnx,zynqmp-sc\", \"xlnx,zynqmp\";\n\n\taliases {\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n spi1 = &spi0;\n spi2 = &spi1;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tkey-fwuen {\n\t\t\tlabel = \"sw16\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds40-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t\tds44-led {\n\t\t\tlabel = \"status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tsi5332_2: si5332_2 { /* u42 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\tpwm-fan {\n\t\tcompatible = \"pwm-fan\";\n\t\tpwms = <&ttc0 2 40000 1>;\n\t};\n\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\"QSPI_CS_B\", \"\", \"LED1\", \"LED2\", \"\", /* 5 - 9 */\n\t\t\"\", \"ZU4_TRIGGER\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\"I2C1_SDA\", \"UART0_RXD\", \"UART0_TXD\", \"\", \"\", /* 25 - 29 */\n\t\t\"\", \"\", \"\", \"\", \"I2C0_SCL\", /* 30 - 34 */\n\t\t\"I2C0_SDA\", \"UART1_TXD\", \"UART1_RXD\", \"GEM_TX_CLK\", \"GEM_TX_D0\", /* 35 - 39 */\n\t\t\"GEM_TX_D1\", \"GEM_TX_D2\", \"GEM_TX_D3\", \"GEM_TX_CTL\", \"GEM_RX_CLK\", /* 40 - 44 */\n\t\t\"GEM_RX_D0\", \"GEM_RX_D1\", \"GEM_RX_D2\", \"GEM_RX_D3\", \"GEM_RX_CTL\", /* 45 - 49 */\n\t\t\"GEM_MDC\", \"GEM_MDIO\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t\"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t\"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\"\", \"\", \"ETH_RESET_B\", /* 75 - 77, MIO end and EMIO start */\n\t\t\"\", \"\", /* 78 - 79 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem1_default>;\n\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy0: ethernet-phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = ;\n\t\t\tti,tx-internal-delay = ;\n\t\t\tti,fifo-depth = ;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t};\n\t};\n};\n\n&i2c0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\tclock-frequency = <100000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n};\n\n&i2c1 { /* i2c1 MIO 24-25 */\n\tbootph-all;\n\tclock-frequency = <100000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t/* No reason to do pinctrl setup at u-boot stage */\n\t/* Use for storing information about SC board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tbootph-all;\n\t};\n};\n\n/* USB 3.0 only */\n&psgtr {\n\t/* nc, nc, usb3 */\n\tclocks = <&si5332_2>;\n\tclock-names = \"ref2\";\n};\n\n&qspi { /* MIO 0-5 */\n\t/* QSPI should also have PINCTRL setup */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x40000>; /* 256B but 256KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2280000 {\n\t\t\tlabel = \"Secure OS Storage\";\n\t\t\treg = <0x2280000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@22A0000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x22A0000 0x1d60000>; /* 29.375 MB */\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&ttc0 {\n\t#pwm-cells = <3>;\n};\n\n&uart1 { /* uart0 MIO36-37 */\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&pinctrl0 { /* required by spec */\n\tstatus = \"okay\";\n\tpinctrl_uart1_default: uart1-default {\n\t\tconf {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO37\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO36\";\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tconf {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tconf {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\t};\n\n\tpinctrl_gem1_default: gem1-default {\n\t\tconf {\n\t\t\tgroups = \"ethernet1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO44\", \"MIO46\", \"MIO48\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-bootstrap {\n\t\t\tpins = \"MIO45\", \"MIO47\", \"MIO49\";\n\t\t\tbias-disable;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO38\", \"MIO39\", \"MIO40\",\n\t\t\t\t\"MIO41\", \"MIO42\", \"MIO43\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio1\";\n\t\t\tgroups = \"mdio1_0_grp\";\n\t\t};\n\n\t\tmux {\n\t\t\tfunction = \"ethernet1\";\n\t\t\tgroups = \"ethernet1_0_grp\";\n\t\t};\n\t};\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sc-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP Generic System Controller\n *\n * Copyright (C) 2021-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sc-revb.dtsi\"\n\n/ {\n\tmodel = \"ZynqMP Generic System Controller\";\n\tcompatible = \"xlnx,zynqmp-sc-revC\", \"xlnx,zynqmp-sc\", \"xlnx,zynqmp\";\n};\n\n&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */\n\t/delete-node/ mdio;\n\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy0: ethernet-phy@1 { /* ADI1300 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id0283.bc30\";\n\t\t\treg = <1>;\n\t\t adi,rx-internal-delay-ps = <2400>;\n\t\t\tadi,tx-internal-delay-ps = <2400>;\n\t\t\tadi,fifo-depth-bits = <8>;\n\t\t\treset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;\n\t\t\treset-assert-us = <10>;\n\t\t\treset-deassert-us = <5000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sc-vek280-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VEK280 revA\n *\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n\n&{/} {\n\tcompatible = \"xlnx,zynqmp-sc-vek280-revA\", \"xlnx,zynqmp-vek280-revA\",\n\t\t \"xlnx,zynqmp-vek280\", \"xlnx,zynqmp\";\n\n\tvc7_xin: vc7-xin {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <50000000>;\n\t};\n\n\tgtclk1_1: sys-clk-0 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 0>;\n\t};\n\n\tgtclk1_2: sys-clk-1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 1>;\n\t};\n\n\tgtclk1_3: sys-clk-2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 2>;\n\t};\n\n\tgtclk1_6: gtclk1-out6 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 3>;\n\t};\n\n\tgtclk1_7: gtclk1-out7 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 4>;\n\t};\n\n\tgtclk1_8: gtclk1-out8 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 5>;\n\t};\n\n\tgtclk1_10: ps-ref-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 6>;\n\t};\n\n\tgtclk1_11: gtclk1-out11 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 7>;\n\t};\n};\n\n&i2c0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\ttca6416_u233: gpio@20 { /* u233 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"\", \"\", \"SFP_MOD_ABS\", \"SFP_TX_DISABLE\", /* 0 - 3 */\n\t\t\t\t\"PMBUS2_INA226_ALERT\", \"\", \"\", \"\", /* 4 - 7 */\n\t\t\t\t\"FMCP1_FMC_PRSNT_M2C_B\", \"\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"\", /* 10 - 13 */\n\t\t\t\t\"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\tir35215_46: pmic@46 { /* IR35215 - u152 */\n\t\t\t\tcompatible = \"infineon,ir35215\";\n\t\t\t\treg = <0x46>; /* i2c addr - 0x16 */\n\t\t\t};\n\t\t\tirps5401_47: pmic5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* i2c addr 0x17 */\n\t\t\t};\n\t\t\tirps5401_48: pmic@48 { /* IRPS5401 - u279 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x48>; /* i2c addr 0x18 */\n\t\t\t};\n\t\t\tir38064_49: regulator@49 { /* IR38064 - u295 */\n\t\t\t\tcompatible = \"infineon,ir38064\";\n\t\t\t\treg = <0x49>; /* i2c addr 0x19 */\n\t\t\t};\n\t\t\tirps5401_4c: pmic@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: pmic@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* i2c addr 0x1d */\n\t\t\t};\n\t\t\tir38060_4e: regulator@4e { /* IR38060 - u282 */\n\t\t\t\tcompatible = \"infineon,ir38060\";\n\t\t\t\treg = <0x4e>; /* i2c addr 0x1e */\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* alerts coming to u233 and SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <500>; /* r440 */\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <500>; /* r1702 */\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* r382 */\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u355 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r2417 */\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>; /* r1830 */\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u260 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* r2386 */\n\t\t\t};\n\t\t\tvcco_hdio: ina226@46 { /* u356 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>; /* r2392 */\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpmbus2_ina226_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* alerts coming to u233 and SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* r2384 */\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>; /* r2000 */\n\t\t\t};\n\t\t\tmgtavcc: ina226@42 { /* u265 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* r1829 */\n\t\t\t};\n\t\t\tvcc1v5: ina226@43 { /* u264 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r2397 */\n\t\t\t};\n\t\t\tvcco_mio: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* r2401 */\n\t\t\t};\n\t\t\tmgtavtt: ina226@46 { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <500>; /* r1384 */\n\t\t\t};\n\t\t\tvcco_502: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* r1994 */\n\t\t\t};\n\t\t\tmgtvccaux: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>; /* r2384 */\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u306 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <500>; /* r2064 */\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u281 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>; /* r2031 */\n\t\t\t};\n\t\t\tlpdmgtyavcc: ina226@4b { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>; /* r2004 */\n\t\t\t};\n\t\t\tlpdmgtyavtt: ina226@4c { /* u309 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>; /* r1229 */\n\t\t\t};\n\t\t\tlpdmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>; /* r1679 */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\trc21008a_gtclk1: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* connector j374 */\n\t\t\t/* rc21008a at 0x9 u299 */\n\t\t\tvc7: clock-generator@9 {\n\t\t\t\tcompatible = \"renesas,rc21008a\";\n\t\t\t\treg = <0x9>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&vc7_xin>;\n\t\t\t\tclock-names = \"xin\";\n\t\t\t};\n\t\t};\n\t\tfmcp1_iic: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* to j51c */\n\t\t};\n\t\tsfp: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* sfp+ connector J376 */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sc-vek280-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VEK280 revB\n *\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sc-vek280-reva.dtsi\"\n\n&{/} {\n\tcompatible = \"xlnx,zynqmp-sc-vek280-revB\", \"xlnx,zynqmp-vek280-revB\",\n\t\t \"xlnx,zynqmp-vek280\", \"xlnx,zynqmp\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sm-k24-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SM-K24 RevA\n *\n * (C) Copyright 2020 - 2021, Xilinx, Inc.\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sm-k26-reva.dtsi\"\n\n/ {\n\tmodel = \"ZynqMP SM-K24 RevA/B/1\";\n\tcompatible = \"xlnx,zynqmp-sm-k24-rev1\", \"xlnx,zynqmp-sm-k24-revB\",\n\t\t \"xlnx,zynqmp-sm-k24-revA\", \"xlnx,zynqmp-sm-k24\",\n\t\t \"xlnx,zynqmp\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sm-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SM-K26 rev1/B/A\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP SM-K26 Rev1/B/A\";\n\tcompatible = \"xlnx,zynqmp-sm-k26-rev1\", \"xlnx,zynqmp-sm-k26-revB\",\n\t\t \"xlnx,zynqmp-sm-k26-revA\", \"xlnx,zynqmp-sm-k26\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\treserved-memory {\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tpmu_region: pmu@7ff00000 {\n\t\t\treg = <0x0 0x7ff00000 0x0 0x100000>;\n\t\t\tno-map;\n\t\t};\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tkey-fwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36-led {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n\tpwm-fan {\n\t\tcompatible = \"pwm-fan\";\n\t\tpwms = <&ttc0 2 40000 0>;\n\t};\n};\n\n&modepin_gpio {\n\tlabel = \"modepin\";\n};\n\n&ttc0 {\n\t#pwm-cells = <3>;\n};\n\n&pinctrl0 {\n status = \"okay\";\n pinctrl_sdhci0_default: sdhci0-default {\n conf {\n groups = \"sdio0_0_grp\";\n slew-rate = ;\n power-source = ;\n bias-disable;\n };\n\n mux {\n groups = \"sdio0_0_grp\";\n function = \"sdio0\";\n };\n };\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tspi_flash: flash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Image Selector\";\n\t\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"Image Selector Golden\";\n\t\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"Persistent Register\";\n\t\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@120000 {\n\t\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@140000 {\n\t\t\t\tlabel = \"Open_1\";\n\t\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t\t};\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t\t};\n\t\t\tpartition@f00000 {\n\t\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@f80000 {\n\t\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t\t};\n\t\t\tpartition@1c80000 {\n\t\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@1d00000 {\n\t\t\t\tlabel = \"Open_2\";\n\t\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t\t};\n\t\t\tpartition@1e00000 {\n\t\t\t\tlabel = \"Recovery Image\";\n\t\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@2000000 {\n\t\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@2200000 {\n\t\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@2220000 {\n\t\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@2240000 {\n\t\t\t\tlabel = \"SHA256\";\n\t\t\t\treg = <0x2240000 0x40000>; /* 256B but 256KB sector */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@2280000 {\n\t\t\t\tlabel = \"Secure OS Storage\";\n\t\t\t\treg = <0x2280000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@22A0000 {\n\t\t\t\tlabel = \"User\";\n\t\t\t\treg = <0x22A0000 0x1d60000>; /* 29.375 MB */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tassigned-clock-rates = <187498123>;\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tbootph-all;\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tbootph-all;\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tbootph-all;\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues to be fixed in next board revision.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-smk-k24-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SMK-K24 RevA\n *\n * (C) Copyright 2020 - 2021, Xilinx, Inc.\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sm-k24-reva.dtsi\"\n\n/ {\n\tmodel = \"ZynqMP SMK-K24 RevA\";\n\tcompatible = \"xlnx,zynqmp-smk-k24-revA\", \"xlnx,zynqmp-smk-k24\",\n\t\t \"xlnx,zynqmp\";\n};\n\n&sdhci0 {\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-smk-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sm-k26-reva.dtsi\"\n\n/ {\n model = \"ZynqMP SMK-K26 Rev1/B/A\";\n compatible = \"xlnx,zynqmp-smk-k26-rev1\", \"xlnx,zynqmp-smk-k26-revB\",\n \"xlnx,zynqmp-smk-k26-revA\", \"xlnx,zynqmp-smk-k26\",\n \"xlnx,zynqmp\";\n};\n\n&sdhci0 {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on vp-x-a2785-00 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vp-x-a2785-00-revA\",\n\t\t \"xlnx,zynqmp-vp-x-a2785-00\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n usb1 = &usb1;\n nvmem0 = &eeprom;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tkey-j383 {\n\t\t\tlabel = \"j383\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds52 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* u285 - mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>; /* maybe 4 here */\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* sd MIO 45-51 */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tbootph-all;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 { /* u131 - M88e1512 */\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"\", \"\", \"\", \"VCCINT_FAULT_B\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\treg_vccint: tps53681@60 { /* u266 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@10 { /* u274 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@11 { /* u275 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@12 { /* u276 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc_cpm: tps544@14 { /* u272 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_util_3v3: tps544@1d { /* u278 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvcc_cpm: ina226@44 { /* u273 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpcie_smbus: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tpcie2_smbus: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\ti2c@3 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\t/* 6-7 unused */\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VPK120 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on VPK120 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vpk120-revA\",\n\t\t \"xlnx,zynqmp-vpk120\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n usb1 = &usb1;\n nvmem0 = &eeprom;\n };\n\n\tsi570_user1_fmc_clk: si570-user1-fmc-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&user_si570_1>;\n\t};\n\n\tsi570_ref_clk: si570-ref-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&ref_clk>;\n\t};\n\n\tsi570_lpddr4_clk3: si570-lpddr4-clk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk3>;\n\t};\n\n\tsi570_lpddr4_clk2: si570-lpddr4-clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570-lpddr4-clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk1>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tbutton-16 {\n\t\t\tlabel = \"sw16\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds40 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tbootph-all;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"\", \"\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"\", /* 85 - 89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"QSFPDD1_MODSELL\", \"QSFPDD1_MODSELL\", /* 0 - 3 */\n\t\t\t\t \"PMBUS2_INA226_ALERT\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP1_FMC_PRSNT_M2C_B\", \"\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\tir38060_41: regulator@41 { /* IR38060 - u259 */\n\t\t\t\tcompatible = \"infineon,ir38060\", \"infineon,ir38064\";\n\t\t\t\treg = <0x41>; /* i2c addr 0x11 */\n\t\t\t};\n\t\t\tir38164_43: regulator@43 { /* IR38164 - u13 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x43>; /* i2c addr 0x13 */\n\t\t\t};\n\t\t\tir35221_45: pmic@46 { /* IR35221 - u152 */\n\t\t\t\tcompatible = \"infineon,ir35221\";\n\t\t\t\treg = <0x46>; /* PMBUS - 0x16 */\n\t\t\t};\n\t\t\tirps5401_47: pmic5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* i2c addr 0x17 */\n\t\t\t};\n\t\t\tir38164_49: regulator@49 { /* IR38164 - u189 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x49>; /* i2c addr 0x19 */\n\t\t\t};\n\t\t\tirps5401_4c: pmic@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: pmic@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tir38164_4e: regulator@4e { /* IR38164 - u184 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4e>; /* i2c addr 0x1e */\n\t\t\t};\n\t\t\tir38164_4f: regulator@4f { /* IR38164 - u187 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4f>; /* i2c addr 0x1f */\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u5 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpmbus2_ina226_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@42 { /* u265 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v5: ina226@43 { /* u264 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_mio: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavtt: ina226@46 { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtvccaux: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyavcc: ina226@4b { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tlpdmgtyavtt: ina226@4c { /* u260 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tuser_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"fmc_si570\";\n\t\t\t};\n\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tref_clk_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\tfmcp1_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tlpddr4_si570_clk3_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlpddr4_clk3: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk3\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\tqsfpdd_i2c: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* J1/J2 connectors */\n\t\t};\n\t\tidt8a34001_i2c: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* Via J310 connector */\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u219B */\n\t\t\t\treg = <0x5b>; /* FIXME not in schematics */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/clock/xlnx-versal-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_VERSAL_H\n#define _DT_BINDINGS_CLK_VERSAL_H\n\n#define PMC_PLL\t\t\t\t\t1\n#define APU_PLL\t\t\t\t\t2\n#define RPU_PLL\t\t\t\t\t3\n#define CPM_PLL\t\t\t\t\t4\n#define NOC_PLL\t\t\t\t\t5\n#define PLL_MAX\t\t\t\t\t6\n#define PMC_PRESRC\t\t\t\t7\n#define PMC_POSTCLK\t\t\t\t8\n#define PMC_PLL_OUT\t\t\t\t9\n#define PPLL\t\t\t\t\t10\n#define NOC_PRESRC\t\t\t\t11\n#define NOC_POSTCLK\t\t\t\t12\n#define NOC_PLL_OUT\t\t\t\t13\n#define NPLL\t\t\t\t\t14\n#define APU_PRESRC\t\t\t\t15\n#define APU_POSTCLK\t\t\t\t16\n#define APU_PLL_OUT\t\t\t\t17\n#define APLL\t\t\t\t\t18\n#define RPU_PRESRC\t\t\t\t19\n#define RPU_POSTCLK\t\t\t\t20\n#define RPU_PLL_OUT\t\t\t\t21\n#define RPLL\t\t\t\t\t22\n#define CPM_PRESRC\t\t\t\t23\n#define CPM_POSTCLK\t\t\t\t24\n#define CPM_PLL_OUT\t\t\t\t25\n#define CPLL\t\t\t\t\t26\n#define PPLL_TO_XPD\t\t\t\t27\n#define NPLL_TO_XPD\t\t\t\t28\n#define APLL_TO_XPD\t\t\t\t29\n#define RPLL_TO_XPD\t\t\t\t30\n#define EFUSE_REF\t\t\t\t31\n#define SYSMON_REF\t\t\t\t32\n#define IRO_SUSPEND_REF\t\t\t\t33\n#define USB_SUSPEND\t\t\t\t34\n#define SWITCH_TIMEOUT\t\t\t\t35\n#define RCLK_PMC\t\t\t\t36\n#define RCLK_LPD\t\t\t\t37\n#define WDT\t\t\t\t\t38\n#define TTC0\t\t\t\t\t39\n#define TTC1\t\t\t\t\t40\n#define TTC2\t\t\t\t\t41\n#define TTC3\t\t\t\t\t42\n#define GEM_TSU\t\t\t\t\t43\n#define GEM_TSU_LB\t\t\t\t44\n#define MUXED_IRO_DIV2\t\t\t\t45\n#define MUXED_IRO_DIV4\t\t\t\t46\n#define PSM_REF\t\t\t\t\t47\n#define GEM0_RX\t\t\t\t\t48\n#define GEM0_TX\t\t\t\t\t49\n#define GEM1_RX\t\t\t\t\t50\n#define GEM1_TX\t\t\t\t\t51\n#define CPM_CORE_REF\t\t\t\t52\n#define CPM_LSBUS_REF\t\t\t\t53\n#define CPM_DBG_REF\t\t\t\t54\n#define CPM_AUX0_REF\t\t\t\t55\n#define CPM_AUX1_REF\t\t\t\t56\n#define QSPI_REF\t\t\t\t57\n#define OSPI_REF\t\t\t\t58\n#define SDIO0_REF\t\t\t\t59\n#define SDIO1_REF\t\t\t\t60\n#define PMC_LSBUS_REF\t\t\t\t61\n#define I2C_REF\t\t\t\t\t62\n#define TEST_PATTERN_REF\t\t\t63\n#define DFT_OSC_REF\t\t\t\t64\n#define PMC_PL0_REF\t\t\t\t65\n#define PMC_PL1_REF\t\t\t\t66\n#define PMC_PL2_REF\t\t\t\t67\n#define PMC_PL3_REF\t\t\t\t68\n#define CFU_REF\t\t\t\t\t69\n#define SPARE_REF\t\t\t\t70\n#define NPI_REF\t\t\t\t\t71\n#define HSM0_REF\t\t\t\t72\n#define HSM1_REF\t\t\t\t73\n#define SD_DLL_REF\t\t\t\t74\n#define FPD_TOP_SWITCH\t\t\t\t75\n#define FPD_LSBUS\t\t\t\t76\n#define ACPU\t\t\t\t\t77\n#define DBG_TRACE\t\t\t\t78\n#define DBG_FPD\t\t\t\t\t79\n#define LPD_TOP_SWITCH\t\t\t\t80\n#define ADMA\t\t\t\t\t81\n#define LPD_LSBUS\t\t\t\t82\n#define CPU_R5\t\t\t\t\t83\n#define CPU_R5_CORE\t\t\t\t84\n#define CPU_R5_OCM\t\t\t\t85\n#define CPU_R5_OCM2\t\t\t\t86\n#define IOU_SWITCH\t\t\t\t87\n#define GEM0_REF\t\t\t\t88\n#define GEM1_REF\t\t\t\t89\n#define GEM_TSU_REF\t\t\t\t90\n#define USB0_BUS_REF\t\t\t\t91\n#define UART0_REF\t\t\t\t92\n#define UART1_REF\t\t\t\t93\n#define SPI0_REF\t\t\t\t94\n#define SPI1_REF\t\t\t\t95\n#define CAN0_REF\t\t\t\t96\n#define CAN1_REF\t\t\t\t97\n#define I2C0_REF\t\t\t\t98\n#define I2C1_REF\t\t\t\t99\n#define DBG_LPD\t\t\t\t\t100\n#define TIMESTAMP_REF\t\t\t\t101\n#define DBG_TSTMP\t\t\t\t102\n#define CPM_TOPSW_REF\t\t\t\t103\n#define USB3_DUAL_REF\t\t\t\t104\n#define OUTCLK_MAX\t\t\t\t105\n#define REF_CLK\t\t\t\t\t106\n#define PL_ALT_REF_CLK\t\t\t\t107\n#define MUXED_IRO\t\t\t\t108\n#define PL_EXT\t\t\t\t\t109\n#define PL_LB\t\t\t\t\t110\n#define MIO_50_OR_51\t\t\t\t111\n#define MIO_24_OR_25\t\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/clock/xlnx-versal-net-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2022, Xilinx Inc.\n * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.\n */\n\n#ifndef _DT_BINDINGS_CLK_VERSAL_NET_H\n#define _DT_BINDINGS_CLK_VERSAL_NET_H\n\n#include \n\n#define GEM0_REF_RX\t0xA9\n#define GEM0_REF_TX\t0xA8\n#define GEM1_REF_RX\t0xA2\n#define GEM1_REF_TX\t0xA1\n#define CAN0_REF_2X\t0x9E\n#define CAN1_REF_2X\t0xAC\n#define FPD_WWDT\t0x96\n#define ACPU_0\t\t0x98\n#define ACPU_1\t\t0x9B\n#define ACPU_2\t\t0x9A\n#define ACPU_3\t\t0x99\n#define I3C0_REF\t0x9D\n#define I3C1_REF\t0x9F\n#define USB1_BUS_REF\t0xAE\n#define LPD_WWDT\t0xAD\n\n/* Remove Versal specific node IDs */\n#undef APU_PLL\n#undef RPU_PLL\n#undef CPM_PLL\n#undef APU_PRESRC\n#undef APU_POSTCLK\n#undef APU_PLL_OUT\n#undef APLL\n#undef RPU_PRESRC\n#undef RPU_POSTCLK\n#undef RPU_PLL_OUT\n#undef RPLL\n#undef CPM_PRESRC\n#undef CPM_POSTCLK\n#undef CPM_PLL_OUT\n#undef CPLL\n#undef APLL_TO_XPD\n#undef RPLL_TO_XPD\n#undef RCLK_PMC\n#undef RCLK_LPD\n#undef WDT\n#undef MUXED_IRO_DIV2\n#undef MUXED_IRO_DIV4\n#undef PSM_REF\n#undef CPM_CORE_REF\n#undef CPM_LSBUS_REF\n#undef CPM_DBG_REF\n#undef CPM_AUX0_REF\n#undef CPM_AUX1_REF\n#undef CPU_R5\n#undef CPU_R5_CORE\n#undef CPU_R5_OCM\n#undef CPU_R5_OCM2\n#undef CAN0_REF\n#undef CAN1_REF\n#undef I2C0_REF\n#undef I2C1_REF\n#undef CPM_TOPSW_REF\n#undef USB3_DUAL_REF\n#undef MUXED_IRO\n#undef PL_EXT\n#undef PL_LB\n#undef MIO_50_OR_51\n#undef MIO_24_OR_25\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Xilinx Zynq MPSoC Firmware layer\n *\n * Copyright (C) 2014-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_ZYNQMP_H\n#define _DT_BINDINGS_CLK_ZYNQMP_H\n\n#define IOPLL\t\t\t0\n#define RPLL\t\t\t1\n#define APLL\t\t\t2\n#define DPLL\t\t\t3\n#define VPLL\t\t\t4\n#define IOPLL_TO_FPD\t\t5\n#define RPLL_TO_FPD\t\t6\n#define APLL_TO_LPD\t\t7\n#define DPLL_TO_LPD\t\t8\n#define VPLL_TO_LPD\t\t9\n#define ACPU\t\t\t10\n#define ACPU_HALF\t\t11\n#define DBF_FPD\t\t\t12\n#define DBF_LPD\t\t\t13\n#define DBG_TRACE\t\t14\n#define DBG_TSTMP\t\t15\n#define DP_VIDEO_REF\t\t16\n#define DP_AUDIO_REF\t\t17\n#define DP_STC_REF\t\t18\n#define GDMA_REF\t\t19\n#define DPDMA_REF\t\t20\n#define DDR_REF\t\t\t21\n#define SATA_REF\t\t22\n#define PCIE_REF\t\t23\n#define GPU_REF\t\t\t24\n#define GPU_PP0_REF\t\t25\n#define GPU_PP1_REF\t\t26\n#define TOPSW_MAIN\t\t27\n#define TOPSW_LSBUS\t\t28\n#define GTGREF0_REF\t\t29\n#define LPD_SWITCH\t\t30\n#define LPD_LSBUS\t\t31\n#define USB0_BUS_REF\t\t32\n#define USB1_BUS_REF\t\t33\n#define USB3_DUAL_REF\t\t34\n#define USB0\t\t\t35\n#define USB1\t\t\t36\n#define CPU_R5\t\t\t37\n#define CPU_R5_CORE\t\t38\n#define CSU_SPB\t\t\t39\n#define CSU_PLL\t\t\t40\n#define PCAP\t\t\t41\n#define IOU_SWITCH\t\t42\n#define GEM_TSU_REF\t\t43\n#define GEM_TSU\t\t\t44\n#define GEM0_TX\t\t\t45\n#define GEM1_TX\t\t\t46\n#define GEM2_TX\t\t\t47\n#define GEM3_TX\t\t\t48\n#define GEM0_RX\t\t\t49\n#define GEM1_RX\t\t\t50\n#define GEM2_RX\t\t\t51\n#define GEM3_RX\t\t\t52\n#define QSPI_REF\t\t53\n#define SDIO0_REF\t\t54\n#define SDIO1_REF\t\t55\n#define UART0_REF\t\t56\n#define UART1_REF\t\t57\n#define SPI0_REF\t\t58\n#define SPI1_REF\t\t59\n#define NAND_REF\t\t60\n#define I2C0_REF\t\t61\n#define I2C1_REF\t\t62\n#define CAN0_REF\t\t63\n#define CAN1_REF\t\t64\n#define CAN0\t\t\t65\n#define CAN1\t\t\t66\n#define DLL_REF\t\t\t67\n#define ADMA_REF\t\t68\n#define TIMESTAMP_REF\t\t69\n#define AMS_REF\t\t\t70\n#define PL0_REF\t\t\t71\n#define PL1_REF\t\t\t72\n#define PL2_REF\t\t\t73\n#define PL3_REF\t\t\t74\n#define WDT\t\t\t75\n#define IOPLL_INT\t\t76\n#define IOPLL_PRE_SRC\t\t77\n#define IOPLL_HALF\t\t78\n#define IOPLL_INT_MUX\t\t79\n#define IOPLL_POST_SRC\t\t80\n#define RPLL_INT\t\t81\n#define RPLL_PRE_SRC\t\t82\n#define RPLL_HALF\t\t83\n#define RPLL_INT_MUX\t\t84\n#define RPLL_POST_SRC\t\t85\n#define APLL_INT\t\t86\n#define APLL_PRE_SRC\t\t87\n#define APLL_HALF\t\t88\n#define APLL_INT_MUX\t\t89\n#define APLL_POST_SRC\t\t90\n#define DPLL_INT\t\t91\n#define DPLL_PRE_SRC\t\t92\n#define DPLL_HALF\t\t93\n#define DPLL_INT_MUX\t\t94\n#define DPLL_POST_SRC\t\t95\n#define VPLL_INT\t\t96\n#define VPLL_PRE_SRC\t\t97\n#define VPLL_HALF\t\t98\n#define VPLL_INT_MUX\t\t99\n#define VPLL_POST_SRC\t\t100\n#define CAN0_MIO\t\t101\n#define CAN1_MIO\t\t102\n#define ACPU_FULL\t\t103\n#define GEM0_REF\t\t104\n#define GEM1_REF\t\t105\n#define GEM2_REF\t\t106\n#define GEM3_REF\t\t107\n#define GEM0_REF_UNG\t\t108\n#define GEM1_REF_UNG\t\t109\n#define GEM2_REF_UNG\t\t110\n#define GEM3_REF_UNG\t\t111\n#define LPD_WDT\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h", "content": "/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */\n/*\n * Copyright 2019 Laurent Pinchart \n */\n\n#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n\n#define ZYNQMP_DPDMA_VIDEO0\t\t0\n#define ZYNQMP_DPDMA_VIDEO1\t\t1\n#define ZYNQMP_DPDMA_VIDEO2\t\t2\n#define ZYNQMP_DPDMA_GRAPHICS\t\t3\n#define ZYNQMP_DPDMA_AUDIO0\t\t4\n#define ZYNQMP_DPDMA_AUDIO1\t\t5\n\n#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/gpio/gpio.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most GPIO bindings.\n *\n * Most GPIO bindings include a flags cell as part of the GPIO specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_GPIO_GPIO_H\n#define _DT_BINDINGS_GPIO_GPIO_H\n\n/* Bit 0 express polarity */\n#define GPIO_ACTIVE_HIGH 0\n#define GPIO_ACTIVE_LOW 1\n\n/* Bit 1 express single-endedness */\n#define GPIO_PUSH_PULL 0\n#define GPIO_SINGLE_ENDED 2\n\n/* Bit 2 express Open drain or open source */\n#define GPIO_LINE_OPEN_SOURCE 0\n#define GPIO_LINE_OPEN_DRAIN 4\n\n/*\n * Open Drain/Collector is the combination of single-ended open drain interface.\n * Open Source/Emitter is the combination of single-ended open source interface.\n */\n#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)\n#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)\n\n/* Bit 3 express GPIO suspend/resume and reset persistence */\n#define GPIO_PERSISTENT 0\n#define GPIO_TRANSITORY 8\n\n/* Bit 4 express pull up */\n#define GPIO_PULL_UP 16\n\n/* Bit 5 express pull down */\n#define GPIO_PULL_DOWN 32\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/input/input.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most input bindings.\n *\n * Most input bindings include key code, matrix key code format.\n * In most cases, key code and matrix key code format uses\n * the standard values/macro defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INPUT_INPUT_H\n#define _DT_BINDINGS_INPUT_INPUT_H\n\n/*\n * Device properties and quirks\n */\n\n#define INPUT_PROP_POINTER\t\t0x00\t/* needs a pointer */\n#define INPUT_PROP_DIRECT\t\t0x01\t/* direct input devices */\n#define INPUT_PROP_BUTTONPAD\t\t0x02\t/* has button(s) under pad */\n#define INPUT_PROP_SEMI_MT\t\t0x03\t/* touch rectangle only */\n#define INPUT_PROP_TOPBUTTONPAD\t\t0x04\t/* softbuttons at top of pad */\n#define INPUT_PROP_POINTING_STICK\t0x05\t/* is a pointing stick */\n#define INPUT_PROP_ACCELEROMETER\t0x06\t/* has accelerometer */\n\n#define INPUT_PROP_MAX\t\t\t0x1f\n#define INPUT_PROP_CNT\t\t\t(INPUT_PROP_MAX + 1)\n\n\n/*\n * Event types\n */\n\n#define EV_SYN\t\t\t0x00\n#define EV_KEY\t\t\t0x01\n#define EV_REL\t\t\t0x02\n#define EV_ABS\t\t\t0x03\n#define EV_MSC\t\t\t0x04\n#define EV_SW\t\t\t0x05\n#define EV_LED\t\t\t0x11\n#define EV_SND\t\t\t0x12\n#define EV_REP\t\t\t0x14\n#define EV_FF\t\t\t0x15\n#define EV_PWR\t\t\t0x16\n#define EV_FF_STATUS\t\t0x17\n#define EV_MAX\t\t\t0x1f\n#define EV_CNT\t\t\t(EV_MAX+1)\n\n/*\n * Synchronization events.\n */\n\n#define SYN_REPORT\t\t0\n#define SYN_CONFIG\t\t1\n#define SYN_MT_REPORT\t\t2\n#define SYN_DROPPED\t\t3\n#define SYN_MAX\t\t\t0xf\n#define SYN_CNT\t\t\t(SYN_MAX+1)\n\n/*\n * Keys and buttons\n *\n * Most of the keys/buttons are modeled after USB HUT 1.12\n * (see http://www.usb.org/developers/hidpage).\n * Abbreviations in the comments:\n * AC - Application Control\n * AL - Application Launch Button\n * SC - System Control\n */\n\n#define KEY_RESERVED\t\t0\n#define KEY_ESC\t\t\t1\n#define KEY_1\t\t\t2\n#define KEY_2\t\t\t3\n#define KEY_3\t\t\t4\n#define KEY_4\t\t\t5\n#define KEY_5\t\t\t6\n#define KEY_6\t\t\t7\n#define KEY_7\t\t\t8\n#define KEY_8\t\t\t9\n#define KEY_9\t\t\t10\n#define KEY_0\t\t\t11\n#define KEY_MINUS\t\t12\n#define KEY_EQUAL\t\t13\n#define KEY_BACKSPACE\t\t14\n#define KEY_TAB\t\t\t15\n#define KEY_Q\t\t\t16\n#define KEY_W\t\t\t17\n#define KEY_E\t\t\t18\n#define KEY_R\t\t\t19\n#define KEY_T\t\t\t20\n#define KEY_Y\t\t\t21\n#define KEY_U\t\t\t22\n#define KEY_I\t\t\t23\n#define KEY_O\t\t\t24\n#define KEY_P\t\t\t25\n#define KEY_LEFTBRACE\t\t26\n#define KEY_RIGHTBRACE\t\t27\n#define KEY_ENTER\t\t28\n#define KEY_LEFTCTRL\t\t29\n#define KEY_A\t\t\t30\n#define KEY_S\t\t\t31\n#define KEY_D\t\t\t32\n#define KEY_F\t\t\t33\n#define KEY_G\t\t\t34\n#define KEY_H\t\t\t35\n#define KEY_J\t\t\t36\n#define KEY_K\t\t\t37\n#define KEY_L\t\t\t38\n#define KEY_SEMICOLON\t\t39\n#define KEY_APOSTROPHE\t\t40\n#define KEY_GRAVE\t\t41\n#define KEY_LEFTSHIFT\t\t42\n#define KEY_BACKSLASH\t\t43\n#define KEY_Z\t\t\t44\n#define KEY_X\t\t\t45\n#define KEY_C\t\t\t46\n#define KEY_V\t\t\t47\n#define KEY_B\t\t\t48\n#define KEY_N\t\t\t49\n#define KEY_M\t\t\t50\n#define KEY_COMMA\t\t51\n#define KEY_DOT\t\t\t52\n#define KEY_SLASH\t\t53\n#define KEY_RIGHTSHIFT\t\t54\n#define KEY_KPASTERISK\t\t55\n#define KEY_LEFTALT\t\t56\n#define KEY_SPACE\t\t57\n#define KEY_CAPSLOCK\t\t58\n#define KEY_F1\t\t\t59\n#define KEY_F2\t\t\t60\n#define KEY_F3\t\t\t61\n#define KEY_F4\t\t\t62\n#define KEY_F5\t\t\t63\n#define KEY_F6\t\t\t64\n#define KEY_F7\t\t\t65\n#define KEY_F8\t\t\t66\n#define KEY_F9\t\t\t67\n#define KEY_F10\t\t\t68\n#define KEY_NUMLOCK\t\t69\n#define KEY_SCROLLLOCK\t\t70\n#define KEY_KP7\t\t\t71\n#define KEY_KP8\t\t\t72\n#define KEY_KP9\t\t\t73\n#define KEY_KPMINUS\t\t74\n#define KEY_KP4\t\t\t75\n#define KEY_KP5\t\t\t76\n#define KEY_KP6\t\t\t77\n#define KEY_KPPLUS\t\t78\n#define KEY_KP1\t\t\t79\n#define KEY_KP2\t\t\t80\n#define KEY_KP3\t\t\t81\n#define KEY_KP0\t\t\t82\n#define KEY_KPDOT\t\t83\n\n#define KEY_ZENKAKUHANKAKU\t85\n#define KEY_102ND\t\t86\n#define KEY_F11\t\t\t87\n#define KEY_F12\t\t\t88\n#define KEY_RO\t\t\t89\n#define KEY_KATAKANA\t\t90\n#define KEY_HIRAGANA\t\t91\n#define KEY_HENKAN\t\t92\n#define KEY_KATAKANAHIRAGANA\t93\n#define KEY_MUHENKAN\t\t94\n#define KEY_KPJPCOMMA\t\t95\n#define KEY_KPENTER\t\t96\n#define KEY_RIGHTCTRL\t\t97\n#define KEY_KPSLASH\t\t98\n#define KEY_SYSRQ\t\t99\n#define KEY_RIGHTALT\t\t100\n#define KEY_LINEFEED\t\t101\n#define KEY_HOME\t\t102\n#define KEY_UP\t\t\t103\n#define KEY_PAGEUP\t\t104\n#define KEY_LEFT\t\t105\n#define KEY_RIGHT\t\t106\n#define KEY_END\t\t\t107\n#define KEY_DOWN\t\t108\n#define KEY_PAGEDOWN\t\t109\n#define KEY_INSERT\t\t110\n#define KEY_DELETE\t\t111\n#define KEY_MACRO\t\t112\n#define KEY_MUTE\t\t113\n#define KEY_VOLUMEDOWN\t\t114\n#define KEY_VOLUMEUP\t\t115\n#define KEY_POWER\t\t116\t/* SC System Power Down */\n#define KEY_KPEQUAL\t\t117\n#define KEY_KPPLUSMINUS\t\t118\n#define KEY_PAUSE\t\t119\n#define KEY_SCALE\t\t120\t/* AL Compiz Scale (Expose) */\n\n#define KEY_KPCOMMA\t\t121\n#define KEY_HANGEUL\t\t122\n#define KEY_HANGUEL\t\tKEY_HANGEUL\n#define KEY_HANJA\t\t123\n#define KEY_YEN\t\t\t124\n#define KEY_LEFTMETA\t\t125\n#define KEY_RIGHTMETA\t\t126\n#define KEY_COMPOSE\t\t127\n#define KEY_STOP\t\t128\t/* AC Stop */\n#define KEY_AGAIN\t\t129\n#define KEY_PROPS\t\t130\t/* AC Properties */\n#define KEY_UNDO\t\t131\t/* AC Undo */\n#define KEY_FRONT\t\t132\n#define KEY_COPY\t\t133\t/* AC Copy */\n#define KEY_OPEN\t\t134\t/* AC Open */\n#define KEY_PASTE\t\t135\t/* AC Paste */\n#define KEY_FIND\t\t136\t/* AC Search */\n#define KEY_CUT\t\t\t137\t/* AC Cut */\n#define KEY_HELP\t\t138\t/* AL Integrated Help Center */\n#define KEY_MENU\t\t139\t/* Menu (show menu) */\n#define KEY_CALC\t\t140\t/* AL Calculator */\n#define KEY_SETUP\t\t141\n#define KEY_SLEEP\t\t142\t/* SC System Sleep */\n#define KEY_WAKEUP\t\t143\t/* System Wake Up */\n#define KEY_FILE\t\t144\t/* AL Local Machine Browser */\n#define KEY_SENDFILE\t\t145\n#define KEY_DELETEFILE\t\t146\n#define KEY_XFER\t\t147\n#define KEY_PROG1\t\t148\n#define KEY_PROG2\t\t149\n#define KEY_WWW\t\t\t150\t/* AL Internet Browser */\n#define KEY_MSDOS\t\t151\n#define KEY_COFFEE\t\t152\t/* AL Terminal Lock/Screensaver */\n#define KEY_SCREENLOCK\t\tKEY_COFFEE\n#define KEY_ROTATE_DISPLAY\t153\t/* Display orientation for e.g. tablets */\n#define KEY_DIRECTION\t\tKEY_ROTATE_DISPLAY\n#define KEY_CYCLEWINDOWS\t154\n#define KEY_MAIL\t\t155\n#define KEY_BOOKMARKS\t\t156\t/* AC Bookmarks */\n#define KEY_COMPUTER\t\t157\n#define KEY_BACK\t\t158\t/* AC Back */\n#define KEY_FORWARD\t\t159\t/* AC Forward */\n#define KEY_CLOSECD\t\t160\n#define KEY_EJECTCD\t\t161\n#define KEY_EJECTCLOSECD\t162\n#define KEY_NEXTSONG\t\t163\n#define KEY_PLAYPAUSE\t\t164\n#define KEY_PREVIOUSSONG\t165\n#define KEY_STOPCD\t\t166\n#define KEY_RECORD\t\t167\n#define KEY_REWIND\t\t168\n#define KEY_PHONE\t\t169\t/* Media Select Telephone */\n#define KEY_ISO\t\t\t170\n#define KEY_CONFIG\t\t171\t/* AL Consumer Control Configuration */\n#define KEY_HOMEPAGE\t\t172\t/* AC Home */\n#define KEY_REFRESH\t\t173\t/* AC Refresh */\n#define KEY_EXIT\t\t174\t/* AC Exit */\n#define KEY_MOVE\t\t175\n#define KEY_EDIT\t\t176\n#define KEY_SCROLLUP\t\t177\n#define KEY_SCROLLDOWN\t\t178\n#define KEY_KPLEFTPAREN\t\t179\n#define KEY_KPRIGHTPAREN\t180\n#define KEY_NEW\t\t\t181\t/* AC New */\n#define KEY_REDO\t\t182\t/* AC Redo/Repeat */\n\n#define KEY_F13\t\t\t183\n#define KEY_F14\t\t\t184\n#define KEY_F15\t\t\t185\n#define KEY_F16\t\t\t186\n#define KEY_F17\t\t\t187\n#define KEY_F18\t\t\t188\n#define KEY_F19\t\t\t189\n#define KEY_F20\t\t\t190\n#define KEY_F21\t\t\t191\n#define KEY_F22\t\t\t192\n#define KEY_F23\t\t\t193\n#define KEY_F24\t\t\t194\n\n#define KEY_PLAYCD\t\t200\n#define KEY_PAUSECD\t\t201\n#define KEY_PROG3\t\t202\n#define KEY_PROG4\t\t203\n#define KEY_DASHBOARD\t\t204\t/* AL Dashboard */\n#define KEY_SUSPEND\t\t205\n#define KEY_CLOSE\t\t206\t/* AC Close */\n#define KEY_PLAY\t\t207\n#define KEY_FASTFORWARD\t\t208\n#define KEY_BASSBOOST\t\t209\n#define KEY_PRINT\t\t210\t/* AC Print */\n#define KEY_HP\t\t\t211\n#define KEY_CAMERA\t\t212\n#define KEY_SOUND\t\t213\n#define KEY_QUESTION\t\t214\n#define KEY_EMAIL\t\t215\n#define KEY_CHAT\t\t216\n#define KEY_SEARCH\t\t217\n#define KEY_CONNECT\t\t218\n#define KEY_FINANCE\t\t219\t/* AL Checkbook/Finance */\n#define KEY_SPORT\t\t220\n#define KEY_SHOP\t\t221\n#define KEY_ALTERASE\t\t222\n#define KEY_CANCEL\t\t223\t/* AC Cancel */\n#define KEY_BRIGHTNESSDOWN\t224\n#define KEY_BRIGHTNESSUP\t225\n#define KEY_MEDIA\t\t226\n\n#define KEY_SWITCHVIDEOMODE\t227\t/* Cycle between available video\n\t\t\t\t\t outputs (Monitor/LCD/TV-out/etc) */\n#define KEY_KBDILLUMTOGGLE\t228\n#define KEY_KBDILLUMDOWN\t229\n#define KEY_KBDILLUMUP\t\t230\n\n#define KEY_SEND\t\t231\t/* AC Send */\n#define KEY_REPLY\t\t232\t/* AC Reply */\n#define KEY_FORWARDMAIL\t\t233\t/* AC Forward Msg */\n#define KEY_SAVE\t\t234\t/* AC Save */\n#define KEY_DOCUMENTS\t\t235\n\n#define KEY_BATTERY\t\t236\n\n#define KEY_BLUETOOTH\t\t237\n#define KEY_WLAN\t\t238\n#define KEY_UWB\t\t\t239\n\n#define KEY_UNKNOWN\t\t240\n#define KEY_VIDEO_NEXT\t\t241\t/* drive next video source */\n#define KEY_VIDEO_PREV\t\t242\t/* drive previous video source */\n#define KEY_BRIGHTNESS_CYCLE\t243\t/* brightness up, after max is min */\n#define KEY_BRIGHTNESS_AUTO\t244\t/* Set Auto Brightness: manual\n\t\t\t\t\t brightness control is off,\n\t\t\t\t\t rely on ambient */\n#define KEY_BRIGHTNESS_ZERO\tKEY_BRIGHTNESS_AUTO\n#define KEY_DISPLAY_OFF\t\t245\t/* display device to off state */\n\n#define KEY_WWAN\t\t246\t/* Wireless WAN (LTE, UMTS, GSM, etc.) */\n#define KEY_WIMAX\t\tKEY_WWAN\n#define KEY_RFKILL\t\t247\t/* Key that controls all radios */\n\n#define KEY_MICMUTE\t\t248\t/* Mute / unmute the microphone */\n\n/* Code 255 is reserved for special needs of AT keyboard driver */\n\n#define BTN_MISC\t\t0x100\n#define BTN_0\t\t\t0x100\n#define BTN_1\t\t\t0x101\n#define BTN_2\t\t\t0x102\n#define BTN_3\t\t\t0x103\n#define BTN_4\t\t\t0x104\n#define BTN_5\t\t\t0x105\n#define BTN_6\t\t\t0x106\n#define BTN_7\t\t\t0x107\n#define BTN_8\t\t\t0x108\n#define BTN_9\t\t\t0x109\n\n#define BTN_MOUSE\t\t0x110\n#define BTN_LEFT\t\t0x110\n#define BTN_RIGHT\t\t0x111\n#define BTN_MIDDLE\t\t0x112\n#define BTN_SIDE\t\t0x113\n#define BTN_EXTRA\t\t0x114\n#define BTN_FORWARD\t\t0x115\n#define BTN_BACK\t\t0x116\n#define BTN_TASK\t\t0x117\n\n#define BTN_JOYSTICK\t\t0x120\n#define BTN_TRIGGER\t\t0x120\n#define BTN_THUMB\t\t0x121\n#define BTN_THUMB2\t\t0x122\n#define BTN_TOP\t\t\t0x123\n#define BTN_TOP2\t\t0x124\n#define BTN_PINKIE\t\t0x125\n#define BTN_BASE\t\t0x126\n#define BTN_BASE2\t\t0x127\n#define BTN_BASE3\t\t0x128\n#define BTN_BASE4\t\t0x129\n#define BTN_BASE5\t\t0x12a\n#define BTN_BASE6\t\t0x12b\n#define BTN_DEAD\t\t0x12f\n\n#define BTN_GAMEPAD\t\t0x130\n#define BTN_SOUTH\t\t0x130\n#define BTN_A\t\t\tBTN_SOUTH\n#define BTN_EAST\t\t0x131\n#define BTN_B\t\t\tBTN_EAST\n#define BTN_C\t\t\t0x132\n#define BTN_NORTH\t\t0x133\n#define BTN_X\t\t\tBTN_NORTH\n#define BTN_WEST\t\t0x134\n#define BTN_Y\t\t\tBTN_WEST\n#define BTN_Z\t\t\t0x135\n#define BTN_TL\t\t\t0x136\n#define BTN_TR\t\t\t0x137\n#define BTN_TL2\t\t\t0x138\n#define BTN_TR2\t\t\t0x139\n#define BTN_SELECT\t\t0x13a\n#define BTN_START\t\t0x13b\n#define BTN_MODE\t\t0x13c\n#define BTN_THUMBL\t\t0x13d\n#define BTN_THUMBR\t\t0x13e\n\n#define BTN_DIGI\t\t0x140\n#define BTN_TOOL_PEN\t\t0x140\n#define BTN_TOOL_RUBBER\t\t0x141\n#define BTN_TOOL_BRUSH\t\t0x142\n#define BTN_TOOL_PENCIL\t\t0x143\n#define BTN_TOOL_AIRBRUSH\t0x144\n#define BTN_TOOL_FINGER\t\t0x145\n#define BTN_TOOL_MOUSE\t\t0x146\n#define BTN_TOOL_LENS\t\t0x147\n#define BTN_TOOL_QUINTTAP\t0x148\t/* Five fingers on trackpad */\n#define BTN_TOUCH\t\t0x14a\n#define BTN_STYLUS\t\t0x14b\n#define BTN_STYLUS2\t\t0x14c\n#define BTN_TOOL_DOUBLETAP\t0x14d\n#define BTN_TOOL_TRIPLETAP\t0x14e\n#define BTN_TOOL_QUADTAP\t0x14f\t/* Four fingers on trackpad */\n\n#define BTN_WHEEL\t\t0x150\n#define BTN_GEAR_DOWN\t\t0x150\n#define BTN_GEAR_UP\t\t0x151\n\n#define KEY_OK\t\t\t0x160\n#define KEY_SELECT\t\t0x161\n#define KEY_GOTO\t\t0x162\n#define KEY_CLEAR\t\t0x163\n#define KEY_POWER2\t\t0x164\n#define KEY_OPTION\t\t0x165\n#define KEY_INFO\t\t0x166\t/* AL OEM Features/Tips/Tutorial */\n#define KEY_TIME\t\t0x167\n#define KEY_VENDOR\t\t0x168\n#define KEY_ARCHIVE\t\t0x169\n#define KEY_PROGRAM\t\t0x16a\t/* Media Select Program Guide */\n#define KEY_CHANNEL\t\t0x16b\n#define KEY_FAVORITES\t\t0x16c\n#define KEY_EPG\t\t\t0x16d\n#define KEY_PVR\t\t\t0x16e\t/* Media Select Home */\n#define KEY_MHP\t\t\t0x16f\n#define KEY_LANGUAGE\t\t0x170\n#define KEY_TITLE\t\t0x171\n#define KEY_SUBTITLE\t\t0x172\n#define KEY_ANGLE\t\t0x173\n#define KEY_ZOOM\t\t0x174\n#define KEY_MODE\t\t0x175\n#define KEY_KEYBOARD\t\t0x176\n#define KEY_SCREEN\t\t0x177\n#define KEY_PC\t\t\t0x178\t/* Media Select Computer */\n#define KEY_TV\t\t\t0x179\t/* Media Select TV */\n#define KEY_TV2\t\t\t0x17a\t/* Media Select Cable */\n#define KEY_VCR\t\t\t0x17b\t/* Media Select VCR */\n#define KEY_VCR2\t\t0x17c\t/* VCR Plus */\n#define KEY_SAT\t\t\t0x17d\t/* Media Select Satellite */\n#define KEY_SAT2\t\t0x17e\n#define KEY_CD\t\t\t0x17f\t/* Media Select CD */\n#define KEY_TAPE\t\t0x180\t/* Media Select Tape */\n#define KEY_RADIO\t\t0x181\n#define KEY_TUNER\t\t0x182\t/* Media Select Tuner */\n#define KEY_PLAYER\t\t0x183\n#define KEY_TEXT\t\t0x184\n#define KEY_DVD\t\t\t0x185\t/* Media Select DVD */\n#define KEY_AUX\t\t\t0x186\n#define KEY_MP3\t\t\t0x187\n#define KEY_AUDIO\t\t0x188\t/* AL Audio Browser */\n#define KEY_VIDEO\t\t0x189\t/* AL Movie Browser */\n#define KEY_DIRECTORY\t\t0x18a\n#define KEY_LIST\t\t0x18b\n#define KEY_MEMO\t\t0x18c\t/* Media Select Messages */\n#define KEY_CALENDAR\t\t0x18d\n#define KEY_RED\t\t\t0x18e\n#define KEY_GREEN\t\t0x18f\n#define KEY_YELLOW\t\t0x190\n#define KEY_BLUE\t\t0x191\n#define KEY_CHANNELUP\t\t0x192\t/* Channel Increment */\n#define KEY_CHANNELDOWN\t\t0x193\t/* Channel Decrement */\n#define KEY_FIRST\t\t0x194\n#define KEY_LAST\t\t0x195\t/* Recall Last */\n#define KEY_AB\t\t\t0x196\n#define KEY_NEXT\t\t0x197\n#define KEY_RESTART\t\t0x198\n#define KEY_SLOW\t\t0x199\n#define KEY_SHUFFLE\t\t0x19a\n#define KEY_BREAK\t\t0x19b\n#define KEY_PREVIOUS\t\t0x19c\n#define KEY_DIGITS\t\t0x19d\n#define KEY_TEEN\t\t0x19e\n#define KEY_TWEN\t\t0x19f\n#define KEY_VIDEOPHONE\t\t0x1a0\t/* Media Select Video Phone */\n#define KEY_GAMES\t\t0x1a1\t/* Media Select Games */\n#define KEY_ZOOMIN\t\t0x1a2\t/* AC Zoom In */\n#define KEY_ZOOMOUT\t\t0x1a3\t/* AC Zoom Out */\n#define KEY_ZOOMRESET\t\t0x1a4\t/* AC Zoom */\n#define KEY_WORDPROCESSOR\t0x1a5\t/* AL Word Processor */\n#define KEY_EDITOR\t\t0x1a6\t/* AL Text Editor */\n#define KEY_SPREADSHEET\t\t0x1a7\t/* AL Spreadsheet */\n#define KEY_GRAPHICSEDITOR\t0x1a8\t/* AL Graphics Editor */\n#define KEY_PRESENTATION\t0x1a9\t/* AL Presentation App */\n#define KEY_DATABASE\t\t0x1aa\t/* AL Database App */\n#define KEY_NEWS\t\t0x1ab\t/* AL Newsreader */\n#define KEY_VOICEMAIL\t\t0x1ac\t/* AL Voicemail */\n#define KEY_ADDRESSBOOK\t\t0x1ad\t/* AL Contacts/Address Book */\n#define KEY_MESSENGER\t\t0x1ae\t/* AL Instant Messaging */\n#define KEY_DISPLAYTOGGLE\t0x1af\t/* Turn display (LCD) on and off */\n#define KEY_BRIGHTNESS_TOGGLE\tKEY_DISPLAYTOGGLE\n#define KEY_SPELLCHECK\t\t0x1b0 /* AL Spell Check */\n#define KEY_LOGOFF\t\t0x1b1 /* AL Logoff */\n\n#define KEY_DOLLAR\t\t0x1b2\n#define KEY_EURO\t\t0x1b3\n\n#define KEY_FRAMEBACK\t\t0x1b4\t/* Consumer - transport controls */\n#define KEY_FRAMEFORWARD\t0x1b5\n#define KEY_CONTEXT_MENU\t0x1b6\t/* GenDesc - system context menu */\n#define KEY_MEDIA_REPEAT\t0x1b7\t/* Consumer - transport control */\n#define KEY_10CHANNELSUP\t0x1b8\t/* 10 channels up (10+) */\n#define KEY_10CHANNELSDOWN\t0x1b9\t/* 10 channels down (10-) */\n#define KEY_IMAGES\t\t0x1ba\t/* AL Image Browser */\n\n#define KEY_DEL_EOL\t\t0x1c0\n#define KEY_DEL_EOS\t\t0x1c1\n#define KEY_INS_LINE\t\t0x1c2\n#define KEY_DEL_LINE\t\t0x1c3\n\n#define KEY_FN\t\t\t0x1d0\n#define KEY_FN_ESC\t\t0x1d1\n#define KEY_FN_F1\t\t0x1d2\n#define KEY_FN_F2\t\t0x1d3\n#define KEY_FN_F3\t\t0x1d4\n#define KEY_FN_F4\t\t0x1d5\n#define KEY_FN_F5\t\t0x1d6\n#define KEY_FN_F6\t\t0x1d7\n#define KEY_FN_F7\t\t0x1d8\n#define KEY_FN_F8\t\t0x1d9\n#define KEY_FN_F9\t\t0x1da\n#define KEY_FN_F10\t\t0x1db\n#define KEY_FN_F11\t\t0x1dc\n#define KEY_FN_F12\t\t0x1dd\n#define KEY_FN_1\t\t0x1de\n#define KEY_FN_2\t\t0x1df\n#define KEY_FN_D\t\t0x1e0\n#define KEY_FN_E\t\t0x1e1\n#define KEY_FN_F\t\t0x1e2\n#define KEY_FN_S\t\t0x1e3\n#define KEY_FN_B\t\t0x1e4\n\n#define KEY_BRL_DOT1\t\t0x1f1\n#define KEY_BRL_DOT2\t\t0x1f2\n#define KEY_BRL_DOT3\t\t0x1f3\n#define KEY_BRL_DOT4\t\t0x1f4\n#define KEY_BRL_DOT5\t\t0x1f5\n#define KEY_BRL_DOT6\t\t0x1f6\n#define KEY_BRL_DOT7\t\t0x1f7\n#define KEY_BRL_DOT8\t\t0x1f8\n#define KEY_BRL_DOT9\t\t0x1f9\n#define KEY_BRL_DOT10\t\t0x1fa\n\n#define KEY_NUMERIC_0\t\t0x200\t/* used by phones, remote controls, */\n#define KEY_NUMERIC_1\t\t0x201\t/* and other keypads */\n#define KEY_NUMERIC_2\t\t0x202\n#define KEY_NUMERIC_3\t\t0x203\n#define KEY_NUMERIC_4\t\t0x204\n#define KEY_NUMERIC_5\t\t0x205\n#define KEY_NUMERIC_6\t\t0x206\n#define KEY_NUMERIC_7\t\t0x207\n#define KEY_NUMERIC_8\t\t0x208\n#define KEY_NUMERIC_9\t\t0x209\n#define KEY_NUMERIC_STAR\t0x20a\n#define KEY_NUMERIC_POUND\t0x20b\n#define KEY_NUMERIC_A\t\t0x20c\t/* Phone key A - HUT Telephony 0xb9 */\n#define KEY_NUMERIC_B\t\t0x20d\n#define KEY_NUMERIC_C\t\t0x20e\n#define KEY_NUMERIC_D\t\t0x20f\n\n#define KEY_CAMERA_FOCUS\t0x210\n#define KEY_WPS_BUTTON\t\t0x211\t/* WiFi Protected Setup key */\n\n#define KEY_TOUCHPAD_TOGGLE\t0x212\t/* Request switch touchpad on or off */\n#define KEY_TOUCHPAD_ON\t\t0x213\n#define KEY_TOUCHPAD_OFF\t0x214\n\n#define KEY_CAMERA_ZOOMIN\t0x215\n#define KEY_CAMERA_ZOOMOUT\t0x216\n#define KEY_CAMERA_UP\t\t0x217\n#define KEY_CAMERA_DOWN\t\t0x218\n#define KEY_CAMERA_LEFT\t\t0x219\n#define KEY_CAMERA_RIGHT\t0x21a\n\n#define KEY_ATTENDANT_ON\t0x21b\n#define KEY_ATTENDANT_OFF\t0x21c\n#define KEY_ATTENDANT_TOGGLE\t0x21d\t/* Attendant call on or off */\n#define KEY_LIGHTS_TOGGLE\t0x21e\t/* Reading light on or off */\n\n#define BTN_DPAD_UP\t\t0x220\n#define BTN_DPAD_DOWN\t\t0x221\n#define BTN_DPAD_LEFT\t\t0x222\n#define BTN_DPAD_RIGHT\t\t0x223\n\n#define KEY_ALS_TOGGLE\t\t0x230\t/* Ambient light sensor */\n\n#define KEY_BUTTONCONFIG\t\t0x240\t/* AL Button Configuration */\n#define KEY_TASKMANAGER\t\t0x241\t/* AL Task/Project Manager */\n#define KEY_JOURNAL\t\t0x242\t/* AL Log/Journal/Timecard */\n#define KEY_CONTROLPANEL\t\t0x243\t/* AL Control Panel */\n#define KEY_APPSELECT\t\t0x244\t/* AL Select Task/Application */\n#define KEY_SCREENSAVER\t\t0x245\t/* AL Screen Saver */\n#define KEY_VOICECOMMAND\t\t0x246\t/* Listening Voice Command */\n\n#define KEY_BRIGHTNESS_MIN\t\t0x250\t/* Set Brightness to Minimum */\n#define KEY_BRIGHTNESS_MAX\t\t0x251\t/* Set Brightness to Maximum */\n\n#define KEY_KBDINPUTASSIST_PREV\t\t0x260\n#define KEY_KBDINPUTASSIST_NEXT\t\t0x261\n#define KEY_KBDINPUTASSIST_PREVGROUP\t\t0x262\n#define KEY_KBDINPUTASSIST_NEXTGROUP\t\t0x263\n#define KEY_KBDINPUTASSIST_ACCEPT\t\t0x264\n#define KEY_KBDINPUTASSIST_CANCEL\t\t0x265\n\n#define BTN_TRIGGER_HAPPY\t\t0x2c0\n#define BTN_TRIGGER_HAPPY1\t\t0x2c0\n#define BTN_TRIGGER_HAPPY2\t\t0x2c1\n#define BTN_TRIGGER_HAPPY3\t\t0x2c2\n#define BTN_TRIGGER_HAPPY4\t\t0x2c3\n#define BTN_TRIGGER_HAPPY5\t\t0x2c4\n#define BTN_TRIGGER_HAPPY6\t\t0x2c5\n#define BTN_TRIGGER_HAPPY7\t\t0x2c6\n#define BTN_TRIGGER_HAPPY8\t\t0x2c7\n#define BTN_TRIGGER_HAPPY9\t\t0x2c8\n#define BTN_TRIGGER_HAPPY10\t\t0x2c9\n#define BTN_TRIGGER_HAPPY11\t\t0x2ca\n#define BTN_TRIGGER_HAPPY12\t\t0x2cb\n#define BTN_TRIGGER_HAPPY13\t\t0x2cc\n#define BTN_TRIGGER_HAPPY14\t\t0x2cd\n#define BTN_TRIGGER_HAPPY15\t\t0x2ce\n#define BTN_TRIGGER_HAPPY16\t\t0x2cf\n#define BTN_TRIGGER_HAPPY17\t\t0x2d0\n#define BTN_TRIGGER_HAPPY18\t\t0x2d1\n#define BTN_TRIGGER_HAPPY19\t\t0x2d2\n#define BTN_TRIGGER_HAPPY20\t\t0x2d3\n#define BTN_TRIGGER_HAPPY21\t\t0x2d4\n#define BTN_TRIGGER_HAPPY22\t\t0x2d5\n#define BTN_TRIGGER_HAPPY23\t\t0x2d6\n#define BTN_TRIGGER_HAPPY24\t\t0x2d7\n#define BTN_TRIGGER_HAPPY25\t\t0x2d8\n#define BTN_TRIGGER_HAPPY26\t\t0x2d9\n#define BTN_TRIGGER_HAPPY27\t\t0x2da\n#define BTN_TRIGGER_HAPPY28\t\t0x2db\n#define BTN_TRIGGER_HAPPY29\t\t0x2dc\n#define BTN_TRIGGER_HAPPY30\t\t0x2dd\n#define BTN_TRIGGER_HAPPY31\t\t0x2de\n#define BTN_TRIGGER_HAPPY32\t\t0x2df\n#define BTN_TRIGGER_HAPPY33\t\t0x2e0\n#define BTN_TRIGGER_HAPPY34\t\t0x2e1\n#define BTN_TRIGGER_HAPPY35\t\t0x2e2\n#define BTN_TRIGGER_HAPPY36\t\t0x2e3\n#define BTN_TRIGGER_HAPPY37\t\t0x2e4\n#define BTN_TRIGGER_HAPPY38\t\t0x2e5\n#define BTN_TRIGGER_HAPPY39\t\t0x2e6\n#define BTN_TRIGGER_HAPPY40\t\t0x2e7\n\n/* We avoid low common keys in module aliases so they don't get huge. */\n#define KEY_MIN_INTERESTING\tKEY_MUTE\n#define KEY_MAX\t\t\t0x2ff\n#define KEY_CNT\t\t\t(KEY_MAX+1)\n\n/*\n * Relative axes\n */\n\n#define REL_X\t\t\t0x00\n#define REL_Y\t\t\t0x01\n#define REL_Z\t\t\t0x02\n#define REL_RX\t\t\t0x03\n#define REL_RY\t\t\t0x04\n#define REL_RZ\t\t\t0x05\n#define REL_HWHEEL\t\t0x06\n#define REL_DIAL\t\t0x07\n#define REL_WHEEL\t\t0x08\n#define REL_MISC\t\t0x09\n#define REL_MAX\t\t\t0x0f\n#define REL_CNT\t\t\t(REL_MAX+1)\n\n/*\n * Absolute axes\n */\n\n#define ABS_X\t\t\t0x00\n#define ABS_Y\t\t\t0x01\n#define ABS_Z\t\t\t0x02\n#define ABS_RX\t\t\t0x03\n#define ABS_RY\t\t\t0x04\n#define ABS_RZ\t\t\t0x05\n#define ABS_THROTTLE\t\t0x06\n#define ABS_RUDDER\t\t0x07\n#define ABS_WHEEL\t\t0x08\n#define ABS_GAS\t\t\t0x09\n#define ABS_BRAKE\t\t0x0a\n#define ABS_HAT0X\t\t0x10\n#define ABS_HAT0Y\t\t0x11\n#define ABS_HAT1X\t\t0x12\n#define ABS_HAT1Y\t\t0x13\n#define ABS_HAT2X\t\t0x14\n#define ABS_HAT2Y\t\t0x15\n#define ABS_HAT3X\t\t0x16\n#define ABS_HAT3Y\t\t0x17\n#define ABS_PRESSURE\t\t0x18\n#define ABS_DISTANCE\t\t0x19\n#define ABS_TILT_X\t\t0x1a\n#define ABS_TILT_Y\t\t0x1b\n#define ABS_TOOL_WIDTH\t\t0x1c\n\n#define ABS_VOLUME\t\t0x20\n\n#define ABS_MISC\t\t0x28\n\n#define ABS_MT_SLOT\t\t0x2f\t/* MT slot being modified */\n#define ABS_MT_TOUCH_MAJOR\t0x30\t/* Major axis of touching ellipse */\n#define ABS_MT_TOUCH_MINOR\t0x31\t/* Minor axis (omit if circular) */\n#define ABS_MT_WIDTH_MAJOR\t0x32\t/* Major axis of approaching ellipse */\n#define ABS_MT_WIDTH_MINOR\t0x33\t/* Minor axis (omit if circular) */\n#define ABS_MT_ORIENTATION\t0x34\t/* Ellipse orientation */\n#define ABS_MT_POSITION_X\t0x35\t/* Center X touch position */\n#define ABS_MT_POSITION_Y\t0x36\t/* Center Y touch position */\n#define ABS_MT_TOOL_TYPE\t0x37\t/* Type of touching device */\n#define ABS_MT_BLOB_ID\t\t0x38\t/* Group a set of packets as a blob */\n#define ABS_MT_TRACKING_ID\t0x39\t/* Unique ID of initiated contact */\n#define ABS_MT_PRESSURE\t\t0x3a\t/* Pressure on contact area */\n#define ABS_MT_DISTANCE\t\t0x3b\t/* Contact hover distance */\n#define ABS_MT_TOOL_X\t\t0x3c\t/* Center X tool position */\n#define ABS_MT_TOOL_Y\t\t0x3d\t/* Center Y tool position */\n\n\n#define ABS_MAX\t\t\t0x3f\n#define ABS_CNT\t\t\t(ABS_MAX+1)\n\n/*\n * Switch events\n */\n\n#define SW_LID\t\t\t0x00 /* set = lid shut */\n#define SW_TABLET_MODE\t\t0x01 /* set = tablet mode */\n#define SW_HEADPHONE_INSERT\t0x02 /* set = inserted */\n#define SW_RFKILL_ALL\t\t0x03 /* rfkill master switch, type \"any\"\n\t\t\t\t\t set = radio enabled */\n#define SW_RADIO\t\tSW_RFKILL_ALL\t/* deprecated */\n#define SW_MICROPHONE_INSERT\t0x04 /* set = inserted */\n#define SW_DOCK\t\t\t0x05 /* set = plugged into dock */\n#define SW_LINEOUT_INSERT\t0x06 /* set = inserted */\n#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */\n#define SW_VIDEOOUT_INSERT\t0x08 /* set = inserted */\n#define SW_CAMERA_LENS_COVER\t0x09 /* set = lens covered */\n#define SW_KEYPAD_SLIDE\t\t0x0a /* set = keypad slide out */\n#define SW_FRONT_PROXIMITY\t0x0b /* set = front proximity sensor active */\n#define SW_ROTATE_LOCK\t\t0x0c /* set = rotate locked/disabled */\n#define SW_LINEIN_INSERT\t0x0d /* set = inserted */\n#define SW_MUTE_DEVICE\t\t0x0e /* set = device disabled */\n#define SW_MAX\t\t\t0x0f\n#define SW_CNT\t\t\t(SW_MAX+1)\n\n/*\n * Misc events\n */\n\n#define MSC_SERIAL\t\t0x00\n#define MSC_PULSELED\t\t0x01\n#define MSC_GESTURE\t\t0x02\n#define MSC_RAW\t\t\t0x03\n#define MSC_SCAN\t\t0x04\n#define MSC_TIMESTAMP\t\t0x05\n#define MSC_MAX\t\t\t0x07\n#define MSC_CNT\t\t\t(MSC_MAX+1)\n\n/*\n * LEDs\n */\n\n#define LED_NUML\t\t0x00\n#define LED_CAPSL\t\t0x01\n#define LED_SCROLLL\t\t0x02\n#define LED_COMPOSE\t\t0x03\n#define LED_KANA\t\t0x04\n#define LED_SLEEP\t\t0x05\n#define LED_SUSPEND\t\t0x06\n#define LED_MUTE\t\t0x07\n#define LED_MISC\t\t0x08\n#define LED_MAIL\t\t0x09\n#define LED_CHARGING\t\t0x0a\n#define LED_MAX\t\t\t0x0f\n#define LED_CNT\t\t\t(LED_MAX+1)\n\n/*\n * Autorepeat values\n */\n\n#define REP_DELAY\t\t0x00\n#define REP_PERIOD\t\t0x01\n#define REP_MAX\t\t\t0x01\n#define REP_CNT\t\t\t(REP_MAX+1)\n\n/*\n * Sounds\n */\n\n#define SND_CLICK\t\t0x00\n#define SND_BELL\t\t0x01\n#define SND_TONE\t\t0x02\n#define SND_MAX\t\t\t0x07\n#define SND_CNT\t\t\t(SND_MAX+1)\n\n#define MATRIX_KEY(row, col, code)\t\\\n\t((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))\n\n#endif /* _DT_BINDINGS_INPUT_INPUT_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/interrupt-controller/irq.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most IRQ bindings.\n *\n * Most IRQ bindings include a flags cell as part of the IRQ specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n\n#define IRQ_TYPE_NONE\t\t0\n#define IRQ_TYPE_EDGE_RISING\t1\n#define IRQ_TYPE_EDGE_FALLING\t2\n#define IRQ_TYPE_EDGE_BOTH\t(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)\n#define IRQ_TYPE_LEVEL_HIGH\t4\n#define IRQ_TYPE_LEVEL_LOW\t8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/net/mscc-phy-vsc8531.h", "content": "/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */\n/*\n * Device Tree constants for Microsemi VSC8531 PHY\n *\n * Author: Nagaraju Lakkaraju\n *\n * Copyright (c) 2017 Microsemi Corporation\n */\n\n#ifndef _DT_BINDINGS_MSCC_VSC8531_H\n#define _DT_BINDINGS_MSCC_VSC8531_H\n\n/* PHY LED Modes */\n#define VSC8531_LINK_ACTIVITY\t\t\t0\n#define VSC8531_LINK_1000_ACTIVITY\t\t1\n#define VSC8531_LINK_100_ACTIVITY\t\t2\n#define VSC8531_LINK_10_ACTIVITY\t\t3\n#define VSC8531_LINK_100_1000_ACTIVITY\t\t4\n#define VSC8531_LINK_10_1000_ACTIVITY\t\t5\n#define VSC8531_LINK_10_100_ACTIVITY\t\t6\n#define VSC8584_LINK_100FX_1000X_ACTIVITY\t7\n#define VSC8531_DUPLEX_COLLISION\t\t8\n#define VSC8531_COLLISION\t\t\t9\n#define VSC8531_ACTIVITY\t\t\t10\n#define VSC8584_100FX_1000X_ACTIVITY\t\t11\n#define VSC8531_AUTONEG_FAULT\t\t\t12\n#define VSC8531_SERIAL_MODE\t\t\t13\n#define VSC8531_FORCE_LED_OFF\t\t\t14\n#define VSC8531_FORCE_LED_ON\t\t\t15\n\n#define VSC8531_RGMII_CLK_DELAY_0_2_NS\t0\n#define VSC8531_RGMII_CLK_DELAY_0_8_NS\t1\n#define VSC8531_RGMII_CLK_DELAY_1_1_NS\t2\n#define VSC8531_RGMII_CLK_DELAY_1_7_NS\t3\n#define VSC8531_RGMII_CLK_DELAY_2_0_NS\t4\n#define VSC8531_RGMII_CLK_DELAY_2_3_NS\t5\n#define VSC8531_RGMII_CLK_DELAY_2_6_NS\t6\n#define VSC8531_RGMII_CLK_DELAY_3_4_NS\t7\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/net/ti-dp83867.h", "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Device Tree constants for the Texas Instruments DP83867 PHY\n *\n * Author: Dan Murphy \n *\n * Copyright: (C) 2015 Texas Instruments, Inc.\n */\n\n#ifndef _DT_BINDINGS_TI_DP83867_H\n#define _DT_BINDINGS_TI_DP83867_H\n\n/* PHY CTRL bits */\n#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB\t0x00\n#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB\t0x01\n#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB\t0x02\n#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB\t0x03\n\n/* RGMIIDCTL internal delay for rx and tx */\n#define\tDP83867_RGMIIDCTL_250_PS\t0x0\n#define\tDP83867_RGMIIDCTL_500_PS\t0x1\n#define\tDP83867_RGMIIDCTL_750_PS\t0x2\n#define\tDP83867_RGMIIDCTL_1_NS\t\t0x3\n#define\tDP83867_RGMIIDCTL_1_25_NS\t0x4\n#define\tDP83867_RGMIIDCTL_1_50_NS\t0x5\n#define\tDP83867_RGMIIDCTL_1_75_NS\t0x6\n#define\tDP83867_RGMIIDCTL_2_00_NS\t0x7\n#define\tDP83867_RGMIIDCTL_2_25_NS\t0x8\n#define\tDP83867_RGMIIDCTL_2_50_NS\t0x9\n#define\tDP83867_RGMIIDCTL_2_75_NS\t0xa\n#define\tDP83867_RGMIIDCTL_3_00_NS\t0xb\n#define\tDP83867_RGMIIDCTL_3_25_NS\t0xc\n#define\tDP83867_RGMIIDCTL_3_50_NS\t0xd\n#define\tDP83867_RGMIIDCTL_3_75_NS\t0xe\n#define\tDP83867_RGMIIDCTL_4_00_NS\t0xf\n\n/* IO_MUX_CFG - Clock output selection */\n#define DP83867_CLK_O_SEL_CHN_A_RCLK\t\t0x0\n#define DP83867_CLK_O_SEL_CHN_B_RCLK\t\t0x1\n#define DP83867_CLK_O_SEL_CHN_C_RCLK\t\t0x2\n#define DP83867_CLK_O_SEL_CHN_D_RCLK\t\t0x3\n#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5\t0x4\n#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5\t0x5\n#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5\t0x6\n#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5\t0x7\n#define DP83867_CLK_O_SEL_CHN_A_TCLK\t\t0x8\n#define DP83867_CLK_O_SEL_CHN_B_TCLK\t\t0x9\n#define DP83867_CLK_O_SEL_CHN_C_TCLK\t\t0xA\n#define DP83867_CLK_O_SEL_CHN_D_TCLK\t\t0xB\n#define DP83867_CLK_O_SEL_REF_CLK\t\t0xC\n/* Special flag to indicate clock should be off */\n#define DP83867_CLK_O_SEL_OFF\t\t\t0xFFFFFFFF\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/phy/phy.h", "content": "/*\n *\n * This header provides constants for the phy framework\n *\n * Copyright (C) 2014 STMicroelectronics\n * Author: Gabriel Fernandez \n * License terms: GNU General Public License (GPL), version 2\n */\n\n#ifndef _DT_BINDINGS_PHY\n#define _DT_BINDINGS_PHY\n\n#define PHY_NONE\t\t0\n#define PHY_TYPE_SATA\t\t1\n#define PHY_TYPE_PCIE\t\t2\n#define PHY_TYPE_USB2\t\t3\n#define PHY_TYPE_USB3\t\t4\n#define PHY_TYPE_UFS\t\t5\n#define PHY_TYPE_DP\t\t6\n#define PHY_TYPE_XPCS\t\t7\n#define PHY_TYPE_SGMII\t\t8\n#define PHY_TYPE_QSGMII\t\t9\n\n#endif /* _DT_BINDINGS_PHY */\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * MIO pin configuration defines for Xilinx ZynqMP\n *\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H\n#define _DT_BINDINGS_PINCTRL_ZYNQMP_H\n\n/* Bit value for different voltage levels */\n#define IO_STANDARD_LVCMOS33\t0\n#define IO_STANDARD_LVCMOS18\t1\n\n/* Bit values for Slew Rates */\n#define SLEW_RATE_FAST\t\t0\n#define SLEW_RATE_SLOW\t\t1\n\n/* Bit values for Pin drive strength */\n#define DRIVE_STRENGTH_2MA\t2\n#define DRIVE_STRENGTH_4MA\t4\n#define DRIVE_STRENGTH_8MA\t8\n#define DRIVE_STRENGTH_12MA\t12\n\n#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/power/xlnx-versal-net-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2022, Xilinx, Inc.\n * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_NET_POWER_H\n#define _DT_BINDINGS_VERSAL_NET_POWER_H\n\n#include \n\n#define PM_DEV_USB_1\t\t\t\t(0x182240D7U)\n#define PM_DEV_FPD_SWDT_0\t\t\t(0x182240DBU)\n#define PM_DEV_FPD_SWDT_1\t\t\t(0x182240DCU)\n#define PM_DEV_FPD_SWDT_2\t\t\t(0x182240DDU)\n#define PM_DEV_FPD_SWDT_3\t\t\t(0x182240DEU)\n#define PM_DEV_TCM_A_0A\t\t\t\t(0x183180CBU)\n#define PM_DEV_TCM_A_0B\t\t\t\t(0x183180CCU)\n#define PM_DEV_TCM_A_0C\t\t\t\t(0x183180CDU)\n#define PM_DEV_RPU_A_0\t\t\t\t(0x181100BFU)\n#define PM_DEV_LPD_SWDT_0\t\t\t(0x182240D9U)\n#define PM_DEV_LPD_SWDT_1\t\t\t(0x182240DAU)\n\n/* Remove Versal specific node IDs */\n#undef PM_DEV_RPU0_0\n#undef PM_DEV_RPU0_1\n#undef PM_DEV_OCM_0\n#undef PM_DEV_OCM_1\n#undef PM_DEV_OCM_2\n#undef PM_DEV_OCM_3\n#undef PM_DEV_TCM_0_A\n#undef PM_DEV_TCM_1_A\n#undef PM_DEV_TCM_0_B\n#undef PM_DEV_TCM_1_B\n#undef PM_DEV_SWDT_FPD\n#undef PM_DEV_AI\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/power/xlnx-versal-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_POWER_H\n#define _DT_BINDINGS_VERSAL_POWER_H\n\n#define PM_DEV_USB_0\t\t\t\t(0x18224018U)\n#define PM_DEV_GEM_0\t\t\t\t(0x18224019U)\n#define PM_DEV_GEM_1\t\t\t\t(0x1822401aU)\n#define PM_DEV_SPI_0\t\t\t\t(0x1822401bU)\n#define PM_DEV_SPI_1\t\t\t\t(0x1822401cU)\n#define PM_DEV_I2C_0\t\t\t\t(0x1822401dU)\n#define PM_DEV_I2C_1\t\t\t\t(0x1822401eU)\n#define PM_DEV_I2C_PMC (0x1822402dU)\n#define PM_DEV_CAN_FD_0\t\t\t\t(0x1822401fU)\n#define PM_DEV_CAN_FD_1\t\t\t\t(0x18224020U)\n#define PM_DEV_UART_0\t\t\t\t(0x18224021U)\n#define PM_DEV_UART_1\t\t\t\t(0x18224022U)\n#define PM_DEV_GPIO\t\t\t\t(0x18224023U)\n#define PM_DEV_TTC_0\t\t\t\t(0x18224024U)\n#define PM_DEV_TTC_1\t\t\t\t(0x18224025U)\n#define PM_DEV_TTC_2\t\t\t\t(0x18224026U)\n#define PM_DEV_TTC_3\t\t\t\t(0x18224027U)\n#define PM_DEV_SWDT_LPD\t\t\t\t(0x18224028U)\n#define PM_DEV_SWDT_FPD\t\t\t\t(0x18224029U)\n#define PM_DEV_OSPI\t\t\t\t(0x1822402aU)\n#define PM_DEV_QSPI\t\t\t\t(0x1822402bU)\n#define PM_DEV_GPIO_PMC\t\t\t\t(0x1822402cU)\n#define PM_DEV_SDIO_0\t\t\t\t(0x1822402eU)\n#define PM_DEV_SDIO_1\t\t\t\t(0x1822402fU)\n#define PM_DEV_RTC\t\t\t\t(0x18224034U)\n#define PM_DEV_ADMA_0\t\t\t\t(0x18224035U)\n#define PM_DEV_ADMA_1\t\t\t\t(0x18224036U)\n#define PM_DEV_ADMA_2\t\t\t\t(0x18224037U)\n#define PM_DEV_ADMA_3\t\t\t\t(0x18224038U)\n#define PM_DEV_ADMA_4\t\t\t\t(0x18224039U)\n#define PM_DEV_ADMA_5\t\t\t\t(0x1822403aU)\n#define PM_DEV_ADMA_6\t\t\t\t(0x1822403bU)\n#define PM_DEV_ADMA_7\t\t\t\t(0x1822403cU)\n#define PM_DEV_AI\t\t\t\t(0x18224072U)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/power/xlnx-versal-regnode.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2022-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_REGNODE_H\n#define _DT_BINDINGS_VERSAL_REGNODE_H\n\n#define PM_REGNODE_SYSMON_ROOT_0\t\t\t(0x18224055U)\n#define PM_REGNODE_SYSMON_ROOT_1\t\t\t(0x18225055U)\n#define PM_REGNODE_SYSMON_ROOT_2\t\t\t(0x18226055U)\n#define PM_REGNODE_SYSMON_ROOT_3\t\t\t(0x18227055U)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/power/xlnx-zynqmp-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_POWER_H\n#define _DT_BINDINGS_ZYNQMP_POWER_H\n\n#define\t\tPD_USB_0\t22\n#define\t\tPD_USB_1\t23\n#define\t\tPD_TTC_0\t24\n#define\t\tPD_TTC_1\t25\n#define\t\tPD_TTC_2\t26\n#define\t\tPD_TTC_3\t27\n#define\t\tPD_SATA\t\t28\n#define\t\tPD_ETH_0\t29\n#define\t\tPD_ETH_1\t30\n#define\t\tPD_ETH_2\t31\n#define\t\tPD_ETH_3\t32\n#define\t\tPD_UART_0\t33\n#define\t\tPD_UART_1\t34\n#define\t\tPD_SPI_0\t35\n#define\t\tPD_SPI_1\t36\n#define\t\tPD_I2C_0\t37\n#define\t\tPD_I2C_1\t38\n#define\t\tPD_SD_0\t\t39\n#define\t\tPD_SD_1\t\t40\n#define\t\tPD_DP\t\t41\n#define\t\tPD_GDMA\t\t42\n#define\t\tPD_ADMA\t\t43\n#define\t\tPD_NAND\t\t44\n#define\t\tPD_QSPI\t\t45\n#define\t\tPD_GPIO\t\t46\n#define\t\tPD_CAN_0\t47\n#define\t\tPD_CAN_1\t48\n#define\t\tPD_GPU\t\t58\n#define\t\tPD_PCIE\t\t59\n#define\t\tPD_PL\t\t69\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/reset/xlnx-versal-net-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H\n#define _DT_BINDINGS_VERSAL_NET_RESETS_H\n\n#include \"xlnx-versal-resets.h\"\n\n#define VERSAL_RST_USB_1\t\t\t(0xC1040C6U)\n\n/* Remove Versal specific reset IDs */\n#undef VERSAL_RST_ACPU_0_POR\n#undef VERSAL_RST_ACPU_1_POR\n#undef VERSAL_RST_OCM2_POR\n#undef VERSAL_RST_APU\n#undef VERSAL_RST_ACPU_0\n#undef VERSAL_RST_ACPU_1\n#undef VERSAL_RST_ACPU_L2\n#undef VERSAL_RST_RPU_ISLAND\n#undef VERSAL_RST_RPU_AMBA\n#undef VERSAL_RST_R5_0\n#undef VERSAL_RST_R5_1\n#undef VERSAL_RST_OCM2_RST\n#undef VERSAL_RST_I2C_PMC\n#undef VERSAL_RST_I2C_0\n#undef VERSAL_RST_I2C_1\n#undef VERSAL_RST_SWDT_FPD\n#undef VERSAL_RST_SWDT_LPD\n#undef VERSAL_RST_USB\n#undef VERSAL_RST_DPC\n#undef VERSAL_RST_DBG_TRACE\n#undef VERSAL_RST_DBG_TSTMP\n#undef VERSAL_RST_RPU0_DBG\n#undef VERSAL_RST_RPU1_DBG\n#undef VERSAL_RST_HSDP\n#undef VERSAL_RST_CPMDBG\n#undef VERSAL_RST_PCIE_CFG\n#undef VERSAL_RST_PCIE_CORE0\n#undef VERSAL_RST_PCIE_CORE1\n#undef VERSAL_RST_PCIE_DMA\n#undef VERSAL_RST_L2_0\n#undef VERSAL_RST_L2_1\n#undef VERSAL_RST_ADDR_REMAP\n#undef VERSAL_RST_CPI0\n#undef VERSAL_RST_CPI1\n#undef VERSAL_RST_XRAM\n#undef VERSAL_RST_AIE_ARRAY\n#undef VERSAL_RST_AIE_SHIM\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/reset/xlnx-versal-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_RESETS_H\n#define _DT_BINDINGS_VERSAL_RESETS_H\n\n#define VERSAL_RST_PMC_POR\t\t\t(0xc30c001U)\n#define VERSAL_RST_PMC\t\t\t\t(0xc410002U)\n#define VERSAL_RST_PS_POR\t\t\t(0xc30c003U)\n#define VERSAL_RST_PL_POR\t\t\t(0xc30c004U)\n#define VERSAL_RST_NOC_POR\t\t\t(0xc30c005U)\n#define VERSAL_RST_FPD_POR\t\t\t(0xc30c006U)\n#define VERSAL_RST_ACPU_0_POR\t\t\t(0xc30c007U)\n#define VERSAL_RST_ACPU_1_POR\t\t\t(0xc30c008U)\n#define VERSAL_RST_OCM2_POR\t\t\t(0xc30c009U)\n#define VERSAL_RST_PS_SRST\t\t\t(0xc41000aU)\n#define VERSAL_RST_PL_SRST\t\t\t(0xc41000bU)\n#define VERSAL_RST_NOC\t\t\t\t(0xc41000cU)\n#define VERSAL_RST_NPI\t\t\t\t(0xc41000dU)\n#define VERSAL_RST_SYS_RST_1\t\t\t(0xc41000eU)\n#define VERSAL_RST_SYS_RST_2\t\t\t(0xc41000fU)\n#define VERSAL_RST_SYS_RST_3\t\t\t(0xc410010U)\n#define VERSAL_RST_FPD\t\t\t\t(0xc410011U)\n#define VERSAL_RST_PL0\t\t\t\t(0xc410012U)\n#define VERSAL_RST_PL1\t\t\t\t(0xc410013U)\n#define VERSAL_RST_PL2\t\t\t\t(0xc410014U)\n#define VERSAL_RST_PL3\t\t\t\t(0xc410015U)\n#define VERSAL_RST_APU\t\t\t\t(0xc410016U)\n#define VERSAL_RST_ACPU_0\t\t\t(0xc410017U)\n#define VERSAL_RST_ACPU_1\t\t\t(0xc410018U)\n#define VERSAL_RST_ACPU_L2\t\t\t(0xc410019U)\n#define VERSAL_RST_ACPU_GIC\t\t\t(0xc41001aU)\n#define VERSAL_RST_RPU_ISLAND\t\t\t(0xc41001bU)\n#define VERSAL_RST_RPU_AMBA\t\t\t(0xc41001cU)\n#define VERSAL_RST_R5_0\t\t\t\t(0xc41001dU)\n#define VERSAL_RST_R5_1\t\t\t\t(0xc41001eU)\n#define VERSAL_RST_SYSMON_PMC_SEQ_RST\t\t(0xc41001fU)\n#define VERSAL_RST_SYSMON_PMC_CFG_RST\t\t(0xc410020U)\n#define VERSAL_RST_SYSMON_FPD_CFG_RST\t\t(0xc410021U)\n#define VERSAL_RST_SYSMON_FPD_SEQ_RST\t\t(0xc410022U)\n#define VERSAL_RST_SYSMON_LPD\t\t\t(0xc410023U)\n#define VERSAL_RST_PDMA_RST1\t\t\t(0xc410024U)\n#define VERSAL_RST_PDMA_RST0\t\t\t(0xc410025U)\n#define VERSAL_RST_ADMA\t\t\t\t(0xc410026U)\n#define VERSAL_RST_TIMESTAMP\t\t\t(0xc410027U)\n#define VERSAL_RST_OCM\t\t\t\t(0xc410028U)\n#define VERSAL_RST_OCM2_RST\t\t\t(0xc410029U)\n#define VERSAL_RST_IPI\t\t\t\t(0xc41002aU)\n#define VERSAL_RST_SBI\t\t\t\t(0xc41002bU)\n#define VERSAL_RST_LPD\t\t\t\t(0xc41002cU)\n#define VERSAL_RST_QSPI\t\t\t\t(0xc10402dU)\n#define VERSAL_RST_OSPI\t\t\t\t(0xc10402eU)\n#define VERSAL_RST_SDIO_0\t\t\t(0xc10402fU)\n#define VERSAL_RST_SDIO_1\t\t\t(0xc104030U)\n#define VERSAL_RST_I2C_PMC\t\t\t(0xc104031U)\n#define VERSAL_RST_GPIO_PMC\t\t\t(0xc104032U)\n#define VERSAL_RST_GEM_0\t\t\t(0xc104033U)\n#define VERSAL_RST_GEM_1\t\t\t(0xc104034U)\n#define VERSAL_RST_SPARE\t\t\t(0xc104035U)\n#define VERSAL_RST_USB_0\t\t\t(0xc104036U)\n#define VERSAL_RST_UART_0\t\t\t(0xc104037U)\n#define VERSAL_RST_UART_1\t\t\t(0xc104038U)\n#define VERSAL_RST_SPI_0\t\t\t(0xc104039U)\n#define VERSAL_RST_SPI_1\t\t\t(0xc10403aU)\n#define VERSAL_RST_CAN_FD_0\t\t\t(0xc10403bU)\n#define VERSAL_RST_CAN_FD_1\t\t\t(0xc10403cU)\n#define VERSAL_RST_I2C_0\t\t\t(0xc10403dU)\n#define VERSAL_RST_I2C_1\t\t\t(0xc10403eU)\n#define VERSAL_RST_GPIO_LPD\t\t\t(0xc10403fU)\n#define VERSAL_RST_TTC_0\t\t\t(0xc104040U)\n#define VERSAL_RST_TTC_1\t\t\t(0xc104041U)\n#define VERSAL_RST_TTC_2\t\t\t(0xc104042U)\n#define VERSAL_RST_TTC_3\t\t\t(0xc104043U)\n#define VERSAL_RST_SWDT_FPD\t\t\t(0xc104044U)\n#define VERSAL_RST_SWDT_LPD\t\t\t(0xc104045U)\n#define VERSAL_RST_USB\t\t\t\t(0xc104046U)\n#define VERSAL_RST_DPC\t\t\t\t(0xc208047U)\n#define VERSAL_RST_PMCDBG\t\t\t(0xc208048U)\n#define VERSAL_RST_DBG_TRACE\t\t\t(0xc208049U)\n#define VERSAL_RST_DBG_FPD\t\t\t(0xc20804aU)\n#define VERSAL_RST_DBG_TSTMP\t\t\t(0xc20804bU)\n#define VERSAL_RST_RPU0_DBG\t\t\t(0xc20804cU)\n#define VERSAL_RST_RPU1_DBG\t\t\t(0xc20804dU)\n#define VERSAL_RST_HSDP\t\t\t\t(0xc20804eU)\n#define VERSAL_RST_DBG_LPD\t\t\t(0xc20804fU)\n#define VERSAL_RST_CPM_POR\t\t\t(0xc30c050U)\n#define VERSAL_RST_CPM\t\t\t\t(0xc410051U)\n#define VERSAL_RST_CPMDBG\t\t\t(0xc208052U)\n#define VERSAL_RST_PCIE_CFG\t\t\t(0xc410053U)\n#define VERSAL_RST_PCIE_CORE0\t\t\t(0xc410054U)\n#define VERSAL_RST_PCIE_CORE1\t\t\t(0xc410055U)\n#define VERSAL_RST_PCIE_DMA\t\t\t(0xc410056U)\n#define VERSAL_RST_CMN\t\t\t\t(0xc410057U)\n#define VERSAL_RST_L2_0\t\t\t\t(0xc410058U)\n#define VERSAL_RST_L2_1\t\t\t\t(0xc410059U)\n#define VERSAL_RST_ADDR_REMAP\t\t\t(0xc41005aU)\n#define VERSAL_RST_CPI0\t\t\t\t(0xc41005bU)\n#define VERSAL_RST_CPI1\t\t\t\t(0xc41005cU)\n#define VERSAL_RST_XRAM\t\t\t\t(0xc30c05dU)\n#define VERSAL_RST_AIE_ARRAY\t\t\t(0xc10405eU)\n#define VERSAL_RST_AIE_SHIM\t\t\t(0xc10405fU)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H\n#define _DT_BINDINGS_ZYNQMP_RESETS_H\n\n#define\t\tZYNQMP_RESET_PCIE_CFG\t\t0\n#define\t\tZYNQMP_RESET_PCIE_BRIDGE\t1\n#define\t\tZYNQMP_RESET_PCIE_CTRL\t\t2\n#define\t\tZYNQMP_RESET_DP\t\t\t3\n#define\t\tZYNQMP_RESET_SWDT_CRF\t\t4\n#define\t\tZYNQMP_RESET_AFI_FM5\t\t5\n#define\t\tZYNQMP_RESET_AFI_FM4\t\t6\n#define\t\tZYNQMP_RESET_AFI_FM3\t\t7\n#define\t\tZYNQMP_RESET_AFI_FM2\t\t8\n#define\t\tZYNQMP_RESET_AFI_FM1\t\t9\n#define\t\tZYNQMP_RESET_AFI_FM0\t\t10\n#define\t\tZYNQMP_RESET_GDMA\t\t11\n#define\t\tZYNQMP_RESET_GPU_PP1\t\t12\n#define\t\tZYNQMP_RESET_GPU_PP0\t\t13\n#define\t\tZYNQMP_RESET_GPU\t\t14\n#define\t\tZYNQMP_RESET_GT\t\t\t15\n#define\t\tZYNQMP_RESET_SATA\t\t16\n#define\t\tZYNQMP_RESET_ACPU3_PWRON\t17\n#define\t\tZYNQMP_RESET_ACPU2_PWRON\t18\n#define\t\tZYNQMP_RESET_ACPU1_PWRON\t19\n#define\t\tZYNQMP_RESET_ACPU0_PWRON\t20\n#define\t\tZYNQMP_RESET_APU_L2\t\t21\n#define\t\tZYNQMP_RESET_ACPU3\t\t22\n#define\t\tZYNQMP_RESET_ACPU2\t\t23\n#define\t\tZYNQMP_RESET_ACPU1\t\t24\n#define\t\tZYNQMP_RESET_ACPU0\t\t25\n#define\t\tZYNQMP_RESET_DDR\t\t26\n#define\t\tZYNQMP_RESET_APM_FPD\t\t27\n#define\t\tZYNQMP_RESET_SOFT\t\t28\n#define\t\tZYNQMP_RESET_GEM0\t\t29\n#define\t\tZYNQMP_RESET_GEM1\t\t30\n#define\t\tZYNQMP_RESET_GEM2\t\t31\n#define\t\tZYNQMP_RESET_GEM3\t\t32\n#define\t\tZYNQMP_RESET_QSPI\t\t33\n#define\t\tZYNQMP_RESET_UART0\t\t34\n#define\t\tZYNQMP_RESET_UART1\t\t35\n#define\t\tZYNQMP_RESET_SPI0\t\t36\n#define\t\tZYNQMP_RESET_SPI1\t\t37\n#define\t\tZYNQMP_RESET_SDIO0\t\t38\n#define\t\tZYNQMP_RESET_SDIO1\t\t39\n#define\t\tZYNQMP_RESET_CAN0\t\t40\n#define\t\tZYNQMP_RESET_CAN1\t\t41\n#define\t\tZYNQMP_RESET_I2C0\t\t42\n#define\t\tZYNQMP_RESET_I2C1\t\t43\n#define\t\tZYNQMP_RESET_TTC0\t\t44\n#define\t\tZYNQMP_RESET_TTC1\t\t45\n#define\t\tZYNQMP_RESET_TTC2\t\t46\n#define\t\tZYNQMP_RESET_TTC3\t\t47\n#define\t\tZYNQMP_RESET_SWDT_CRL\t\t48\n#define\t\tZYNQMP_RESET_NAND\t\t49\n#define\t\tZYNQMP_RESET_ADMA\t\t50\n#define\t\tZYNQMP_RESET_GPIO\t\t51\n#define\t\tZYNQMP_RESET_IOU_CC\t\t52\n#define\t\tZYNQMP_RESET_TIMESTAMP\t\t53\n#define\t\tZYNQMP_RESET_RPU_R50\t\t54\n#define\t\tZYNQMP_RESET_RPU_R51\t\t55\n#define\t\tZYNQMP_RESET_RPU_AMBA\t\t56\n#define\t\tZYNQMP_RESET_OCM\t\t57\n#define\t\tZYNQMP_RESET_RPU_PGE\t\t58\n#define\t\tZYNQMP_RESET_USB0_CORERESET\t59\n#define\t\tZYNQMP_RESET_USB1_CORERESET\t60\n#define\t\tZYNQMP_RESET_USB0_HIBERRESET\t61\n#define\t\tZYNQMP_RESET_USB1_HIBERRESET\t62\n#define\t\tZYNQMP_RESET_USB0_APB\t\t63\n#define\t\tZYNQMP_RESET_USB1_APB\t\t64\n#define\t\tZYNQMP_RESET_IPI\t\t65\n#define\t\tZYNQMP_RESET_APM_LPD\t\t66\n#define\t\tZYNQMP_RESET_RTC\t\t67\n#define\t\tZYNQMP_RESET_SYSMON\t\t68\n#define\t\tZYNQMP_RESET_AFI_FM6\t\t69\n#define\t\tZYNQMP_RESET_LPD_SWDT\t\t70\n#define\t\tZYNQMP_RESET_FPD\t\t71\n#define\t\tZYNQMP_RESET_RPU_DBG1\t\t72\n#define\t\tZYNQMP_RESET_RPU_DBG0\t\t73\n#define\t\tZYNQMP_RESET_DBG_LPD\t\t74\n#define\t\tZYNQMP_RESET_DBG_FPD\t\t75\n#define\t\tZYNQMP_RESET_APLL\t\t76\n#define\t\tZYNQMP_RESET_DPLL\t\t77\n#define\t\tZYNQMP_RESET_VPLL\t\t78\n#define\t\tZYNQMP_RESET_IOPLL\t\t79\n#define\t\tZYNQMP_RESET_RPLL\t\t80\n#define\t\tZYNQMP_RESET_GPO3_PL_0\t\t81\n#define\t\tZYNQMP_RESET_GPO3_PL_1\t\t82\n#define\t\tZYNQMP_RESET_GPO3_PL_2\t\t83\n#define\t\tZYNQMP_RESET_GPO3_PL_3\t\t84\n#define\t\tZYNQMP_RESET_GPO3_PL_4\t\t85\n#define\t\tZYNQMP_RESET_GPO3_PL_5\t\t86\n#define\t\tZYNQMP_RESET_GPO3_PL_6\t\t87\n#define\t\tZYNQMP_RESET_GPO3_PL_7\t\t88\n#define\t\tZYNQMP_RESET_GPO3_PL_8\t\t89\n#define\t\tZYNQMP_RESET_GPO3_PL_9\t\t90\n#define\t\tZYNQMP_RESET_GPO3_PL_10\t\t91\n#define\t\tZYNQMP_RESET_GPO3_PL_11\t\t92\n#define\t\tZYNQMP_RESET_GPO3_PL_12\t\t93\n#define\t\tZYNQMP_RESET_GPO3_PL_13\t\t94\n#define\t\tZYNQMP_RESET_GPO3_PL_14\t\t95\n#define\t\tZYNQMP_RESET_GPO3_PL_15\t\t96\n#define\t\tZYNQMP_RESET_GPO3_PL_16\t\t97\n#define\t\tZYNQMP_RESET_GPO3_PL_17\t\t98\n#define\t\tZYNQMP_RESET_GPO3_PL_18\t\t99\n#define\t\tZYNQMP_RESET_GPO3_PL_19\t\t100\n#define\t\tZYNQMP_RESET_GPO3_PL_20\t\t101\n#define\t\tZYNQMP_RESET_GPO3_PL_21\t\t102\n#define\t\tZYNQMP_RESET_GPO3_PL_22\t\t103\n#define\t\tZYNQMP_RESET_GPO3_PL_23\t\t104\n#define\t\tZYNQMP_RESET_GPO3_PL_24\t\t105\n#define\t\tZYNQMP_RESET_GPO3_PL_25\t\t106\n#define\t\tZYNQMP_RESET_GPO3_PL_26\t\t107\n#define\t\tZYNQMP_RESET_GPO3_PL_27\t\t108\n#define\t\tZYNQMP_RESET_GPO3_PL_28\t\t109\n#define\t\tZYNQMP_RESET_GPO3_PL_29\t\t110\n#define\t\tZYNQMP_RESET_GPO3_PL_30\t\t111\n#define\t\tZYNQMP_RESET_GPO3_PL_31\t\t112\n#define\t\tZYNQMP_RESET_RPU_LS\t\t113\n#define\t\tZYNQMP_RESET_PS_ONLY\t\t114\n#define\t\tZYNQMP_RESET_PL\t\t\t115\n#define\t\tZYNQMP_RESET_PS_PL0\t\t116\n#define\t\tZYNQMP_RESET_PS_PL1\t\t117\n#define\t\tZYNQMP_RESET_PS_PL2\t\t118\n#define\t\tZYNQMP_RESET_PS_PL3\t\t119\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/versal/versal-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-versal-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-power.h\"\n#include \"include/dt-bindings/power/xlnx-versal-regnode.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-resets.h\"\n/ {\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tcan0_clk: can0_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN0_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tcan1_clk: can1_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN1_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tbootph-all;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tbootph-all;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t};\n\t\t\tversal_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,versal-pinctrl\";\n\t\t\t};\n\n\t\t\tversal_sec_cfg: versal-sec-cfg {\n\t\t\t\tcompatible = \"xlnx,versal-sec-cfg\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tbbram_zeroize: bbram-zeroize@4 {\n\t\t\t\t\treg = <0x04 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_key: bbram-key@10 {\n\t\t\t\t\treg = <0x10 0x20>;\n\t\t\t\t};\n\n\t\t\t\tbbram_usr: bbram-usr@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_lock: bbram-lock@48 {\n\t\t\t\t\treg = <0x48 0x4>;\n\t\t\t\t};\n\n\t\t\t\tuser_key0: user-key@110 {\n\t\t\t\t\treg = <0x110 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key1: user-key@130 {\n\t\t\t\t\treg = <0x130 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key2: user-key@150 {\n\t\t\t\t\treg = <0x150 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key3: user-key@170 {\n\t\t\t\t\treg = <0x170 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key4: user-key@190 {\n\t\t\t\t\treg = <0x190 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key5: user-key@1b0 {\n\t\t\t\t\treg = <0x1b0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key6: user-key@1d0 {\n\t\t\t\t\treg = <0x1d0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key7: user-key@1f0 {\n\t\t\t\t\treg = <0x1f0 0x20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk ACPU>;\n};\n\n&can0 {\n\tclocks = <&can0_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_0>;\n};\n\n&can1 {\n\tclocks = <&can1_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_1>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_0>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_1>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk PMC_LSBUS_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO_PMC>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk I2C0_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_0>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk I2C1_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_1>;\n};\n\n&i2c2 {\n\tclocks = <&versal_clk I2C_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_PMC>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_0>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_1>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_2>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_3>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_4>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_5>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_6>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_7>;\n};\n\n&qspi {\n\tclocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_QSPI>;\n};\n\n&ospi {\n\tclocks = <&versal_clk OSPI_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_OSPI>;\n\treset-names = \"qspi\";\n\tresets = <&versal_reset VERSAL_RST_OSPI>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware PM_DEV_RTC>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_0>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_1>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>,\n\t\t<&versal_clk SD_DLL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_0>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>,\n\t\t<&versal_clk SD_DLL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_1>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_0>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_1>;\n};\n\n&ttc0 {\n\tclocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_0>;\n};\n\n&ttc1 {\n\tclocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_1>;\n};\n\n&ttc2 {\n\tclocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_2>;\n};\n\n&ttc3 {\n\tclocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_3>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_USB_0>;\n\tresets = <&versal_reset VERSAL_RST_USB_0>;\n};\n\n&dwc3_0 {\n\tclocks = <&versal_clk USB0_BUS_REF>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk FPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SWDT_FPD>;\n};\n\n&watchdog1 {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SWDT_LPD>;\n};\n\n&sysmon0 {\n\txlnx,nodeid = ;\n};\n\n&sysmon1 {\n\txlnx,nodeid = ;\n};\n\n&sysmon2 {\n\txlnx,nodeid = ;\n};\n\n&sysmon3 {\n\txlnx,nodeid = ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/versal/versal-spp-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\talt_ref_clk: alt_ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware-wip\";\n\t\t\tbootph-all;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tbootph-all;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"alt_ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk 77>;\n};\n\n&can0 {\n\tclocks = <&versal_clk 96>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401f>;\n};\n\n&can1 {\n\tclocks = <&versal_clk 97>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224020>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x18224019>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x1822401a>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk 61>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk 98>;\n\tpower-domains = <&versal_firmware 0x1822401d>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk 99>;\n\tpower-domains = <&versal_firmware 0x1822401e>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224035>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224036>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224037>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224038>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224039>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403a>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403b>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403c>;\n};\n\n&qspi {\n\tclocks = <&versal_clk 57>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402b>;\n};\n\n&ospi {\n\tclocks = <&versal_clk 58>, <&versal_clk 82>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware 0x18224034>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk 92>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224021>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk 93>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224022>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk 59>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402e>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk 60>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402f>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk 94>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401b>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk 95>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401c>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk 91>, <&versal_clk 104>;\n\tpower-domains = <&versal_firmware 0x18224018>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk 82>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/versal/versal.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal\";\n\n\toptions {\n\t\tu-boot {\n\t\t\tcompatible = \"u-boot,config\";\n\t\t\tbootscr-address = /bits/ 64 <0x20000000>;\n\t\t};\n\t};\n\n\tcpus: cpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <1>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: opp-table-cpu {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tbootph-all;\n\t};\n\n\tfpga: fpga {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&versal_fpga>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tpsci: psci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 7 0x304>;\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t};\n\n\tversal_fpga: versal-fpga {\n\t\tcompatible = \"xlnx,versal-fpga\";\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t\tinterrupt-parent = <&gic>;\n\t\tbootph-all;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\t\t\treg = <0 0xf9000000 0 0x80000>, /* GICD */\n\t\t\t <0 0xf9080000 0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\n\t\t\tgic_its: msi-controller@f9020000 {\n\t\t\t\tcompatible = \"arm,gic-v3-its\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tmsi-controller;\n\t\t\t\t#msi-cells = <1>;\n\t\t\t\treg = <0 0xf9020000 0 0x20000>;\n\t\t\t};\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff060000 0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff070000 0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcci: cci@fd000000 {\n\t\t\tcompatible = \"arm,cci-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd000000 0 0x10000>;\n\t\t\tranges = <0 0 0xfd000000 0xa0000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcci_pmu: pmu@10000 {\n\t\t\t\tcompatible = \"arm,cci-500-pmu,r0\";\n\t\t\t\treg = <0x10000 0x90000>;\n\t\t\t\tinterrupts = <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>;\n\t\t\t};\n\t\t};\n\n\t\tlpd_dma_chan0: dma-controller@ffa80000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa80000 0 0x1000>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan1: dma-controller@ffa90000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa90000 0 0x1000>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan2: dma-controller@ffaa0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaa0000 0 0x1000>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\n\t\tlpd_dma_chan3: dma-controller@ffab0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffab0000 0 0x1000>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan4: dma-controller@ffac0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffac0000 0 0x1000>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan5: dma-controller@ffad0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffad0000 0 0x1000>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan6: dma-controller@ffae0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffae0000 0 0x1000>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan7: dma-controller@ffaf0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaf0000 0 0x1000>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tgem0: ethernet@ff0c0000 {\n compatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0c0000 0 0x1000>;\n\t\t\tinterrupts = <0 56 4>, <0 56 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t/* iommus = <&smmu 0x234>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0d0000 {\n compatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0d0000 0 0x1000>;\n\t\t\tinterrupts = <0 58 4>, <0 58 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t/* iommus = <&smmu 0x235>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tgpio0: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0b0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff020000 0 0x1000>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\tclock-frequency = <100000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff030000 0 0x1000>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tclock-frequency = <100000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c2: i2c@f1000000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1000000 0 0x1000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tclock-frequency = <100000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tmc0: memory-controller@f6150000\t{\n\t\t\tcompatible = \"xlnx,versal-ddrmc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;\n\t\t\treg-names = \"base\", \"noc\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t};\n\n\t\tmc1: memory-controller@f62c0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>;\n\t\t\treg-names = \"base\", \"noc\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t};\n\n\t\tmc2: memory-controller@f6430000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>;\n\t\t\treg-names = \"base\", \"noc\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t};\n\n\t\tmc3: memory-controller@f65a0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>;\n\t\t\treg-names = \"base\", \"noc\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tcalibration = <0x7FFF>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff000000 0 0x1000>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tbootph-all;\n\t\t};\n\n\t\tserial1: serial@ff010000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff010000 0 0x1000>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tbootph-all;\n\t\t};\n\n\t\tsmmu: iommu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd800000 0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,trigger-address = <0xC0000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff040000 0 0x1000>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff050000 0 0x1000>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsysmon0: sysmon@f1270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\treg = <0x0 0xf1270000 0x0 0x4000>;\n\t\t\tinterrupts = <0 144 4>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tsysmon1: sysmon@109270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x09270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tsysmon2: sysmon@111270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x11270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tsysmon3: sysmon@119270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x19270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tttc0: timer@ff0e0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff0f0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 40 4>, <0 41 4>, <0 42 4>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff100000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 46 4>, <0 47 4>, <0 48 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tusb0: usb@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff9d0000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_0: usb@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0 0xfe200000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"host\", \"peripheral\", \"otg\", \"wakeup\";\n\t\t\t\tinterrupts = <0 0x16 4>, <0 0x16 4>, <0 0x1a 4>, <0x0 0x4a 0x4>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\tcpm_pciea: pci@fca10000 {\n\t\t\tdevice_type = \"pci\";\n\t\t\t#address-cells = <3>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"xlnx,versal-cpm-host-1.00\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc_0 0>,\n\t\t\t\t\t<0 0 0 2 &pcie_intc_0 1>,\n\t\t\t\t\t<0 0 0 3 &pcie_intc_0 2>,\n\t\t\t\t\t<0 0 0 4 &pcie_intc_0 3>;\n\t\t\tinterrupt-map-mask = <0 0 0 7>;\n\t\t\tinterrupt-names = \"misc\";\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>,\n\t\t\t\t <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>;\n\t\t\tmsi-map = <0x0 &gic_its 0x0 0x10000>;\n\t\t\treg = <0x0 0xfca10000 0x0 0x1000>,\n\t\t\t <0x6 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"cpm_slcr\", \"cfg\";\n\t\t\tpcie_intc_0: interrupt-controller {\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\tinterrupt-controller ;\n\t\t\t};\n\t\t};\n\n\t\tcpm5_pcie: pcie@fcdd0000 {\n\t\t\tdevice_type = \"pci\";\n\t\t\t#address-cells = <3>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"xlnx,versal-cpm5-host\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc_1 0>,\n\t\t\t\t\t<0 0 0 2 &pcie_intc_1 1>,\n\t\t\t\t\t<0 0 0 3 &pcie_intc_1 2>,\n\t\t\t\t\t<0 0 0 4 &pcie_intc_1 3>;\n\t\t\tinterrupt-map-mask = <0 0 0 7>;\n\t\t\tinterrupt-names = \"misc\";\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,\n\t\t\t\t <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;\n\t\t\tmsi-map = <0x0 &gic_its 0x0 0x10000>;\n\t\t\treg = <0x00 0xfcdd0000 0x00 0x1000>,\n\t\t\t <0x06 0x00000000 0x00 0x1000000>,\n\t\t\t <0x00 0xfce20000 0x00 0x1000000>;\n\t\t\treg-names = \"cpm_slcr\", \"cfg\", \"cpm_csr\";\n\t\t\tpcie_intc_1: interrupt-controller {\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\tinterrupt-controller;\n\t\t\t};\n\t\t};\n\n\t\twatchdog: watchdog@fd4d0000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd4d0000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\t\twatchdog1: watchdog@ff120000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff120000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\t\txilsem_edac: edac@f2014050 {\n\t\t\tcompatible = \"xlnx,versal-xilsem-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf2014050 0x0 0xc4>;\n\t\t};\n\t};\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/versal-net/versal-net-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * Copyright (C) 2022, Xilinx, Inc.\n * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/clock/xlnx-versal-net-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-net-power.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tref_clk: ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tcan0_clk: can0-clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_net_clk CAN0_REF_2X>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tcan1_clk: can1-clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_net_clk CAN1_REF_2X>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\", \"xlnx,versal-firmware\";\n\t\t\tbootph-all;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tversal_net_clk: clock-controller {\n\t\t\t\tbootph-all;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-net-clk\", \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tversal_net_power: zynqmp-power { /* untested */\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 57 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tversal_sec_cfg: versal-sec-cfg { /* untested */\n\t\t\t\tcompatible = \"xlnx,versal-sec-cfg\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tbbram_zeroize: bbram-zeroize@4 {\n\t\t\t\t\treg = <0x04 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_key: bbram-key@10 {\n\t\t\t\t\treg = <0x10 0x20>;\n\t\t\t\t};\n\n\t\t\t\tbbram_usr: bbram-usr@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_lock: bbram-lock@48 {\n\t\t\t\t\treg = <0x48 0x4>;\n\t\t\t\t};\n\n\t\t\t\tuser_key0: user-key@110 {\n\t\t\t\t\treg = <0x110 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key1: user-key@130 {\n\t\t\t\t\treg = <0x130 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key2: user-key@150 {\n\t\t\t\t\treg = <0x150 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key3: user-key@170 {\n\t\t\t\t\treg = <0x170 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key4: user-key@190 {\n\t\t\t\t\treg = <0x190 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key5: user-key@1b0 {\n\t\t\t\t\treg = <0x1b0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key6: user-key@1d0 {\n\t\t\t\t\treg = <0x1d0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key7: user-key@1f0 {\n\t\t\t\t\treg = <0x1f0 0x20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp-ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 57 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@eb3f0440 {\n\t\t\treg = <0 0xeb3f0440 0 0x20>,\n\t\t\t <0 0xeb3f0460 0 0x20>,\n\t\t\t <0 0xeb3f0280 0 0x20>,\n\t\t\t <0 0xeb3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu100 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu200 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu300 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu10000 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu10100 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu10200 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu10300 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu20000 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu20100 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu20200 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu20300 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu30000 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&cpu30100 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&cpu30200 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&cpu30300 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&can0 {\n\tclocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>;\n};\n\n&can1 {\n\tclocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>;\n};\n\n&gem0 {\n\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>,\n\t\t <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GEM_0>;\n};\n\n&gem1 {\n\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>,\n\t\t <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GEM_1>;\n};\n\n&gpio0 {\n\tclocks = <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GPIO>;\n};\n\n&gpio1 {\n\tclocks = <&versal_net_clk PMC_LSBUS_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>;\n};\n\n&i2c0 {\n\tclocks = <&versal_net_clk I3C0_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n};\n\n&i2c1 {\n\tclocks = <&versal_net_clk I3C1_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n};\n\n&i3c0 {\n\tclocks = <&versal_net_clk I3C0_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n};\n\n&i3c1 {\n\tclocks = <&versal_net_clk I3C1_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n};\n\n&adma0 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_0>;\n};\n\n&adma1 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_1>;\n};\n\n&adma2 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_2>;\n};\n\n&adma3 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_3>;\n};\n\n&adma4 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_4>;\n};\n\n&adma5 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_5>;\n};\n\n&adma6 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_6>;\n};\n\n&adma7 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_7>;\n};\n\n&qspi {\n\tclocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_QSPI>;\n};\n\n&ospi {\n\tclocks = <&versal_net_clk OSPI_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_OSPI>;\n\tresets = <&versal_net_reset VERSAL_RST_OSPI>;\n};\n\n&rtc {\n\tpower-domains = <&versal_net_firmware PM_DEV_RTC>;\n};\n\n&serial0 {\n\tclocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_UART_0>;\n};\n\n&serial1 {\n\tclocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_UART_1>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>,\n\t\t<&versal_net_clk SD_DLL_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_0>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>,\n\t\t<&versal_net_clk SD_DLL_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_1>;\n};\n\n&spi0 {\n\tclocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SPI_0>;\n};\n\n&spi1 {\n\tclocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SPI_1>;\n};\n\n&ttc0 {\n\tclocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_0>;\n};\n\n&ttc1 {\n\tclocks = <&versal_net_clk TTC1>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_1>;\n};\n\n&ttc2 {\n\tclocks = <&versal_net_clk TTC2>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_2>;\n};\n\n&ttc3 {\n\tclocks = <&versal_net_clk TTC3>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_3>;\n};\n\n&usb0 {\n\tclocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_USB_0>;\n\tresets = <&versal_net_reset VERSAL_RST_USB_0>;\n};\n\n&dwc3_0 {\n\tclocks = <&versal_net_clk USB0_BUS_REF>;\n};\n\n&usb1 {\n\tclocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_USB_1>;\n\tresets = <&versal_net_reset VERSAL_RST_USB_1>;\n};\n\n&dwc3_1 {\n\tclocks = <&versal_net_clk USB1_BUS_REF>;\n};\n\n&wwdt0 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>;\n};\n\n&wwdt1 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>;\n};\n\n&wwdt2 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>;\n};\n\n&wwdt3 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>;\n};\n\n&lpd_wwdt0 {\n\tclocks = <&versal_net_clk LPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_0>;\n};\n\n&lpd_wwdt1 {\n\tclocks = <&versal_net_clk LPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_1>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/versal-net/versal-net-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET fixed clock\n *\n * (C) Copyright 2022-2024, Xilinx, Inc.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tclk60: clk60 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <60000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk150: clk150 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <150000000>;\n\t};\n\n\tclk160: clk160 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <160000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk450: clk450 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <450000000>;\n\t};\n\n\tclk1200: clk1200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <1200000000>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\", \"xlnx,versal-firmware\";\n\t\t\tbootph-all;\n\t\t\tmethod = \"smc\";\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&adma0 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma1 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma2 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma3 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma4 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma5 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma6 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma7 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&can0 {\n\tclocks = <&clk160>, <&clk160>;\n};\n\n&can1 {\n\tclocks = <&clk160>, <&clk160>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;\n};\n\n\n&gpio0 {\n\tclocks = <&clk100>;\n};\n\n&gpio1 {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&i3c0 {\n\tclocks = <&clk100>;\n};\n\n&i3c1 {\n\tclocks = <&clk100>;\n};\n\n&ospi {\n\tclocks = <&clk200>;\n\tresets = <&versal_net_reset VERSAL_RST_OSPI>;\n};\n\n&qspi {\n\tclocks = <&clk300>, <&clk300>;\n};\n\n&rtc {\n\t/* Nothing */\n};\n\n&sdhci0 {\n\tclocks = <&clk200>, <&clk200>, <&clk1200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200>, <&clk200>, <&clk1200>;\n};\n\n&serial0 {\n\tclocks = <&clk100>, <&clk100>;\n\tclock = <1000000>;\n};\n\n&serial1 {\n\tclocks = <&clk100>, <&clk100>;\n\tclock = <100000000>;\n};\n\n&spi0 {\n\tclocks = <&clk200>, <&clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200>, <&clk200>;\n};\n\n&ttc0 {\n\tclocks = <&clk150>;\n};\n\n&usb0 {\n\tclocks = <&clk60>, <&clk60>;\n};\n\n&dwc3_0 {\n\t/* Nothing */\n};\n\n&usb1 {\n\tclocks = <&clk60>, <&clk60>;\n};\n\n&dwc3_1 {\n\t/* Nothing */\n};\n\n&wwdt0 {\n\tclocks = <&clk150>;\n};\n\n&wwdt1 {\n\tclocks = <&clk150>;\n};\n\n&wwdt2 {\n\tclocks = <&clk150>;\n};\n\n&wwdt3 {\n\tclocks = <&clk150>;\n};\n\n&lpd_wwdt0 {\n\tclocks = <&clk150>;\n};\n\n&lpd_wwdt1 {\n\tclocks = <&clk150>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/versal-net/versal-net-ipp-rev1.9.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/clock/xlnx-versal-net-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-net-power.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-net-ipp-1.9\", \"xlnx,versal-net-spp-5.0\", \"xlnx,versal-net-spp\", \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal NET SPP 5.0/IPP 1.9\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t};\n\t};\n\n\tmemory: memory@0 {\n\t\treg = <0 0 0 0x80000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tserial2 = &dcc;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tbootph-all;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tref_clk: ref_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\tbootph-all;\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\", \"xlnx,versal-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tbootph-all;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x01>;\n\n\t\t\tversal_net_clk: clock-controller {\n\t\t\t\tbootph-all;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-net-clk\", \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupts = <0 57 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t<&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tzynqmp-ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupts = <0 57 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@eb3f0440 {\n\t\t\treg = <0 0xeb3f0440 0 0x20>,\n\t\t\t <0 0xeb3f0460 0 0x20>,\n\t\t\t <0 0xeb3f0280 0 0x20>,\n\t\t\t <0 0xeb3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tbootph-all;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tadma0: dma-controller@ebd00000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd00000 0 0x1000>;\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_0>;\n\t\t};\n\n\t\tadma1: dma-controller@ebd10000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd10000 0 0x1000>;\n\t\t\tinterrupts = <0 73 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_1>;\n\t\t};\n\n\t\tadma2: dma-controller@ebd20000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd20000 0 0x1000>;\n\t\t\tinterrupts = <0 74 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_2>;\n\t\t};\n\n\t\tadma3: dma-controller@ebd30000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd30000 0 0x1000>;\n\t\t\tinterrupts = <0 75 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_3>;\n\t\t};\n\n\t\tadma4: dma-controller@ebd40000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd40000 0 0x1000>;\n\t\t\tinterrupts = <0 76 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_4>;\n\t\t};\n\n\t\tadma5: dma-controller@ebd50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd50000 0 0x1000>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_5>;\n\t\t};\n\n\t\tadma6: dma-controller@ebd60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd60000 0 0x1000>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_6>;\n\t\t};\n\n\t\tadma7: dma-controller@ebd70000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd70000 0 0x1000>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_7>;\n\t\t};\n\n\t\tcan0: can@f1980000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1980000 0 0x6000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>;\n\t\t};\n\n\t\tcan1: can@f1990000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1990000 0 0x6000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>;\n\t\t};\n\n\t\tgem0: ethernet@f19e0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19e0000 0 0x1000>;\n\t\t\tinterrupts = <0 39 4>, <0 39 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>,\n\t\t\t\t <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_0>;\n\t\t\tmdio0: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\t\t#phy-cells = <1>;\n\t\t\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t\tti,rx-internal-delay = <11>;\n\t\t\t\t\tti,tx-internal-delay = <10>;\n\t\t\t\t\tti,fifo-depth = <1>;\n\t\t\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgem1: ethernet@f19f0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19f0000 0 0x1000>;\n\t\t\tinterrupts = <0 41 4>, <0 41 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy2>;\n\t\t\tphy-mode = \"rmii\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>,\n\t\t\t\t <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_1>;\n\t\t\tmdio1: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\t\tcompatible = \"ethernet-phy-id0007.0762\"; /* Vitesse VSC8540 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t};\n\n\t\tgpio0: gpio@f19d0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\treg = <0 0xf19d0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO>;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk PMC_LSBUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>;\n\t\t};\n\n\t\ti2c0: i2c@f1940000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1940000 0 0x1000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C0_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@f1950000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1950000 0 0x1000>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C1_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n\t\t};\n\n\t\ti3c: i3c-master@f1948000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\treg = <0 0xf1948000 0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclocks = <&versal_net_clk I2C_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_PMC>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 182 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,trigger-address = <0xc0000000>;\n\t\t\tclocks = <&versal_net_clk OSPI_REF>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_OSPI>;\n\t\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\t\t\tmt35xu02g: flash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tcdns,read-delay = <0>;\n\t\t\t\tcdns,tshsl-ns = <0>;\n\t\t\t\tcdns,tsd2d-ns = <0>;\n\t\t\t\tcdns,tchsh-ns = <1>;\n\t\t\t\tcdns,tslch-ns = <1>;\n\t\t\t\tspi-tx-bus-width = <8>;\n\t\t\t\tspi-rx-bus-width = <8>;\n\t\t\t\tspi-max-frequency = <20000000>;\n\t\t\t\tbroken-flash-reset;\n\t\t\t\tno-wp;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"ospi-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"ospi-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 183 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tnum-cs = <2>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\t\t\tclocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_QSPI>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>, <1>;\n\t\t\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <10000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi0-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"qspi0-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupts = <0 200 4>, <0 201 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 184 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_1>;\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 186 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_0>;\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_UART_0>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tserial1: serial@f1930000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1930000 0 0x1000>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_UART_1>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tsmmu: smmu@ec000000 {\n\t\t\tcompatible = \"arm,smmu-v3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xec000000 0 0x40000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tinterrupt-names = \"combined\";\n\t\t\tinterrupts = <0 169 4>;\n\t\t};\n\n\t\tspi0: spi@f1960000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupts = <0 23 4>;\n\t\t\treg = <0 0xf1960000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_0>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@f1970000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0 0xf1970000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_1>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tttc0: timer@f1dc0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dc0000 0x0 0x1000>;\n\t\t\tclocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_TTC_0>;\n\t\t};\n\n\t\tusb0: usb@f1e00000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0 0xf1e00000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t/* clocks = <&clk60>, <&clk60>; */\n\t\t\tclocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_0>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_0>;\n\n\t\t\tdwc3_0: usb@f1b00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0 0xf1b00000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 29 4>, <0 33 4>, <0 98 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"peripheral\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@f1e10000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0x0 0xf1e10000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tclocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_1>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_1>;\n\n\t\t\tdwc3_1: usb@f1c00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0x0 0xf1c00000 0x0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 34 4>, <0 38 4>, <0 99 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\twwdt0: watchdog@ecc10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecc10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>;\n\t\t};\n\n\t\twwdt1: watchdog@ecd10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecd10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>;\n\t\t};\n\n\t\twwdt2: watchdog@ece10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xece10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>;\n\t\t};\n\n\t\twwdt3: watchdog@ecf10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecf10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/versal-net/versal-net.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * Copyright (C) 2022, Xilinx, Inc.\n * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal NET\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\toptions {\n\t\tu-boot {\n\t\t\tcompatible = \"u-boot,config\";\n\t\t\tbootscr-address = /bits/ 64 <0x20000000>;\n\t\t};\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tcluster2 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu20000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu20100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu20200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu20300>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tcluster3 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu30000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu30100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu30200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu30300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu20000: cpu@20000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20000>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu20100: cpu@20100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20100>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu20200: cpu@20200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20200>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu20300: cpu@20300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20300>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu30000: cpu@30000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30000>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu30100: cpu@30100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30100>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu30200: cpu@30200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30200>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu30300: cpu@30300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30300>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-1066000000 {\n\t\t\topp-hz = /bits/ 64 <1066000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-1866000000 {\n\t\t\topp-hz = /bits/ 64 <1866000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-1900000000 {\n\t\t\topp-hz = /bits/ 64 <1900000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-1999000000 {\n\t\t\topp-hz = /bits/ 64 <1999000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2050000000 {\n\t\t\topp-hz = /bits/ 64 <2050000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2100000000 {\n\t\t\topp-hz = /bits/ 64 <2100000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2200000000 {\n\t\t\topp-hz = /bits/ 64 <2200000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2400000000 {\n\t\t\topp-hz = /bits/ 64 <2400000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n };\n };\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tserial2 = &dcc;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\trtc = &rtc;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t\tspi0 = &ospi;\n\t\tspi1 = &qspi;\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tbootph-all;\n\t};\n\n\tfirmware {\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tfpga: fpga {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&versal_fpga>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tversal_fpga: versal-fpga {\n\t\tcompatible = \"xlnx,versal-fpga\";\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tbootph-all;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tadma0: dma-controller@ebd00000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd00000 0 0x1000>;\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma1: dma-controller@ebd10000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd10000 0 0x1000>;\n\t\t\tinterrupts = <0 73 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma2: dma-controller@ebd20000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd20000 0 0x1000>;\n\t\t\tinterrupts = <0 74 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma3: dma-controller@ebd30000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd30000 0 0x1000>;\n\t\t\tinterrupts = <0 75 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma4: dma-controller@ebd40000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd40000 0 0x1000>;\n\t\t\tinterrupts = <0 76 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma5: dma-controller@ebd50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd50000 0 0x1000>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma6: dma-controller@ebd60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd60000 0 0x1000>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma7: dma-controller@ebd70000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd70000 0 0x1000>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tcan0: can@f1980000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1980000 0 0x6000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t};\n\n\t\tcan1: can@f1990000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1990000 0 0x6000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t};\n\n\t\tgem0: ethernet@f19e0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf19e0000 0 0x1000>;\n\t\t\tinterrupts = <0 39 4>, <0 39 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\",\n\t\t\t \"tsu_clk\";\n\t\t};\n\n\t\tgem1: ethernet@f19f0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf19f0000 0 0x1000>;\n\t\t\tinterrupts = <0 41 4>, <0 41 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\",\n\t\t\t\t \"tsu_clk\";\n\t\t};\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>,\n\t\t\t <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\t\t\tits: msi-controller@e2040000 {\n\t\t\t\tcompatible = \"arm,gic-v3-its\";\n\t\t\t\tmsi-controller;\n\t\t\t\t#msi-cells = <1>;\n\t\t\t\treg = <0 0xe2040000 0 0x20000>;\n\t\t\t};\n\t\t};\n\n\t\tgpio0: gpio@f19d0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf19d0000 0 0x1000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 180 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\ti2c0: i2c@f1940000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1940000 0 0x1000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@f1950000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1950000 0 0x1000>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti3c0: i3c-master@f1948000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1948000 0 0x1000>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t};\n\n\t\ti3c1: i3c-master@f1958000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1958000 0 0x1000>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000>,\n\t\t\t <0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 182 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>; /* u-boot specific */\n\t\t\t/* cdns,is-stig-pgm = <1>; - unused - checking with Sai */\n\t\t\tcdns,trigger-address = <0xc0000000>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1030000 0 0x1000>; /* missing one more reg range - checking with Sai */\n\t\t\tinterrupts = <0 183 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupts = <0 200 4>, <0 201 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 184 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-net-emmc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 186 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tserial1: serial@f1930000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1930000 0 0x1000>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tsmmu: iommu@ec000000 {\n\t\t\tcompatible = \"arm,smmu-v3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xec000000 0 0x40000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tinterrupt-names = \"combined\";\n\t\t\tinterrupts = <0 169 4>;\n\t\t\tdma-coherent;\n\t\t};\n\n\t\tspi0: spi@f1960000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 23 4>;\n\t\t\treg = <0 0xf1960000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t};\n\n\t\tspi1: spi@f1970000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0 0xf1970000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t};\n\n\t\tsysmon0: sysmon@f1270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf1270000 0x0 0x4000>;\n\t\t\tinterrupts = <0 202 4>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tttc0: timer@f1dc0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dc0000 0x0 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f1dd0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 46 4>, <0 47 4>, <0 48 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dd0000 0x0 0x1000>;\n\t\t};\n\n\t\tttc2: timer@f1de0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 49 4>, <0 50 4>, <0 51 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1de0000 0x0 0x1000>;\n\t\t};\n\n\t\tttc3: timer@f1df0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 52 4>, <0 53 4>, <0 54 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1df0000 0x0 0x1000>;\n\t\t};\n\n\t\tusb0: usb@f1e00000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1e00000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_0: usb@f1b00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0 0xf1b00000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"host\", \"peripheral\", \"otg\", \"wakeup\";\n\t\t\t\tinterrupts = <0 29 4>, <0 29 4>, <0 33 4>, <0 98 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"peripheral\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\t/*phy-names = \"usb3-phy\";- checking with Pyiush */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@f1e10000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf1e10000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\tinterrupt-names = \"usb-wakeup\";\n\t\t\tinterrupts = <0 99 4>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_1: usb@f1c00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xf1c00000 0x0 0x10000>;\n\t\t\t\tinterrupt-names = \"host\", \"peripheral\", \"otg\", \"wakeup\";\n\t\t\t\tinterrupts = <0 34 4>, <0 34 4>, <0 38 4>, <0 99 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\t/* phy-names = \"usb3-phy\"; - checking with Pyiush */\n\t\t\t};\n\t\t};\n\n\t\twwdt0: watchdog@ecc10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xecc10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\twwdt1: watchdog@ecd10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xecd10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\twwdt2: watchdog@ece10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xece10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\twwdt3: watchdog@ecf10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xecf10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\tlpd_wwdt0: watchdog@ea420000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xea420000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\tlpd_wwdt1: watchdog@ea430000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xea430000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/zynq/skeleton.dtsi", "content": "/*\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/zynq/zynq-7000.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\toptions {\n\t\tu-boot {\n\t\t\tcompatible = \"u-boot,config\";\n\t\t\tbootscr-address = /bits/ 64 <0x3000000>;\n\t\t};\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-region {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\treplicator {\n\t\tcompatible = \"arm,coresight-static-replicator\";\n\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\tout-ports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\t/* replicator output ports */\n\t\t\tport@0 {\n\t\t\t\treg = <0>;\n\t\t\t\treplicator_out_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&tpiu_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tport@1 {\n\t\t\t\treg = <1>;\n\t\t\t\treplicator_out_port1: endpoint {\n\t\t\t\t\tremote-endpoint = <&etb_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tin-ports {\n\t\t\t/* replicator input port */\n\t\t\tport {\n\t\t\t\treplicator_in_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&funnel_out_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tamba: axi {\n\t\tbootph-all;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocm: sram@fffc0000 {\n\t\t\tcompatible = \"mmio-sram\";\n\t\t\treg = <0xfffc0000 0x10000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n compatible = \"xlnx,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n compatible = \"xlnx,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\", \"arm,primecell\";\n\t\t\treg = <0xe000e000 0x0001000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"apb_pclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */\n\t\t\t\t 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */\n\t\t\t\t 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tnfc0: nand-controller@0,0 {\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0 0 0x1000000>;\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t};\n\t\t\tnor0: flash@1,0 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <1 0 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tsdhci0: mmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: mmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\tbootph-all;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\tbootph-all;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n dmac_s: dma-controller@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n /*\n\t\t\t * interrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t * \"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\t */\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tbootph-all;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\tetb@f8801000 {\n\t\t\tcompatible = \"arm,coresight-etb10\", \"arm,primecell\";\n\t\t\treg = <0xf8801000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\tetb_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ttpiu@f8803000 {\n\t\t\tcompatible = \"arm,coresight-tpiu\", \"arm,primecell\";\n\t\t\treg = <0xf8803000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\ttpiu_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tfunnel@f8804000 {\n\t\t\tcompatible = \"arm,coresight-static-funnel\", \"arm,primecell\";\n\t\t\treg = <0xf8804000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\t\t/* funnel output ports */\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tfunnel_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint =\n\t\t\t\t\t\t\t<&replicator_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tin-ports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\t/* funnel input ports */\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tfunnel0_in_port0: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm0_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tfunnel0_in_port1: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm1_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tfunnel0_in_port2: endpoint {\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t/* The other input ports are not connect to anything */\n\t\t\t};\n\t\t};\n\n\t\tptm@f889c000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889c000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu0>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm0_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889d000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889d000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu1>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm1_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/zynqmp/zynqmp-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-zynqmp-clk.h\"\n\n/ {\n\tpss_ref_clk: pss_ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&zynqmp_firmware {\n\tzynqmp_clk: clock-controller {\n\t\tbootph-all;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,\n\t\t\t <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\",\n\t\t\t \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t};\n};\n\n&can0 {\n\tclocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&can1 {\n\tclocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&cpu0 {\n\tclocks = <&zynqmp_clk ACPU>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gpu {\n\tclocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&nand0 {\n\tclocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gem0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>,\n\t\t <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>;\n\tassigned-clocks = <&zynqmp_clk GEM_TSU>;\n};\n\n&gem1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>,\n\t\t <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>;\n\tassigned-clocks = <&zynqmp_clk GEM_TSU>;\n};\n\n&gem2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>,\n\t\t <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>;\n\tassigned-clocks = <&zynqmp_clk GEM_TSU>;\n};\n\n&gem3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>,\n\t\t <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>;\n\tassigned-clocks = <&zynqmp_clk GEM_TSU>;\n};\n\n&gpio {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&i2c0 {\n\tclocks = <&zynqmp_clk I2C0_REF>;\n};\n\n&i2c1 {\n\tclocks = <&zynqmp_clk I2C1_REF>;\n};\n\n&perf_monitor_ocm {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&perf_monitor_ddr {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_cci {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_lpd {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&pcie {\n\tclocks = <&zynqmp_clk PCIE_REF>;\n};\n\n&qspi {\n\tclocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&sata {\n\tclocks = <&zynqmp_clk SATA_REF>;\n};\n\n&sdhci0 {\n\tclocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;\n\tassigned-clocks = <&zynqmp_clk SDIO0_REF>;\n};\n\n&sdhci1 {\n\tclocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;\n\tassigned-clocks = <&zynqmp_clk SDIO1_REF>;\n};\n\n&spi0 {\n\tclocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&spi1 {\n\tclocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart0 {\n\tclocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart1 {\n\tclocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&usb0 {\n\tclocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n\tassigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&dwc3_0 {\n\tclocks = <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&usb1 {\n\tclocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n\tassigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&dwc3_1 {\n\tclocks = <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&watchdog0 {\n\tclocks = <&zynqmp_clk WDT>;\n};\n\n&lpd_watchdog {\n\tclocks = <&zynqmp_clk LPD_WDT>;\n};\n\n&xilinx_ams {\n\tclocks = <&zynqmp_clk AMS_REF>;\n};\n\n&zynqmp_dpdma {\n\tclocks = <&zynqmp_clk DPDMA_REF>;\n\tassigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */\n};\n\n&zynqmp_dpsub {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>,\n\t\t<&zynqmp_clk DP_AUDIO_REF>,\n\t\t<&zynqmp_clk DP_VIDEO_REF>;\n\tassigned-clocks = <&zynqmp_clk DP_STC_REF>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */\n};\n\n&zynqmp_dp_snd_codec0 {\n\tclocks = <&zynqmp_clk DP_AUDIO_REF>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.1/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n#include \"include/dt-bindings/dma/xlnx-zynqmp-dpdma.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/power/xlnx-zynqmp-power.h\"\n#include \"include/dt-bindings/reset/xlnx-zynqmp-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\toptions {\n\t\tu-boot {\n\t\t\tcompatible = \"u-boot,config\";\n\t\t\tbootscr-address = /bits/ 64 <0x20000000>;\n\t\t};\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tL2: l2-cache {\n\t\t\tcompatible = \"cache\";\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: opp-table-cpu {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tzynqmp_ipi: zynqmp-ipi {\n\t\tbootph-all;\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t\txlnx,ipi-id = <0>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff9905c0 {\n\t\t\tbootph-all;\n\t\t\treg = <0x0 0xff9905c0 0x0 0x20>,\n\t\t\t <0x0 0xff9905e0 0x0 0x20>,\n\t\t\t <0x0 0xff990e80 0x0 0x20>,\n\t\t\t <0x0 0xff990ea0 0x0 0x20>;\n\t\t\treg-names = \"local_request_region\",\n\t\t\t\t \"local_response_region\",\n\t\t\t\t \"remote_request_region\",\n\t\t\t\t \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <4>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tbootph-all;\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t\tinterrupt-affinity = <&cpu0>,\n\t\t\t\t <&cpu1>,\n\t\t\t\t <&cpu2>,\n\t\t\t\t <&cpu3>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tzynqmp_firmware: zynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\tbootph-all;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x1>;\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tbootph-all;\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tsoc-nvmem {\n\t\t\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t\t\tnvmem-layout {\n\t\t\t\t\tcompatible = \"fixed-layout\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tsoc_revision: soc-revision@0 {\n\t\t\t\t\t\treg = <0x0 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\t/* efuse access */\n\t\t\t\t\tefuse_dna: efuse-dna@c {\n\t\t\t\t\t\treg = <0xc 0xc>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr0: efuse-usr0@20 {\n\t\t\t\t\t\treg = <0x20 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr1: efuse-usr1@24 {\n\t\t\t\t\t\treg = <0x24 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr2: efuse-usr2@28 {\n\t\t\t\t\t\treg = <0x28 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr3: efuse-usr3@2c {\n\t\t\t\t\t\treg = <0x2c 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr4: efuse-usr4@30 {\n\t\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr5: efuse-usr5@34 {\n\t\t\t\t\t\treg = <0x34 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr6: efuse-usr6@38 {\n\t\t\t\t\t\treg = <0x38 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr7: efuse-usr7@3c {\n\t\t\t\t\t\treg = <0x3c 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_miscusr: efuse-miscusr@40 {\n\t\t\t\t\t\treg = <0x40 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_chash: efuse-chash@50 {\n\t\t\t\t\t\treg = <0x50 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_pufmisc: efuse-pufmisc@54 {\n\t\t\t\t\t\treg = <0x54 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_sec: efuse-sec@58 {\n\t\t\t\t\t\treg = <0x58 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_spkid: efuse-spkid@5c {\n\t\t\t\t\t\treg = <0x5c 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_aeskey: efuse-aeskey@60 {\n\t\t\t\t\t\treg = <0x60 0x20>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_ppk0hash: efuse-ppk0hash@a0 {\n\t\t\t\t\t\treg = <0xa0 0x30>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_ppk1hash: efuse-ppk1hash@d0 {\n\t\t\t\t\t\treg = <0xd0 0x30>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_pufuser: efuse-pufuser@100 {\n\t\t\t\t\t\treg = <0x100 0x7F>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tzynqmp_pcap: pcap {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t\t\t};\n\n\t\t\tzynqmp_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\tmodepin_gpio: gpio {\n\t\t\t\tcompatible = \"xlnx,zynqmp-gpio-modepin\";\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\n\tfpga_full: fpga-region {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&zynqmp_pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t};\n\n\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tbootph-all;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_CAN0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_CAN1>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma-controller@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma-controller@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma-controller@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma-controller@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma-controller@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma-controller@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma-controller@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma-controller@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x0 0x10000>,\n\t\t\t <0x0 0xf9020000 0x0 0x20000>,\n\t\t\t <0x0 0xf9040000 0x0 0x20000>,\n\t\t\t <0x0 0xf9060000 0x0 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-mali\", \"arm,mali-400\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"gp\", \"gpmmu\", \"pp0\", \"ppmmu0\", \"pp1\", \"ppmmu1\";\n\t\t\tclock-names = \"bus\", \"core\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPU>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma-controller@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma-controller@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma-controller@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma-controller@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma-controller@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma-controller@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma-controller@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma-controller@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand-controller@ff100000 {\n\t\t\tcompatible = \"xlnx,zynqmp-nand-controller\", \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"controller\", \"bus\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_NAND>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_0>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;\n\t\t\treset-names = \"gem0_rst\";\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_1>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;\n\t\t\treset-names = \"gem1_rst\";\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_2>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;\n\t\t\treset-names = \"gem2_rst\";\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_3>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;\n\t\t\treset-names = \"gem3_rst\";\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPIO>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tperf_monitor_ocm: perf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa00000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_ddr: perf-monitor@fd0b0000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd0b0000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <6>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <10>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_cci: perf-monitor@fd490000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd490000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_lpd: perf-monitor@ffa10000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa10000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x10000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tiommus = <&smmu 0x4d0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_PCIE>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_QSPI>;\n\t\t};\n\n\t\tpsgtr: phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\";\n\t\t\t#phy-cells = <4>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x7FFF>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SATA>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SATA>;\n\t\t/*\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;*/\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_0>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"xlnx,zynqmp-uart\", \"cdns,uart-r1p12\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"xlnx,zynqmp-uart\", \"cdns,uart-r1p12\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_1>;\n\t\t};\n\n\t\tusb0: usb@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_0>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\t\t\treset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tranges;\n\n\t\t\tdwc3_0: usb@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"host\", \"peripheral\", \"otg\", \"wakeup\";\n\t\t\t\tinterrupts = <0 65 4>, <0 65 4>, <0 69 4>, <0 75 4>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\tsnps,resume-hs-terminations;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_1>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\n\t\t\tranges;\n\n\t\t\tdwc3_1: usb@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"host\", \"peripheral\", \"otg\", \"wakeup\";\n\t\t\t\tinterrupts = <0 70 4>, <0 70 4>, <0 74 4>, <0 76 4>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\tsnps,resume-hs-terminations;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <60>;\n\t\t\treset-on-timeout;\n\t\t};\n\n\t\tlpd_watchdog: watchdog@ff150000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 52 1>;\n\t\t\treg = <0x0 0xff150000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges = <0 0 0xffa50800 0x800>;\n\n\t\t\tams_ps: ams-ps@0 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams-pl@400 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x400 0x400>;\n\t\t\t};\n\t\t};\n\n\t\tzynqmp_dpdma: dma-controller@fd4c0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tdma-channels = <6>;\n\t\t\tiommus = <&smmu 0xce4>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tzynqmp_dpaud_setting: dp-aud@fd4ac000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpaud-setting\", \"syscon\";\n\t\t\treg = <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t};\n\n\t\tzynqmp_dpsub: display@fd4a0000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>;\n\t\t\treg-names = \"dp\", \"blend\", \"av_buf\";\n\t\t\txlnx,dpaud-reg = <&zynqmp_dpaud_setting>;\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tiommus = <&smmu 0xce3>;\n\t\t\tclock-names = \"dp_apb_clk\", \"dp_aud_clk\", \"dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_DP>;\n\t\t\tdma-names = \"vid0\", \"vid1\", \"vid2\", \"gfx0\";\n\t\t\tdmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;\n\n\t\t\t/* dummy node to to indicate there's no child i2c device */\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0: zynqmp-dp-snd-codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0: zynqmp-dp-snd-pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm0\";\n\t\t\t\tdmas = <&zynqmp_dpdma 4>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1: zynqmp-dp-snd-pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm1\";\n\t\t\t\tdmas = <&zynqmp_dpdma 5>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card0: zynqmp-dp-snd-card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,\n\t\t\t\t\t\t <&zynqmp_dp_snd_pcm1>;\n\t\t\t\txlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/ac701-full.dtsi", "content": "&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/ac701-lite.dtsi", "content": "&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n i2c0 = &i2c1;\n rtc0 = &rtc;\n serial0 = &uart1;\n serial1 = &uart0;\n serial2 = &dcc;\n spi0 = &spi0;\n spi1 = &spi1;\n usb0 = &usb0;\n usb1 = &usb1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2954: ltc2954 { /* U7 */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */\n\t\tkill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n\n\tsi5335_0: si5335_0 { /* clk0_usb - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5335_1: si5335_1 { /* clk1_dp - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 IRQ_TYPE_LEVEL_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO3\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO2\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO1\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n};\n\n&psgtr {\n\t/* usb3, dp */\n\tclocks = <&si5335_0>, <&si5335_1>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n\t/delete-property/ reset-gpios;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"super-speed\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n\treset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/kc705-full.dtsi", "content": "&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/kc705-lite.dtsi", "content": "&iic_main {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&axi_ethernetlite {\n\tphy-handle = <&phy0>;\n\taxi_ethernetlite_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@7 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/kcu105-tmr.dtsi", "content": "&tmr_0_MB1_axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/kcu105.dtsi", "content": "&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/sp701-rev1.0.dtsi", "content": "&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@1 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0x3>;\n\t\t\tti,tx-internal-delay = <0x3>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/vcu118-rev2.0.dtsi", "content": "&axi_ethernet_0 {\n\tphy-handle = <&phy0>;\n\t/delete-property/ pcs-handle ;\n\t/delete-property/ managed ;\n\t/delete-property/ xlnx,switch-x-sgmii ;\n\t/delete-node/ mdio;\n\taxi_ethernet_mdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@3 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\tti,sgmii-ref-clock-output-enable;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\treg = <3>;\n\t\t};\n\t};\n};\n\n&axi_iic_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t};\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-a2197-sc-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller RevA\";\n\tcompatible = \"xlnx,versal-sc-revA\", \"xlnx,versal-sc\", \"xlnx,zynqmp\";\n\n\t/* SC Bank 43\n\tFIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS\n\tSYSCTLR_GPIO0 - 5 - conneced to versal */\n\t/* cpu thermal for MAX6643 fan control */\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tdc38_led {\n\t\t\tlabel = \"ds38-green\"; /* sc AB11 500_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc37_led {\n\t\t\tlabel = \"ds37-green\"; /* sc AD10 501_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t\tdc36_led {\n\t\t\tlabel = \"ds36-green\"; /* sc AD11 502_RBIAS_LED */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */\n\t\t};\n\t};\n};\n\n/* usb - type C - pl\n and micro usb 2.0, gt\n*/\n/* Feb 28/2019 version */\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tbootph-all;\n};\n\n&uart1 { /* uart1 MIO40-41 */\n\tbootph-all;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n/* TODO\nUSB0 MIO52-63\nUSB1 MIO64-75\n*/\n\n/*eth MDIO 76/77\neth reset MIO42\nmarwell m88e1512 - SGMII */\n&gem0 {\n\tphy-handle = <&phy0>;\n\t/* phy-mode = \"sgmii\"; DTG generates this properly */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: phy@21 {\n\t\treg = <21>; /* FIXME */\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5- 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 0 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\"; /* FIXME no linux driver */\n\t\t\t\treg = <0xc0>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <10000000>; /* 10 ohm */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\ti2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* FIXME connection to Samtec J212D */\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t/* FIXME connection to Samtec J53C */\n\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@5d { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@5d { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@5d { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"LPDDR4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-emb-plus-ve2302-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal Embedded+ VE2302 revA\n *\n * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-emb-plus-ve2302-revA\",\n\t\t \"xlnx,versal-emb-plus-ve2302\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal Embedded+ VE2302 revA\";\n\n\tchosen {\n\t\tbootargs = \"earlycon clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\ti2c0 = &i2c0;\n\t};\n\n\t/* For extension board */\n\tonewire {\n\t\tcompatible = \"w1-gpio\";\n\t\tgpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&gpio0 {\n\tgpio-line-names = \"GPIO_LED2\", \"GPIO_LED3\", \"GPIO_LED4\", \"\", \"1WIRE\", /* 0 - 4 */\n\t\t\t\"\", \"FUSA\", \"\", \"EGPIO\", \"AGPIO\", /* 5 - 9 */\n\t\t\t\"I2C0_SCL\", \"I2C0_SDA\", \"\", \"\", \"\", /* 10 - 14 */\n\t\t\t\"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t\t\"\", \"\", \"\", \"\", \"3V3_MON_N\", /* 20 - 24 */\n\t\t\t\"3V3_MON_P\", /* 25, MIO end and EMIO start */\n\t\t\t\"\", \"\", \"\", /* 26 - 29 */\n\t\t\t\"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t\"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t\"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t\"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t\"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t\"\", \"\", \"\"; /* 55 - 57 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-emu-itr8-cn13940875.dtsi", "content": "/ {\n\tcompatible = \"xlnx,versal-emu-itr8\", \"xlnx,versal-emu\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal EMU ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:9600\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n\n\tclk0212: clk0212 {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <212000>;\n\t};\n\n\tclk25: clk25 {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n};\n\n&timer {\n clock-frequency = <440000>;\n};\n\n&serial0 {\n status = \"okay\";\n clocks = <&clk0212 &clk0212>;\n\tcurrent-speed = <9600>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk0212 &clk0212>;\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-net-emu-rev1.9.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tcompatible = \"xlnx,versal-net-emu-1.9\", \"xlnx,versal-net-emu\";\n\tmodel = \"Xilinx Versal NET EMU 1.9\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t};\n\t};\n\n\tmemory: memory@0 {\n\t\treg = <0 0 0 0x10000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 rdinit=/bin/sh\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tfirmware {\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tclk1: clk1 {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <1000000>; /* it doesn't matter on EMU */\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tbootph-all;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&clk1>, <&clk1>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET IPP/SPP OSPI\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-net-ipp-rev1.9.dtsi\"\n\n/ {\n\tmodel = \"Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI\";\n};\n\n&ospi {\n\tstatus = \"okay\";\n};\n\n&qspi {\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-net-ipp-rev1.9.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/clock/xlnx-versal-net-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-net-power.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-net-ipp-1.9\", \"xlnx,versal-net-spp-5.0\", \"xlnx,versal-net-spp\", \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal NET SPP 5.0/IPP 1.9\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t};\n\t};\n\n\tmemory: memory@0 {\n\t\treg = <0 0 0 0x80000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tserail2 = &dcc;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tbootph-all;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tref_clk: ref_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\tbootph-all;\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\", \"xlnx,versal-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tbootph-all;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x01>;\n\n\t\t\tversal_net_clk: clock-controller {\n\t\t\t\tbootph-all;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-net-clk\", \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupts = <0 57 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t<&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tzynqmp-ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupts = <0 57 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@eb3f0440 {\n\t\t\treg = <0 0xeb3f0440 0 0x20>,\n\t\t\t <0 0xeb3f0460 0 0x20>,\n\t\t\t <0 0xeb3f0280 0 0x20>,\n\t\t\t <0 0xeb3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tbootph-all;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tadma0: dma-controller@ebd00000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd00000 0 0x1000>;\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_0>;\n\t\t};\n\n\t\tadma1: dma-controller@ebd10000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd10000 0 0x1000>;\n\t\t\tinterrupts = <0 73 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_1>;\n\t\t};\n\n\t\tadma2: dma-controller@ebd20000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd20000 0 0x1000>;\n\t\t\tinterrupts = <0 74 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_2>;\n\t\t};\n\n\t\tadma3: dma-controller@ebd30000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd30000 0 0x1000>;\n\t\t\tinterrupts = <0 75 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_3>;\n\t\t};\n\n\t\tadma4: dma-controller@ebd40000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd40000 0 0x1000>;\n\t\t\tinterrupts = <0 76 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_4>;\n\t\t};\n\n\t\tadma5: dma-controller@ebd50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd50000 0 0x1000>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_5>;\n\t\t};\n\n\t\tadma6: dma-controller@ebd60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd60000 0 0x1000>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_6>;\n\t\t};\n\n\t\tadma7: dma-controller@ebd70000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd70000 0 0x1000>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_7>;\n\t\t};\n\n\t\tcan0: can@f1980000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1980000 0 0x6000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>;\n\t\t};\n\n\t\tcan1: can@f1990000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1990000 0 0x6000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>;\n\t\t};\n\n\t\tgem0: ethernet@f19e0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19e0000 0 0x1000>;\n\t\t\tinterrupts = <0 39 4>, <0 39 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>,\n\t\t\t\t <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_0>;\n\t\t\tmdio0: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\t\t#phy-cells = <1>;\n\t\t\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t\tti,rx-internal-delay = <11>;\n\t\t\t\t\tti,tx-internal-delay = <10>;\n\t\t\t\t\tti,fifo-depth = <1>;\n\t\t\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgem1: ethernet@f19f0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19f0000 0 0x1000>;\n\t\t\tinterrupts = <0 41 4>, <0 41 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy2>;\n\t\t\tphy-mode = \"rmii\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>,\n\t\t\t\t <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_1>;\n\t\t\tmdio1: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\t\tcompatible = \"ethernet-phy-id0007.0762\"; /* Vitesse VSC8540 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t};\n\n\t\tgpio0: gpio@f19d0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\treg = <0 0xf19d0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO>;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk PMC_LSBUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>;\n\t\t};\n\n\t\ti2c0: i2c@f1940000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1940000 0 0x1000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C0_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@f1950000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1950000 0 0x1000>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C1_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n\t\t};\n\n\t\ti3c: i3c-master@f1948000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\treg = <0 0xf1948000 0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclocks = <&versal_net_clk I2C_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_PMC>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 182 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,trigger-address = <0xc0000000>;\n\t\t\tclocks = <&versal_net_clk OSPI_REF>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_OSPI>;\n\n\t\t\tmt35xu02g: flash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tcdns,read-delay = <0>;\n\t\t\t\tcdns,tshsl-ns = <0>;\n\t\t\t\tcdns,tsd2d-ns = <0>;\n\t\t\t\tcdns,tchsh-ns = <1>;\n\t\t\t\tcdns,tslch-ns = <1>;\n\t\t\t\tspi-tx-bus-width = <8>;\n\t\t\t\tspi-rx-bus-width = <8>;\n\t\t\t\tspi-max-frequency = <20000000>;\n\t\t\t\tbroken-flash-reset;\n\t\t\t\tno-wp;\n\t\t\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"ospi-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"ospi-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 183 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tnum-cs = <2>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\t\t\tclocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_QSPI>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>, <1>;\n\t\t\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <10000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi0-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"qspi0-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupts = <0 200 4>, <0 201 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 184 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_1>;\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 186 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_0>;\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_UART_0>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tserial1: serial@f1930000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1930000 0 0x1000>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_UART_1>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tsmmu: smmu@ec000000 {\n\t\t\tcompatible = \"arm,smmu-v3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xec000000 0 0x40000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tinterrupt-names = \"combined\";\n\t\t\tinterrupts = <0 169 4>;\n\t\t};\n\n\t\tspi0: spi@f1960000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupts = <0 23 4>;\n\t\t\treg = <0 0xf1960000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_0>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@f1970000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0 0xf1970000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_1>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tttc0: timer@f1dc0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dc0000 0x0 0x1000>;\n\t\t\tclocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_TTC_0>;\n\t\t};\n\n\t\tusb0: usb@f1e00000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0 0xf1e00000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t/* clocks = <&clk60>, <&clk60>; */\n\t\t\tclocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_0>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_0>;\n\n\t\t\tdwc3_0: usb@f1b00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0 0xf1b00000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"host\", \"peripheral\", \"otg\", \"wakeup\";\n\t\t\t\tinterrupts = <0 29 4>, <0 29 4>, <0 33 4>, <0 98 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"peripheral\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@f1e10000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0x0 0xf1e10000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tclocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_1>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_1>;\n\n\t\t\tdwc3_1: usb@f1c00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0x0 0xf1c00000 0x0 0x10000>;\n\t\t\t\tinterrupt-names = \"host\", \"peripheral\", \"otg\", \"wakeup\";\n\t\t\t\tinterrupts = <0 34 4>, <0 34 4>, <0 38 4>, <0 99 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\twwdt0: watchdog@ecc10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecc10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>;\n\t\t};\n\n\t\twwdt1: watchdog@ecd10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecd10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>;\n\t\t};\n\n\t\twwdt2: watchdog@ece10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xece10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>;\n\t\t};\n\n\t\twwdt3: watchdog@ecf10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecf10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-net-vn-p-b2197-00-reva-pl.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VN-P-B2197 (Tenzing2)\n *\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n\ti2c-mux@70 {\n\t\tcompatible = \"nxp,pca9545\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x70>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tqsfp56g_0: gpio@20 { /* u118 */\n\t\t\t\tcompatible = \"ti,tca6408\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"QSFP56G_0_OC_B\", \"QSFP56G_0_PWR_EN\", /* 0, 1 */\n\t\t\t\t\t\t\"QSFP56G_0_LED_1\", \"QSFP56G_0_LED_0\", /* 2, 3 */\n\t\t\t\t\t\t\"QSFP56G_0_MODPRS_B\", \"QSFP56G_0_LPMODE\", /* 4, 5 */\n\t\t\t\t\t\t\"QSFP56G_0_RESET_B\", \"QSFP56G_0_MODSEL_B\"; /* 6, 7 */\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tqsfp56g_1: gpio@20 { /* u117 */\n\t\t\t\tcompatible = \"ti,tca6408\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"QSFP56G_1_OC_B\", \"QSFP56G_1_PWR_EN\", /* 0, 1 */\n\t\t\t\t\t\t\"QSFP56G_1_LED_1\", \"QSFP56G_1_LED_0\", /* 2, 3 */\n\t\t\t\t\t\t\"QSFP56G_1_MODPRS_B\", \"QSFP56G_1_LPMODE\", /* 4, 5 */\n\t\t\t\t\t\t\"QSFP56G_1_RESET_B\", \"QSFP56G_1_MODSEL_B\"; /* 6, 7 */\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* J48 connector */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* J47 connector */\n\t\t};\n\t};\n/*\n\tGPIO_DIP_SW0-1\n\tGPIO_LED0-1\n\tGPIO_PB0-1\n\tGPIO_SMA\n\n*/\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-net-vn-p-b2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2)\n *\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n\n/ {\n\tcompatible = \"xlnx,versal-net-vn-p-b2197-00-revA\",\n\t\t \"xlnx,versal-net-vn-p-b2197-00\", \"xlnx,versal-net\";\n};\n\n&i2c0 {\n\t/* Access via J70/J71 or J82/J83 */\n\tclock-frequency = <100000>;\n};\n\n&i2c1 {\n\t/* Access via J70/J71 or J82/J83 */\n\t/* By default this bus should have eeprom for board identification at 0x54 */\n\t/* SE/X-PRC card identification is also on this bus at 0x52 */\n\tclock-frequency = <100000>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-net-vn-x-b2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal Net VNX board\n *\n * (C) Copyright 2022, Xilinx, Inc.\n * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-net-vn-x-b2197-00-revA\",\n\t\t \"xlnx,versal-net-vn-x-b2197-00\", \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal Net VNX\";\n\n\taliases {\n\t\tnvmem0 = &eeprom0;\n\t};\n};\n\n&adma0 {\n\tstatus = \"okay\";\n};\n\n&adma1 {\n\tstatus = \"okay\";\n};\n\n&adma2 {\n\tstatus = \"okay\";\n};\n\n&adma3 {\n\tstatus = \"okay\";\n};\n\n&adma4 {\n\tstatus = \"okay\";\n};\n\n&adma5 {\n\tstatus = \"okay\";\n};\n\n&adma6 {\n\tstatus = \"okay\";\n};\n\n&adma7 {\n\tstatus = \"okay\";\n};\n\n&lpd_wwdt0 {\n\tstatus = \"okay\";\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tphy-handle = <&phy>;\n\tphy-mode = \"rmii\";\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy: ethernet-phy {\n\t\t\treg = <4>;\n\t\t};\n\t};\n};\n\n&gpio0 {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\teeprom0: eeprom@51 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t\tbootph-all;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\teeprom1: eeprom@55 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x55>;\n\t\tbootph-all;\n\t};\n};\n\n&ospi {\n\tstatus = \"okay\";\n\tis-dual = <0>;\n\tis-stacked = <1>;\n\treset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n\treset-names = \"qspi\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tmt35xu02g: flash@0 {\n\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <5000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"ospi-flash0\";\n\t\t\t\treg = <0 0x8000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\tno-1-8-v;\n};\n\n&serial0 {\n\tstatus = \"okay\";\n};\n\n&serial1 {\n\tstatus = \"okay\";\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tnum-cs = <3>;\n};\n\n&usb1 {\n\tstatus = \"okay\";\n};\n\n&dwc3_1 {\n\tstatus = \"okay\";\n\tsnps,refclk_fladj;\n\tsnps,mask_phy_reset;\n\tphy-names = \"usb3-phy\";\n};\n\n&wwdt0 {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-spp-itr8-cn13940875.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-spp-itr8-cn13940875\", \"xlnx,versal-spp-itr8\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal SPP ITR8 HW 4.0\";\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &ospi;\n\t\tspi2 = &spi0;\n\t\tspi3 = &spi1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tusb0 = &usb0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>;\n\t};\n\tchosen {\n\t\tbootargs = \"rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tclk25: clk25 {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n};\n\n&timer {\n\tclock-frequency = <2720000>;\n};\n\n&serial0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n};\n\n&lpd_dma_chan0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan2 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan3 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan4 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan5 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan6 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&lpd_dma_chan7 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n};\n\n&dwc3_0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n\tmaximum-speed = \"high-speed\";\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n phy0: phy@0 {\n\t\treg = <0x0>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125 &clk125 &clk125>;\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n phy1: phy@1 {\n\t\treg = <0x1>;\n\t\tmax-speed = <100>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tclocks = <&clk25 &clk25>;\n\txlnx,mio_bank = <0>;\n};\n\n&qspi {\n\tstatus = \"okay\";\n\tnum-cs = <0x1>;\n\treg = <0x0 0xf1030000 0x0 0x1000>;\n\tclocks = <&clk125 &clk125>;\n\tis-dual = <1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot-boot.bin\";\n\t\t\t\treg = <0x0 0x6400000>;\n\t\t\t};\n\t\t\tpartition@6400000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x6400000 0x500000>;\n\t\t\t};\n\t\t\tpartition@6900000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x6900000 0x20000>;\n\t\t\t};\n\t\t\tpartition@6920000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x6920000 0x5E0000>;\n\t\t\t};\n\t\t\tpartition@7f40000 {\n\t\t\t\tlabel = \"qspi-bootenv\";\n\t\t\t\treg = <0x7f40000 0x40000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ospi {\n\tstatus = \"disabled\";\n\tclocks = <&clk125 &clk125>;\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\tcdns,fifo-depth = <508>;\n\tcdns,fifo-width = <4>;\n\tcdns,is-dma = <1>;\n\tcdns,trigger-address = <0x00000000>;\n\tflash@0 {\n\t\tcompatible = \"n25q512a\", \"micron,m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <108000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t};\n\t\t\tpartition@600000 {\n\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t};\n\t\t\tpartition@620000 {\n\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <1>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tclocks = <&clk125 &clk125>;\n\tnum-cs = <3>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0x0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\treg = <0x0 0x84000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclocks = <&clk100 &clk100>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-v350-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal v350 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-v350-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal v350 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &ospi;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&serial1 {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-01 revA OSPI\";\n\n\taliases {\n\t\tspi0 = &ospi;\n\t};\n};\n\n/* Mutually exclusive */\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treset-names = \"qspi\";\n\tresets = <&versal_reset VERSAL_RST_OSPI>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&qspi {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n compatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n \"xlnx,versal-vc-p-a2197-00\",\n \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n model = \"Xilinx Versal A2197 Processor board revA\";\n\n chosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n stdout-path = \"serial0:115200\";\n };\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tgpio0 = &gpio;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n\n};\n\n&dcc {\n status = \"okay\";\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tis-dual = <0x1>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"spi-flash\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tphy1: phy@1 {\n\t\treg = <1>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n\tphy2: phy@2 {\n\t\treg = <2>;\n\t\tti,rx-internal-delay = <0xb>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <1>;\n\t\tti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-01 revA (SE1)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-01 revA QSPI\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* U104 */\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy1>; /* u128 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t\tphy2: phy@2 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <2>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U116 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U117 and U118 */\n};\n\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-02 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem0 {\n\tphy-handle = <&phy0>; /* u9 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: phy@1 { /* Marvell 88E1512; U9 */\n\t\t\treg = <1>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\txlnx,mio-bank = <1>;\n};\n\n&sdhci1 { /* U1A */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n\n&dwc3_0 { /* U4 */\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"high-speed\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* U12 Catalyst EEPROM - AT24 should be equivalent */\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n\n\t/* FIXME - U13 and U15 */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U18 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <3>;\t/* FIXME - check SPI1_SS0-2_B */\n\n\tflash@0 { /* U19 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst26vf016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-flash0\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-03 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tserial0 = &serial0;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\t/* Must be enabled via J90/J91 */\n\teeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */\n\t\tcompatible = \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 64Mb */\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x800000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* J99 MIO28 - MIO33 */\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U6 - IS25LQ032B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lq032b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi\"\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tspi0 = &ospi;\n\t};\n};\n\n&qspi {\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-04 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy1>; /* u175 */\n\tphy-mode = \"rgmii-id\"; /* RTL8211DN */\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: phy@1 {\n\t\t\treg = <2>;\n\t\t};\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 { /* U153 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\teeprom: eeprom@51 { /* U155 */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 512MB */\n\t\treg = <0>, <1>;\n\t\tstacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x20000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */\n\tdisable-wp;\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\n\tflash@0 { /* U171 - IS25LP016B - 16Mb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"issi,is25lp016b\", \"m25p80\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x200000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host - U99 */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vc-p-a2197-00-reva.dtsi\"\n#include \"include/dt-bindings/net/mscc-phy-vsc8531.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA - x-prc-05 revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t};\n};\n\n&gem0 {\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: phy@1 { /* 88e1510 */\n\t\t\treg = <1>;\n\t\t};\n\t\tphy2: phy@2 { /* VSC8531 */\n\t\t\treg = <2>;\n\t\t\trx-internal-delay-ps = <2600>;\n\t\t\ttx-internal-delay-ps = <2600>;\n\t\t};\n\t};\n};\n\n&gem1 {\n\tphy-handle = <&phy2>;\n\tphy-mode = \"rgmii-id\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\teeprom_versal: eeprom@51 {\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x51>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <0x1>;\n\tspi-tx-bus-width = <4>;\n\tspi-rx-bus-width = <4>;\n\n\tflash@0 { /* MX25U12835 128Mbit */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 16MB */\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <104000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x1000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc0 */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME */\n};\n\n&sdhci1 { /* connector */\n\txlnx,mio-bank = <1>; /* FIXME */\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-vc-p-a2197-00-revA\",\n\t\t \"xlnx,versal-vc-p-a2197-00\",\n\t\t \"xlnx,versal-vc-p-a2197\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal A2197 Processor board revA\";\n\n\taliases {\n\t\tserial2 = &dcc;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci0 {\n\tno-1-8-v;\n};\n\n&sdhci1 {\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-01-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-01-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (QSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-02-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-02-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (EMMC)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1-x-ebm-03-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1-x-ebm-03-revA\",\n \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1 (OSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 rev1.1\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board rev1.1\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva-x-ebm-01-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-01-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (QSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva-x-ebm-02-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-02-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (EMMC)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva-x-ebm-03-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA-x-ebm-03-revA\",\n \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA (OSPI)\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VCK190 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vck190-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vck190 Eval board revA\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck5000-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vck5000 revA\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vck5000-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vck5000 board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &ospi;\n\t};\n\n};\n\n&ospi {\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcdns,read-delay = <0x0>;\n\t\tcdns,tshsl-ns = <0x0>;\n\t\tcdns,tsd2d-ns = <0x0>;\n\t\tcdns,tchsh-ns = <0x1>;\n\t\tcdns,tslch-ns = <0x1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x10000000>;\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&serial1 {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vek280-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VEK280 revA\n *\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vek280-revA\", \"xlnx,versal-vek280\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vek280 Eval board revA\";\n\n\tmemory: memory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* VADJ_FMC_EN - LPD MIO23 */\n/* FAN - LPD MIO21/22 */\n/* VCC_PL_EN - LPD MIO20 */\n/* PCIE_PERST - LPD MIO18/19 */\n/* SD_BUSPWR - PMC MIO51 */\n/* PCIE_WAKE - PMC MIO50 */\n/* VCCPSLP_EN - PMC MIO49 */\n/* I2C SYSMON - PMC MIO39 - 41 */\n/* PCIE_PWRBRK - PMC MIO38 */\n/* ZU4_TRIGGER - PMC MIO37 */\n/* VCC_AUX_1V2 - MIO11 */\n\n&ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\treset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = ;\n\t\t\tti,tx-internal-delay = ;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vek280-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VEK280 revB\n *\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vek280-revB\", \"xlnx,versal-vek280\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vek280 Eval board revB\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* VADJ_FMC_EN - LPD MIO23 */\n/* FAN - LPD MIO21/22 */\n/* VCC_PL_EN - LPD MIO20 */\n/* PCIE_PERST - LPD MIO18/19 */\n/* SD_BUSPWR - PMC MIO51 */\n/* PCIE_WAKE - PMC MIO50 */\n/* VCCPSLP_EN - PMC MIO49 */\n/* I2C SYSMON - PMC MIO39 - 41 */\n/* PCIE_PWRBRK - PMC MIO38 */\n/* ZU4_TRIGGER - PMC MIO37 */\n/* VCC_AUX_1V2 - MIO11 */\n\n&ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#stream-id-cells = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\treset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@1 { /* u198 - ADI1300 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id0283.bc30\";\n\t\t\treg = <1>;\n\t\t adi,rx-internal-delay-ps = <2000>;\n\t\t\tadi,tx-internal-delay-ps = <2000>;\n\t\t\tadi,fifo-depth-bits = <8>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t\treset-assert-us = <10>;\n\t\t\treset-deassert-us = <5000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vhk158-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VHK158 revA\n *\n * (C) Copyright 2022-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vhk158-revA\", \"xlnx,versal-vhk158\",\n\t\t \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vhk158 Eval board revA\";\n\n\tmemory: memory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &ospi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* ZU4_TRIGGER - PMC MIO37 */\n/* PCIE_PWRBRK - PMC MIO38 */\n/* I2C SYSMON - PMC MIO39 - 41 */\n/* VCCPSLP_EN - PMC MIO49 */\n/* PCIE_WAKE - PMC MIO50 */\n/* SOC_EN - LPD MIO13 */\n/* PSFP_EN - LPD MIO15 */\n/* AUX_1V2_EN - LPD MIO16 */\n/* HBM_EN - LPD MIO17 */\n/* PCIE_PERST - LPD MIO18/19 */\n/* VCC_PL_EN - LPD MIO20 */\n/* FAN - LPD MIO21/22 */\n/* VADJ_FMC_EN - LPD MIO23 */\n\n&ospi { /* PMC MIO0 - 12, U297 MT35XU02G */\n\tstatus = \"okay\";\n\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\tbus-num = <2>;\n\tnum-cs = <1>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tflash@0 {\n\t\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcdns,read-delay = <0>;\n\t\tcdns,tshsl-ns = <0>;\n\t\tcdns,tsd2d-ns = <0>;\n\t\tcdns,tchsh-ns = <1>;\n\t\tcdns,tslch-ns = <1>;\n\t\tspi-tx-bus-width = <8>;\n\t\tspi-rx-bus-width = <8>;\n\t\tspi-max-frequency = <20000000>;\n\t\tno-wp;\n\t\treset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = ;\n\t\t\tti,tx-internal-delay = ;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-virt.dtsi", "content": "#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-virt\", \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal Virtual\";\n\n\toptions {\n\t\tu-boot {\n\t\t\tcompatible = \"u-boot,config\";\n\t\t\tbootscr-address = /bits/ 64 <0x20000000>;\n\t\t};\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tclk2: clk2 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <2670000>;\n\t};\n\n\tclk25: clk25 {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t\tclock-frequency = <2720000>;\n\t};\n\n\tamba_apu: amba_apu {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */\n\t\t\t <0x0 0xf9080000 0x0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x1 0x9 4>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tbootph-all;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x2>;\n\t\tranges;\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"apb_clk\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff060000 0x0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t\treg = <0x0 0xff070000 0x0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x20>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom1: eeprom@53 {\n\t\t\t\treg = <0x53>;\n\t\t\t\tcompatible = \"at,24c08\";\n\t\t\t};\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk25>;\n\t\t\teeprom2: eeprom@55 {\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x55>;\n\t\t\t};\n\t\t};\n\n\t\tgpio: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tgpio-controller;\n\t\t\tclocks = <&clk25>;\n\t\t};\n\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&clk100 &clk100>;\n\t\t};\n\n\t\tethernet0: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 56 4>, <0x0 56 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t/* iommus = <&smmu 0x234>; */\n\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy0: phy@0 {\n\t\t\t\treg = <0x0>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tethernet1: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0x0 58 4>, <0x0 58 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\";\n\t\t\tclocks = <&clk2 &clk125 &clk125 &clk125>;\n\t\t\t#address-cells = <0x1>;\n\t\t\t#size-cells = <0x0>;\n\t\t\t/* iommus = <&smmu 0x235>; */\n\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\tphy1: phy@1 {\n\t\t\t\treg = <0x1>;\n\t\t\t\tmax-speed = <100>;\n\t\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\t\tti,fifo-depth = <0x1>;\n\t\t\t\tti,rxctrl-strap-worka;\n\t\t\t};\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xf12a0000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"okay\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>, <0 125 4>;\n\t\t\tnum-cs = <0x1>;\n\t\t\treg = <0x0 0xf1030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tis-dual = <1>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"n25q512a\", \"micron,m25p80\";\n\t\t\t\treg = <0x0>;\n\t\t\t\tspi-tx-bus-width = <4>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <108000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@100000 {\n\t\t\t\t\t\tlabel = \"qspi-linux\";\n\t\t\t\t\t\treg = <0x100000 0x500000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@600000 {\n\t\t\t\t\t\tlabel = \"qspi-device-tree\";\n\t\t\t\t\t\treg = <0x600000 0x20000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@620000 {\n\t\t\t\t\t\tlabel = \"qspi-rootfs\";\n\t\t\t\t\t\treg = <0x620000 0x5E0000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <1>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&clk125 &clk125>;\n\t\t\tnum-cs = <3>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <50000000>;\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0x0 0x84000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\n\t\tsdhci0: sdhci@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>, <0 126 4>;\n\t\t\treg = <0x0 0xf1040000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t};\n\n\t\tsdhci1: sdhci@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"okay\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>, <0 128 4>;\n\t\t\treg = <0x0 0xf1050000 0x0 0x10000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clk25 &clk25>;\n\t\t\txlnx,mio_bank = <0>;\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t};\n\n\t\tusb0: usb0@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\t#address-cells = <0x2>;\n\t\t\t#size-cells = <0x2>;\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tranges;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tclocks = <&clk125 &clk125>;\n\n\t\t\tdwc3@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x10000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = ðernet0;\n\t\tethernet1 = ðernet1;\n\t\tqspi = &qspi;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-01-revA\",\n\t\t \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1 (QSPI)\";\n};\n\n&qspi {\n#include \"versal-x-ebm-01-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-02-revA\",\n\t\t \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1 (EMMC)\";\n};\n\n&sdhci1 {\n#include \"versal-x-ebm-02-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-rev1.1.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-rev1.1-x-ebm-03-revA\",\n \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board rev1.1 (OSPI)\";\n};\n\n&ospi {\n#include \"versal-x-ebm-03-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 rev1.1\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-rev1.1\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board rev1.1\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-01-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (QSPI)\";\n};\n\n&qspi {\n#include \"versal-x-ebm-01-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-02-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (EMMC)\";\n};\n\n&sdhci1 {\n#include \"versal-x-ebm-02-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"versal-vmk180-reva.dtsi\"\n\n/ {\n compatible = \"xlnx,versal-vmk180-revA-x-ebm-03-revA\",\n \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n model = \"Xilinx Versal vmk180 Eval board revA (OSPI)\";\n\n aliases {\n spi0 = &ospi;\n };\n};\n\n&ospi {\n#include \"versal-x-ebm-03-reva.dtsi\"\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal VMK180 revA\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-vmk180-revA\", \"xlnx,versal\";\n\tmodel = \"Xilinx Versal vmk180 Eval board revA\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n};\n\n/* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */\n/* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sdhci1 { /* PMC_MIO26-36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n&gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy1: ethernet-phy@1 { /* u198 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tphy2: ethernet-phy@2 { /* u134 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <2>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t\treset-gpios = <&gpio1 49 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gem1 { /* PMC_MIO_49, LPD_MIO12-23 */\n\tphy-handle = <&phy2>; /* u134 */\n\tphy-mode = \"rgmii-id\";\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vp-x-a2785-00 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vp-x-a2785-00 Eval board revA\";\n\tcompatible = \"xlnx,versal-vp-x-a2785-00-revA\",\n\t\t \"xlnx,versal-vp-x-a2785-00\", \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tstatus = \"okay\"; /* u93 and u92 */\n\tnum-cs = <2>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\tstatus = \"okay\";\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tstatus = \"okay\";\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk120 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk120 Eval board revA\";\n\tcompatible = \"xlnx,versal-vpk120-revA\", \"xlnx,versal-vpk120\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <2>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vpk120-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk120 revB\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk120 Eval board revB\";\n\tcompatible = \"xlnx,versal-vpk120-revB\", \"xlnx,versal-vpk120\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <2>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\t/* Use for storing information about board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tbootph-all;\n\t};\n\n};\n\n/* PCIe at MIO 38/39/40/50 */\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vpk180-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal vpk180 revA\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Xilinx Versal vpk180 Eval board revA\";\n\tcompatible = \"xlnx,versal-vpk180-revA\", \"xlnx,versal-vpk180\",\n\t\t \"xlnx,versal\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial2 = &dcc;\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\tspi0 = &qspi;\n\t\tusb0 = &usb0;\n\t\trtc0 = &rtc;\n\t};\n\t/* Missing any LED for heartbeat */\n};\n\n&qspi { /* PMC_MIO_500 0 - 12 */\n\tnum-cs = <2>;\n\tspi-rx-bus-width = <4>;\n\tspi-tx-bus-width = <4>;\n\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <35000000>;\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-flash0\";\n\t\t\treg = <0x0 0x8000000>;\n\t\t};\n\t};\n};\n\n&dwc3_0 { /* USB 2.0 host */\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\"; /* FIXME */\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tsnps,usb3_lpm_capable;\n};\n\n&sdhci1 { /* PMC_MIO_501 26 - 36/51 */\n\txlnx,mio-bank = <1>;\n\tno-1-8-v;\n\tclk-phase-sd-hs = <111>, <48>;\n\tclk-phase-uhs-sdr25 = <114>, <48>;\n\tclk-phase-uhs-ddr50 = <126>, <36>;\n};\n\n&i2c1 { /* PMC_MIO44/45 */\n\n\t/* Use for storing information about board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tbootph-all;\n\t};\n};\n\n&gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */\n\tphy-handle = <&phy1>; /* u198 */\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = <0xb>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t};\n\t};\n};\n\n&gpio0 {\n\t/* FIXME Fill names when versal starts */\n};\n\n&gpio1 {\n\t/* FIXME Fill names when versal starts */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-x-ebm-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-01 revA for vck190/vmk180\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\nnum-cs = <2>;\nspi-tx-bus-width = <4>;\nspi-rx-bus-width = <4>;\n#address-cells = <1>;\n#size-cells = <0>;\nflash@0 {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 256MB */\n\treg = <0>, <1>;\n\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\tspi-tx-bus-width = <4>;\n\tspi-rx-bus-width = <4>;\n\tspi-max-frequency = <150000000>;\n\tpartition@0 {\n\t\tlabel = \"spi0-flash0\";\n\t\treg = <0x0 0x10000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-x-ebm-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-02 revA for vck190/vmk180\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/* emmc MIO 0-13 - MTFC8GAKAJCN */\nnon-removable;\ndisable-wp;\nbus-width = <8>;\nxlnx,mio-bank = <0>;\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/versal-x-ebm-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx X-EBM-03 revA for vck190/vmk180\n *\n * (C) Copyright 2020-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-resets.h\"\n/* U97 MT35XU02G */\ncompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\nbus-num = <2>;\nnum-cs = <1>;\n#address-cells = <1>;\n#size-cells = <0>;\n\nflash@0 {\n\tcompatible = \"mt35xu02g\", \"micron,m25p80\", \"jedec,spi-nor\";\n\treg = <0>;\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcdns,read-delay = <0x0>;\n\tcdns,tshsl-ns = <0x0>;\n\tcdns,tsd2d-ns = <0x0>;\n\tcdns,tchsh-ns = <0x1>;\n\tcdns,tslch-ns = <0x1>;\n\tspi-tx-bus-width = <8>;\n\tspi-rx-bus-width = <8>;\n\tspi-max-frequency = <20000000>;\n\tno-wp;\n\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>;\n\tpartition@0 {\n\t\tlabel = \"spi0-flash0\";\n\t\treg = <0x0 0x8000000>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n\n\t aliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB FIXME */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n rtc0 = &rtc;\n serial0 = &uart0;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tclock_si5338_0: clk27 {\t/* u55 SI5338-GM */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tclock_si5338_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_si5338_3: clk150 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <150000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO34\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO35\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio0_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_38_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n};\n\n&psgtr {\n\tstatus = \"okay\";\n\t/* dp, usb3, sata */\n\tclocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* Micron MT25QU512ABB8ESF */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tbus-width = <8>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tphy-names = \"usb3-phy\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem2;\n i2c0 = &i2c0;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n spi0 = &spi0;\n spi1 = &spi1;\n usb0 = &usb1;\n };\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem2 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem2_default>;\n\tphy0: ethernet-phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&nand0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand0_default>;\n\tarasan,has-mdma;\n\n\tnand@0 {\n\t\treg = <0x0>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"hw\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-0\";\n\t\tnand-ecc-step-size = <1024>;\n\t\tnand-ecc-strength = <24>;\n\t\tnand-on-flash-bbt;\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n\tnand@1 {\n\t\treg = <0x1>;\n\t\t#address-cells = <0x2>;\n\t\t#size-cells = <0x1>;\n\t\tnand-ecc-mode = \"hw\";\n\t\tnand-rb = <0>;\n\t\tlabel = \"main-storage-1\";\n\t\tnand-ecc-step-size = <1024>;\n\t\tnand-ecc-strength = <24>;\n\t\tnand-on-flash-bbt;\n\n\n\t\tpartition@0 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-fsbl-uboot\";\n\t\t\treg = <0x0 0x0 0x400000>;\n\t\t};\n\t\tpartition@1 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-linux\";\n\t\t\treg = <0x0 0x400000 0x1400000>;\n\t\t};\n\t\tpartition@2 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-device-tree\";\n\t\t\treg = <0x0 0x1800000 0x400000>;\n\t\t};\n\t\tpartition@3 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-rootfs\";\n\t\t\treg = <0x0 0x1c00000 0x1400000>;\n\t\t};\n\t\tpartition@4 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-bitstream\";\n\t\t\treg = <0x0 0x3000000 0x400000>;\n\t\t};\n\t\tpartition@5 {\t/* for testing purpose */\n\t\t\tlabel = \"nand1-misc\";\n\t\t\treg = <0x0 0x3400000 0xfcc00000>;\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO38\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_8_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_8_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO33\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO32\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_6_grp\", \"gpio0_7_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO42\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO43\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO41\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO40\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem2_default: gem2-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet2\";\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO58\", \"MIO59\", \"MIO60\", \"MIO61\", \"MIO62\",\n\t\t\t\t\t\t\t\t\t\"MIO63\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO54\", \"MIO55\", \"MIO56\",\n\t\t\t\t\t\t\t\t\t\"MIO57\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio2\";\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio2_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_nand0_default: nand0-default {\n\t\tmux {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tfunction = \"nand0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"nand0_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tfunction = \"nand0_ce\";\n\t\t};\n\n\t\tconf-ce {\n\t\t\tgroups = \"nand0_ce_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tfunction = \"nand0_rb\";\n\t\t};\n\n\t\tconf-rb {\n\t\t\tgroups = \"nand0_rb_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tfunction = \"nand0_dqs\";\n\t\t};\n\n\t\tconf-dqs {\n\t\t\tgroups = \"nand0_dqs_0_grp\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_0_grp\", \"spi0_ss_1_grp\",\n\t\t\t\t\t\t\t\"spi0_ss_2_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tio-standard = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_9_grp\", \"spi1_ss_10_grp\",\n\t\t\t\t\t\t\t\"spi1_ss_11_grp\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi0_default>;\n\n\tspi0_flash0: flash@0 {\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi0-data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tnum-cs = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_spi1_default>;\n\n\tspi1_flash0: flash@0 {\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"spi1-data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zc702.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n#include \n\n/ {\n\tmodel = \"Zynq ZC702 Development Board\";\n\tcompatible = \"xlnx,zynq-zc702\", \"xlnx,zynq-7000\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n serial0 = &uart1;\n spi0 = &qspi;\n mmc0 = &sdhci0;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n switch-14 {\n\t\t\tlabel = \"sw14\";\n\t\t\tgpios = <&gpio0 12 0>;\n\t\t\tlinux,code = <108>; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n switch-13 {\n\t\t\tlabel = \"sw13\";\n\t\t\tgpios = <&gpio0 14 0>;\n\t\t\tlinux,code = <103>; /* up */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tds23 {\n\t\t\tlabel = \"ds23\";\n\t\t\tgpios = <&gpio0 10 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&can0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can0_default>;\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\tphy-reset-gpio = <&gpio0 11 0>;\n\tphy-reset-active-low;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"right\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\thwmon@34 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x34>;\n\t\t\t};\n\t\t\thwmon@35 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\thwmon@36 {\n\t\t\t\tcompatible = \"ti,ucd9248\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_can0_default: can0-default {\n\t\tmux {\n\t\t\tfunction = \"can0\";\n\t\t\tgroups = \"can0_9_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can0_9_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO46\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO47\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_8_grp\", \"gpio0_9_grp\",\n\t\t\t\t \"gpio0_10_grp\", \"gpio0_11_grp\", \"gpio0_12_grp\",\n\t\t\t\t \"gpio0_13_grp\", \"gpio0_14_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO9\", \"MIO10\", \"MIO11\", \"MIO12\", \"MIO13\", \"MIO14\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\", \"MIO8\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_50_grp\", \"gpio0_51_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tbootph-all;\n\tis-dual = <0>;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tbootph-all;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tbootph-all;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zc706.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n * Copyright (C) 2012 National Instruments Corp.\n */\n\n/ {\n\tmodel = \"Zynq ZC706 Development Board\";\n\tcompatible = \"xlnx,zynq-zc706\", \"xlnx,zynq-7000\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n serial0 = &uart1;\n spi0 = &qspi;\n mmc0 = &sdhci0;\n };\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem0_default>;\n\n\tethernet_phy: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&gpio0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio0_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tsi570: clock-generator@5d {\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\treg = <0x5d>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tadv7511: hdmi-tx@39 {\n\t\t\t\tcompatible = \"adi,adv7511\";\n\t\t\t\treg = <0x39>;\n\t\t\t\tadi,input-depth = <8>;\n\t\t\t\tadi,input-colorspace = \"yuv422\";\n\t\t\t\tadi,input-clock = \"1x\";\n\t\t\t\tadi,input-style = <3>;\n\t\t\t\tadi,input-justification = \"evenly\";\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\teeprom@54 {\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tgpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\trtc@51 {\n\t\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\tucd90120@65 {\n\t\t\t\tcompatible = \"ti,ucd90120\";\n\t\t\t\treg = <0x65>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tpinctrl_gem0_default: gem0-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet0\";\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <4>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO22\", \"MIO23\", \"MIO24\", \"MIO25\", \"MIO26\", \"MIO27\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO16\", \"MIO17\", \"MIO18\", \"MIO19\", \"MIO20\", \"MIO21\";\n\t\t\tlow-power-enable;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio0\";\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_gpio0_default: gpio0-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_7_grp\", \"gpio0_46_grp\", \"gpio0_47_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO46\", \"MIO47\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO7\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_10_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_2_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"gpio0_14_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tfunction = \"sdio0_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"gpio0_15_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_10_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO49\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO48\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tslew-rate = <0>;\n\t\t\tpower-source = <1>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO29\", \"MIO31\", \"MIO36\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO28\", \"MIO30\", \"MIO32\", \"MIO33\", \"MIO34\",\n\t\t\t \"MIO35\", \"MIO37\", \"MIO38\", \"MIO39\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tbootph-all;\n\tis-dual = <1>;\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@0 {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@c00000 {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tbootph-all;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n};\n\n&uart1 {\n\tbootph-all;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n};\n\n&watchdog0 {\n\treset-on-timeout;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu100-reva.dtsi", "content": "/ {\n\tmodel = \"ZynqMP ZCU100 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revA\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO7 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 7 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tclk3_6: clk3_6 { /* for spi uart max3107 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <3600000>;\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\tcompatible = \"lltc,ltc2952\";\n\t\tstatus = \"disabled\";\n\t\ttrigger-gpios = <&gpio 23 1>; /* INT line - input */\n\t\twatchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */\n\t\tkill-gpios = <&gpio 25 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&max3107 1 1>; /* WIFI_EN */\n\t};\n};\n\n&i2c0 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <39 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/*\n\t\t\t * SYSMON\n\t\t\t */\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * EEPROM with globally unique ID (will provide MAC address)\n\t\t\t */\n\t\t\teeprom@50 { /* u35 - 24aa02E48T */\n\t\t\t\tcompatible = \"atmel,24c02\"; /* 8 blocks 50-57 - works */\n\t\t\t\treg = <0x50>; /* low 3 bits: don't care */\n\t\t\t};\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t\t/* FIXME 0x2c 0x2d - disabled because of SMBUS */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 { /* single x4 - 16 MB flash at U13 */\n\t\tcompatible = \"n25q128a13\", \"jedec,spi-nor\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@qspi-fsbl-uboot { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x9E0000>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\txlnx,mio-bank = <0>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tmax-frequency = <16000000>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 {\n\tmax3107: max3107@0 { /* I'm assuming no offset...? */\n\t\tcompatible = \"maxim,max3107\";\n\t\tspi-max-frequency = <26000000>;\n\t\treg = <0>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <77 8>;\n\t\tclocks = <&clk3_6>;\n\t\tclock-names = \"osc\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n/*\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */\n\tmaximum-speed = \"high-speed\"; /* super-speed */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu100-revb.dtsi", "content": "/ {\n\tmodel = \"ZynqMP ZCU100 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revB\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>; /* shared with pmic IRQ */\n\t\t\tlinux,code = <108>; /* down */\n\t\t\tgpio-key,wakeup; /* FIXME test this */\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\t/* FIXME this is not correct - used fixed-regulator for it */\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tltc2952: ltc2952 { /* U7 */\n\t\t/*\n\t\t * FIXME this is ltc2954 not ltc2952 - try this driver and\n\t\t * maybe just extend compatible string.\n\t\t */\n\t\tcompatible = \"lltc,ltc2954\", \"lltc,ltc2952\";\n\t\ttrigger-gpios = <&gpio 26 1>; /* INT line - input */\n\t\t/* If there is HW watchdog on mezzanine this signal should be connected there */\n\t\twatchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */\n\t\tkill-gpios = <&gpio 34 1>; /* KILL signal - output */\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&pmufw {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pmu_default>;\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 0>;\n\tsda-gpios = <&gpio 5 0>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 { /* i2c mw 75 0 1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t};\n\t\ti2csw_1: i2c@1 { /* i2c mw 75 0 2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t};\n\t\ti2csw_2: i2c@2 { /* i2c mw 75 0 4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t};\n\t\ti2csw_3: i2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t};\n\t\ti2csw_4: i2c@4 { /* i2c mw 75 0 10 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\t/* Comment it out because will be pre-programmed\n\t\t\t at the factory */\n\n\t\t\tpmic: tps65086x@5e { // Custom TI PMIC u33\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <23 1>; /* shared with pmic IRQ */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\n/*\n\t\t\t\tsys-supply = <&some_reg>;\n\t\t\t\t// spec 12V\n\n\t\t\t\tbuck1 5V0\n\t\t\t\tbuck2 PSINTLP (no idea)\n\t\t\t\tbuck3 VCC_PSDDR 1V1\n\t\t\t\tbuck4 3V3\n\t\t\t\tbuck5 1V2\n\t\t\t\tbuck6 VCC_PSAUX 1V8\n\n\t\t\t\tvin-sm0-supply = <&some_reg>;\n\t\t\t\tvin-sm1-supply = <&some_reg>;\n\t\t\t\tvin-sm2-supply = <&some_reg>;\n\t\t\t\tvinldo01-supply = <...>;\n\t\t\t\tvinldo23-supply = <...>;\n\t\t\t\tvinldo4-supply = <...>;\n\t\t\t\tvinldo678-supply = <...>;\n\t\t\t\tvinldo9-supply = <...>;\n\n\t\t\t\tregulators {\n\t\t\t\t\tsys_reg: sys {\n\t\t\t\t\t regulator-name = \"vdd_sys\";\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm0_reg: sm0 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm1_reg: sm1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tsm2_reg: sm2 {\n\t\t\t\t\t regulator-min-microvolt = <3000000>;\n\t\t\t\t\t regulator-max-microvolt = <4550000>;\n\t\t\t\t\t regulator-boot-on;\n\t\t\t\t\t regulator-always-on;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo0_reg: ldo0 {\n\t\t\t\t\t regulator-name = \"PCIE CLK\";\n\t\t\t\t\t regulator-min-microvolt = <3300000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo1_reg: ldo1 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo2_reg: ldo2 {\n\t\t\t\t\t regulator-min-microvolt = < 725000>;\n\t\t\t\t\t regulator-max-microvolt = <1500000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo3_reg: ldo3 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo4_reg: ldo4 {\n\t\t\t\t\t regulator-min-microvolt = <1700000>;\n\t\t\t\t\t regulator-max-microvolt = <2475000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo5_reg: ldo5 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo6_reg: ldo6 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo7_reg: ldo7 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo8_reg: ldo8 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tldo9_reg: ldo9 {\n\t\t\t\t\t regulator-min-microvolt = <1250000>;\n\t\t\t\t\t regulator-max-microvolt = <3300000>;\n\t\t\t\t\t};\n\n\t\t\t\t// FIXME look at this one\n\t\t\t\t\tldo_rtc {\n\t\t\t\t\t\tregulator-name = \"vdd_rtc_out,vdd_cell\";\n\t\t\t\t\t\tregulator-min-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\t\t\tregulator-always-on;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t*/\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 { /* i2c mw 75 0 20 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 { /* i2c mw 75 0 40 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 { /* i2c mw 75 0 80 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n\n\tpinctrl_pmu_default: pmu-default {\n\t\tmux {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tfunction = \"pmu0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"pmu0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = <1>;\n\t\t\tpower-source = <1>;\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wlcore@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane2 4 0 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tphy-names = \"usb3-phy\";\n\tphys = <&lane3 4 1 0 26000000>;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\t aliases {\n i2c0 = &i2c1;\n rtc0 = &rtc;\n serial0 = &uart1;\n serial1 = &uart0;\n serial2 = &dcc;\n spi0 = &spi0;\n spi1 = &spi1;\n usb0 = &usb0;\n usb1 = &usb1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tiio-hwmon {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t <&xilinx_ams 9>, <&xilinx_ams 10>,\n\t\t\t <&xilinx_ams 11>, <&xilinx_ams 12>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n led-vbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;\n\t};\n\n\tsi5335_0: si5335_0 { /* clk0_usb - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tsi5335_1: si5335_1 { /* clk1_dp - u23 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 IRQ_TYPE_LEVEL_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu35: ina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_1_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_4_grp\", \"gpio0_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci0_default: sdhci0-default {\n\t\tmux {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tfunction = \"sdio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio0_3_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tfunction = \"sdio0_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio0_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_2_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_spi0_default: spi0-default {\n\t\tmux {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tfunction = \"spi0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi0_3_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tfunction = \"spi0_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi0_ss_9_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_spi1_default: spi1-default {\n\t\tmux {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tfunction = \"spi1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"spi1_0_grp\";\n\t\t\tbias-disable;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tfunction = \"spi1_ss\";\n\t\t};\n\n\t\tconf-cs {\n\t\t\tgroups = \"spi1_ss_0_grp\";\n\t\t\tbias-disable;\n\t\t};\n\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO3\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO2\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO1\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_usb1_default: usb1-default {\n\t\tmux {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tfunction = \"usb1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb1_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO67\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO66\", \"MIO68\", \"MIO69\", \"MIO70\", \"MIO71\",\n\t\t\t \"MIO72\", \"MIO73\", \"MIO74\", \"MIO75\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* usb3, dp */\n\tclocks = <&si5335_0>, <&si5335_1>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 0>;\n\t/delete-property/ reset-gpios;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"super-speed\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb1_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_USB3 1 0>;\n\treset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;\n};\n\n&dwc3_1 {\n\tdr_mode = \"host\";\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zcu102-revb.dtsi\"\n\n/ {\n model = \"ZynqMP ZCU102 Rev1.0\";\n compatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n};\n\n&eeprom {\n #address-cells = <1>;\n #size-cells = <1>;\n\n board_sn: board-sn@0 {\n reg = <0x0 0x14>;\n };\n\n eth_mac: eth-mac@20 {\n reg = <0x20 0x6>;\n };\n\n board_name: board-name@d0 {\n reg = <0xd0 0x6>;\n };\n\n board_revision: board-revision@e0 {\n reg = <0xe0 0x3>;\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@21 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <21>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"PS_GTR_LAN_SEL0\", \"PS_GTR_LAN_SEL1\", \"PS_GTR_LAN_SEL2\", \"PS_GTR_LAN_SEL3\",\n\t\t\t\t\"PCI_CLK_DIR_SEL\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\",\n\t\t\t\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller; /* IRQ not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t\tgpio-line-names = \"VCCPSPLL_EN\", \"MGTRAVCC_EN\", \"MGTRAVTT_EN\", \"VCCPSDDRPLL_EN\", \"MIO26_PMU_INPUT_LS\",\n\t\t\t\t\"PL_PMBUS_ALERT\", \"PS_PMBUS_ALERT\", \"MAXIM_PMBUS_ALERT\", \"PL_DDR4_VTERM_EN\",\n\t\t\t\t\"PL_DDR4_VPP_2V5_EN\", \"PS_DIMM_VDDQ_TO_PSVCCO_ON\", \"PS_DIMM_SUSPEND_EN\",\n\t\t\t\t\"PS_DDR4_VTERM_EN\", \"PS_DDR4_VPP_2V5_EN\", \"\", \"\";\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 FIXME - not detected */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_4: out@4 {\n\t\t\t\t\t/* refclk4 for PS-GT, used for PCIE slot */\n\t\t\t\t\treg = <4>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 for PS-GT, used for PCIE */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux-sw {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf-sw {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\", \"MIO23\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* pcie, sata, usb3, dp */\n\tclocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref0\", \"ref1\", \"ref2\", \"ref3\";\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\t/*\n\t * 1.0 revision has level shifter and this property should be\n\t * removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zcu102-reva.dtsi\"\n\n/ {\n model = \"ZynqMP ZCU102 RevB\";\n compatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n};\n\n&gem3 {\n phy-handle = <&phyc>;\n\tmdio: mdio {\n\t\tphyc: ethernet-phy@c {\n\t\t\t#phy-cells = <0x1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t/* Cleanup from RevA */\n\t\t/delete-node/ ethernet-phy@21;\n };\n};\n\n/* Fix collision with u61 */\n&i2c0 {\n i2c-mux@75 {\n i2c@2 {\n max15303@1b { /* u8 */\n compatible = \"maxim,max15303\";\n reg = <0x1b>;\n };\n /delete-node/ max15303@20;\n };\n };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* 8T49N287 - u182 */\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@20 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x20>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu104-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revC\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tina226 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;\n\t};\n\n\tclock_8t49n287_5: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclock_8t49n287_2: clk26 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\n\tclock_8t49n287_3: clk27 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - IRPS5401_ALERT_B\n\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t * 2 - MAX6643_OT_B\n\t\t * 3 - MAX6643_FANFAIL_B\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t * 4, 10 - 17 - not connected\n\t\t */\n\t};\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* 8T49N287 - u182 */\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>; /* pmbus / i2c 0x13 */\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u180 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* pmbus / i2c 0x14 */\n\t\t\t};\n\t\t};\n\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tu183: ina226@40 { /* u183 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 4, 6 not connected */\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* n25q512a 128MiB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tno-1-8-v;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\txlnx,mio-bank = <1>;\n\tdisable-wp;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\n\tina226-u76 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u87 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;\n\t};\n\tina226-u85 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;\n\t};\n\tina226-u86 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;\n\t};\n\tina226-u93 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;\n\t};\n\tina226-u88 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;\n\t};\n\tina226-u15 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;\n\t};\n\tina226-u92 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u81 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;\n\t};\n\tina226-u80 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n\tina226-u16 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\trefhdmi: refhdmi {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <114285000>;\n\t};\n};\n\n&can1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_can1_default>;\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\treg = <0xc>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tu76: ina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u76\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu87: ina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u87\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu85: ina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u85\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu86: ina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u86\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu93: ina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u93\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu88: ina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u88\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu15: ina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u15\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu92: ina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u92\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tu79: ina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu81: ina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u81\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu80: ina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u80\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu84: ina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu16: ina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u16\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu74: ina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu75: ina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_7: out@7 {\n\t\t\t\t\t/* refclk7 PL CLK74 */\n\t\t\t\t\treg = <7>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\tcompatible = \"silabs,si5328\";\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&refhdmi>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5328\";\n\n\t\t\t\tsi5328_clk: clk0@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tclock-frequency = <27000000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_uart1_default: uart1-default {\n\t\tmux {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart1_5_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO21\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO20\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_can1_default: can1-default {\n\t\tmux {\n\t\t\tfunction = \"can1\";\n\t\t\tgroups = \"can1_6_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"can1_6_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO25\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO24\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tfunction = \"sdio1_wp\";\n\t\t};\n\n\t\tconf-wp {\n\t\t\tgroups = \"sdio1_wp_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, sata, usb3, dp */\n\tclocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 1>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\n\tina226-u67 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;\n\t};\n\tina226-u59 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;\n\t};\n\tina226-u61 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;\n\t};\n\tina226-u60 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;\n\t};\n\tina226-u64 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;\n\t};\n\tina226-u69 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;\n\t};\n\tina226-u66 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;\n\t};\n\tina226-u65 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;\n\t};\n\tina226-u63 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;\n\t};\n\tina226-u3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;\n\t};\n\tina226-u71 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;\n\t};\n\tina226-u77 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;\n\t};\n\tina226-u73 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem3_default>;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gpio_default>;\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tu67: ina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u67\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu59: ina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u59\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu61: ina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u61\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu60: ina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u60\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu64: ina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u64\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu69: ina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u69\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tu66: ina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u66\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu65: ina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u65\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu63: ina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u63\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu3: ina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u3\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu71: ina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u71\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu77: ina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u77\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu73: ina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u73\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u57 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_0: out@0 {\n\t\t\t\t\t/* refclk0 for PS-GT, used for DP */\n\t\t\t\t\treg = <0>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SI5382 - u48 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 { /* i2c mw 75 0 8 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t\tdev@19 { /* u-boot detection FIXME */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\tdev@30 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x30>;\n\t\t\t};\n\t\t\tdev@35 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x35>;\n\t\t\t};\n\t\t\tdev@36 { /* u-boot detection */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\t\t\tdev@51 { /* u-boot detection - maybe SPD */\n\t\t\t\tcompatible = \"xxx\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_uart0_default: uart0-default {\n\t\tmux {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tfunction = \"uart0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"uart0_4_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO18\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO19\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_usb0_default: usb0-default {\n\t\tmux {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tfunction = \"usb0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"usb0_0_grp\";\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO52\", \"MIO53\", \"MIO55\";\n\t\t\tbias-high-impedance;\n\t\t\tdrive-strength = <12>;\n\t\t\tslew-rate = ;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO54\", \"MIO56\", \"MIO57\", \"MIO58\", \"MIO59\",\n\t\t\t \"MIO60\", \"MIO61\", \"MIO62\", \"MIO63\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <4>;\n\t\t\tslew-rate = ;\n\t\t};\n\t};\n\n\tpinctrl_gem3_default: gem3-default {\n\t\tmux {\n\t\t\tfunction = \"ethernet3\";\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"ethernet3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO70\", \"MIO71\", \"MIO72\", \"MIO73\", \"MIO74\",\n\t\t\t\t\t\t\t\t\t\"MIO75\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO64\", \"MIO65\", \"MIO66\", \"MIO67\", \"MIO68\",\n\t\t\t\t\t\t\t\t\t\"MIO69\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio3\";\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio3_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tpinctrl_sdhci1_default: sdhci1-default {\n\t\tmux {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tfunction = \"sdio1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"sdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tfunction = \"sdio1_cd\";\n\t\t};\n\n\t\tconf-cd {\n\t\t\tgroups = \"sdio1_cd_0_grp\";\n\t\t\tbias-high-impedance;\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t};\n\n\tpinctrl_gpio_default: gpio-default {\n\t\tmux {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_22_grp\", \"gpio0_23_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux-msp {\n\t\t\tfunction = \"gpio0\";\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t};\n\n\t\tconf-msp {\n\t\t\tgroups = \"gpio0_13_grp\", \"gpio0_38_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-pull-up {\n\t\t\tpins = \"MIO22\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-pull-none {\n\t\t\tpins = \"MIO13\", \"MIO23\", \"MIO38\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&psgtr {\n\t/* nc, dp, usb3, sata */\n\tclocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref1\", \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci1_default>;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0_default>;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb0_default>;\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revA\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu1275-revb.dtsi", "content": "/*\n * dts file for Xilinx ZynqMP ZCU1275 RevB\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1275 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu1275-revB\", \"xlnx,zynqmp-zcu1275\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n mmc0 = &sdhci1;\n ethernet0 = &gem1;\n };\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@100000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@600000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@620000 { /* for testing purpose */\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t* 1.0 revision has level shifter and this property should be\n\t* removed for supporting UHS mode\n\t*/\n\tno-1-8-v;\n};\n\n&gem1 {\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu1285-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU1285 RevA\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU1285 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu1285-revA\", \"xlnx,zynqmp-zcu1285\", \"xlnx,zynqmp\";\n\n\taliases {\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n mmc0 = &sdhci1;\n ethernet0 = &gem1; /* EMIO */\n i2c = &i2c0; /* EMIO */\n };\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n};\n\n&gem1 {\n\tmdio {\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */\n\t\t\trxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */\n\t\t\ttxc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */\n\t\t\ttxen-skew-ps = <900>; /* Skew control of TX_CTL pad input */\n\t\t\trxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */\n\t\t\trxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */\n\t\t\trxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */\n\t\t\trxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */\n\t\t\trxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */\n\t\t\ttxd0-skew-ps = <900>; /* Skew control of TXD0 pad input */\n\t\t\ttxd1-skew-ps = <900>; /* Skew control of TXD1 pad input */\n\t\t\ttxd2-skew-ps = <900>; /* Skew control of TXD2 pad input */\n\t\t\ttxd3-skew-ps = <900>; /* Skew control of TXD3 pad input */\n\t\t};\n\t};\n};\n\n&qspi {\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <1>;\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sdhci1 {\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu208-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU208\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU208 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu208-revA\", \"xlnx,zynqmp-zcu208\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu216-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU216\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU216 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu216-revA\", \"xlnx,zynqmp-zcu216\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n};\n\n&psgtr {\n\t/* nc, nc, usb3, sata */\n\tclocks = <&si5341 0 2>, <&si5341 0 3>;\n\tclock-names = \"ref2\", \"ref3\";\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5341: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u43 */\n\t\t\t\tcompatible = \"silabs,si5341\";\n\t\t\t\treg = <0x36>;\n\t\t\t\t#clock-cells = <2>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tclocks = <&ref48>;\n\t\t\t\tclock-names = \"xtal\";\n\t\t\t\tclock-output-names = \"si5341\";\n\n\t\t\t\tsi5341_2: out@2 {\n\t\t\t\t\t/* refclk2 for PS-GT, used for USB3 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_3: out@3 {\n\t\t\t\t\t/* refclk3 for PS-GT, used for SATA */\n\t\t\t\t\treg = <3>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_5: out@5 {\n\t\t\t\t\t/* refclk5 PL CLK100 */\n\t\t\t\t\treg = <5>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_6: out@6 {\n\t\t\t\t\t/* refclk6 PL CLK125 */\n\t\t\t\t\treg = <6>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t\tsi5341_9: out@9 {\n\t\t\t\t\t/* refclk9 used for PS_REF_CLK 33.3 MHz */\n\t\t\t\t\treg = <9>;\n\t\t\t\t\talways-on; /* assigned-clocks does not enable, so do it here */\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u409B */\n\t\t\t\treg = <0x5b>;\n\t\t\t};\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_user_c1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER C1 SI570 - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c1\";\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* MSP430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 1Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n&sata {\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tphy-names = \"sata-phy\";\n\tphys = <&psgtr 3 PHY_TYPE_SATA 1 3>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n\tmaximum-speed = \"super-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu670-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR)\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU670 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu670-revA\", \"xlnx,zynqmp-zcu670\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\"; /* DS1 */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5381_6: si5381_6 { /* refclk_usb3 - u43 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"SFP3_TX_DISABLE\", \"SFP2_TX_DISABLE\", \"SFP1_TX_DISABLE\", /* 25 - 29 */\n\t\t \"SFP0_TX_DISABLE\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"SD_PWR_RST\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"SI5381_INT_ALM\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* Not in schematics */\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5381: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SI5381 - u43 */\n\t\t\t/*si5381: clock-generator@68 {\n\t\t\t\treg = <0x68>;\n\t\t\t};*/\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_psrefclk: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"si570_ps_ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 2Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n};\n\n&psgtr {\n\t/* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */\n\tclocks = <&si5381_6>;\n\tclock-names = \"ref2\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zcu670-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP ZCU670 (67DR) revB\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU670 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu670-revB\", \"xlnx,zynqmp-zcu670\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem3;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n };\n\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tswitch-1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\"; /* DS1 */\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vccint-io-bram-ps {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;\n\t};\n\tina226-vcc1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;\n\t};\n\tina226-vcc1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;\n\t};\n\tina226-mgt1v2 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;\n\t};\n\tina226-mgt1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;\n\t};\n\tina226-vccint-ams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;\n\t};\n\tina226-dac-avtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;\n\t};\n\tina226-dac-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;\n\t};\n\tina226-adc-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;\n\t};\n\tina226-adc-avccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;\n\t};\n\tina226-dac-avcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;\n\t};\n\n\t/* 48MHz reference crystal */\n\tref48: ref48M {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <48000000>;\n\t};\n\n\tsi5381_6: si5381_6 { /* refclk_usb3 - u43 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@c {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <0xc>;\n\t\t\tti,rx-internal-delay = <0x8>;\n\t\t\tti,tx-internal-delay = <0xa>;\n\t\t\tti,fifo-depth = <0x1>;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_LWR_CLK\", \"QSPI_LWR_DQ1\", \"QSPI_LWR_DQ2\", \"QSPI_LWR_DQ3\", \"QSPI_LWR_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_LWR_CS_B\", \"\", \"QSPI_UPR_CS_B\", \"QSPI_UPR_DQ0\", \"QSPI_UPR_DQ1\", /* 5 - 9 */\n\t\t \"QSPI_UPR_DQ2\", \"QSPI_UPR_DQ3\", \"QSPI_UPR_CLK\", \"PS_GPIO2\", \"I2C0_SCL\", /* 10 - 14 */\n\t\t \"I2C0_SDA\", \"I2C1_SCL\", \"I2C1_SDA\", \"UART0_TXD\", \"UART0_RXD\", /* 15 - 19 */\n\t\t \"\", \"\", \"BUTTON\", \"LED\", \"\", /* 20 - 24 */\n\t\t \"\", \"PMU_INPUT\", \"SFP3_TX_DISABLE\", \"SFP2_TX_DISABLE\", \"SFP1_TX_DISABLE\", /* 25 - 29 */\n\t\t \"SFP0_TX_DISABLE\", \"\", \"PMU_GPO0\", \"PMU_GPO1\", \"PMU_GPO2\", /* 30 - 34 */\n\t\t \"PMU_GPO3\", \"PMU_GPO4\", \"PMU_GPO5\", \"PS_GPIO1\", \"SDIO_SEL\", /* 35 - 39 */\n\t\t \"SDIO_DIR_CMD\", \"SDIO_DIR_DAT0\", \"SDIO_DIR_DAT1\", \"SD_PWR_RST\", \"\", /* 40 - 44 */\n\t\t \"SDIO_DETECT\", \"SDIO_DAT0\", \"SDIO_DAT1\", \"SDIO_DAT2\", \"SDIO_DAT3\", /* 45 - 49 */\n\t\t \"SDIO_CMD\", \"SDIO_CLK\", \"USB_CLK\", \"USB_DIR\", \"USB_DATA2\", /* 50 - 54 */\n\t\t \"USB_NXT\", \"USB_DATA0\", \"USB_DATA1\", \"USB_STP\", \"USB_DATA3\", /* 55 - 59 */\n\t\t \"USB_DATA4\", \"USB_DATA5\", \"USB_DATA6\", \"USB_DATA7\", \"ENET_TX_CLK\", /* 60 - 64 */\n\t\t \"ENET_TX_D0\", \"ENET_TX_D1\", \"ENET_TX_D2\", \"ENET_TX_D3\", \"ENET_TX_CTRL\", /* 65 - 69 */\n\t\t \"ENET_RX_CLK\", \"ENET_RX_D0\", \"ENET_RX_D1\", \"ENET_RX_D2\", \"ENET_RX_D3\", /* 70 - 74 */\n\t\t \"ENET_RX_CTRL\", \"ENET_MDC\", \"ENET_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u15: gpio@20 { /* u15 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"MIO26_PMU_INPUT_LS\", \"DAC_AVTT_VOUT_SEL\", /* 0 - 3 */\n\t\t\t\t \"SI5381_INT_ALM\", \"IIC_MUX_RESET_B\", \"GEM3_EXP_RESET_B\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP_HSPC_PRSNT_M2C_B\", \"\", \"\", \"VCCINT_VRHOT_B\", /* 10 - 13 */\n\t\t\t\t \"\", \"8A34001_EXP_RST_B\", \"IRPS5401_ALERT_B\", \"INA226_PMBUS_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@75 { /* u17 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_io_bram_ps: ina226@41 { /* u57 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-io-bram-ps\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v8: ina226@42 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v8\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcc1v2: ina226@43 { /* u58 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@45 { /* u62 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@46 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtavcc\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tmgt1v2: ina226@47 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v2\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* Not in schematics */\n\t\t\t};\n\t\t\tmgt1v8: ina226@48 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgt1v8\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccint_ams: ina226@49 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint-ams\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avtt: ina226@4a { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avtt\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avccaux: ina226@4b { /* u124 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avccaux\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avcc: ina226@4c { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avcc\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tadc_avccaux: ina226@4d { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-adc-avccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tdac_avcc: ina226@4e { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-dac-avcc\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u104 - ir35215 0x10/0x40 */\n\t\t\t/* u127 - ir38164 0x1b/0x4b */\n\t\t\t/* u112 - ir38164 0x13/0x43 */\n\t\t\t/* u123 - ir38164 0x1c/0x4c */\n\n\t\t\tirps5401_44: irps5401@44 { /* IRPS5401 - u53 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x44>; /* i2c addr 0x14 */\n\t\t\t};\n\t\t\tirps5401_45: irps5401@45 { /* IRPS5401 - u55 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x45>; /* i2c addr 0x15 */\n\t\t\t};\n\t\t\t/* J21 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 {\n\t\tcompatible = \"nxp,pca9548\"; /* u20 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c_eeprom: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u21 */\n\t\t\t\tcompatible = \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c_si5381: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SI5381 - u43 */\n\t\t\t/*si5381: clock-generator@68 {\n\t\t\t\treg = <0x68>;\n\t\t\t};*/\n\t\t};\n\t\ti2c_si570_user_c0: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER C0 SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_user_c0\";\n\t\t\t};\n\t\t};\n\t\ti2c_si570_mgt: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u48 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_mgt\";\n\t\t\t};\n\t\t};\n\t\ti2c_8a34001: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* U409B - 8a34001 */\n\t\t};\n\t\ti2c_clk104: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* CLK104_SDA */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* RFMCP connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u22 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\t/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c_si570_psrefclk: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"si570_ps_ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n\t/* u38 MPS430 */\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_3_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_14_grp\", \"gpio0_15_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_4_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_16_grp\", \"gpio0_17_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* U11 and U12 MT25QU02GCBBE12 2Gb */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */\n\t\tspi-max-frequency = <108000000>; /* Based on DC1 spec */\n\t};\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tdisable-wp;\n\t/*\n\t * This property should be removed for supporting UHS mode\n\t */\n\tno-1-8-v;\n\txlnx,mio-bank = <1>;\n\tclk-phase-sd-hs = <120>, <60>;\n\tclk-phase-uhs-sdr25 = <132>, <60>;\n\tclk-phase-uhs-ddr50 = <153>, <48>;\n};\n\n&psgtr {\n\t/* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */\n\tclocks = <&si5381_6>;\n\tclock-names = \"ref2\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 2 PHY_TYPE_USB3 0 2>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\tsnps,usb3_lpm_capable;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zedboard.dtsi", "content": "/ {\n\tmodel = \"Zynq Zed Development Board\";\n\tcompatible = \"xlnx,zynq-zed\", \"xlnx,zynq-7000\";\n\n\tusb_phy0: phy0@e0002000 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = <0>;\n\t\treg = <0xe0002000 0x1000>;\n\t\tview-port = <0x0170>;\n\t\tdrv-vbus;\n\t};\n};\n\n&clkc {\n\tps-clk-frequency = <33333333>;\n};\n\n&gem0 {\n\tphy-handle = <ðernet_phy>;\n\tethernet_phy: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tdevice_type = \"ethernet-phy\";\n\t};\n};\n\n&qspi {\n\tbootph-all;\n\tnum-cs = <1>;\n\tflash@0 {\n\t\tcompatible = \"n25q128a11\", \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <1>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <50000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tpartition@qspi-fsbl-uboot {\n\t\t\tlabel = \"qspi-fsbl-uboot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t\tpartition@qspi-linux {\n\t\t\tlabel = \"qspi-linux\";\n\t\t\treg = <0x100000 0x500000>;\n\t\t};\n\t\tpartition@qspi-device-tree {\n\t\t\tlabel = \"qspi-device-tree\";\n\t\t\treg = <0x600000 0x20000>;\n\t\t};\n\t\tpartition@qspi-rootfs {\n\t\t\tlabel = \"qspi-rootfs\";\n\t\t\treg = <0x620000 0x5E0000>;\n\t\t};\n\t\tpartition@qspi-bitstream {\n\t\t\tlabel = \"qspi-bitstream\";\n\t\t\treg = <0xC00000 0x400000>;\n\t\t};\n\t};\n};\n\n&sdhci0 {\n\tbootph-all;\n};\n\n&uart1 {\n\tbootph-all;\n};\n\n&usb0 {\n\tdr_mode = \"host\";\n\tusb-phy = <&usb_phy0>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-a2197-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"Versal System Controller on a2197 board RevA\";\n\tcompatible = \"xlnx,zynqmp-a2197-revA\", \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n i2c0 = &i2c0;\n nvmem0 = &eeprom1;\n nvmem1 = &eeprom0;\n serial0 = &uart0;\n };\n\n};\n\n&i2c0 {\n\tbootph-all;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* this cover MGT board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tbootph-all;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tbootph-all;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tbootph-all;\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* This cover processor board */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\tbootph-all;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\tbootph-all;\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-e-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevA\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci1;\n nvmem0 = &eeprom;\n nvmem1 = &eeprom_ebm;\n nvmem2 = &eeprom_fmc1;\n nvmem3 = &eeprom_fmc2;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n };\n\n\n\tref_clk: ref-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tsi570_ddrdimm1_clk: si570-ddrdimm1-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tsi570_lpddr4_clk2: si570-lpddr4-clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570-lpddr4-clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4clk1>;\n\t};\n\n\tsi570_hsdp_clk: si570-hsdp-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi570_zsfp_clk: si570-zsfp-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_zsfp>;\n\t};\n\n\tsi570_user1_clk: si570-user1-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_user1>;\n\t};\n\n\tsi5332_1: si5332_1 { /* u142 - GEM0 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tina226-vccint {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;\n\t};\n\tina226-vcc-soc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;\n\t};\n\tina226-vcc-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc-pslp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;\n\t};\n\tina226-vcc-psfp {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;\n\t};\n\tina226-vccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;\n\t};\n\tina226-vccaux-pmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;\n\t};\n\tina226-vcco-500 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;\n\t};\n\tina226-vcco-501 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;\n\t};\n\tina226-vcco-502 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;\n\t};\n\tina226-vcco-503 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;\n\t};\n\tina226-vcc-1v8 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;\n\t};\n\tina226-vcc-3v3 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;\n\t};\n\tina226-vcc-1v2-ddr4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;\n\t};\n\tina226-vcc-1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vadj-fmc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;\n\t};\n\tina226-mgtyavcc {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;\n\t};\n\tina226-mgtyavtt {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;\n\t};\n\tina226-mgtyvccaux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;\n\t};\n\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n/* GEM SGMII */\n&psgtr {\n\tstatus = \"okay\";\n\t/* gem0 */\n\tclocks = <&si5332_1>;\n\tclock-names = \"ref0\";\n};\n\n&gem0 {\n\tphys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@0 { /* u131 M88E1512 */\n\t\t\treg = <0>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"ZU4_TRIGGER\", \"SYSCTLR_PB\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"\", /* 85 - 89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"PMBUS_ALERT\", \"\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ttca6416_u233: gpio@20 { /* u233 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"\", \"\", /* 0 - 3 */\n\t\t\t\t\"PMBUS2_INA226_ALERT\", \"\", \"\", \"MAX6643_FULLSPD\", /* 4 - 7 */\n\t\t\t\t\"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 10 - 13 */\n\t\t\t\t\"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* u152 IR35215 0x16/0x46 vcc_soc */\n\t\t\t/* u179 ir38164 0x19/0x49 vcco_500 */\n\t\t\t/* u181 ir38164 0x1a/0x4a vcco_501 */\n\t\t\t/* u183 ir38164 0x1b/0x4b vcco_502 */\n\t\t\t/* u185 ir38164 0x1e/0x4e vadj_fmc */\n\t\t\t/* u187 ir38164 0x1F/0x4f mgtyavcc */\n\t\t\t/* u189 ir38164 0x20/0x50 mgtyavtt */\n\t\t\t/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */\n\t\t\t/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */\n\n\t\t\tirps5401_47: irps5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* pmbus / i2c 0x17 */\n\t\t\t};\n\t\t\tirps5401_4c: irps5401@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* pmbus / i2c 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: irps5401@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* pmbus / i2c 0x1d */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccint\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <500>; /* R440 */\n\t\t\t\t/* 0.80V @ 32A 1 of 6 Phases*/\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-soc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <500>; /* R1702 */\n\t\t\t\t/* 0.80V @ 18A */\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pmc\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* R1214 */\n\t\t\t\t/* 0.78V @ 500mA */\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u162 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r1221 */\n\t\t\t\t/* 0.78V @ 4A */\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-pslp\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>; /* R1216 */\n\t\t\t\t/* 0.78V @ 1A */\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-psfp\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1219 */\n\t\t\t\t/* 0.78V @ 2A */\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* u39 8T49N240 */\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* R382 */\n\t\t\t\t/* 1.5V @ 3A */\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vccaux-pmc\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>; /* R1246 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u178 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-500\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <2000>; /* R1300 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u180 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-501\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <2000>; /* R1313 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u182 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-502\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <2000>; /* R1330 */\n\t\t\t\t/* 3.3V @ 5A */\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcco-503\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* R1229 */\n\t\t\t\t/* 1.8V @ 2A */\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u173 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v8\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>; /* R400 */\n\t\t\t\t/* 1.8V @ 6A */\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-3v3\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* R1232 */\n\t\t\t\t/* 3.3V @ 500mA */\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-1v2-ddr4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>; /* R1275 */\n\t\t\t\t/* 1.2V @ 4A */\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>; /* R1286 */\n\t\t\t\t/* 1.1V @ 4A */\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vadj-fmc\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>; /* R1350 */\n\t\t\t\t/* 1.5V @ 10A */\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavcc\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <2000>; /* R1367 */\n\t\t\t\t/* 0.88V @ 6A */\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyavtt\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>; /* R1384 */\n\t\t\t\t/* 1.2V @ 10A */\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-mgtyvccaux\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>; /* r1679 */\n\t\t\t\t/* 1.5V @ 500mA */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t\ti2c@5 { /* zSFP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_zsfp: clock-generator@5d { /* u192 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_zsfp_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* USER_SI570_1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_user1: clock-generator@5f { /* u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>; /* FIXME check address */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"si570_user1\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\n\t\t};\n\t\ti2c@7 { /* USER_SI570_2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* FIXME wires ready but chip is missing */\n\t\t};\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c-mux-idle-disconnect;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* 0x5c too */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* and connector J212D */\n\t\t\teeprom_ebm: eeprom@52 { /* x-ebm module */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\t\t};\n\t\tfmc1: i2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t\teeprom_fmc1: eeprom@50 {\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\tfmc2: i2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 FMC cards */\n\t\t\teeprom_fmc2: eeprom@50 {\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LPDDR4_SI570_CLK2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_lpddr4clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk2\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4clk1: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk1\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* 8A34001 - U219B and J310 connector */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n\ti2c-mux@75 { /* u214 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c-mux-idle-disconnect;\n\t\ti2c@0 { /* SFP0_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* SFP0 */\n\t\t};\n\t\ti2c@1 { /* SFP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@2 { /* QSFP1_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* QSFP1 */\n\t\t};\n\t\t/* 3 - 7 unused */\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-e-a2197-00-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevB System Controller\n *\n * (C) Copyright 2019-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-e-a2197-00-reva.dtsi\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Eval board RevB\"; /* VCK190/VMK180 */\n\tcompatible = \"xlnx,zynqmp-e-a2197-00-revB\", \"xlnx,zynqmp-a2197-revB\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\t/delete-node/ ina226-vcco-500;\n\t/delete-node/ ina226-vcco-501;\n\t/delete-node/ ina226-vcco-502;\n};\n\n&i2c0 {\n\ti2c-mux@74 { /* u33 */\n\t\ti2c@2 { /* PCIE_CLK */\n\t\t\t/delete-node/ clock-generator@6c;\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t/delete-node/ ina226@42;\n\t\t\t/delete-node/ ina226@43;\n\t\t\t/delete-node/ ina226@44;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-g-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller on MGT\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 MGT Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-g-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\t aliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n mmc0 = &sdhci0;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &dcc;\n usb0 = &usb0;\n };\n\n\n\tina226-u74 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;\n\t};\n\tina226-u75 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;\n\t};\n\tina226-u78 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;\n\t};\n\tina226-u79 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;\n\t};\n\tina226-u82 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;\n\t};\n\tina226-u84 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&gem0 { /* eth MDIO 76/77 */\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\tis-internal-pcspma;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 */\n\t\treg = <0>;\n\t\treset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 5 - 9 */\n\t\t \"\", \"\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"\", \"\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\ti2c-mux@74 { /* u94 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@50 { /* u96 - 24LC32A - 256B */\n\t\t\t\tcompatible = \"atmel,24c32\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* CM_I2C_SCL - Samtec */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* PMBUS - AFX_PMBUS */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\ttps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\ttps544@10 { /* u73 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\ttps544@11 { /* u76 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\ttps544@12 { /* u77 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\ttps544@13 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\ttps544@14 { /* u81 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\ttps544@15 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\ttps544@16 { /* u63 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\ttps544@17 { /* u66 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\ttps544@18 { /* u67 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\ttps544@19 { /* u69 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\ttps544@1d { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\ttps544@1e { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\ttps544@1f { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t\ttps544@20 { /* u71 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\t\t\tu74: ina226@40 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u74\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu75: ina226@41 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u75\"\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu78: ina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u78\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tu79: ina226@43 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u79\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu82: ina226@44 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u82\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tu84: ina226@45 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-u84\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\ttps53681@60 { /* u53- 0xc0 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* fmc1 via JA2G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\teeprom_fmc1: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* fmc2 via JA3G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\teeprom_fmc2: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* fmc3 via JA4G */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\teeprom_fmc3: eeprom@50 { /* on FMC */\n\t\t\t\tcompatible = \"atmel,24c04\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* ddr dimm */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"high-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-m-a2197-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-01-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n spi0 = &qspi;\n };\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\tina226-vcc0v6-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc0v6_lp4: ina226@49 { /* u101 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc0v6-lp4\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@60 { /* u69 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@5d { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_LP4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n status = \"disabled\"; /* not at mem board */\n};\n\n&dwc3_1 {\n /delete-property/ phy-names ;\n /delete-property/ phys ;\n maximum-speed = \"high-speed\";\n snps,dis_u2_susphy_quirk ;\n snps,dis_u3_susphy_quirk ;\n status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-m-a2197-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-02-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n spi0 = &qspi;\n };\n\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@60 { /* u69 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* C0_DDR4_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\ti2c@6 { /* C2_DDR5_RDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\ti2c@7 { /* C3_DDR4_UDIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_RLD3 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_RLD3_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_DDR5 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_DDR5_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-m-a2197-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Memory Char board RevA\";\n\tcompatible = \"xlnx,zynqmp-m-a2197-03-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t \"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n spi0 = &qspi;\n };\n\n\n\tina226-vcc-aux {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;\n\t};\n\tina226-vcc-ram {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;\n\t};\n\tina226-vcc1v1-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;\n\t};\n\tina226-vcc1v2-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;\n\t};\n\tina226-vdd1-1v8-lp4 {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;\n\t};\n};\n\n&qspi {\n\tnum-cs = <2>;\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* 32MB */\n\t\treg = <0>, <1>;\n\t\tparallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>; /* FIXME tap delay */\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tstatus = \"disable\";\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tphy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;\n\tphy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */\n\t\treg = <0>;\n/*\t\txlnx,phy-type = ; */\n\t};\n/*\tphy-names = \"...\";\n\tphys = <&lane0 PHY_TYPE_SGMII ... >\n\tNote: lane0 sgmii/lane1 usb3 */\n};\n\n&gpio {\n\tgpio-line-names = \"SCLK_OUT\", \"MISO_MO1\", \"MO2\", \"MO3\", \"MOSI_MIO0\", /* 0 - 4 */\n\t\t \"N_SS_OUT\", \"\", \"SYS_CTRL0\", \"SYS_CTRL1\", \"SYS_CTRL2\", /* 5 - 9 */\n\t\t \"SYS_CTRL3\", \"SYS_CTRL4\", \"SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"RXD0_IN\", \"TXD0_OUT\", \"TXD1_OUT\", \"RXD1_IN\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u46 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */\n\t\ti2c@0 { /* PMBUS must be enabled via SW21 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\treg_vcc1v2_lp4: tps544@15 { /* u97 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u95 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vdd1_1v8_lp4: tps544@17 { /* u99 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\t/* UTIL_PMBUS connection */\n\t\t\treg_vcc1v8: tps544@13 { /* u92 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u93 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc5v0: tps544@1e { /* u94 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@18 { /* u3022 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tvcc_aux: ina226@42 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-aux\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc-ram\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@46 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v1-lp4\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v2_lp4: ina226@47 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vcc1v2-lp4\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvdd1_1v8_lp4: ina226@48 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\t#io-channel-cells = <1>;\n\t\t\t\tlabel = \"ina226-vdd1-1v8-lp4\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\treg_vccint: tps53681@60 { /* u69 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc_pmc: tps544@7 { /* u80 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x7>;\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u82 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u83 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u84 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_pmc: tps544@e { /* u87 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u88 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u89 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u90 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u91 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* MEM PMBUS - FIXME bug in schematics */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\t/* reg = <3>; */\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to U20G */\n\t\t};\n\t\ti2c@5 { /* DDR4_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n/* TODO teensy via U30 PCA9543A bus 1 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u47 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u26 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"REF_CLK\"; /* FIXME */\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec U20D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* C0_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_c0_ddr4: clock-generator@55 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C0_DD4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* C1_SODIMM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_c1_lp4: clock-generator@55 { /* u7 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C1_SODIMM_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* C2_QDRIV */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_c2_lp4: clock-generator@55 { /* u10 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C2_QDRIV_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@5 { /* C3_DDR4 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_c3_lp4: clock-generator@55 { /* u15 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x55>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <30000000>;\n\t\t\t\tclock-frequency = <30000000>;\n\t\t\t\tclock-output-names = \"C3_LP4_SI570_CLK\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u19 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"HSDP_SI570\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&dwc3_0 {\n\tdr_mode = \"host\";\n\t/* dr_mode = \"peripheral\"; */\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"disabled\"; /* not at mem board */\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-01-revA\", \"xlnx,zynqmp-x-prc-01\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\",\"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-02-revA\", \"xlnx,zynqmp-x-prc-02\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-03-revA\", \"xlnx,zynqmp-x-prc-03\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tx_prc_si5338: clock-generator@70 { /* U9 */\n\t\t\t\tcompatible = \"silabs,si5338\";\n\t\t\t\treg = <0x70>; /* FIXME */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-04-revA\", \"xlnx,zynqmp-x-prc-04\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5)\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-x-prc-05-revA\", \"xlnx,zynqmp-x-prc-05\", \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\n\tref_clk: ref_clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4_dimm1_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4_dimm2_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp_si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 174 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\t/* Connection via Samtec J212D */\n\t\t\t/* Use for storing information about X-PRC card */\n\t\t\tx_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */\n\t\t\t\tcompatible = \"atmel,24c02\";\n\t\t\t\treg = <0x52>;\n\t\t\t};\n\n\t\t\t/* Use for setting up certain features on X-PRC card */\n\t\t\tx_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */\n\t\t\t\tcompatible = \"nxp,pca9534\";\n\t\t\t\treg = <0x22>;\n\t\t\t\tgpio-controller; /* IRQ not connected */\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-line-names = \"sw4_1\", \"sw4_2\", \"sw4_3\", \"sw4_4\",\n\t\t\t\t\t\t \"\", \"\", \"\", \"\";\n\t\t\t\tgtr-sel0 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <0 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_1\";\n\t\t\t\t};\n\t\t\t\tgtr-sel1 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <1 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_2\";\n\t\t\t\t};\n\t\t\t\tgtr-sel2 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <2 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_3\";\n\t\t\t\t};\n\t\t\t\tgtr-sel3 {\n\t\t\t\t\tgpio-hog;\n\t\t\t\t\tgpios = <3 0>;\n\t\t\t\t\tinput; /* FIXME add meaning */\n\t\t\t\t\tline-name = \"sw4_4\";\n\t\t\t\t};\n\t\t\t};\n\t\t\tsi570_gem_tsu: clock-generator@5d { /* u164 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>; /* FIXME */\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t\tclock-output-names = \"si570_gem_tsu_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\tclock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */\n\t\t\t\t#clock-cells = <1>; /* author David Cater */\n\t\t\t\tcompatible = \"idt,8t49n240\", \"idt,8t49n241\"; /* FIXME no driver for 240 */\n\t\t\t\treg = <0xd8>;\n\t\t\t\t/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */\n\t\t\t\t/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */\n\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-p-a2197-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal a2197 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"Versal System Controller on a2197 Processor Char board RevA\"; /* Tenzing */\n\tcompatible = \"xlnx,zynqmp-p-a2197-00-revA\", \"xlnx,zynqmp-a2197-revA\",\n\t\t\t\t\"xlnx,zynqmp-a2197\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n usb0 = &usb0;\n usb1 = &usb1;\n };\n\n\n\tref_clk: ref-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ref_clk>;\n\t};\n\n\tddr4_dimm1_si570: ddr4-dimm1-si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm1>;\n\t};\n\n\tddr4_dimm2_si570: ddr4-dimm2-si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_ddr_dimm2>;\n\t};\n\n\tlpddr4_si570: lpddr4-si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_lpddr4>;\n\t};\n\n\thsdp_si570: hsdp-si570 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&si570_hsdp>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&sdhci1 { /* sd1 MIO45-51 cd in place */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"\", \"\", \"\", \"\", \"\", /* 0 - 4 */\n\t\t \"\", \"\", \"DC_SYS_CTRL0\", \"DC_SYS_CTRL1\", \"DC_SYS_CTRL2\", /* 5 - 9 */\n\t\t \"DC_SYS_CTRL3\", \"DC_SYS_CTRL4\", \"DC_SYS_CTRL5\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"UART1_TXD_OUT\", \"UART1_RXD_IN\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD_B\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\", /* 60 - 64 */\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\", /* 65 - 69 */\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\", /* 70 - 74 */\n\t\t \"USB1_DATA7\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"DC_PRSNT\", \"SYSCTLR_POWER_EN\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"SYSCTLR_LP_I2C_SM_ALERT\", /* 85 -89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"VCCO_500_RBIAS\", \"VCCO_501_RBIAS\", \"VCCO_502_RBIAS\", \"VCCO_500_RBIAS_LED\", /* 95 - 99 */\n\t\t \"VCCO_501_RBIAS_LED\", \"VCCO_502_RBIAS_LED\", \"SYSCTLR_VCCINT_EN\", \"SYSCTLR_VCC_IO_SOC_EN\", \"SYSCTLR_VCC_PMC_EN\", /* 100 - 104 */\n\t\t \"SYSCTLR_VCC_RAM_EN\", \"SYSCTLR_VCC_PSLP_EN\", \"SYSCTLR_VCC_PSFP_EN\", \"SYSCTLR_VCCAUX_EN\", \"SYSCTLR_VCCAUX_PMC_EN\", /* 105 - 109 */\n\t\t \"SYSCTLR_VCCO_500_EN\", \"SYSCTLR_VCCO_501_EN\", \"SYSCTLR_VCCO_502_EN\", \"SYSCTLR_VCCO_503_EN\", \"SYSCTLR_VCC1V8_EN\", /* 110 - 114 */\n\t\t \"SYSCTLR_VCC3V3_EN\", \"SYSCTLR_VCC1V2_DDR4_EN\", \"SYSCTLR_VCC1V1_LP4_EN\", \"SYSCTLR_VDD1_1V8_LP4_EN\", \"SYSCTLR_VADJ_FMC_EN\", /* 115 - 119 */\n\t\t \"SYSCTLR_MGTYAVCC_EN\", \"SYSCTLR_MGTYAVTT_EN\", \"SYSCTLR_MGTYVCCAUX_EN\", \"SYSCTLR_UTIL_1V13_EN\", \"SYSCTLR_UTIL_1V8_EN\", /* 120 - 124 */\n\t\t \"SYSCTLR_UTIL_2V5_EN\", \"FMCP1_FMC_PRSNT_M2C_B\", \"FMCP2_FMC_PRSNT_M2C_B\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"FMCP2_FMCP_PRSNT_M2C_B\", /* 125 - 129 */\n\t\t \"PMBUS1_INA226_ALERT\", \"PMBUS2_INA226_ALERT\", \"SYSCTLR_USBC_SBU1\", \"SYSCTLR_USBC_SBU2\", \"TI_CABLE1\", /* 130 - 134 */\n\t\t \"TI_CABLE2\", \"SYSCTLR_MIC2005_EN_B\", \"SYSCTLR_MIC2005_FAULT_B\", \"SYSCTLR_TUSB320_INT_B\", \"SYSCTLR_TUSB320_ID\", /* 135 - 139 */\n\t\t \"PMBUS1_ALERT\", \"PMBUS2_ALERT\", \"SYSCTLR_ETH_RESET_B\", \"SYSCTLR_VCC0V85_TG\", \"MAX6643_OT_B\", /* 140 - 144 */\n\t\t \"MAX6643_FANFINAL_B\", \"MAX6643_FULLSPD\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\ti2c@0 { /* PMBUS1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J98 */\n\t\t\treg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x7>;\n\t\t\t\tregulator-name = \"reg_vcc_fmc\";\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <2600000>;\n\t\t\t\t/* enable-gpio = <&gpio0 23 0x4>; optional */\n\t\t\t};\n\t\t\treg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\t\t\treg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\t\t\treg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\treg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t\t/* vccint, vcc_io_soc */\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* PMBUS1_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvcc_fmc: ina226@42 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u82 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* PMBUS2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* On connector J104 */\n\t\t\treg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xe>;\n\t\t\t};\n\t\t\treg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0xf>;\n\t\t\t};\n\t\t\treg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\treg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\treg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\treg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x19>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\treg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1c>;\n\t\t\t};\n\t\t\treg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\treg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1e>;\n\t\t\t};\n\t\t\treg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */\n\t\t\t\tcompatible = \"ti,tps544b25\"; /* Documentation/hwmon/pmbus - wiring is missing */\n\t\t\t\treg = <0x1f>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 { /* PMBUS2_INA226 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts comming to SC */\n\t\t\tvccaux: ina226@40 { /* u89 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_fmc: ina226@41 { /* u91 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_500: ina226@42 { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_501: ina226@43 { /* u94 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@44 { /* u96 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_503: ina226@45 { /* u98 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v8: ina226@46 { /* u100 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_3v3: ina226@47 { /* u103 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_1v2_ddr4: ina226@48 { /* u105 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u107 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u110 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtyavcc: ina226@4b { /* u112 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyavtt: ina226@4c { /* u113 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t\tmgtyvccaux: ina226@4d { /* u116 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_bat: ina226@4e { /* u12 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\t/* 10 ohm real value - setup 1ohm because of driver limitation */\n\t\t\t\tshunt-resistor = <1000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* LP_I2C_SM */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* connected to J212G */\n\t\t\t/* zynqmp sm alert or samtec J212H */\n\t\t};\n\t\t/* 5-7 unused */\n\t};\n};\n\n/* TODO sysctrl via J239 */\n/* TODO samtec J212G/H via J242 */\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\n\t/* Must be enabled via J242 */\n\teeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */\n\t\tcompatible = \"atmel,24c02\";\n\t\treg = <0x51>;\n\t};\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 { /* DC_I2C */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@60 { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* 570JAC000900DG */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* FMCP1_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* FMCP2_IIC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* FIXME connection to Samtec J53C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@3 { /* DDR4_DIMM1 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_ddr_dimm1: clock-generator@60 { /* u2 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm1_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@4 { /* DDR4_DIMM2 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi570_ddr_dimm2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_ddrdimm2_clk\";\n\t\t\t};\n\t\t\t/* 0x50 SPD? */\n\t\t};\n\t\ti2c@5 { /* LPDDR4_SI570_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tsi570_lpddr4: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"si570_lpddr4_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@6 { /* HSDP_SI570 */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tsi570_hsdp: clock-generator@5d { /* u5 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>; /* FIXME addr */\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <156250000>;\n\t\t\t\tclock-output-names = \"si570_hsdp_clk\";\n\t\t\t};\n\t\t};\n\t\ti2c@7 { /* PCIE_CLK */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */\n\t\t\t/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */\n\t\t\t/* u39 8T49N240 - pcie clocking 3 */\n\t\t};\n\t};\n};\n\n&usb0 {\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&dwc3_1 {\n\t/delete-property/ phy-names ;\n\t/delete-property/ phys ;\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n\tsnps,dis_u2_susphy_quirk ;\n\tsnps,dis_u3_susphy_quirk ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sc-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP Generic System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/net/ti-dp83867.h\"\n\n/ {\n\tmodel = \"ZynqMP Generic System Controller\";\n\tcompatible = \"xlnx,zynqmp-sc-revB\", \"xlnx,zynqmp-sc\", \"xlnx,zynqmp\";\n\n\taliases {\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n mmc1 = &sdhci1;\n nvmem0 = &eeprom;\n rtc0 = &rtc;\n serial0 = &uart0;\n serial1 = &uart1;\n serial2 = &dcc;\n spi0 = &qspi;\n spi1 = &spi0;\n spi2 = &spi1;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tkey-fwuen {\n\t\t\tlabel = \"sw16\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds40-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t\tds44-led {\n\t\t\tlabel = \"status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tsi5332_2: si5332_2 { /* u42 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <26000000>;\n\t};\n\tpwm-fan {\n\t\tcompatible = \"pwm-fan\";\n\t\tpwms = <&ttc0 2 40000 1>;\n\t};\n\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\"QSPI_CS_B\", \"\", \"LED1\", \"LED2\", \"\", /* 5 - 9 */\n\t\t\"\", \"ZU4_TRIGGER\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\"I2C1_SDA\", \"UART0_RXD\", \"UART0_TXD\", \"\", \"\", /* 25 - 29 */\n\t\t\"\", \"\", \"\", \"\", \"I2C0_SCL\", /* 30 - 34 */\n\t\t\"I2C0_SDA\", \"UART1_TXD\", \"UART1_RXD\", \"GEM_TX_CLK\", \"GEM_TX_D0\", /* 35 - 39 */\n\t\t\"GEM_TX_D1\", \"GEM_TX_D2\", \"GEM_TX_D3\", \"GEM_TX_CTL\", \"GEM_RX_CLK\", /* 40 - 44 */\n\t\t\"GEM_RX_D0\", \"GEM_RX_D1\", \"GEM_RX_D2\", \"GEM_RX_D3\", \"GEM_RX_CTL\", /* 45 - 49 */\n\t\t\"GEM_MDC\", \"GEM_MDIO\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t\"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t\"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\"\", \"\", \"ETH_RESET_B\", /* 75 - 77, MIO end and EMIO start */\n\t\t\"\", \"\", /* 78 - 79 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 85 -89 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_gem1_default>;\n\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy0: ethernet-phy@1 {\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\treg = <1>;\n\t\t\tti,rx-internal-delay = ;\n\t\t\tti,tx-internal-delay = ;\n\t\t\tti,fifo-depth = ;\n\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\treset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;\n\t\t\treset-assert-us = <100>;\n\t\t\treset-deassert-us = <280>;\n\t\t};\n\t};\n};\n\n&i2c0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\tclock-frequency = <100000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n};\n\n&i2c1 { /* i2c1 MIO 24-25 */\n\tbootph-all;\n\tclock-frequency = <100000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t/* No reason to do pinctrl setup at u-boot stage */\n\t/* Use for storing information about SC board */\n\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\treg = <0x54>; /* & 0x5c */\n\t\tbootph-all;\n\t};\n};\n\n/* USB 3.0 only */\n&psgtr {\n\t/* nc, nc, usb3 */\n\tclocks = <&si5332_2>;\n\tclock-names = \"ref2\";\n};\n\n&qspi { /* MIO 0-5 */\n\t/* QSPI should also have PINCTRL setup */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartition@0 {\n\t\t\tlabel = \"Image Selector\";\n\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@80000 {\n\t\t\tlabel = \"Image Selector Golden\";\n\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@100000 {\n\t\t\tlabel = \"Persistent Register\";\n\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@120000 {\n\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@140000 {\n\t\t\tlabel = \"Open_1\";\n\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@f00000 {\n\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@f80000 {\n\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t};\n\t\tpartition@1c80000 {\n\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@1d00000 {\n\t\t\tlabel = \"Open_2\";\n\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t};\n\t\tpartition@1e00000 {\n\t\t\tlabel = \"Recovery Image\";\n\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2000000 {\n\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2200000 {\n\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2220000 {\n\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@2240000 {\n\t\t\tlabel = \"SHA256\";\n\t\t\treg = <0x2240000 0x40000>; /* 256B but 256KB sector */\n\t\t\tread-only;\n\t\t\tlock;\n\t\t};\n\t\tpartition@2280000 {\n\t\t\tlabel = \"Secure OS Storage\";\n\t\t\treg = <0x2280000 0x20000>; /* 128KB */\n\t\t};\n\t\tpartition@22A0000 {\n\t\t\tlabel = \"User\";\n\t\t\treg = <0x22A0000 0x1d60000>; /* 29.375 MB */\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&ttc0 {\n\t#pwm-cells = <3>;\n};\n\n&uart1 { /* uart0 MIO36-37 */\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart1_default>;\n};\n\n&pinctrl0 { /* required by spec */\n\tstatus = \"okay\";\n\tpinctrl_uart1_default: uart1-default {\n\t\tconf {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO37\";\n\t\t\tbias-high-impedance;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO36\";\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"uart1_9_grp\";\n\t\t\tfunction = \"uart1\";\n\t\t};\n\t};\n\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tconf {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"i2c1_6_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tconf {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tmux {\n\t\t\tgroups = \"gpio0_24_grp\", \"gpio0_25_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\t};\n\n\tpinctrl_gem1_default: gem1-default {\n\t\tconf {\n\t\t\tgroups = \"ethernet1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\n\t\tconf-rx {\n\t\t\tpins = \"MIO44\", \"MIO46\", \"MIO48\";\n\t\t\tbias-high-impedance;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-bootstrap {\n\t\t\tpins = \"MIO45\", \"MIO47\", \"MIO49\";\n\t\t\tbias-disable;\n\t\t\tlow-power-disable;\n\t\t};\n\n\t\tconf-tx {\n\t\t\tpins = \"MIO38\", \"MIO39\", \"MIO40\",\n\t\t\t\t\"MIO41\", \"MIO42\", \"MIO43\";\n\t\t\tbias-disable;\n\t\t\tlow-power-enable;\n\t\t};\n\n\t\tconf-mdio {\n\t\t\tgroups = \"mdio1_0_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux-mdio {\n\t\t\tfunction = \"mdio1\";\n\t\t\tgroups = \"mdio1_0_grp\";\n\t\t};\n\n\t\tmux {\n\t\t\tfunction = \"ethernet1\";\n\t\t\tgroups = \"ethernet1_0_grp\";\n\t\t};\n\t};\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sc-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP Generic System Controller\n *\n * Copyright (C) 2021-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sc-revb.dtsi\"\n\n/ {\n\tmodel = \"ZynqMP Generic System Controller\";\n\tcompatible = \"xlnx,zynqmp-sc-revC\", \"xlnx,zynqmp-sc\", \"xlnx,zynqmp\";\n};\n\n&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */\n\t/delete-node/ mdio;\n\n\tmdio: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy0: ethernet-phy@1 { /* ADI1300 */\n\t\t\t#phy-cells = <1>;\n\t\t\tcompatible = \"ethernet-phy-id0283.bc30\";\n\t\t\treg = <1>;\n\t\t adi,rx-internal-delay-ps = <2400>;\n\t\t\tadi,tx-internal-delay-ps = <2400>;\n\t\t\tadi,fifo-depth-bits = <8>;\n\t\t\treset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;\n\t\t\treset-assert-us = <10>;\n\t\t\treset-deassert-us = <5000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sc-vek280-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VEK280 revA\n *\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n\n&{/} {\n\tcompatible = \"xlnx,zynqmp-sc-vek280-revA\", \"xlnx,zynqmp-vek280-revA\",\n\t\t \"xlnx,zynqmp-vek280\", \"xlnx,zynqmp\";\n\n\tvc7_xin: vc7-xin {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <50000000>;\n\t};\n\n\tgtclk1_1: sys-clk-0 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 0>;\n\t};\n\n\tgtclk1_2: sys-clk-1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 1>;\n\t};\n\n\tgtclk1_3: sys-clk-2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 2>;\n\t};\n\n\tgtclk1_6: gtclk1-out6 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 3>;\n\t};\n\n\tgtclk1_7: gtclk1-out7 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 4>;\n\t};\n\n\tgtclk1_8: gtclk1-out8 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 5>;\n\t};\n\n\tgtclk1_10: ps-ref-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 6>;\n\t};\n\n\tgtclk1_11: gtclk1-out11 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&vc7 7>;\n\t};\n};\n\n&i2c0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\ttca6416_u233: gpio@20 { /* u233 */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"\", \"\", \"SFP_MOD_ABS\", \"SFP_TX_DISABLE\", /* 0 - 3 */\n\t\t\t\t\"PMBUS2_INA226_ALERT\", \"\", \"\", \"\", /* 4 - 7 */\n\t\t\t\t\"FMCP1_FMC_PRSNT_M2C_B\", \"\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"\", /* 10 - 13 */\n\t\t\t\t\"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\tir35215_46: pmic@46 { /* IR35215 - u152 */\n\t\t\t\tcompatible = \"infineon,ir35215\";\n\t\t\t\treg = <0x46>; /* i2c addr - 0x16 */\n\t\t\t};\n\t\t\tirps5401_47: pmic5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* i2c addr 0x17 */\n\t\t\t};\n\t\t\tirps5401_48: pmic@48 { /* IRPS5401 - u279 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x48>; /* i2c addr 0x18 */\n\t\t\t};\n\t\t\tir38064_49: regulator@49 { /* IR38064 - u295 */\n\t\t\t\tcompatible = \"infineon,ir38064\";\n\t\t\t\treg = <0x49>; /* i2c addr 0x19 */\n\t\t\t};\n\t\t\tirps5401_4c: pmic@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: pmic@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* i2c addr 0x1d */\n\t\t\t};\n\t\t\tir38060_4e: regulator@4e { /* IR38060 - u282 */\n\t\t\t\tcompatible = \"infineon,ir38060\";\n\t\t\t\treg = <0x4e>; /* i2c addr 0x1e */\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* alerts coming to u233 and SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <500>; /* r440 */\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <500>; /* r1702 */\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* r382 */\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u355 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r2417 */\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>; /* r1830 */\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u260 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* r2386 */\n\t\t\t};\n\t\t\tvcco_hdio: ina226@46 { /* u356 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>; /* r2392 */\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpmbus2_ina226_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* alerts coming to u233 and SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>; /* r2384 */\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>; /* r2000 */\n\t\t\t};\n\t\t\tmgtavcc: ina226@42 { /* u265 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>; /* r1829 */\n\t\t\t};\n\t\t\tvcc1v5: ina226@43 { /* u264 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>; /* r2397 */\n\t\t\t};\n\t\t\tvcco_mio: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>; /* r2401 */\n\t\t\t};\n\t\t\tmgtavtt: ina226@46 { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <500>; /* r1384 */\n\t\t\t};\n\t\t\tvcco_502: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>; /* r1994 */\n\t\t\t};\n\t\t\tmgtvccaux: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>; /* r2384 */\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u306 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <500>; /* r2064 */\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u281 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>; /* r2031 */\n\t\t\t};\n\t\t\tlpdmgtyavcc: ina226@4b { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>; /* r2004 */\n\t\t\t};\n\t\t\tlpdmgtyavtt: ina226@4c { /* u309 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>; /* r1229 */\n\t\t\t};\n\t\t\tlpdmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>; /* r1679 */\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\trc21008a_gtclk1: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* connector j374 */\n\t\t\t/* rc21008a at 0x9 u299 */\n\t\t\tvc7: clock-generator@9 {\n\t\t\t\tcompatible = \"renesas,rc21008a\";\n\t\t\t\treg = <0x9>;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&vc7_xin>;\n\t\t\t\tclock-names = \"xin\";\n\t\t\t};\n\t\t};\n\t\tfmcp1_iic: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* to j51c */\n\t\t};\n\t\tsfp: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* sfp+ connector J376 */\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sc-vek280-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VEK280 revB\n *\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sc-vek280-reva.dtsi\"\n\n&{/} {\n\tcompatible = \"xlnx,zynqmp-sc-vek280-revB\", \"xlnx,zynqmp-vek280-revB\",\n\t\t \"xlnx,zynqmp-vek280\", \"xlnx,zynqmp\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sm-k24-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SM-K24 RevA\n *\n * (C) Copyright 2020 - 2021, Xilinx, Inc.\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sm-k26-reva.dtsi\"\n\n/ {\n\tmodel = \"ZynqMP SM-K24 RevA/B/1\";\n\tcompatible = \"xlnx,zynqmp-sm-k24-rev1\", \"xlnx,zynqmp-sm-k24-revB\",\n\t\t \"xlnx,zynqmp-sm-k24-revA\", \"xlnx,zynqmp-sm-k24\",\n\t\t \"xlnx,zynqmp\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sm-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SM-K26 rev1/B/A\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n\n/ {\n\tmodel = \"ZynqMP SM-K26 Rev1/B/A\";\n\tcompatible = \"xlnx,zynqmp-sm-k26-rev1\", \"xlnx,zynqmp-sm-k26-revB\",\n\t\t \"xlnx,zynqmp-sm-k26-revA\", \"xlnx,zynqmp-sm-k26\",\n\t\t \"xlnx,zynqmp\";\n\n\taliases {\n\t\tgpio0 = &gpio;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tnvmem0 = &eeprom;\n\t\tnvmem1 = &eeprom_cc;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t\tspi0 = &qspi;\n\t\tspi1 = &spi0;\n\t\tspi2 = &spi1;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial1:115200n8\";\n\t};\n\n\treserved-memory {\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tpmu_region: pmu@7ff00000 {\n\t\t\treg = <0x0 0x7ff00000 0x0 0x100000>;\n\t\t\tno-map;\n\t\t};\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tkey-fwuen {\n\t\t\tlabel = \"fwuen\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds35-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds36-led {\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tams {\n\t\tcompatible = \"iio-hwmon\";\n\t\tio-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,\n\t\t\t<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,\n\t\t\t<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,\n\t\t\t<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,\n\t\t\t<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,\n\t\t\t<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,\n\t\t\t<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,\n\t\t\t<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,\n\t\t\t<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,\n\t\t\t<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;\n\t};\n\tpwm-fan {\n\t\tcompatible = \"pwm-fan\";\n\t\tpwms = <&ttc0 2 40000 0>;\n\t};\n};\n\n&modepin_gpio {\n\tlabel = \"modepin\";\n};\n\n&ttc0 {\n\t#pwm-cells = <3>;\n};\n\n&pinctrl0 {\n status = \"okay\";\n pinctrl_sdhci0_default: sdhci0-default {\n conf {\n groups = \"sdio0_0_grp\";\n slew-rate = ;\n power-source = ;\n bias-disable;\n };\n\n mux {\n groups = \"sdio0_0_grp\";\n function = \"sdio0\";\n };\n };\n};\n\n&qspi { /* MIO 0-5 - U143 */\n\tspi_flash: flash@0 { /* MT25QU512A */\n\t\tcompatible = \"mt25qu512a\", \"jedec,spi-nor\"; /* 64MB */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <40000000>; /* 40MHz */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Image Selector\";\n\t\t\t\treg = <0x0 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"Image Selector Golden\";\n\t\t\t\treg = <0x80000 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"Persistent Register\";\n\t\t\t\treg = <0x100000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@120000 {\n\t\t\t\tlabel = \"Persistent Register Backup\";\n\t\t\t\treg = <0x120000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@140000 {\n\t\t\t\tlabel = \"Open_1\";\n\t\t\t\treg = <0x140000 0xC0000>; /* 768KB */\n\t\t\t};\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"Image A (FSBL, PMU, ATF, U-Boot)\";\n\t\t\t\treg = <0x200000 0xD00000>; /* 13MB */\n\t\t\t};\n\t\t\tpartition@f00000 {\n\t\t\t\tlabel = \"ImgSel Image A Catch\";\n\t\t\t\treg = <0xF00000 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@f80000 {\n\t\t\t\tlabel = \"Image B (FSBL, PMU, ATF, U-Boot)\";\n\t\t\t\treg = <0xF80000 0xD00000>; /* 13MB */\n\t\t\t};\n\t\t\tpartition@1c80000 {\n\t\t\t\tlabel = \"ImgSel Image B Catch\";\n\t\t\t\treg = <0x1C80000 0x80000>; /* 512KB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@1d00000 {\n\t\t\t\tlabel = \"Open_2\";\n\t\t\t\treg = <0x1D00000 0x100000>; /* 1MB */\n\t\t\t};\n\t\t\tpartition@1e00000 {\n\t\t\t\tlabel = \"Recovery Image\";\n\t\t\t\treg = <0x1E00000 0x200000>; /* 2MB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@2000000 {\n\t\t\t\tlabel = \"Recovery Image Backup\";\n\t\t\t\treg = <0x2000000 0x200000>; /* 2MB */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@2200000 {\n\t\t\t\tlabel = \"U-Boot storage variables\";\n\t\t\t\treg = <0x2200000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@2220000 {\n\t\t\t\tlabel = \"U-Boot storage variables backup\";\n\t\t\t\treg = <0x2220000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@2240000 {\n\t\t\t\tlabel = \"SHA256\";\n\t\t\t\treg = <0x2240000 0x40000>; /* 256B but 256KB sector */\n\t\t\t\tread-only;\n\t\t\t\tlock;\n\t\t\t};\n\t\t\tpartition@2280000 {\n\t\t\t\tlabel = \"Secure OS Storage\";\n\t\t\t\treg = <0x2280000 0x20000>; /* 128KB */\n\t\t\t};\n\t\t\tpartition@22A0000 {\n\t\t\t\tlabel = \"User\";\n\t\t\t\treg = <0x22A0000 0x1d60000>; /* 29.375 MB */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_sdhci0_default>;\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n\tassigned-clock-rates = <187498123>;\n};\n\n&spi1 { /* MIO6, 9-11 */\n\tlabel = \"TPM\";\n\tnum-cs = <1>;\n\ttpm@0 { /* slm9670 - U144 */\n\t\tcompatible = \"infineon,slb9670\", \"tcg,tpm_tis-spi\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <18500000>;\n\t};\n};\n\n&i2c1 {\n\tbootph-all;\n\tclock-frequency = <400000>;\n\tscl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\n\teeprom: eeprom@50 { /* u46 - also at address 0x58 */\n\t\tbootph-all;\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x50>;\n\t\t/* WP pin EE_WP_EN connected to slg7x644092@68 */\n\t};\n\n\teeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */\n\t\tbootph-all;\n\t\tcompatible = \"st,24c64\", \"atmel,24c64\"; /* st m24c64 */\n\t\treg = <0x51>;\n\t};\n\n\t/* da9062@30 - u170 - also at address 0x31 */\n\t/* da9131@33 - u167 */\n\tda9131: pmic@33 {\n\t\tcompatible = \"dlg,da9131\";\n\t\treg = <0x33>;\n\t\tregulators {\n\t\t\tda9131_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9131_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t\tda9131_buck2: buck2 {\n\t\t\t\tregulator-name = \"da9131_buck2\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* da9130@32 - u166 */\n\tda9130: pmic@32 {\n\t\tcompatible = \"dlg,da9130\";\n\t\treg = <0x32>;\n\t\tregulators {\n\t\t\tda9130_buck1: buck1 {\n\t\t\t\tregulator-name = \"da9130_buck1\";\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-always-on;\n\t\t\t};\n\t\t};\n\t};\n\n\t/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */\n\t/*\n\t * stdp4320 - u27 FW has below two issues to be fixed in next board revision.\n\t * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.\n\t * Address conflict with slg7x644091@70 making both the devices NOT accessible.\n\t * With the FW fix, stdp4320 should respond to address 0x73 only.\n\t */\n\t/* slg7x644092@68 - u169 */\n\t/* Also connected via JA1C as C23/C24 */\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t\t \"QSPI_CS_B\", \"SPI_CLK\", \"LED1\", \"LED2\", \"SPI_CS_B\", /* 5 - 9 */\n\t\t\t \"SPI_MISO\", \"SPI_MOSI\", \"FWUEN\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST\", \"I2C1_SCL\", /* 20 - 24 */\n\t\t\t \"I2C1_SDA\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 30 - 34 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 35 - 39 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 40 - 44 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 50 - 54 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 55 - 59 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 60 - 64 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t\t \"\", \"\", \"\", /* 75 - 77, MIO end and EMIO start */\n\t\t\t \"\", \"\", /* 78 - 79 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-smk-k24-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SMK-K24 RevA\n *\n * (C) Copyright 2020 - 2021, Xilinx, Inc.\n * (C) Copyright 2022-2024, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sm-k24-reva.dtsi\"\n\n/ {\n\tmodel = \"ZynqMP SMK-K24 RevA\";\n\tcompatible = \"xlnx,zynqmp-smk-k24-revA\", \"xlnx,zynqmp-smk-k24\",\n\t\t \"xlnx,zynqmp\";\n};\n\n&sdhci0 {\n\tstatus = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-smk-k26-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"zynqmp-sm-k26-reva.dtsi\"\n\n/ {\n model = \"ZynqMP SMK-K26 Rev1/B/A\";\n compatible = \"xlnx,zynqmp-smk-k26-rev1\", \"xlnx,zynqmp-smk-k26-revB\",\n \"xlnx,zynqmp-smk-k26-revA\", \"xlnx,zynqmp-smk-k26\",\n \"xlnx,zynqmp\";\n};\n\n&sdhci0 {\n\t status = \"disabled\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on vp-x-a2785-00 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vp-x-a2785-00-revA\",\n\t\t \"xlnx,zynqmp-vp-x-a2785-00\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n usb1 = &usb1;\n nvmem0 = &eeprom;\n };\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tkey-j383 {\n\t\t\tlabel = \"j383\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds52 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb - u142 */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* u285 - mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>; /* maybe 4 here */\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci1 { /* sd MIO 45-51 */\n\tno-1-8-v;\n\tdisable-wp;\n\txlnx,mio-bank = <1>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tbootph-all;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 { /* u131 - M88e1512 */\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"\", \"\", /* 10 - 14 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 15 - 19 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"SD1_CD\", \"SD1_DATA0\", \"SD1_DATA1\", \"SD1_DATA2\", \"SD1_DATA3\", /* 45 - 49 */\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"\", \"\", /* 78 - 79 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 80 - 84 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 85 - 89 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 90 - 94 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"\", \"\", /* 0 - 3 */\n\t\t\t\t \"\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"\", \"\", \"\", \"VCCINT_FAULT_B\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\treg_vccint: tps53681@60 { /* u266 - 0xc0 */\n\t\t\t\tcompatible = \"ti,tps53681\", \"ti,tps53679\";\n\t\t\t\treg = <0x60>;\n\t\t\t};\n\t\t\treg_vcc1v1_lp4: tps544@d { /* u85 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0xd>;\n\t\t\t};\n\t\t\treg_mgtyavcc: tps544@10 { /* u274 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\treg_mgtyavtt: tps544@11 { /* u275 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\treg_vccaux: tps544@12 { /* u276 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\treg_vcc_cpm: tps544@14 { /* u272 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\treg_util_3v3: tps544@1d { /* u278 */\n\t\t\t\tcompatible = \"ti,tps544b25\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvcc_cpm: ina226@44 { /* u273 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <1000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpcie_smbus: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tpcie2_smbus: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tdc_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tsi570_ref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\ti2c@1 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\ti2c@3 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\t/* 6-7 unused */\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-vpk120-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx ZynqMP VPK120 RevA System Controller\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/pinctrl/pinctrl-zynqmp.h\"\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/phy/phy.h\"\n\n/ {\n\tmodel = \"ZynqMP System Controller on VPK120 board RevA\";\n\tcompatible = \"xlnx,zynqmp-vpk120-revA\",\n\t\t \"xlnx,zynqmp-vpk120\", \"xlnx,zynqmp\";\n\n\taliases {\n ethernet0 = &gem0;\n i2c0 = &i2c0;\n i2c1 = &i2c1;\n mmc0 = &sdhci0;\n serial0 = &uart0;\n serial1 = &dcc;\n spi0 = &qspi;\n usb0 = &usb0;\n usb1 = &usb1;\n nvmem0 = &eeprom;\n };\n\n\tsi570_user1_fmc_clk: si570-user1-fmc-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&user_si570_1>;\n\t};\n\n\tsi570_ref_clk: si570-ref-clk {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&ref_clk>;\n\t};\n\n\tsi570_lpddr4_clk3: si570-lpddr4-clk3 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk3>;\n\t};\n\n\tsi570_lpddr4_clk2: si570-lpddr4-clk2 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk2>;\n\t};\n\n\tsi570_lpddr4_clk1: si570-lpddr4-clk1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"xlnx,fclk\";\n\t\tclocks = <&lpddr4_clk1>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tbutton-16 {\n\t\t\tlabel = \"sw16\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led { /* ds40 */\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n\n\tsi5332_0: si5332_0 { /* ps_ref_clk */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tsi5332_1: si5332_1 { /* clk0_sgmii */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>; /* FIXME */\n\t};\n\n\tsi5332_2: si5332_2 { /* clk1_usb */\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&psgtr {\n\t/* sgmii, usb3 */\n\tclocks = <&si5332_1>, <&si5332_2>;\n\tclock-names = \"ref0\", \"ref1\";\n};\n\n&qspi { /* MIO 0-5 */\n\tflash@0 {\n\t\tcompatible = \"m25p80\", \"jedec,spi-nor\"; /* mt25qu512abb8e12 512Mib */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-max-frequency = <108000000>;\n\t\tpartition@0 { /* for testing purpose */\n\t\t\tlabel = \"qspi\";\n\t\t\treg = <0 0x4000000>;\n\t\t};\n\t};\n};\n\n&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */\n\tnon-removable;\n\tdisable-wp;\n\tbus-width = <8>;\n\txlnx,mio-bank = <0>;\n};\n\n&uart0 { /* uart0 MIO38-39 */\n\tbootph-all;\n};\n\n&gem0 {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\"; /* DTG generates this properly 1512 */\n\tis-internal-pcspma;\n\t/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */\n\t/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"QSPI_CLK\", \"QSPI_DQ1\", \"QSPI_DQ2\", \"QSPI_DQ3\", \"QSPI_DQ0\", /* 0 - 4 */\n\t\t \"QSPI_CS_B\", \"\", \"\", \"SYSCTLR_GPIO\", \"SYSCTLR_LED\", /* 5 - 9 */\n\t\t \"SYSCTLR_PB\", \"PMC_ZU4_TRIGGER\", \"\", \"EMMC_DAT0\", \"EMMC_DAT1\", /* 10 - 14 */\n\t\t \"EMMC_DAT2\", \"EMMC_DAT3\", \"EMMC_DAT4\", \"EMMC_DAT5\", \"EMMC_DAT6\", /* 15 - 19 */\n\t\t \"EMMC_DAT7\", \"EMMC_CMD\", \"EMMC_CLK\", \"EMMC_RST_B\", \"\", /* 20 - 24 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 25 - 29 */\n\t\t \"\", \"\", \"\", \"\", \"LP_I2C0_PMC_SCL\", /* 30 - 34 */\n\t\t \"LP_I2C0_PMC_SDA\", \"LP_I2C1_SCL\", \"LP_I2C1_SDA\", \"UART0_RXD_IN\", \"UART0_TXD_OUT\", /* 35 - 39 */\n\t\t \"\", \"\", \"ETH_RESET_B\", \"\", \"\", /* 40 - 44 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 45 - 49 */\n\t\t \"\", \"\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\", /* 50 - 54 */\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\", /* 55 - 59 */\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"\", /* 60 - 64 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 65 - 69 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 70 - 74 */\n\t\t \"\", \"ETH_MDC\", \"ETH_MDIO\", /* 75 - 77, MIO end and EMIO start */\n\t\t \"SYSCTLR_VERSAL_MODE0\", \"SYSCTLR_VERSAL_MODE1\", /* 78 - 79 */\n\t\t \"SYSCTLR_VERSAL_MODE2\", \"SYSCTLR_VERSAL_MODE3\", \"SYSCTLR_POR_B_LS\", \"\", \"\", /* 80 - 84 */\n\t\t \"SYSCTLR_JTAG_S0\", \"SYSCTLR_JTAG_S1\", \"SYSCTLR_IIC_MUX0_RESET_B\", \"SYSCTLR_IIC_MUX1_RESET_B\", \"\", /* 85 - 89 */\n\t\t \"SYSCTLR_GPIO0\", \"SYSCTLR_GPIO1\", \"SYSCTLR_GPIO2\", \"SYSCTLR_GPIO3\", \"SYSCTLR_GPIO4\", /* 90 - 94 */\n\t\t \"SYSCTLR_GPIO5\", \"\", \"\", \"\", \"\", /* 95 - 99 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 100 - 104 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 105 - 109 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 110 - 114 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 115 - 119 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 120 - 124 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 125 - 129 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 130 - 134 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 135 - 139 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 140 - 144 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 145 - 149 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 150 - 154 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 155 - 159 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 160 - 164 */\n\t\t \"\", \"\", \"\", \"\", \"\", /* 165 - 169 */\n\t\t \"\", \"\", \"\", \"\"; /* 170 - 173 */\n};\n\n&i2c0 { /* MIO 34-35 - can't stay here */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c0_default>;\n\tpinctrl-1 = <&pinctrl_i2c0_gpio>;\n\tscl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\n\ttca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"MAX6643_OT_B\", \"MAX6643_FANFAIL_B\", \"QSFPDD1_MODSELL\", \"QSFPDD1_MODSELL\", /* 0 - 3 */\n\t\t\t\t \"PMBUS2_INA226_ALERT\", \"\", \"\", \"MAX6643_FULL_SPEED\", /* 4 - 7 */\n\t\t\t\t \"FMCP1_FMC_PRSNT_M2C_B\", \"\", \"FMCP1_FMCP_PRSNT_M2C_B\", \"\", /* 10 - 13 */\n\t\t\t\t \"VCCINT_VRHOT_B\", \"8A34001_EXP_RST_B\", \"PMBUS_ALERT\", \"PMBUS1_INA226_ALERT\"; /* 14 - 17 */\n\t};\n\n\ti2c-mux@74 { /* u33 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tpmbus_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* On connector J325 */\n\t\t\tir38060_41: regulator@41 { /* IR38060 - u259 */\n\t\t\t\tcompatible = \"infineon,ir38060\", \"infineon,ir38064\";\n\t\t\t\treg = <0x41>; /* i2c addr 0x11 */\n\t\t\t};\n\t\t\tir38164_43: regulator@43 { /* IR38164 - u13 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x43>; /* i2c addr 0x13 */\n\t\t\t};\n\t\t\tir35221_45: pmic@46 { /* IR35221 - u152 */\n\t\t\t\tcompatible = \"infineon,ir35221\";\n\t\t\t\treg = <0x46>; /* PMBUS - 0x16 */\n\t\t\t};\n\t\t\tirps5401_47: pmic5401@47 { /* IRPS5401 - u160 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x47>; /* i2c addr 0x17 */\n\t\t\t};\n\t\t\tir38164_49: regulator@49 { /* IR38164 - u189 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x49>; /* i2c addr 0x19 */\n\t\t\t};\n\t\t\tirps5401_4c: pmic@4c { /* IRPS5401 - u167 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4c>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tirps5401_4d: pmic@4d { /* IRPS5401 - u175 */\n\t\t\t\tcompatible = \"infineon,irps5401\";\n\t\t\t\treg = <0x4d>; /* i2c addr 0x1c */\n\t\t\t};\n\t\t\tir38164_4e: regulator@4e { /* IR38164 - u184 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4e>; /* i2c addr 0x1e */\n\t\t\t};\n\t\t\tir38164_4f: regulator@4f { /* IR38164 - u187 */\n\t\t\t\tcompatible = \"infineon,ir38164\";\n\t\t\t\treg = <0x4f>; /* i2c addr 0x1f */\n\t\t\t};\n\t\t};\n\t\tpmbus1_ina226_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccint: ina226@40 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_soc: ina226@41 { /* u161 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pmc: ina226@42 { /* u163 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_ram: ina226@43 { /* u5 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_pslp: ina226@44 { /* u165 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc_psfp: ina226@45 { /* u164 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 { /* NC */ /* FIXME maybe remove */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tpmbus2_ina226_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* FIXME check alerts coming to SC */\n\t\t\tvccaux: ina226@40 { /* u166 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvccaux_pmc: ina226@41 { /* u168 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavcc: ina226@42 { /* u265 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v5: ina226@43 { /* u264 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcco_mio: ina226@45 { /* u172 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtavtt: ina226@46 { /* u188 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvcco_502: ina226@47 { /* u174 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tmgtvccaux: ina226@48 { /* u176 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tvcc1v1_lp4: ina226@49 { /* u186 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tvadj_fmc: ina226@4a { /* u184 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyavcc: ina226@4b { /* u177 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tlpdmgtyavtt: ina226@4c { /* u260 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tlpdmgtyvccaux: ina226@4d { /* u234 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t};\n\t\ti2c@5 { /* NC */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\t\tuser_si570: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\tuser_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5f>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <100000000>;\n\t\t\t\tclock-frequency = <100000000>;\n\t\t\t\tclock-output-names = \"fmc_si570\";\n\t\t\t};\n\n\t\t};\n\t\t/* 7 unused */\n\t};\n};\n\n&i2c1 { /* i2c1 MIO 36-37 */\n\tclock-frequency = <400000>;\n\tpinctrl-names = \"default\", \"gpio\";\n\tpinctrl-0 = <&pinctrl_i2c1_default>;\n\tpinctrl-1 = <&pinctrl_i2c1_gpio>;\n\tscl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\tsda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\ti2c-mux@74 { /* u35 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\t/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */\n\t\tref_clk_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* Use for storing information about SC board */\n\t\t\teeprom: eeprom@54 { /* u34 - m24128 16kB */\n\t\t\t\tcompatible = \"st,24c128\", \"atmel,24c128\";\n\t\t\t\treg = <0x54>; /* & 0x5c */\n\t\t\t};\n\t\t\tref_clk: clock-generator@5d { /* u32 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <33333333>;\n\t\t\t\tclock-frequency = <33333333>;\n\t\t\t\tclock-output-names = \"ref_clk\";\n\t\t\t\tsilabs,skip-recall;\n\t\t\t};\n\t\t};\n\t\tfmcp1_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* FIXME connection to Samtec J51C */\n\t\t\t/* expected eeprom 0x50 SE cards */\n\t\t};\n\t\ti2c@2 { /* NC - FIXME */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t};\n\t\tlpddr4_si570_clk3_i2c: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlpddr4_clk3: clock-generator@60 { /* u4 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk3\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk2_i2c: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tlpddr4_clk2: clock-generator@60 { /* u3 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk2\";\n\t\t\t};\n\t\t};\n\t\tlpddr4_si570_clk1_i2c: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\tlpddr4_clk1: clock-generator@60 { /* u248 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x60>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <200000000>;\n\t\t\t\tclock-frequency = <200000000>;\n\t\t\t\tclock-output-names = \"lpddr4_clk1\";\n\t\t\t};\n\t\t};\n\t\tqsfpdd_i2c: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* J1/J2 connectors */\n\t\t};\n\t\tidt8a34001_i2c: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* Via J310 connector */\n\t\t\tidt_8a34001: phc@5b {\n\t\t\t\tcompatible = \"idt,8a34001\"; /* u219B */\n\t\t\t\treg = <0x5b>; /* FIXME not in schematics */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 { /* MIO52 - MIO63 */\n\tphy-names = \"usb3-phy\";\n\tphys = <&psgtr 1 PHY_TYPE_USB3 0 1>;\n};\n\n&dwc3_0 {\n\tdr_mode = \"peripheral\";\n\tsnps,dis_u2_susphy_quirk;\n\tsnps,dis_u3_susphy_quirk;\n\tmaximum-speed = \"super-speed\";\n};\n\n&pinctrl0 {\n\tstatus = \"okay\";\n\tpinctrl_i2c0_default: i2c0-default {\n\t\tmux {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tfunction = \"i2c0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c0_8_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c0_gpio: i2c0-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_34_grp\", \"gpio0_35_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_default: i2c1-default {\n\t\tmux {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tfunction = \"i2c1\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"i2c1_9_grp\";\n\t\t\tbias-pull-up;\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n\n\tpinctrl_i2c1_gpio: i2c1-gpio {\n\t\tmux {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tfunction = \"gpio0\";\n\t\t};\n\n\t\tconf {\n\t\t\tgroups = \"gpio0_36_grp\", \"gpio0_37_grp\";\n\t\t\tslew-rate = ;\n\t\t\tpower-source = ;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/clock/xlnx-versal-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_VERSAL_H\n#define _DT_BINDINGS_CLK_VERSAL_H\n\n#define PMC_PLL\t\t\t\t\t1\n#define APU_PLL\t\t\t\t\t2\n#define RPU_PLL\t\t\t\t\t3\n#define CPM_PLL\t\t\t\t\t4\n#define NOC_PLL\t\t\t\t\t5\n#define PLL_MAX\t\t\t\t\t6\n#define PMC_PRESRC\t\t\t\t7\n#define PMC_POSTCLK\t\t\t\t8\n#define PMC_PLL_OUT\t\t\t\t9\n#define PPLL\t\t\t\t\t10\n#define NOC_PRESRC\t\t\t\t11\n#define NOC_POSTCLK\t\t\t\t12\n#define NOC_PLL_OUT\t\t\t\t13\n#define NPLL\t\t\t\t\t14\n#define APU_PRESRC\t\t\t\t15\n#define APU_POSTCLK\t\t\t\t16\n#define APU_PLL_OUT\t\t\t\t17\n#define APLL\t\t\t\t\t18\n#define RPU_PRESRC\t\t\t\t19\n#define RPU_POSTCLK\t\t\t\t20\n#define RPU_PLL_OUT\t\t\t\t21\n#define RPLL\t\t\t\t\t22\n#define CPM_PRESRC\t\t\t\t23\n#define CPM_POSTCLK\t\t\t\t24\n#define CPM_PLL_OUT\t\t\t\t25\n#define CPLL\t\t\t\t\t26\n#define PPLL_TO_XPD\t\t\t\t27\n#define NPLL_TO_XPD\t\t\t\t28\n#define APLL_TO_XPD\t\t\t\t29\n#define RPLL_TO_XPD\t\t\t\t30\n#define EFUSE_REF\t\t\t\t31\n#define SYSMON_REF\t\t\t\t32\n#define IRO_SUSPEND_REF\t\t\t\t33\n#define USB_SUSPEND\t\t\t\t34\n#define SWITCH_TIMEOUT\t\t\t\t35\n#define RCLK_PMC\t\t\t\t36\n#define RCLK_LPD\t\t\t\t37\n#define WDT\t\t\t\t\t38\n#define TTC0\t\t\t\t\t39\n#define TTC1\t\t\t\t\t40\n#define TTC2\t\t\t\t\t41\n#define TTC3\t\t\t\t\t42\n#define GEM_TSU\t\t\t\t\t43\n#define GEM_TSU_LB\t\t\t\t44\n#define MUXED_IRO_DIV2\t\t\t\t45\n#define MUXED_IRO_DIV4\t\t\t\t46\n#define PSM_REF\t\t\t\t\t47\n#define GEM0_RX\t\t\t\t\t48\n#define GEM0_TX\t\t\t\t\t49\n#define GEM1_RX\t\t\t\t\t50\n#define GEM1_TX\t\t\t\t\t51\n#define CPM_CORE_REF\t\t\t\t52\n#define CPM_LSBUS_REF\t\t\t\t53\n#define CPM_DBG_REF\t\t\t\t54\n#define CPM_AUX0_REF\t\t\t\t55\n#define CPM_AUX1_REF\t\t\t\t56\n#define QSPI_REF\t\t\t\t57\n#define OSPI_REF\t\t\t\t58\n#define SDIO0_REF\t\t\t\t59\n#define SDIO1_REF\t\t\t\t60\n#define PMC_LSBUS_REF\t\t\t\t61\n#define I2C_REF\t\t\t\t\t62\n#define TEST_PATTERN_REF\t\t\t63\n#define DFT_OSC_REF\t\t\t\t64\n#define PMC_PL0_REF\t\t\t\t65\n#define PMC_PL1_REF\t\t\t\t66\n#define PMC_PL2_REF\t\t\t\t67\n#define PMC_PL3_REF\t\t\t\t68\n#define CFU_REF\t\t\t\t\t69\n#define SPARE_REF\t\t\t\t70\n#define NPI_REF\t\t\t\t\t71\n#define HSM0_REF\t\t\t\t72\n#define HSM1_REF\t\t\t\t73\n#define SD_DLL_REF\t\t\t\t74\n#define FPD_TOP_SWITCH\t\t\t\t75\n#define FPD_LSBUS\t\t\t\t76\n#define ACPU\t\t\t\t\t77\n#define DBG_TRACE\t\t\t\t78\n#define DBG_FPD\t\t\t\t\t79\n#define LPD_TOP_SWITCH\t\t\t\t80\n#define ADMA\t\t\t\t\t81\n#define LPD_LSBUS\t\t\t\t82\n#define CPU_R5\t\t\t\t\t83\n#define CPU_R5_CORE\t\t\t\t84\n#define CPU_R5_OCM\t\t\t\t85\n#define CPU_R5_OCM2\t\t\t\t86\n#define IOU_SWITCH\t\t\t\t87\n#define GEM0_REF\t\t\t\t88\n#define GEM1_REF\t\t\t\t89\n#define GEM_TSU_REF\t\t\t\t90\n#define USB0_BUS_REF\t\t\t\t91\n#define UART0_REF\t\t\t\t92\n#define UART1_REF\t\t\t\t93\n#define SPI0_REF\t\t\t\t94\n#define SPI1_REF\t\t\t\t95\n#define CAN0_REF\t\t\t\t96\n#define CAN1_REF\t\t\t\t97\n#define I2C0_REF\t\t\t\t98\n#define I2C1_REF\t\t\t\t99\n#define DBG_LPD\t\t\t\t\t100\n#define TIMESTAMP_REF\t\t\t\t101\n#define DBG_TSTMP\t\t\t\t102\n#define CPM_TOPSW_REF\t\t\t\t103\n#define USB3_DUAL_REF\t\t\t\t104\n#define OUTCLK_MAX\t\t\t\t105\n#define REF_CLK\t\t\t\t\t106\n#define PL_ALT_REF_CLK\t\t\t\t107\n#define MUXED_IRO\t\t\t\t108\n#define PL_EXT\t\t\t\t\t109\n#define PL_LB\t\t\t\t\t110\n#define MIO_50_OR_51\t\t\t\t111\n#define MIO_24_OR_25\t\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/clock/xlnx-versal-net-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2022, Xilinx Inc.\n * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.\n */\n\n#ifndef _DT_BINDINGS_CLK_VERSAL_NET_H\n#define _DT_BINDINGS_CLK_VERSAL_NET_H\n\n#include \n\n#define GEM0_REF_RX\t0xA9\n#define GEM0_REF_TX\t0xA8\n#define GEM1_REF_RX\t0xA2\n#define GEM1_REF_TX\t0xA1\n#define CAN0_REF_2X\t0x9E\n#define CAN1_REF_2X\t0xAC\n#define FPD_WWDT\t0x96\n#define ACPU_0\t\t0x98\n#define ACPU_1\t\t0x9B\n#define ACPU_2\t\t0x9A\n#define ACPU_3\t\t0x99\n#define I3C0_REF\t0x9D\n#define I3C1_REF\t0x9F\n#define USB1_BUS_REF\t0xAE\n#define LPD_WWDT\t0xAD\n\n/* Remove Versal specific node IDs */\n#undef APU_PLL\n#undef RPU_PLL\n#undef CPM_PLL\n#undef APU_PRESRC\n#undef APU_POSTCLK\n#undef APU_PLL_OUT\n#undef APLL\n#undef RPU_PRESRC\n#undef RPU_POSTCLK\n#undef RPU_PLL_OUT\n#undef RPLL\n#undef CPM_PRESRC\n#undef CPM_POSTCLK\n#undef CPM_PLL_OUT\n#undef CPLL\n#undef APLL_TO_XPD\n#undef RPLL_TO_XPD\n#undef RCLK_PMC\n#undef RCLK_LPD\n#undef WDT\n#undef MUXED_IRO_DIV2\n#undef MUXED_IRO_DIV4\n#undef PSM_REF\n#undef CPM_CORE_REF\n#undef CPM_LSBUS_REF\n#undef CPM_DBG_REF\n#undef CPM_AUX0_REF\n#undef CPM_AUX1_REF\n#undef CPU_R5\n#undef CPU_R5_CORE\n#undef CPU_R5_OCM\n#undef CPU_R5_OCM2\n#undef CAN0_REF\n#undef CAN1_REF\n#undef I2C0_REF\n#undef I2C1_REF\n#undef CPM_TOPSW_REF\n#undef USB3_DUAL_REF\n#undef MUXED_IRO\n#undef PL_EXT\n#undef PL_LB\n#undef MIO_50_OR_51\n#undef MIO_24_OR_25\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Xilinx Zynq MPSoC Firmware layer\n *\n * Copyright (C) 2014-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n */\n\n#ifndef _DT_BINDINGS_CLK_ZYNQMP_H\n#define _DT_BINDINGS_CLK_ZYNQMP_H\n\n#define IOPLL\t\t\t0\n#define RPLL\t\t\t1\n#define APLL\t\t\t2\n#define DPLL\t\t\t3\n#define VPLL\t\t\t4\n#define IOPLL_TO_FPD\t\t5\n#define RPLL_TO_FPD\t\t6\n#define APLL_TO_LPD\t\t7\n#define DPLL_TO_LPD\t\t8\n#define VPLL_TO_LPD\t\t9\n#define ACPU\t\t\t10\n#define ACPU_HALF\t\t11\n#define DBF_FPD\t\t\t12\n#define DBF_LPD\t\t\t13\n#define DBG_TRACE\t\t14\n#define DBG_TSTMP\t\t15\n#define DP_VIDEO_REF\t\t16\n#define DP_AUDIO_REF\t\t17\n#define DP_STC_REF\t\t18\n#define GDMA_REF\t\t19\n#define DPDMA_REF\t\t20\n#define DDR_REF\t\t\t21\n#define SATA_REF\t\t22\n#define PCIE_REF\t\t23\n#define GPU_REF\t\t\t24\n#define GPU_PP0_REF\t\t25\n#define GPU_PP1_REF\t\t26\n#define TOPSW_MAIN\t\t27\n#define TOPSW_LSBUS\t\t28\n#define GTGREF0_REF\t\t29\n#define LPD_SWITCH\t\t30\n#define LPD_LSBUS\t\t31\n#define USB0_BUS_REF\t\t32\n#define USB1_BUS_REF\t\t33\n#define USB3_DUAL_REF\t\t34\n#define USB0\t\t\t35\n#define USB1\t\t\t36\n#define CPU_R5\t\t\t37\n#define CPU_R5_CORE\t\t38\n#define CSU_SPB\t\t\t39\n#define CSU_PLL\t\t\t40\n#define PCAP\t\t\t41\n#define IOU_SWITCH\t\t42\n#define GEM_TSU_REF\t\t43\n#define GEM_TSU\t\t\t44\n#define GEM0_TX\t\t\t45\n#define GEM1_TX\t\t\t46\n#define GEM2_TX\t\t\t47\n#define GEM3_TX\t\t\t48\n#define GEM0_RX\t\t\t49\n#define GEM1_RX\t\t\t50\n#define GEM2_RX\t\t\t51\n#define GEM3_RX\t\t\t52\n#define QSPI_REF\t\t53\n#define SDIO0_REF\t\t54\n#define SDIO1_REF\t\t55\n#define UART0_REF\t\t56\n#define UART1_REF\t\t57\n#define SPI0_REF\t\t58\n#define SPI1_REF\t\t59\n#define NAND_REF\t\t60\n#define I2C0_REF\t\t61\n#define I2C1_REF\t\t62\n#define CAN0_REF\t\t63\n#define CAN1_REF\t\t64\n#define CAN0\t\t\t65\n#define CAN1\t\t\t66\n#define DLL_REF\t\t\t67\n#define ADMA_REF\t\t68\n#define TIMESTAMP_REF\t\t69\n#define AMS_REF\t\t\t70\n#define PL0_REF\t\t\t71\n#define PL1_REF\t\t\t72\n#define PL2_REF\t\t\t73\n#define PL3_REF\t\t\t74\n#define WDT\t\t\t75\n#define IOPLL_INT\t\t76\n#define IOPLL_PRE_SRC\t\t77\n#define IOPLL_HALF\t\t78\n#define IOPLL_INT_MUX\t\t79\n#define IOPLL_POST_SRC\t\t80\n#define RPLL_INT\t\t81\n#define RPLL_PRE_SRC\t\t82\n#define RPLL_HALF\t\t83\n#define RPLL_INT_MUX\t\t84\n#define RPLL_POST_SRC\t\t85\n#define APLL_INT\t\t86\n#define APLL_PRE_SRC\t\t87\n#define APLL_HALF\t\t88\n#define APLL_INT_MUX\t\t89\n#define APLL_POST_SRC\t\t90\n#define DPLL_INT\t\t91\n#define DPLL_PRE_SRC\t\t92\n#define DPLL_HALF\t\t93\n#define DPLL_INT_MUX\t\t94\n#define DPLL_POST_SRC\t\t95\n#define VPLL_INT\t\t96\n#define VPLL_PRE_SRC\t\t97\n#define VPLL_HALF\t\t98\n#define VPLL_INT_MUX\t\t99\n#define VPLL_POST_SRC\t\t100\n#define CAN0_MIO\t\t101\n#define CAN1_MIO\t\t102\n#define ACPU_FULL\t\t103\n#define GEM0_REF\t\t104\n#define GEM1_REF\t\t105\n#define GEM2_REF\t\t106\n#define GEM3_REF\t\t107\n#define GEM0_REF_UNG\t\t108\n#define GEM1_REF_UNG\t\t109\n#define GEM2_REF_UNG\t\t110\n#define GEM3_REF_UNG\t\t111\n#define LPD_WDT\t\t\t112\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h", "content": "/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */\n/*\n * Copyright 2019 Laurent Pinchart \n */\n\n#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__\n\n#define ZYNQMP_DPDMA_VIDEO0\t\t0\n#define ZYNQMP_DPDMA_VIDEO1\t\t1\n#define ZYNQMP_DPDMA_VIDEO2\t\t2\n#define ZYNQMP_DPDMA_GRAPHICS\t\t3\n#define ZYNQMP_DPDMA_AUDIO0\t\t4\n#define ZYNQMP_DPDMA_AUDIO1\t\t5\n\n#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/gpio/gpio.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most GPIO bindings.\n *\n * Most GPIO bindings include a flags cell as part of the GPIO specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_GPIO_GPIO_H\n#define _DT_BINDINGS_GPIO_GPIO_H\n\n/* Bit 0 express polarity */\n#define GPIO_ACTIVE_HIGH 0\n#define GPIO_ACTIVE_LOW 1\n\n/* Bit 1 express single-endedness */\n#define GPIO_PUSH_PULL 0\n#define GPIO_SINGLE_ENDED 2\n\n/* Bit 2 express Open drain or open source */\n#define GPIO_LINE_OPEN_SOURCE 0\n#define GPIO_LINE_OPEN_DRAIN 4\n\n/*\n * Open Drain/Collector is the combination of single-ended open drain interface.\n * Open Source/Emitter is the combination of single-ended open source interface.\n */\n#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)\n#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)\n\n/* Bit 3 express GPIO suspend/resume and reset persistence */\n#define GPIO_PERSISTENT 0\n#define GPIO_TRANSITORY 8\n\n/* Bit 4 express pull up */\n#define GPIO_PULL_UP 16\n\n/* Bit 5 express pull down */\n#define GPIO_PULL_DOWN 32\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/input/input.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most input bindings.\n *\n * Most input bindings include key code, matrix key code format.\n * In most cases, key code and matrix key code format uses\n * the standard values/macro defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INPUT_INPUT_H\n#define _DT_BINDINGS_INPUT_INPUT_H\n\n/*\n * Device properties and quirks\n */\n\n#define INPUT_PROP_POINTER\t\t0x00\t/* needs a pointer */\n#define INPUT_PROP_DIRECT\t\t0x01\t/* direct input devices */\n#define INPUT_PROP_BUTTONPAD\t\t0x02\t/* has button(s) under pad */\n#define INPUT_PROP_SEMI_MT\t\t0x03\t/* touch rectangle only */\n#define INPUT_PROP_TOPBUTTONPAD\t\t0x04\t/* softbuttons at top of pad */\n#define INPUT_PROP_POINTING_STICK\t0x05\t/* is a pointing stick */\n#define INPUT_PROP_ACCELEROMETER\t0x06\t/* has accelerometer */\n\n#define INPUT_PROP_MAX\t\t\t0x1f\n#define INPUT_PROP_CNT\t\t\t(INPUT_PROP_MAX + 1)\n\n\n/*\n * Event types\n */\n\n#define EV_SYN\t\t\t0x00\n#define EV_KEY\t\t\t0x01\n#define EV_REL\t\t\t0x02\n#define EV_ABS\t\t\t0x03\n#define EV_MSC\t\t\t0x04\n#define EV_SW\t\t\t0x05\n#define EV_LED\t\t\t0x11\n#define EV_SND\t\t\t0x12\n#define EV_REP\t\t\t0x14\n#define EV_FF\t\t\t0x15\n#define EV_PWR\t\t\t0x16\n#define EV_FF_STATUS\t\t0x17\n#define EV_MAX\t\t\t0x1f\n#define EV_CNT\t\t\t(EV_MAX+1)\n\n/*\n * Synchronization events.\n */\n\n#define SYN_REPORT\t\t0\n#define SYN_CONFIG\t\t1\n#define SYN_MT_REPORT\t\t2\n#define SYN_DROPPED\t\t3\n#define SYN_MAX\t\t\t0xf\n#define SYN_CNT\t\t\t(SYN_MAX+1)\n\n/*\n * Keys and buttons\n *\n * Most of the keys/buttons are modeled after USB HUT 1.12\n * (see http://www.usb.org/developers/hidpage).\n * Abbreviations in the comments:\n * AC - Application Control\n * AL - Application Launch Button\n * SC - System Control\n */\n\n#define KEY_RESERVED\t\t0\n#define KEY_ESC\t\t\t1\n#define KEY_1\t\t\t2\n#define KEY_2\t\t\t3\n#define KEY_3\t\t\t4\n#define KEY_4\t\t\t5\n#define KEY_5\t\t\t6\n#define KEY_6\t\t\t7\n#define KEY_7\t\t\t8\n#define KEY_8\t\t\t9\n#define KEY_9\t\t\t10\n#define KEY_0\t\t\t11\n#define KEY_MINUS\t\t12\n#define KEY_EQUAL\t\t13\n#define KEY_BACKSPACE\t\t14\n#define KEY_TAB\t\t\t15\n#define KEY_Q\t\t\t16\n#define KEY_W\t\t\t17\n#define KEY_E\t\t\t18\n#define KEY_R\t\t\t19\n#define KEY_T\t\t\t20\n#define KEY_Y\t\t\t21\n#define KEY_U\t\t\t22\n#define KEY_I\t\t\t23\n#define KEY_O\t\t\t24\n#define KEY_P\t\t\t25\n#define KEY_LEFTBRACE\t\t26\n#define KEY_RIGHTBRACE\t\t27\n#define KEY_ENTER\t\t28\n#define KEY_LEFTCTRL\t\t29\n#define KEY_A\t\t\t30\n#define KEY_S\t\t\t31\n#define KEY_D\t\t\t32\n#define KEY_F\t\t\t33\n#define KEY_G\t\t\t34\n#define KEY_H\t\t\t35\n#define KEY_J\t\t\t36\n#define KEY_K\t\t\t37\n#define KEY_L\t\t\t38\n#define KEY_SEMICOLON\t\t39\n#define KEY_APOSTROPHE\t\t40\n#define KEY_GRAVE\t\t41\n#define KEY_LEFTSHIFT\t\t42\n#define KEY_BACKSLASH\t\t43\n#define KEY_Z\t\t\t44\n#define KEY_X\t\t\t45\n#define KEY_C\t\t\t46\n#define KEY_V\t\t\t47\n#define KEY_B\t\t\t48\n#define KEY_N\t\t\t49\n#define KEY_M\t\t\t50\n#define KEY_COMMA\t\t51\n#define KEY_DOT\t\t\t52\n#define KEY_SLASH\t\t53\n#define KEY_RIGHTSHIFT\t\t54\n#define KEY_KPASTERISK\t\t55\n#define KEY_LEFTALT\t\t56\n#define KEY_SPACE\t\t57\n#define KEY_CAPSLOCK\t\t58\n#define KEY_F1\t\t\t59\n#define KEY_F2\t\t\t60\n#define KEY_F3\t\t\t61\n#define KEY_F4\t\t\t62\n#define KEY_F5\t\t\t63\n#define KEY_F6\t\t\t64\n#define KEY_F7\t\t\t65\n#define KEY_F8\t\t\t66\n#define KEY_F9\t\t\t67\n#define KEY_F10\t\t\t68\n#define KEY_NUMLOCK\t\t69\n#define KEY_SCROLLLOCK\t\t70\n#define KEY_KP7\t\t\t71\n#define KEY_KP8\t\t\t72\n#define KEY_KP9\t\t\t73\n#define KEY_KPMINUS\t\t74\n#define KEY_KP4\t\t\t75\n#define KEY_KP5\t\t\t76\n#define KEY_KP6\t\t\t77\n#define KEY_KPPLUS\t\t78\n#define KEY_KP1\t\t\t79\n#define KEY_KP2\t\t\t80\n#define KEY_KP3\t\t\t81\n#define KEY_KP0\t\t\t82\n#define KEY_KPDOT\t\t83\n\n#define KEY_ZENKAKUHANKAKU\t85\n#define KEY_102ND\t\t86\n#define KEY_F11\t\t\t87\n#define KEY_F12\t\t\t88\n#define KEY_RO\t\t\t89\n#define KEY_KATAKANA\t\t90\n#define KEY_HIRAGANA\t\t91\n#define KEY_HENKAN\t\t92\n#define KEY_KATAKANAHIRAGANA\t93\n#define KEY_MUHENKAN\t\t94\n#define KEY_KPJPCOMMA\t\t95\n#define KEY_KPENTER\t\t96\n#define KEY_RIGHTCTRL\t\t97\n#define KEY_KPSLASH\t\t98\n#define KEY_SYSRQ\t\t99\n#define KEY_RIGHTALT\t\t100\n#define KEY_LINEFEED\t\t101\n#define KEY_HOME\t\t102\n#define KEY_UP\t\t\t103\n#define KEY_PAGEUP\t\t104\n#define KEY_LEFT\t\t105\n#define KEY_RIGHT\t\t106\n#define KEY_END\t\t\t107\n#define KEY_DOWN\t\t108\n#define KEY_PAGEDOWN\t\t109\n#define KEY_INSERT\t\t110\n#define KEY_DELETE\t\t111\n#define KEY_MACRO\t\t112\n#define KEY_MUTE\t\t113\n#define KEY_VOLUMEDOWN\t\t114\n#define KEY_VOLUMEUP\t\t115\n#define KEY_POWER\t\t116\t/* SC System Power Down */\n#define KEY_KPEQUAL\t\t117\n#define KEY_KPPLUSMINUS\t\t118\n#define KEY_PAUSE\t\t119\n#define KEY_SCALE\t\t120\t/* AL Compiz Scale (Expose) */\n\n#define KEY_KPCOMMA\t\t121\n#define KEY_HANGEUL\t\t122\n#define KEY_HANGUEL\t\tKEY_HANGEUL\n#define KEY_HANJA\t\t123\n#define KEY_YEN\t\t\t124\n#define KEY_LEFTMETA\t\t125\n#define KEY_RIGHTMETA\t\t126\n#define KEY_COMPOSE\t\t127\n#define KEY_STOP\t\t128\t/* AC Stop */\n#define KEY_AGAIN\t\t129\n#define KEY_PROPS\t\t130\t/* AC Properties */\n#define KEY_UNDO\t\t131\t/* AC Undo */\n#define KEY_FRONT\t\t132\n#define KEY_COPY\t\t133\t/* AC Copy */\n#define KEY_OPEN\t\t134\t/* AC Open */\n#define KEY_PASTE\t\t135\t/* AC Paste */\n#define KEY_FIND\t\t136\t/* AC Search */\n#define KEY_CUT\t\t\t137\t/* AC Cut */\n#define KEY_HELP\t\t138\t/* AL Integrated Help Center */\n#define KEY_MENU\t\t139\t/* Menu (show menu) */\n#define KEY_CALC\t\t140\t/* AL Calculator */\n#define KEY_SETUP\t\t141\n#define KEY_SLEEP\t\t142\t/* SC System Sleep */\n#define KEY_WAKEUP\t\t143\t/* System Wake Up */\n#define KEY_FILE\t\t144\t/* AL Local Machine Browser */\n#define KEY_SENDFILE\t\t145\n#define KEY_DELETEFILE\t\t146\n#define KEY_XFER\t\t147\n#define KEY_PROG1\t\t148\n#define KEY_PROG2\t\t149\n#define KEY_WWW\t\t\t150\t/* AL Internet Browser */\n#define KEY_MSDOS\t\t151\n#define KEY_COFFEE\t\t152\t/* AL Terminal Lock/Screensaver */\n#define KEY_SCREENLOCK\t\tKEY_COFFEE\n#define KEY_ROTATE_DISPLAY\t153\t/* Display orientation for e.g. tablets */\n#define KEY_DIRECTION\t\tKEY_ROTATE_DISPLAY\n#define KEY_CYCLEWINDOWS\t154\n#define KEY_MAIL\t\t155\n#define KEY_BOOKMARKS\t\t156\t/* AC Bookmarks */\n#define KEY_COMPUTER\t\t157\n#define KEY_BACK\t\t158\t/* AC Back */\n#define KEY_FORWARD\t\t159\t/* AC Forward */\n#define KEY_CLOSECD\t\t160\n#define KEY_EJECTCD\t\t161\n#define KEY_EJECTCLOSECD\t162\n#define KEY_NEXTSONG\t\t163\n#define KEY_PLAYPAUSE\t\t164\n#define KEY_PREVIOUSSONG\t165\n#define KEY_STOPCD\t\t166\n#define KEY_RECORD\t\t167\n#define KEY_REWIND\t\t168\n#define KEY_PHONE\t\t169\t/* Media Select Telephone */\n#define KEY_ISO\t\t\t170\n#define KEY_CONFIG\t\t171\t/* AL Consumer Control Configuration */\n#define KEY_HOMEPAGE\t\t172\t/* AC Home */\n#define KEY_REFRESH\t\t173\t/* AC Refresh */\n#define KEY_EXIT\t\t174\t/* AC Exit */\n#define KEY_MOVE\t\t175\n#define KEY_EDIT\t\t176\n#define KEY_SCROLLUP\t\t177\n#define KEY_SCROLLDOWN\t\t178\n#define KEY_KPLEFTPAREN\t\t179\n#define KEY_KPRIGHTPAREN\t180\n#define KEY_NEW\t\t\t181\t/* AC New */\n#define KEY_REDO\t\t182\t/* AC Redo/Repeat */\n\n#define KEY_F13\t\t\t183\n#define KEY_F14\t\t\t184\n#define KEY_F15\t\t\t185\n#define KEY_F16\t\t\t186\n#define KEY_F17\t\t\t187\n#define KEY_F18\t\t\t188\n#define KEY_F19\t\t\t189\n#define KEY_F20\t\t\t190\n#define KEY_F21\t\t\t191\n#define KEY_F22\t\t\t192\n#define KEY_F23\t\t\t193\n#define KEY_F24\t\t\t194\n\n#define KEY_PLAYCD\t\t200\n#define KEY_PAUSECD\t\t201\n#define KEY_PROG3\t\t202\n#define KEY_PROG4\t\t203\n#define KEY_DASHBOARD\t\t204\t/* AL Dashboard */\n#define KEY_SUSPEND\t\t205\n#define KEY_CLOSE\t\t206\t/* AC Close */\n#define KEY_PLAY\t\t207\n#define KEY_FASTFORWARD\t\t208\n#define KEY_BASSBOOST\t\t209\n#define KEY_PRINT\t\t210\t/* AC Print */\n#define KEY_HP\t\t\t211\n#define KEY_CAMERA\t\t212\n#define KEY_SOUND\t\t213\n#define KEY_QUESTION\t\t214\n#define KEY_EMAIL\t\t215\n#define KEY_CHAT\t\t216\n#define KEY_SEARCH\t\t217\n#define KEY_CONNECT\t\t218\n#define KEY_FINANCE\t\t219\t/* AL Checkbook/Finance */\n#define KEY_SPORT\t\t220\n#define KEY_SHOP\t\t221\n#define KEY_ALTERASE\t\t222\n#define KEY_CANCEL\t\t223\t/* AC Cancel */\n#define KEY_BRIGHTNESSDOWN\t224\n#define KEY_BRIGHTNESSUP\t225\n#define KEY_MEDIA\t\t226\n\n#define KEY_SWITCHVIDEOMODE\t227\t/* Cycle between available video\n\t\t\t\t\t outputs (Monitor/LCD/TV-out/etc) */\n#define KEY_KBDILLUMTOGGLE\t228\n#define KEY_KBDILLUMDOWN\t229\n#define KEY_KBDILLUMUP\t\t230\n\n#define KEY_SEND\t\t231\t/* AC Send */\n#define KEY_REPLY\t\t232\t/* AC Reply */\n#define KEY_FORWARDMAIL\t\t233\t/* AC Forward Msg */\n#define KEY_SAVE\t\t234\t/* AC Save */\n#define KEY_DOCUMENTS\t\t235\n\n#define KEY_BATTERY\t\t236\n\n#define KEY_BLUETOOTH\t\t237\n#define KEY_WLAN\t\t238\n#define KEY_UWB\t\t\t239\n\n#define KEY_UNKNOWN\t\t240\n#define KEY_VIDEO_NEXT\t\t241\t/* drive next video source */\n#define KEY_VIDEO_PREV\t\t242\t/* drive previous video source */\n#define KEY_BRIGHTNESS_CYCLE\t243\t/* brightness up, after max is min */\n#define KEY_BRIGHTNESS_AUTO\t244\t/* Set Auto Brightness: manual\n\t\t\t\t\t brightness control is off,\n\t\t\t\t\t rely on ambient */\n#define KEY_BRIGHTNESS_ZERO\tKEY_BRIGHTNESS_AUTO\n#define KEY_DISPLAY_OFF\t\t245\t/* display device to off state */\n\n#define KEY_WWAN\t\t246\t/* Wireless WAN (LTE, UMTS, GSM, etc.) */\n#define KEY_WIMAX\t\tKEY_WWAN\n#define KEY_RFKILL\t\t247\t/* Key that controls all radios */\n\n#define KEY_MICMUTE\t\t248\t/* Mute / unmute the microphone */\n\n/* Code 255 is reserved for special needs of AT keyboard driver */\n\n#define BTN_MISC\t\t0x100\n#define BTN_0\t\t\t0x100\n#define BTN_1\t\t\t0x101\n#define BTN_2\t\t\t0x102\n#define BTN_3\t\t\t0x103\n#define BTN_4\t\t\t0x104\n#define BTN_5\t\t\t0x105\n#define BTN_6\t\t\t0x106\n#define BTN_7\t\t\t0x107\n#define BTN_8\t\t\t0x108\n#define BTN_9\t\t\t0x109\n\n#define BTN_MOUSE\t\t0x110\n#define BTN_LEFT\t\t0x110\n#define BTN_RIGHT\t\t0x111\n#define BTN_MIDDLE\t\t0x112\n#define BTN_SIDE\t\t0x113\n#define BTN_EXTRA\t\t0x114\n#define BTN_FORWARD\t\t0x115\n#define BTN_BACK\t\t0x116\n#define BTN_TASK\t\t0x117\n\n#define BTN_JOYSTICK\t\t0x120\n#define BTN_TRIGGER\t\t0x120\n#define BTN_THUMB\t\t0x121\n#define BTN_THUMB2\t\t0x122\n#define BTN_TOP\t\t\t0x123\n#define BTN_TOP2\t\t0x124\n#define BTN_PINKIE\t\t0x125\n#define BTN_BASE\t\t0x126\n#define BTN_BASE2\t\t0x127\n#define BTN_BASE3\t\t0x128\n#define BTN_BASE4\t\t0x129\n#define BTN_BASE5\t\t0x12a\n#define BTN_BASE6\t\t0x12b\n#define BTN_DEAD\t\t0x12f\n\n#define BTN_GAMEPAD\t\t0x130\n#define BTN_SOUTH\t\t0x130\n#define BTN_A\t\t\tBTN_SOUTH\n#define BTN_EAST\t\t0x131\n#define BTN_B\t\t\tBTN_EAST\n#define BTN_C\t\t\t0x132\n#define BTN_NORTH\t\t0x133\n#define BTN_X\t\t\tBTN_NORTH\n#define BTN_WEST\t\t0x134\n#define BTN_Y\t\t\tBTN_WEST\n#define BTN_Z\t\t\t0x135\n#define BTN_TL\t\t\t0x136\n#define BTN_TR\t\t\t0x137\n#define BTN_TL2\t\t\t0x138\n#define BTN_TR2\t\t\t0x139\n#define BTN_SELECT\t\t0x13a\n#define BTN_START\t\t0x13b\n#define BTN_MODE\t\t0x13c\n#define BTN_THUMBL\t\t0x13d\n#define BTN_THUMBR\t\t0x13e\n\n#define BTN_DIGI\t\t0x140\n#define BTN_TOOL_PEN\t\t0x140\n#define BTN_TOOL_RUBBER\t\t0x141\n#define BTN_TOOL_BRUSH\t\t0x142\n#define BTN_TOOL_PENCIL\t\t0x143\n#define BTN_TOOL_AIRBRUSH\t0x144\n#define BTN_TOOL_FINGER\t\t0x145\n#define BTN_TOOL_MOUSE\t\t0x146\n#define BTN_TOOL_LENS\t\t0x147\n#define BTN_TOOL_QUINTTAP\t0x148\t/* Five fingers on trackpad */\n#define BTN_TOUCH\t\t0x14a\n#define BTN_STYLUS\t\t0x14b\n#define BTN_STYLUS2\t\t0x14c\n#define BTN_TOOL_DOUBLETAP\t0x14d\n#define BTN_TOOL_TRIPLETAP\t0x14e\n#define BTN_TOOL_QUADTAP\t0x14f\t/* Four fingers on trackpad */\n\n#define BTN_WHEEL\t\t0x150\n#define BTN_GEAR_DOWN\t\t0x150\n#define BTN_GEAR_UP\t\t0x151\n\n#define KEY_OK\t\t\t0x160\n#define KEY_SELECT\t\t0x161\n#define KEY_GOTO\t\t0x162\n#define KEY_CLEAR\t\t0x163\n#define KEY_POWER2\t\t0x164\n#define KEY_OPTION\t\t0x165\n#define KEY_INFO\t\t0x166\t/* AL OEM Features/Tips/Tutorial */\n#define KEY_TIME\t\t0x167\n#define KEY_VENDOR\t\t0x168\n#define KEY_ARCHIVE\t\t0x169\n#define KEY_PROGRAM\t\t0x16a\t/* Media Select Program Guide */\n#define KEY_CHANNEL\t\t0x16b\n#define KEY_FAVORITES\t\t0x16c\n#define KEY_EPG\t\t\t0x16d\n#define KEY_PVR\t\t\t0x16e\t/* Media Select Home */\n#define KEY_MHP\t\t\t0x16f\n#define KEY_LANGUAGE\t\t0x170\n#define KEY_TITLE\t\t0x171\n#define KEY_SUBTITLE\t\t0x172\n#define KEY_ANGLE\t\t0x173\n#define KEY_ZOOM\t\t0x174\n#define KEY_MODE\t\t0x175\n#define KEY_KEYBOARD\t\t0x176\n#define KEY_SCREEN\t\t0x177\n#define KEY_PC\t\t\t0x178\t/* Media Select Computer */\n#define KEY_TV\t\t\t0x179\t/* Media Select TV */\n#define KEY_TV2\t\t\t0x17a\t/* Media Select Cable */\n#define KEY_VCR\t\t\t0x17b\t/* Media Select VCR */\n#define KEY_VCR2\t\t0x17c\t/* VCR Plus */\n#define KEY_SAT\t\t\t0x17d\t/* Media Select Satellite */\n#define KEY_SAT2\t\t0x17e\n#define KEY_CD\t\t\t0x17f\t/* Media Select CD */\n#define KEY_TAPE\t\t0x180\t/* Media Select Tape */\n#define KEY_RADIO\t\t0x181\n#define KEY_TUNER\t\t0x182\t/* Media Select Tuner */\n#define KEY_PLAYER\t\t0x183\n#define KEY_TEXT\t\t0x184\n#define KEY_DVD\t\t\t0x185\t/* Media Select DVD */\n#define KEY_AUX\t\t\t0x186\n#define KEY_MP3\t\t\t0x187\n#define KEY_AUDIO\t\t0x188\t/* AL Audio Browser */\n#define KEY_VIDEO\t\t0x189\t/* AL Movie Browser */\n#define KEY_DIRECTORY\t\t0x18a\n#define KEY_LIST\t\t0x18b\n#define KEY_MEMO\t\t0x18c\t/* Media Select Messages */\n#define KEY_CALENDAR\t\t0x18d\n#define KEY_RED\t\t\t0x18e\n#define KEY_GREEN\t\t0x18f\n#define KEY_YELLOW\t\t0x190\n#define KEY_BLUE\t\t0x191\n#define KEY_CHANNELUP\t\t0x192\t/* Channel Increment */\n#define KEY_CHANNELDOWN\t\t0x193\t/* Channel Decrement */\n#define KEY_FIRST\t\t0x194\n#define KEY_LAST\t\t0x195\t/* Recall Last */\n#define KEY_AB\t\t\t0x196\n#define KEY_NEXT\t\t0x197\n#define KEY_RESTART\t\t0x198\n#define KEY_SLOW\t\t0x199\n#define KEY_SHUFFLE\t\t0x19a\n#define KEY_BREAK\t\t0x19b\n#define KEY_PREVIOUS\t\t0x19c\n#define KEY_DIGITS\t\t0x19d\n#define KEY_TEEN\t\t0x19e\n#define KEY_TWEN\t\t0x19f\n#define KEY_VIDEOPHONE\t\t0x1a0\t/* Media Select Video Phone */\n#define KEY_GAMES\t\t0x1a1\t/* Media Select Games */\n#define KEY_ZOOMIN\t\t0x1a2\t/* AC Zoom In */\n#define KEY_ZOOMOUT\t\t0x1a3\t/* AC Zoom Out */\n#define KEY_ZOOMRESET\t\t0x1a4\t/* AC Zoom */\n#define KEY_WORDPROCESSOR\t0x1a5\t/* AL Word Processor */\n#define KEY_EDITOR\t\t0x1a6\t/* AL Text Editor */\n#define KEY_SPREADSHEET\t\t0x1a7\t/* AL Spreadsheet */\n#define KEY_GRAPHICSEDITOR\t0x1a8\t/* AL Graphics Editor */\n#define KEY_PRESENTATION\t0x1a9\t/* AL Presentation App */\n#define KEY_DATABASE\t\t0x1aa\t/* AL Database App */\n#define KEY_NEWS\t\t0x1ab\t/* AL Newsreader */\n#define KEY_VOICEMAIL\t\t0x1ac\t/* AL Voicemail */\n#define KEY_ADDRESSBOOK\t\t0x1ad\t/* AL Contacts/Address Book */\n#define KEY_MESSENGER\t\t0x1ae\t/* AL Instant Messaging */\n#define KEY_DISPLAYTOGGLE\t0x1af\t/* Turn display (LCD) on and off */\n#define KEY_BRIGHTNESS_TOGGLE\tKEY_DISPLAYTOGGLE\n#define KEY_SPELLCHECK\t\t0x1b0 /* AL Spell Check */\n#define KEY_LOGOFF\t\t0x1b1 /* AL Logoff */\n\n#define KEY_DOLLAR\t\t0x1b2\n#define KEY_EURO\t\t0x1b3\n\n#define KEY_FRAMEBACK\t\t0x1b4\t/* Consumer - transport controls */\n#define KEY_FRAMEFORWARD\t0x1b5\n#define KEY_CONTEXT_MENU\t0x1b6\t/* GenDesc - system context menu */\n#define KEY_MEDIA_REPEAT\t0x1b7\t/* Consumer - transport control */\n#define KEY_10CHANNELSUP\t0x1b8\t/* 10 channels up (10+) */\n#define KEY_10CHANNELSDOWN\t0x1b9\t/* 10 channels down (10-) */\n#define KEY_IMAGES\t\t0x1ba\t/* AL Image Browser */\n\n#define KEY_DEL_EOL\t\t0x1c0\n#define KEY_DEL_EOS\t\t0x1c1\n#define KEY_INS_LINE\t\t0x1c2\n#define KEY_DEL_LINE\t\t0x1c3\n\n#define KEY_FN\t\t\t0x1d0\n#define KEY_FN_ESC\t\t0x1d1\n#define KEY_FN_F1\t\t0x1d2\n#define KEY_FN_F2\t\t0x1d3\n#define KEY_FN_F3\t\t0x1d4\n#define KEY_FN_F4\t\t0x1d5\n#define KEY_FN_F5\t\t0x1d6\n#define KEY_FN_F6\t\t0x1d7\n#define KEY_FN_F7\t\t0x1d8\n#define KEY_FN_F8\t\t0x1d9\n#define KEY_FN_F9\t\t0x1da\n#define KEY_FN_F10\t\t0x1db\n#define KEY_FN_F11\t\t0x1dc\n#define KEY_FN_F12\t\t0x1dd\n#define KEY_FN_1\t\t0x1de\n#define KEY_FN_2\t\t0x1df\n#define KEY_FN_D\t\t0x1e0\n#define KEY_FN_E\t\t0x1e1\n#define KEY_FN_F\t\t0x1e2\n#define KEY_FN_S\t\t0x1e3\n#define KEY_FN_B\t\t0x1e4\n\n#define KEY_BRL_DOT1\t\t0x1f1\n#define KEY_BRL_DOT2\t\t0x1f2\n#define KEY_BRL_DOT3\t\t0x1f3\n#define KEY_BRL_DOT4\t\t0x1f4\n#define KEY_BRL_DOT5\t\t0x1f5\n#define KEY_BRL_DOT6\t\t0x1f6\n#define KEY_BRL_DOT7\t\t0x1f7\n#define KEY_BRL_DOT8\t\t0x1f8\n#define KEY_BRL_DOT9\t\t0x1f9\n#define KEY_BRL_DOT10\t\t0x1fa\n\n#define KEY_NUMERIC_0\t\t0x200\t/* used by phones, remote controls, */\n#define KEY_NUMERIC_1\t\t0x201\t/* and other keypads */\n#define KEY_NUMERIC_2\t\t0x202\n#define KEY_NUMERIC_3\t\t0x203\n#define KEY_NUMERIC_4\t\t0x204\n#define KEY_NUMERIC_5\t\t0x205\n#define KEY_NUMERIC_6\t\t0x206\n#define KEY_NUMERIC_7\t\t0x207\n#define KEY_NUMERIC_8\t\t0x208\n#define KEY_NUMERIC_9\t\t0x209\n#define KEY_NUMERIC_STAR\t0x20a\n#define KEY_NUMERIC_POUND\t0x20b\n#define KEY_NUMERIC_A\t\t0x20c\t/* Phone key A - HUT Telephony 0xb9 */\n#define KEY_NUMERIC_B\t\t0x20d\n#define KEY_NUMERIC_C\t\t0x20e\n#define KEY_NUMERIC_D\t\t0x20f\n\n#define KEY_CAMERA_FOCUS\t0x210\n#define KEY_WPS_BUTTON\t\t0x211\t/* WiFi Protected Setup key */\n\n#define KEY_TOUCHPAD_TOGGLE\t0x212\t/* Request switch touchpad on or off */\n#define KEY_TOUCHPAD_ON\t\t0x213\n#define KEY_TOUCHPAD_OFF\t0x214\n\n#define KEY_CAMERA_ZOOMIN\t0x215\n#define KEY_CAMERA_ZOOMOUT\t0x216\n#define KEY_CAMERA_UP\t\t0x217\n#define KEY_CAMERA_DOWN\t\t0x218\n#define KEY_CAMERA_LEFT\t\t0x219\n#define KEY_CAMERA_RIGHT\t0x21a\n\n#define KEY_ATTENDANT_ON\t0x21b\n#define KEY_ATTENDANT_OFF\t0x21c\n#define KEY_ATTENDANT_TOGGLE\t0x21d\t/* Attendant call on or off */\n#define KEY_LIGHTS_TOGGLE\t0x21e\t/* Reading light on or off */\n\n#define BTN_DPAD_UP\t\t0x220\n#define BTN_DPAD_DOWN\t\t0x221\n#define BTN_DPAD_LEFT\t\t0x222\n#define BTN_DPAD_RIGHT\t\t0x223\n\n#define KEY_ALS_TOGGLE\t\t0x230\t/* Ambient light sensor */\n\n#define KEY_BUTTONCONFIG\t\t0x240\t/* AL Button Configuration */\n#define KEY_TASKMANAGER\t\t0x241\t/* AL Task/Project Manager */\n#define KEY_JOURNAL\t\t0x242\t/* AL Log/Journal/Timecard */\n#define KEY_CONTROLPANEL\t\t0x243\t/* AL Control Panel */\n#define KEY_APPSELECT\t\t0x244\t/* AL Select Task/Application */\n#define KEY_SCREENSAVER\t\t0x245\t/* AL Screen Saver */\n#define KEY_VOICECOMMAND\t\t0x246\t/* Listening Voice Command */\n\n#define KEY_BRIGHTNESS_MIN\t\t0x250\t/* Set Brightness to Minimum */\n#define KEY_BRIGHTNESS_MAX\t\t0x251\t/* Set Brightness to Maximum */\n\n#define KEY_KBDINPUTASSIST_PREV\t\t0x260\n#define KEY_KBDINPUTASSIST_NEXT\t\t0x261\n#define KEY_KBDINPUTASSIST_PREVGROUP\t\t0x262\n#define KEY_KBDINPUTASSIST_NEXTGROUP\t\t0x263\n#define KEY_KBDINPUTASSIST_ACCEPT\t\t0x264\n#define KEY_KBDINPUTASSIST_CANCEL\t\t0x265\n\n#define BTN_TRIGGER_HAPPY\t\t0x2c0\n#define BTN_TRIGGER_HAPPY1\t\t0x2c0\n#define BTN_TRIGGER_HAPPY2\t\t0x2c1\n#define BTN_TRIGGER_HAPPY3\t\t0x2c2\n#define BTN_TRIGGER_HAPPY4\t\t0x2c3\n#define BTN_TRIGGER_HAPPY5\t\t0x2c4\n#define BTN_TRIGGER_HAPPY6\t\t0x2c5\n#define BTN_TRIGGER_HAPPY7\t\t0x2c6\n#define BTN_TRIGGER_HAPPY8\t\t0x2c7\n#define BTN_TRIGGER_HAPPY9\t\t0x2c8\n#define BTN_TRIGGER_HAPPY10\t\t0x2c9\n#define BTN_TRIGGER_HAPPY11\t\t0x2ca\n#define BTN_TRIGGER_HAPPY12\t\t0x2cb\n#define BTN_TRIGGER_HAPPY13\t\t0x2cc\n#define BTN_TRIGGER_HAPPY14\t\t0x2cd\n#define BTN_TRIGGER_HAPPY15\t\t0x2ce\n#define BTN_TRIGGER_HAPPY16\t\t0x2cf\n#define BTN_TRIGGER_HAPPY17\t\t0x2d0\n#define BTN_TRIGGER_HAPPY18\t\t0x2d1\n#define BTN_TRIGGER_HAPPY19\t\t0x2d2\n#define BTN_TRIGGER_HAPPY20\t\t0x2d3\n#define BTN_TRIGGER_HAPPY21\t\t0x2d4\n#define BTN_TRIGGER_HAPPY22\t\t0x2d5\n#define BTN_TRIGGER_HAPPY23\t\t0x2d6\n#define BTN_TRIGGER_HAPPY24\t\t0x2d7\n#define BTN_TRIGGER_HAPPY25\t\t0x2d8\n#define BTN_TRIGGER_HAPPY26\t\t0x2d9\n#define BTN_TRIGGER_HAPPY27\t\t0x2da\n#define BTN_TRIGGER_HAPPY28\t\t0x2db\n#define BTN_TRIGGER_HAPPY29\t\t0x2dc\n#define BTN_TRIGGER_HAPPY30\t\t0x2dd\n#define BTN_TRIGGER_HAPPY31\t\t0x2de\n#define BTN_TRIGGER_HAPPY32\t\t0x2df\n#define BTN_TRIGGER_HAPPY33\t\t0x2e0\n#define BTN_TRIGGER_HAPPY34\t\t0x2e1\n#define BTN_TRIGGER_HAPPY35\t\t0x2e2\n#define BTN_TRIGGER_HAPPY36\t\t0x2e3\n#define BTN_TRIGGER_HAPPY37\t\t0x2e4\n#define BTN_TRIGGER_HAPPY38\t\t0x2e5\n#define BTN_TRIGGER_HAPPY39\t\t0x2e6\n#define BTN_TRIGGER_HAPPY40\t\t0x2e7\n\n/* We avoid low common keys in module aliases so they don't get huge. */\n#define KEY_MIN_INTERESTING\tKEY_MUTE\n#define KEY_MAX\t\t\t0x2ff\n#define KEY_CNT\t\t\t(KEY_MAX+1)\n\n/*\n * Relative axes\n */\n\n#define REL_X\t\t\t0x00\n#define REL_Y\t\t\t0x01\n#define REL_Z\t\t\t0x02\n#define REL_RX\t\t\t0x03\n#define REL_RY\t\t\t0x04\n#define REL_RZ\t\t\t0x05\n#define REL_HWHEEL\t\t0x06\n#define REL_DIAL\t\t0x07\n#define REL_WHEEL\t\t0x08\n#define REL_MISC\t\t0x09\n#define REL_MAX\t\t\t0x0f\n#define REL_CNT\t\t\t(REL_MAX+1)\n\n/*\n * Absolute axes\n */\n\n#define ABS_X\t\t\t0x00\n#define ABS_Y\t\t\t0x01\n#define ABS_Z\t\t\t0x02\n#define ABS_RX\t\t\t0x03\n#define ABS_RY\t\t\t0x04\n#define ABS_RZ\t\t\t0x05\n#define ABS_THROTTLE\t\t0x06\n#define ABS_RUDDER\t\t0x07\n#define ABS_WHEEL\t\t0x08\n#define ABS_GAS\t\t\t0x09\n#define ABS_BRAKE\t\t0x0a\n#define ABS_HAT0X\t\t0x10\n#define ABS_HAT0Y\t\t0x11\n#define ABS_HAT1X\t\t0x12\n#define ABS_HAT1Y\t\t0x13\n#define ABS_HAT2X\t\t0x14\n#define ABS_HAT2Y\t\t0x15\n#define ABS_HAT3X\t\t0x16\n#define ABS_HAT3Y\t\t0x17\n#define ABS_PRESSURE\t\t0x18\n#define ABS_DISTANCE\t\t0x19\n#define ABS_TILT_X\t\t0x1a\n#define ABS_TILT_Y\t\t0x1b\n#define ABS_TOOL_WIDTH\t\t0x1c\n\n#define ABS_VOLUME\t\t0x20\n\n#define ABS_MISC\t\t0x28\n\n#define ABS_MT_SLOT\t\t0x2f\t/* MT slot being modified */\n#define ABS_MT_TOUCH_MAJOR\t0x30\t/* Major axis of touching ellipse */\n#define ABS_MT_TOUCH_MINOR\t0x31\t/* Minor axis (omit if circular) */\n#define ABS_MT_WIDTH_MAJOR\t0x32\t/* Major axis of approaching ellipse */\n#define ABS_MT_WIDTH_MINOR\t0x33\t/* Minor axis (omit if circular) */\n#define ABS_MT_ORIENTATION\t0x34\t/* Ellipse orientation */\n#define ABS_MT_POSITION_X\t0x35\t/* Center X touch position */\n#define ABS_MT_POSITION_Y\t0x36\t/* Center Y touch position */\n#define ABS_MT_TOOL_TYPE\t0x37\t/* Type of touching device */\n#define ABS_MT_BLOB_ID\t\t0x38\t/* Group a set of packets as a blob */\n#define ABS_MT_TRACKING_ID\t0x39\t/* Unique ID of initiated contact */\n#define ABS_MT_PRESSURE\t\t0x3a\t/* Pressure on contact area */\n#define ABS_MT_DISTANCE\t\t0x3b\t/* Contact hover distance */\n#define ABS_MT_TOOL_X\t\t0x3c\t/* Center X tool position */\n#define ABS_MT_TOOL_Y\t\t0x3d\t/* Center Y tool position */\n\n\n#define ABS_MAX\t\t\t0x3f\n#define ABS_CNT\t\t\t(ABS_MAX+1)\n\n/*\n * Switch events\n */\n\n#define SW_LID\t\t\t0x00 /* set = lid shut */\n#define SW_TABLET_MODE\t\t0x01 /* set = tablet mode */\n#define SW_HEADPHONE_INSERT\t0x02 /* set = inserted */\n#define SW_RFKILL_ALL\t\t0x03 /* rfkill master switch, type \"any\"\n\t\t\t\t\t set = radio enabled */\n#define SW_RADIO\t\tSW_RFKILL_ALL\t/* deprecated */\n#define SW_MICROPHONE_INSERT\t0x04 /* set = inserted */\n#define SW_DOCK\t\t\t0x05 /* set = plugged into dock */\n#define SW_LINEOUT_INSERT\t0x06 /* set = inserted */\n#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */\n#define SW_VIDEOOUT_INSERT\t0x08 /* set = inserted */\n#define SW_CAMERA_LENS_COVER\t0x09 /* set = lens covered */\n#define SW_KEYPAD_SLIDE\t\t0x0a /* set = keypad slide out */\n#define SW_FRONT_PROXIMITY\t0x0b /* set = front proximity sensor active */\n#define SW_ROTATE_LOCK\t\t0x0c /* set = rotate locked/disabled */\n#define SW_LINEIN_INSERT\t0x0d /* set = inserted */\n#define SW_MUTE_DEVICE\t\t0x0e /* set = device disabled */\n#define SW_MAX\t\t\t0x0f\n#define SW_CNT\t\t\t(SW_MAX+1)\n\n/*\n * Misc events\n */\n\n#define MSC_SERIAL\t\t0x00\n#define MSC_PULSELED\t\t0x01\n#define MSC_GESTURE\t\t0x02\n#define MSC_RAW\t\t\t0x03\n#define MSC_SCAN\t\t0x04\n#define MSC_TIMESTAMP\t\t0x05\n#define MSC_MAX\t\t\t0x07\n#define MSC_CNT\t\t\t(MSC_MAX+1)\n\n/*\n * LEDs\n */\n\n#define LED_NUML\t\t0x00\n#define LED_CAPSL\t\t0x01\n#define LED_SCROLLL\t\t0x02\n#define LED_COMPOSE\t\t0x03\n#define LED_KANA\t\t0x04\n#define LED_SLEEP\t\t0x05\n#define LED_SUSPEND\t\t0x06\n#define LED_MUTE\t\t0x07\n#define LED_MISC\t\t0x08\n#define LED_MAIL\t\t0x09\n#define LED_CHARGING\t\t0x0a\n#define LED_MAX\t\t\t0x0f\n#define LED_CNT\t\t\t(LED_MAX+1)\n\n/*\n * Autorepeat values\n */\n\n#define REP_DELAY\t\t0x00\n#define REP_PERIOD\t\t0x01\n#define REP_MAX\t\t\t0x01\n#define REP_CNT\t\t\t(REP_MAX+1)\n\n/*\n * Sounds\n */\n\n#define SND_CLICK\t\t0x00\n#define SND_BELL\t\t0x01\n#define SND_TONE\t\t0x02\n#define SND_MAX\t\t\t0x07\n#define SND_CNT\t\t\t(SND_MAX+1)\n\n#define MATRIX_KEY(row, col, code)\t\\\n\t((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))\n\n#endif /* _DT_BINDINGS_INPUT_INPUT_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/interrupt-controller/irq.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * This header provides constants for most IRQ bindings.\n *\n * Most IRQ bindings include a flags cell as part of the IRQ specifier.\n * In most cases, the format of the flags cell uses the standard values\n * defined in this header.\n */\n\n#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H\n\n#define IRQ_TYPE_NONE\t\t0\n#define IRQ_TYPE_EDGE_RISING\t1\n#define IRQ_TYPE_EDGE_FALLING\t2\n#define IRQ_TYPE_EDGE_BOTH\t(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)\n#define IRQ_TYPE_LEVEL_HIGH\t4\n#define IRQ_TYPE_LEVEL_LOW\t8\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/net/mscc-phy-vsc8531.h", "content": "/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */\n/*\n * Device Tree constants for Microsemi VSC8531 PHY\n *\n * Author: Nagaraju Lakkaraju\n *\n * Copyright (c) 2017 Microsemi Corporation\n */\n\n#ifndef _DT_BINDINGS_MSCC_VSC8531_H\n#define _DT_BINDINGS_MSCC_VSC8531_H\n\n/* PHY LED Modes */\n#define VSC8531_LINK_ACTIVITY\t\t\t0\n#define VSC8531_LINK_1000_ACTIVITY\t\t1\n#define VSC8531_LINK_100_ACTIVITY\t\t2\n#define VSC8531_LINK_10_ACTIVITY\t\t3\n#define VSC8531_LINK_100_1000_ACTIVITY\t\t4\n#define VSC8531_LINK_10_1000_ACTIVITY\t\t5\n#define VSC8531_LINK_10_100_ACTIVITY\t\t6\n#define VSC8584_LINK_100FX_1000X_ACTIVITY\t7\n#define VSC8531_DUPLEX_COLLISION\t\t8\n#define VSC8531_COLLISION\t\t\t9\n#define VSC8531_ACTIVITY\t\t\t10\n#define VSC8584_100FX_1000X_ACTIVITY\t\t11\n#define VSC8531_AUTONEG_FAULT\t\t\t12\n#define VSC8531_SERIAL_MODE\t\t\t13\n#define VSC8531_FORCE_LED_OFF\t\t\t14\n#define VSC8531_FORCE_LED_ON\t\t\t15\n\n#define VSC8531_RGMII_CLK_DELAY_0_2_NS\t0\n#define VSC8531_RGMII_CLK_DELAY_0_8_NS\t1\n#define VSC8531_RGMII_CLK_DELAY_1_1_NS\t2\n#define VSC8531_RGMII_CLK_DELAY_1_7_NS\t3\n#define VSC8531_RGMII_CLK_DELAY_2_0_NS\t4\n#define VSC8531_RGMII_CLK_DELAY_2_3_NS\t5\n#define VSC8531_RGMII_CLK_DELAY_2_6_NS\t6\n#define VSC8531_RGMII_CLK_DELAY_3_4_NS\t7\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/net/ti-dp83867.h", "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Device Tree constants for the Texas Instruments DP83867 PHY\n *\n * Author: Dan Murphy \n *\n * Copyright: (C) 2015 Texas Instruments, Inc.\n */\n\n#ifndef _DT_BINDINGS_TI_DP83867_H\n#define _DT_BINDINGS_TI_DP83867_H\n\n/* PHY CTRL bits */\n#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB\t0x00\n#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB\t0x01\n#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB\t0x02\n#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB\t0x03\n\n/* RGMIIDCTL internal delay for rx and tx */\n#define\tDP83867_RGMIIDCTL_250_PS\t0x0\n#define\tDP83867_RGMIIDCTL_500_PS\t0x1\n#define\tDP83867_RGMIIDCTL_750_PS\t0x2\n#define\tDP83867_RGMIIDCTL_1_NS\t\t0x3\n#define\tDP83867_RGMIIDCTL_1_25_NS\t0x4\n#define\tDP83867_RGMIIDCTL_1_50_NS\t0x5\n#define\tDP83867_RGMIIDCTL_1_75_NS\t0x6\n#define\tDP83867_RGMIIDCTL_2_00_NS\t0x7\n#define\tDP83867_RGMIIDCTL_2_25_NS\t0x8\n#define\tDP83867_RGMIIDCTL_2_50_NS\t0x9\n#define\tDP83867_RGMIIDCTL_2_75_NS\t0xa\n#define\tDP83867_RGMIIDCTL_3_00_NS\t0xb\n#define\tDP83867_RGMIIDCTL_3_25_NS\t0xc\n#define\tDP83867_RGMIIDCTL_3_50_NS\t0xd\n#define\tDP83867_RGMIIDCTL_3_75_NS\t0xe\n#define\tDP83867_RGMIIDCTL_4_00_NS\t0xf\n\n/* IO_MUX_CFG - Clock output selection */\n#define DP83867_CLK_O_SEL_CHN_A_RCLK\t\t0x0\n#define DP83867_CLK_O_SEL_CHN_B_RCLK\t\t0x1\n#define DP83867_CLK_O_SEL_CHN_C_RCLK\t\t0x2\n#define DP83867_CLK_O_SEL_CHN_D_RCLK\t\t0x3\n#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5\t0x4\n#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5\t0x5\n#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5\t0x6\n#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5\t0x7\n#define DP83867_CLK_O_SEL_CHN_A_TCLK\t\t0x8\n#define DP83867_CLK_O_SEL_CHN_B_TCLK\t\t0x9\n#define DP83867_CLK_O_SEL_CHN_C_TCLK\t\t0xA\n#define DP83867_CLK_O_SEL_CHN_D_TCLK\t\t0xB\n#define DP83867_CLK_O_SEL_REF_CLK\t\t0xC\n/* Special flag to indicate clock should be off */\n#define DP83867_CLK_O_SEL_OFF\t\t\t0xFFFFFFFF\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/phy/phy.h", "content": "/*\n *\n * This header provides constants for the phy framework\n *\n * Copyright (C) 2014 STMicroelectronics\n * Author: Gabriel Fernandez \n * License terms: GNU General Public License (GPL), version 2\n */\n\n#ifndef _DT_BINDINGS_PHY\n#define _DT_BINDINGS_PHY\n\n#define PHY_NONE\t\t0\n#define PHY_TYPE_SATA\t\t1\n#define PHY_TYPE_PCIE\t\t2\n#define PHY_TYPE_USB2\t\t3\n#define PHY_TYPE_USB3\t\t4\n#define PHY_TYPE_UFS\t\t5\n#define PHY_TYPE_DP\t\t6\n#define PHY_TYPE_XPCS\t\t7\n#define PHY_TYPE_SGMII\t\t8\n#define PHY_TYPE_QSGMII\t\t9\n\n#endif /* _DT_BINDINGS_PHY */\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * MIO pin configuration defines for Xilinx ZynqMP\n *\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H\n#define _DT_BINDINGS_PINCTRL_ZYNQMP_H\n\n/* Bit value for different voltage levels */\n#define IO_STANDARD_LVCMOS33\t0\n#define IO_STANDARD_LVCMOS18\t1\n\n/* Bit values for Slew Rates */\n#define SLEW_RATE_FAST\t\t0\n#define SLEW_RATE_SLOW\t\t1\n\n/* Bit values for Pin drive strength */\n#define DRIVE_STRENGTH_2MA\t2\n#define DRIVE_STRENGTH_4MA\t4\n#define DRIVE_STRENGTH_8MA\t8\n#define DRIVE_STRENGTH_12MA\t12\n\n#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/power/xlnx-versal-net-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2022, Xilinx, Inc.\n * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_NET_POWER_H\n#define _DT_BINDINGS_VERSAL_NET_POWER_H\n\n#include \n\n#define PM_DEV_USB_1\t\t\t\t(0x182240D7U)\n#define PM_DEV_FPD_SWDT_0\t\t\t(0x182240DBU)\n#define PM_DEV_FPD_SWDT_1\t\t\t(0x182240DCU)\n#define PM_DEV_FPD_SWDT_2\t\t\t(0x182240DDU)\n#define PM_DEV_FPD_SWDT_3\t\t\t(0x182240DEU)\n#define PM_DEV_TCM_A_0A\t\t\t\t(0x183180CBU)\n#define PM_DEV_TCM_A_0B\t\t\t\t(0x183180CCU)\n#define PM_DEV_TCM_A_0C\t\t\t\t(0x183180CDU)\n#define PM_DEV_RPU_A_0\t\t\t\t(0x181100BFU)\n#define PM_DEV_LPD_SWDT_0\t\t\t(0x182240D9U)\n#define PM_DEV_LPD_SWDT_1\t\t\t(0x182240DAU)\n\n/* Remove Versal specific node IDs */\n#undef PM_DEV_RPU0_0\n#undef PM_DEV_RPU0_1\n#undef PM_DEV_OCM_0\n#undef PM_DEV_OCM_1\n#undef PM_DEV_OCM_2\n#undef PM_DEV_OCM_3\n#undef PM_DEV_TCM_0_A\n#undef PM_DEV_TCM_1_A\n#undef PM_DEV_TCM_0_B\n#undef PM_DEV_TCM_1_B\n#undef PM_DEV_SWDT_FPD\n#undef PM_DEV_AI\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/power/xlnx-versal-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2019-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_POWER_H\n#define _DT_BINDINGS_VERSAL_POWER_H\n\n#define PM_DEV_USB_0\t\t\t\t(0x18224018U)\n#define PM_DEV_GEM_0\t\t\t\t(0x18224019U)\n#define PM_DEV_GEM_1\t\t\t\t(0x1822401aU)\n#define PM_DEV_SPI_0\t\t\t\t(0x1822401bU)\n#define PM_DEV_SPI_1\t\t\t\t(0x1822401cU)\n#define PM_DEV_I2C_0\t\t\t\t(0x1822401dU)\n#define PM_DEV_I2C_1\t\t\t\t(0x1822401eU)\n#define PM_DEV_I2C_PMC (0x1822402dU)\n#define PM_DEV_CAN_FD_0\t\t\t\t(0x1822401fU)\n#define PM_DEV_CAN_FD_1\t\t\t\t(0x18224020U)\n#define PM_DEV_UART_0\t\t\t\t(0x18224021U)\n#define PM_DEV_UART_1\t\t\t\t(0x18224022U)\n#define PM_DEV_GPIO\t\t\t\t(0x18224023U)\n#define PM_DEV_TTC_0\t\t\t\t(0x18224024U)\n#define PM_DEV_TTC_1\t\t\t\t(0x18224025U)\n#define PM_DEV_TTC_2\t\t\t\t(0x18224026U)\n#define PM_DEV_TTC_3\t\t\t\t(0x18224027U)\n#define PM_DEV_SWDT_LPD\t\t\t\t(0x18224028U)\n#define PM_DEV_SWDT_FPD\t\t\t\t(0x18224029U)\n#define PM_DEV_OSPI\t\t\t\t(0x1822402aU)\n#define PM_DEV_QSPI\t\t\t\t(0x1822402bU)\n#define PM_DEV_GPIO_PMC\t\t\t\t(0x1822402cU)\n#define PM_DEV_SDIO_0\t\t\t\t(0x1822402eU)\n#define PM_DEV_SDIO_1\t\t\t\t(0x1822402fU)\n#define PM_DEV_RTC\t\t\t\t(0x18224034U)\n#define PM_DEV_ADMA_0\t\t\t\t(0x18224035U)\n#define PM_DEV_ADMA_1\t\t\t\t(0x18224036U)\n#define PM_DEV_ADMA_2\t\t\t\t(0x18224037U)\n#define PM_DEV_ADMA_3\t\t\t\t(0x18224038U)\n#define PM_DEV_ADMA_4\t\t\t\t(0x18224039U)\n#define PM_DEV_ADMA_5\t\t\t\t(0x1822403aU)\n#define PM_DEV_ADMA_6\t\t\t\t(0x1822403bU)\n#define PM_DEV_ADMA_7\t\t\t\t(0x1822403cU)\n#define PM_DEV_AI\t\t\t\t(0x18224072U)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/power/xlnx-versal-regnode.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2022-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_REGNODE_H\n#define _DT_BINDINGS_VERSAL_REGNODE_H\n\n#define PM_REGNODE_SYSMON_ROOT_0\t\t\t(0x18224055U)\n#define PM_REGNODE_SYSMON_ROOT_1\t\t\t(0x18225055U)\n#define PM_REGNODE_SYSMON_ROOT_2\t\t\t(0x18226055U)\n#define PM_REGNODE_SYSMON_ROOT_3\t\t\t(0x18227055U)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/power/xlnx-zynqmp-power.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_POWER_H\n#define _DT_BINDINGS_ZYNQMP_POWER_H\n\n#define\t\tPD_USB_0\t22\n#define\t\tPD_USB_1\t23\n#define\t\tPD_TTC_0\t24\n#define\t\tPD_TTC_1\t25\n#define\t\tPD_TTC_2\t26\n#define\t\tPD_TTC_3\t27\n#define\t\tPD_SATA\t\t28\n#define\t\tPD_ETH_0\t29\n#define\t\tPD_ETH_1\t30\n#define\t\tPD_ETH_2\t31\n#define\t\tPD_ETH_3\t32\n#define\t\tPD_UART_0\t33\n#define\t\tPD_UART_1\t34\n#define\t\tPD_SPI_0\t35\n#define\t\tPD_SPI_1\t36\n#define\t\tPD_I2C_0\t37\n#define\t\tPD_I2C_1\t38\n#define\t\tPD_SD_0\t\t39\n#define\t\tPD_SD_1\t\t40\n#define\t\tPD_DP\t\t41\n#define\t\tPD_GDMA\t\t42\n#define\t\tPD_ADMA\t\t43\n#define\t\tPD_NAND\t\t44\n#define\t\tPD_QSPI\t\t45\n#define\t\tPD_GPIO\t\t46\n#define\t\tPD_CAN_0\t47\n#define\t\tPD_CAN_1\t48\n#define\t\tPD_GPU\t\t58\n#define\t\tPD_PCIE\t\t59\n#define\t\tPD_PL\t\t69\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/reset/xlnx-versal-net-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H\n#define _DT_BINDINGS_VERSAL_NET_RESETS_H\n\n#include \"xlnx-versal-resets.h\"\n\n#define VERSAL_RST_USB_1\t\t\t(0xC1040C6U)\n\n/* Remove Versal specific reset IDs */\n#undef VERSAL_RST_ACPU_0_POR\n#undef VERSAL_RST_ACPU_1_POR\n#undef VERSAL_RST_OCM2_POR\n#undef VERSAL_RST_APU\n#undef VERSAL_RST_ACPU_0\n#undef VERSAL_RST_ACPU_1\n#undef VERSAL_RST_ACPU_L2\n#undef VERSAL_RST_RPU_ISLAND\n#undef VERSAL_RST_RPU_AMBA\n#undef VERSAL_RST_R5_0\n#undef VERSAL_RST_R5_1\n#undef VERSAL_RST_OCM2_RST\n#undef VERSAL_RST_I2C_PMC\n#undef VERSAL_RST_I2C_0\n#undef VERSAL_RST_I2C_1\n#undef VERSAL_RST_SWDT_FPD\n#undef VERSAL_RST_SWDT_LPD\n#undef VERSAL_RST_USB\n#undef VERSAL_RST_DPC\n#undef VERSAL_RST_DBG_TRACE\n#undef VERSAL_RST_DBG_TSTMP\n#undef VERSAL_RST_RPU0_DBG\n#undef VERSAL_RST_RPU1_DBG\n#undef VERSAL_RST_HSDP\n#undef VERSAL_RST_CPMDBG\n#undef VERSAL_RST_PCIE_CFG\n#undef VERSAL_RST_PCIE_CORE0\n#undef VERSAL_RST_PCIE_CORE1\n#undef VERSAL_RST_PCIE_DMA\n#undef VERSAL_RST_L2_0\n#undef VERSAL_RST_L2_1\n#undef VERSAL_RST_ADDR_REMAP\n#undef VERSAL_RST_CPI0\n#undef VERSAL_RST_CPI1\n#undef VERSAL_RST_XRAM\n#undef VERSAL_RST_AIE_ARRAY\n#undef VERSAL_RST_AIE_SHIM\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/reset/xlnx-versal-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2020-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_VERSAL_RESETS_H\n#define _DT_BINDINGS_VERSAL_RESETS_H\n\n#define VERSAL_RST_PMC_POR\t\t\t(0xc30c001U)\n#define VERSAL_RST_PMC\t\t\t\t(0xc410002U)\n#define VERSAL_RST_PS_POR\t\t\t(0xc30c003U)\n#define VERSAL_RST_PL_POR\t\t\t(0xc30c004U)\n#define VERSAL_RST_NOC_POR\t\t\t(0xc30c005U)\n#define VERSAL_RST_FPD_POR\t\t\t(0xc30c006U)\n#define VERSAL_RST_ACPU_0_POR\t\t\t(0xc30c007U)\n#define VERSAL_RST_ACPU_1_POR\t\t\t(0xc30c008U)\n#define VERSAL_RST_OCM2_POR\t\t\t(0xc30c009U)\n#define VERSAL_RST_PS_SRST\t\t\t(0xc41000aU)\n#define VERSAL_RST_PL_SRST\t\t\t(0xc41000bU)\n#define VERSAL_RST_NOC\t\t\t\t(0xc41000cU)\n#define VERSAL_RST_NPI\t\t\t\t(0xc41000dU)\n#define VERSAL_RST_SYS_RST_1\t\t\t(0xc41000eU)\n#define VERSAL_RST_SYS_RST_2\t\t\t(0xc41000fU)\n#define VERSAL_RST_SYS_RST_3\t\t\t(0xc410010U)\n#define VERSAL_RST_FPD\t\t\t\t(0xc410011U)\n#define VERSAL_RST_PL0\t\t\t\t(0xc410012U)\n#define VERSAL_RST_PL1\t\t\t\t(0xc410013U)\n#define VERSAL_RST_PL2\t\t\t\t(0xc410014U)\n#define VERSAL_RST_PL3\t\t\t\t(0xc410015U)\n#define VERSAL_RST_APU\t\t\t\t(0xc410016U)\n#define VERSAL_RST_ACPU_0\t\t\t(0xc410017U)\n#define VERSAL_RST_ACPU_1\t\t\t(0xc410018U)\n#define VERSAL_RST_ACPU_L2\t\t\t(0xc410019U)\n#define VERSAL_RST_ACPU_GIC\t\t\t(0xc41001aU)\n#define VERSAL_RST_RPU_ISLAND\t\t\t(0xc41001bU)\n#define VERSAL_RST_RPU_AMBA\t\t\t(0xc41001cU)\n#define VERSAL_RST_R5_0\t\t\t\t(0xc41001dU)\n#define VERSAL_RST_R5_1\t\t\t\t(0xc41001eU)\n#define VERSAL_RST_SYSMON_PMC_SEQ_RST\t\t(0xc41001fU)\n#define VERSAL_RST_SYSMON_PMC_CFG_RST\t\t(0xc410020U)\n#define VERSAL_RST_SYSMON_FPD_CFG_RST\t\t(0xc410021U)\n#define VERSAL_RST_SYSMON_FPD_SEQ_RST\t\t(0xc410022U)\n#define VERSAL_RST_SYSMON_LPD\t\t\t(0xc410023U)\n#define VERSAL_RST_PDMA_RST1\t\t\t(0xc410024U)\n#define VERSAL_RST_PDMA_RST0\t\t\t(0xc410025U)\n#define VERSAL_RST_ADMA\t\t\t\t(0xc410026U)\n#define VERSAL_RST_TIMESTAMP\t\t\t(0xc410027U)\n#define VERSAL_RST_OCM\t\t\t\t(0xc410028U)\n#define VERSAL_RST_OCM2_RST\t\t\t(0xc410029U)\n#define VERSAL_RST_IPI\t\t\t\t(0xc41002aU)\n#define VERSAL_RST_SBI\t\t\t\t(0xc41002bU)\n#define VERSAL_RST_LPD\t\t\t\t(0xc41002cU)\n#define VERSAL_RST_QSPI\t\t\t\t(0xc10402dU)\n#define VERSAL_RST_OSPI\t\t\t\t(0xc10402eU)\n#define VERSAL_RST_SDIO_0\t\t\t(0xc10402fU)\n#define VERSAL_RST_SDIO_1\t\t\t(0xc104030U)\n#define VERSAL_RST_I2C_PMC\t\t\t(0xc104031U)\n#define VERSAL_RST_GPIO_PMC\t\t\t(0xc104032U)\n#define VERSAL_RST_GEM_0\t\t\t(0xc104033U)\n#define VERSAL_RST_GEM_1\t\t\t(0xc104034U)\n#define VERSAL_RST_SPARE\t\t\t(0xc104035U)\n#define VERSAL_RST_USB_0\t\t\t(0xc104036U)\n#define VERSAL_RST_UART_0\t\t\t(0xc104037U)\n#define VERSAL_RST_UART_1\t\t\t(0xc104038U)\n#define VERSAL_RST_SPI_0\t\t\t(0xc104039U)\n#define VERSAL_RST_SPI_1\t\t\t(0xc10403aU)\n#define VERSAL_RST_CAN_FD_0\t\t\t(0xc10403bU)\n#define VERSAL_RST_CAN_FD_1\t\t\t(0xc10403cU)\n#define VERSAL_RST_I2C_0\t\t\t(0xc10403dU)\n#define VERSAL_RST_I2C_1\t\t\t(0xc10403eU)\n#define VERSAL_RST_GPIO_LPD\t\t\t(0xc10403fU)\n#define VERSAL_RST_TTC_0\t\t\t(0xc104040U)\n#define VERSAL_RST_TTC_1\t\t\t(0xc104041U)\n#define VERSAL_RST_TTC_2\t\t\t(0xc104042U)\n#define VERSAL_RST_TTC_3\t\t\t(0xc104043U)\n#define VERSAL_RST_SWDT_FPD\t\t\t(0xc104044U)\n#define VERSAL_RST_SWDT_LPD\t\t\t(0xc104045U)\n#define VERSAL_RST_USB\t\t\t\t(0xc104046U)\n#define VERSAL_RST_DPC\t\t\t\t(0xc208047U)\n#define VERSAL_RST_PMCDBG\t\t\t(0xc208048U)\n#define VERSAL_RST_DBG_TRACE\t\t\t(0xc208049U)\n#define VERSAL_RST_DBG_FPD\t\t\t(0xc20804aU)\n#define VERSAL_RST_DBG_TSTMP\t\t\t(0xc20804bU)\n#define VERSAL_RST_RPU0_DBG\t\t\t(0xc20804cU)\n#define VERSAL_RST_RPU1_DBG\t\t\t(0xc20804dU)\n#define VERSAL_RST_HSDP\t\t\t\t(0xc20804eU)\n#define VERSAL_RST_DBG_LPD\t\t\t(0xc20804fU)\n#define VERSAL_RST_CPM_POR\t\t\t(0xc30c050U)\n#define VERSAL_RST_CPM\t\t\t\t(0xc410051U)\n#define VERSAL_RST_CPMDBG\t\t\t(0xc208052U)\n#define VERSAL_RST_PCIE_CFG\t\t\t(0xc410053U)\n#define VERSAL_RST_PCIE_CORE0\t\t\t(0xc410054U)\n#define VERSAL_RST_PCIE_CORE1\t\t\t(0xc410055U)\n#define VERSAL_RST_PCIE_DMA\t\t\t(0xc410056U)\n#define VERSAL_RST_CMN\t\t\t\t(0xc410057U)\n#define VERSAL_RST_L2_0\t\t\t\t(0xc410058U)\n#define VERSAL_RST_L2_1\t\t\t\t(0xc410059U)\n#define VERSAL_RST_ADDR_REMAP\t\t\t(0xc41005aU)\n#define VERSAL_RST_CPI0\t\t\t\t(0xc41005bU)\n#define VERSAL_RST_CPI1\t\t\t\t(0xc41005cU)\n#define VERSAL_RST_XRAM\t\t\t\t(0xc30c05dU)\n#define VERSAL_RST_AIE_ARRAY\t\t\t(0xc10405eU)\n#define VERSAL_RST_AIE_SHIM\t\t\t(0xc10405fU)\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h", "content": "/* SPDX-License-Identifier: GPL-2.0 */\n/*\n * Copyright (C) 2018-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n */\n\n#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H\n#define _DT_BINDINGS_ZYNQMP_RESETS_H\n\n#define\t\tZYNQMP_RESET_PCIE_CFG\t\t0\n#define\t\tZYNQMP_RESET_PCIE_BRIDGE\t1\n#define\t\tZYNQMP_RESET_PCIE_CTRL\t\t2\n#define\t\tZYNQMP_RESET_DP\t\t\t3\n#define\t\tZYNQMP_RESET_SWDT_CRF\t\t4\n#define\t\tZYNQMP_RESET_AFI_FM5\t\t5\n#define\t\tZYNQMP_RESET_AFI_FM4\t\t6\n#define\t\tZYNQMP_RESET_AFI_FM3\t\t7\n#define\t\tZYNQMP_RESET_AFI_FM2\t\t8\n#define\t\tZYNQMP_RESET_AFI_FM1\t\t9\n#define\t\tZYNQMP_RESET_AFI_FM0\t\t10\n#define\t\tZYNQMP_RESET_GDMA\t\t11\n#define\t\tZYNQMP_RESET_GPU_PP1\t\t12\n#define\t\tZYNQMP_RESET_GPU_PP0\t\t13\n#define\t\tZYNQMP_RESET_GPU\t\t14\n#define\t\tZYNQMP_RESET_GT\t\t\t15\n#define\t\tZYNQMP_RESET_SATA\t\t16\n#define\t\tZYNQMP_RESET_ACPU3_PWRON\t17\n#define\t\tZYNQMP_RESET_ACPU2_PWRON\t18\n#define\t\tZYNQMP_RESET_ACPU1_PWRON\t19\n#define\t\tZYNQMP_RESET_ACPU0_PWRON\t20\n#define\t\tZYNQMP_RESET_APU_L2\t\t21\n#define\t\tZYNQMP_RESET_ACPU3\t\t22\n#define\t\tZYNQMP_RESET_ACPU2\t\t23\n#define\t\tZYNQMP_RESET_ACPU1\t\t24\n#define\t\tZYNQMP_RESET_ACPU0\t\t25\n#define\t\tZYNQMP_RESET_DDR\t\t26\n#define\t\tZYNQMP_RESET_APM_FPD\t\t27\n#define\t\tZYNQMP_RESET_SOFT\t\t28\n#define\t\tZYNQMP_RESET_GEM0\t\t29\n#define\t\tZYNQMP_RESET_GEM1\t\t30\n#define\t\tZYNQMP_RESET_GEM2\t\t31\n#define\t\tZYNQMP_RESET_GEM3\t\t32\n#define\t\tZYNQMP_RESET_QSPI\t\t33\n#define\t\tZYNQMP_RESET_UART0\t\t34\n#define\t\tZYNQMP_RESET_UART1\t\t35\n#define\t\tZYNQMP_RESET_SPI0\t\t36\n#define\t\tZYNQMP_RESET_SPI1\t\t37\n#define\t\tZYNQMP_RESET_SDIO0\t\t38\n#define\t\tZYNQMP_RESET_SDIO1\t\t39\n#define\t\tZYNQMP_RESET_CAN0\t\t40\n#define\t\tZYNQMP_RESET_CAN1\t\t41\n#define\t\tZYNQMP_RESET_I2C0\t\t42\n#define\t\tZYNQMP_RESET_I2C1\t\t43\n#define\t\tZYNQMP_RESET_TTC0\t\t44\n#define\t\tZYNQMP_RESET_TTC1\t\t45\n#define\t\tZYNQMP_RESET_TTC2\t\t46\n#define\t\tZYNQMP_RESET_TTC3\t\t47\n#define\t\tZYNQMP_RESET_SWDT_CRL\t\t48\n#define\t\tZYNQMP_RESET_NAND\t\t49\n#define\t\tZYNQMP_RESET_ADMA\t\t50\n#define\t\tZYNQMP_RESET_GPIO\t\t51\n#define\t\tZYNQMP_RESET_IOU_CC\t\t52\n#define\t\tZYNQMP_RESET_TIMESTAMP\t\t53\n#define\t\tZYNQMP_RESET_RPU_R50\t\t54\n#define\t\tZYNQMP_RESET_RPU_R51\t\t55\n#define\t\tZYNQMP_RESET_RPU_AMBA\t\t56\n#define\t\tZYNQMP_RESET_OCM\t\t57\n#define\t\tZYNQMP_RESET_RPU_PGE\t\t58\n#define\t\tZYNQMP_RESET_USB0_CORERESET\t59\n#define\t\tZYNQMP_RESET_USB1_CORERESET\t60\n#define\t\tZYNQMP_RESET_USB0_HIBERRESET\t61\n#define\t\tZYNQMP_RESET_USB1_HIBERRESET\t62\n#define\t\tZYNQMP_RESET_USB0_APB\t\t63\n#define\t\tZYNQMP_RESET_USB1_APB\t\t64\n#define\t\tZYNQMP_RESET_IPI\t\t65\n#define\t\tZYNQMP_RESET_APM_LPD\t\t66\n#define\t\tZYNQMP_RESET_RTC\t\t67\n#define\t\tZYNQMP_RESET_SYSMON\t\t68\n#define\t\tZYNQMP_RESET_AFI_FM6\t\t69\n#define\t\tZYNQMP_RESET_LPD_SWDT\t\t70\n#define\t\tZYNQMP_RESET_FPD\t\t71\n#define\t\tZYNQMP_RESET_RPU_DBG1\t\t72\n#define\t\tZYNQMP_RESET_RPU_DBG0\t\t73\n#define\t\tZYNQMP_RESET_DBG_LPD\t\t74\n#define\t\tZYNQMP_RESET_DBG_FPD\t\t75\n#define\t\tZYNQMP_RESET_APLL\t\t76\n#define\t\tZYNQMP_RESET_DPLL\t\t77\n#define\t\tZYNQMP_RESET_VPLL\t\t78\n#define\t\tZYNQMP_RESET_IOPLL\t\t79\n#define\t\tZYNQMP_RESET_RPLL\t\t80\n#define\t\tZYNQMP_RESET_GPO3_PL_0\t\t81\n#define\t\tZYNQMP_RESET_GPO3_PL_1\t\t82\n#define\t\tZYNQMP_RESET_GPO3_PL_2\t\t83\n#define\t\tZYNQMP_RESET_GPO3_PL_3\t\t84\n#define\t\tZYNQMP_RESET_GPO3_PL_4\t\t85\n#define\t\tZYNQMP_RESET_GPO3_PL_5\t\t86\n#define\t\tZYNQMP_RESET_GPO3_PL_6\t\t87\n#define\t\tZYNQMP_RESET_GPO3_PL_7\t\t88\n#define\t\tZYNQMP_RESET_GPO3_PL_8\t\t89\n#define\t\tZYNQMP_RESET_GPO3_PL_9\t\t90\n#define\t\tZYNQMP_RESET_GPO3_PL_10\t\t91\n#define\t\tZYNQMP_RESET_GPO3_PL_11\t\t92\n#define\t\tZYNQMP_RESET_GPO3_PL_12\t\t93\n#define\t\tZYNQMP_RESET_GPO3_PL_13\t\t94\n#define\t\tZYNQMP_RESET_GPO3_PL_14\t\t95\n#define\t\tZYNQMP_RESET_GPO3_PL_15\t\t96\n#define\t\tZYNQMP_RESET_GPO3_PL_16\t\t97\n#define\t\tZYNQMP_RESET_GPO3_PL_17\t\t98\n#define\t\tZYNQMP_RESET_GPO3_PL_18\t\t99\n#define\t\tZYNQMP_RESET_GPO3_PL_19\t\t100\n#define\t\tZYNQMP_RESET_GPO3_PL_20\t\t101\n#define\t\tZYNQMP_RESET_GPO3_PL_21\t\t102\n#define\t\tZYNQMP_RESET_GPO3_PL_22\t\t103\n#define\t\tZYNQMP_RESET_GPO3_PL_23\t\t104\n#define\t\tZYNQMP_RESET_GPO3_PL_24\t\t105\n#define\t\tZYNQMP_RESET_GPO3_PL_25\t\t106\n#define\t\tZYNQMP_RESET_GPO3_PL_26\t\t107\n#define\t\tZYNQMP_RESET_GPO3_PL_27\t\t108\n#define\t\tZYNQMP_RESET_GPO3_PL_28\t\t109\n#define\t\tZYNQMP_RESET_GPO3_PL_29\t\t110\n#define\t\tZYNQMP_RESET_GPO3_PL_30\t\t111\n#define\t\tZYNQMP_RESET_GPO3_PL_31\t\t112\n#define\t\tZYNQMP_RESET_RPU_LS\t\t113\n#define\t\tZYNQMP_RESET_PS_ONLY\t\t114\n#define\t\tZYNQMP_RESET_PL\t\t\t115\n#define\t\tZYNQMP_RESET_PS_PL0\t\t116\n#define\t\tZYNQMP_RESET_PS_PL1\t\t117\n#define\t\tZYNQMP_RESET_PS_PL2\t\t118\n#define\t\tZYNQMP_RESET_PS_PL3\t\t119\n\n#endif\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/versal/versal-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-versal-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-power.h\"\n#include \"include/dt-bindings/power/xlnx-versal-regnode.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-resets.h\"\n/ {\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tcan0_clk: can0_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN0_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tcan1_clk: can1_clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_clk CAN1_REF>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tbootph-all;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tbootph-all;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t};\n\t\t\tversal_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,versal-pinctrl\";\n\t\t\t};\n\n\t\t\tversal_sec_cfg: versal-sec-cfg {\n\t\t\t\tcompatible = \"xlnx,versal-sec-cfg\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tbbram_zeroize: bbram-zeroize@4 {\n\t\t\t\t\treg = <0x04 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_key: bbram-key@10 {\n\t\t\t\t\treg = <0x10 0x20>;\n\t\t\t\t};\n\n\t\t\t\tbbram_usr: bbram-usr@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_lock: bbram-lock@48 {\n\t\t\t\t\treg = <0x48 0x4>;\n\t\t\t\t};\n\n\t\t\t\tuser_key0: user-key@110 {\n\t\t\t\t\treg = <0x110 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key1: user-key@130 {\n\t\t\t\t\treg = <0x130 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key2: user-key@150 {\n\t\t\t\t\treg = <0x150 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key3: user-key@170 {\n\t\t\t\t\treg = <0x170 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key4: user-key@190 {\n\t\t\t\t\treg = <0x190 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key5: user-key@1b0 {\n\t\t\t\t\treg = <0x1b0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key6: user-key@1d0 {\n\t\t\t\t\treg = <0x1d0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key7: user-key@1f0 {\n\t\t\t\t\treg = <0x1f0 0x20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk ACPU>;\n};\n\n&can0 {\n\tclocks = <&can0_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_0>;\n};\n\n&can1 {\n\tclocks = <&can1_clk>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_CAN_FD_1>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_0>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>;\n\tpower-domains = <&versal_firmware PM_DEV_GEM_1>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk PMC_LSBUS_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_GPIO_PMC>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk I2C0_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_0>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk I2C1_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_1>;\n};\n\n&i2c2 {\n\tclocks = <&versal_clk I2C_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_I2C_PMC>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_0>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_1>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_2>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_3>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_4>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_5>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_6>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_ADMA_7>;\n};\n\n&qspi {\n\tclocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_QSPI>;\n};\n\n&ospi {\n\tclocks = <&versal_clk OSPI_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_OSPI>;\n\treset-names = \"qspi\";\n\tresets = <&versal_reset VERSAL_RST_OSPI>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware PM_DEV_RTC>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_0>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_UART_1>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>,\n\t\t<&versal_clk SD_DLL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_0>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>,\n\t\t<&versal_clk SD_DLL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_SDIO_1>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_0>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SPI_1>;\n};\n\n&ttc0 {\n\tclocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_0>;\n};\n\n&ttc1 {\n\tclocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_1>;\n};\n\n&ttc2 {\n\tclocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_2>;\n};\n\n&ttc3 {\n\tclocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_TTC_3>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>;\n\tpower-domains = <&versal_firmware PM_DEV_USB_0>;\n\tresets = <&versal_reset VERSAL_RST_USB_0>;\n};\n\n&dwc3_0 {\n\tclocks = <&versal_clk USB0_BUS_REF>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk FPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SWDT_FPD>;\n};\n\n&watchdog1 {\n\tclocks = <&versal_clk LPD_LSBUS>;\n\tpower-domains = <&versal_firmware PM_DEV_SWDT_LPD>;\n};\n\n&sysmon0 {\n\txlnx,nodeid = ;\n};\n\n&sysmon1 {\n\txlnx,nodeid = ;\n};\n\n&sysmon2 {\n\txlnx,nodeid = ;\n};\n\n&sysmon3 {\n\txlnx,nodeid = ;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/versal/versal-spp-pm.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\talt_ref_clk: alt_ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tpl_alt_ref_clk: pl_alt_ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tref_clk: ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_firmware: versal-firmware {\n\t\t\tcompatible = \"xlnx,versal-firmware-wip\";\n\t\t\tbootph-all;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_clk: clock-controller {\n\t\t\t\tbootph-all;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"alt_ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 30 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp_ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 30 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff3f0440 {\n\t\t\treg = <0 0xff3f0440 0 0x20>,\n\t\t\t <0 0xff3f0460 0 0x20>,\n\t\t\t <0 0xff3f0280 0 0x20>,\n\t\t\t <0 0xff3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_clk 77>;\n};\n\n&can0 {\n\tclocks = <&versal_clk 96>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401f>;\n};\n\n&can1 {\n\tclocks = <&versal_clk 97>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224020>;\n};\n\n&gem0 {\n\tclocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x18224019>;\n};\n\n&gem1 {\n\tclocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>;\n\tpower-domains = <&versal_firmware 0x1822401a>;\n};\n\n&gpio0 {\n\tclocks = <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&gpio1 {\n\tclocks = <&versal_clk 61>;\n\tpower-domains = <&versal_firmware 0x18224023>;\n};\n\n&i2c0 {\n\tclocks = <&versal_clk 98>;\n\tpower-domains = <&versal_firmware 0x1822401d>;\n};\n\n&i2c1 {\n\tclocks = <&versal_clk 99>;\n\tpower-domains = <&versal_firmware 0x1822401e>;\n};\n\n&lpd_dma_chan0 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224035>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224036>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224037>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224038>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224039>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403a>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403b>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&versal_clk 81>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822403c>;\n};\n\n&qspi {\n\tclocks = <&versal_clk 57>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402b>;\n};\n\n&ospi {\n\tclocks = <&versal_clk 58>, <&versal_clk 82>;\n};\n\n&rtc {\n\tpower-domains = <&versal_firmware 0x18224034>;\n};\n\n&serial0 {\n\tclocks = <&versal_clk 92>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224021>;\n};\n\n&serial1 {\n\tclocks = <&versal_clk 93>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x18224022>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_clk 59>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402e>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_clk 60>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822402f>;\n};\n\n&spi0 {\n\tclocks = <&versal_clk 94>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401b>;\n};\n\n&spi1 {\n\tclocks = <&versal_clk 95>, <&versal_clk 82>;\n\tpower-domains = <&versal_firmware 0x1822401c>;\n};\n\n&usb0 {\n\tclocks = <&versal_clk 91>, <&versal_clk 104>;\n\tpower-domains = <&versal_firmware 0x18224018>;\n};\n\n&watchdog {\n\tclocks = <&versal_clk 82>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/versal/versal.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tmodel = \"Xilinx Versal\";\n\n\toptions {\n\t\tu-boot {\n\t\t\tcompatible = \"u-boot,config\";\n\t\t\tbootscr-address = /bits/ 64 <0x20000000>;\n\t\t};\n\t};\n\n\tcpus: cpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a72\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a72\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <1>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: opp-table-cpu {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tbootph-all;\n\t};\n\n\tfpga: fpga {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&versal_fpga>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\tpsci: psci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 7 0x304>;\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 4>,\n\t\t\t <1 14 4>,\n\t\t\t <1 11 4>,\n\t\t\t <1 10 4>;\n\t};\n\n\tversal_fpga: versal-fpga {\n\t\tcompatible = \"xlnx,versal-fpga\";\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t\tinterrupt-parent = <&gic>;\n\t\tbootph-all;\n\n\t\tgic: interrupt-controller@f9000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\t\t\treg = <0 0xf9000000 0 0x80000>, /* GICD */\n\t\t\t <0 0xf9080000 0 0x80000>; /* GICR */\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\n\t\t\tgic_its: msi-controller@f9020000 {\n\t\t\t\tcompatible = \"arm,gic-v3-its\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tmsi-controller;\n\t\t\t\t#msi-cells = <1>;\n\t\t\t\treg = <0 0xf9020000 0 0x20000>;\n\t\t\t};\n\t\t};\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff060000 0 0x6000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff070000 0 0x6000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\ttx-mailbox-count = <0x20>;\n\t\t};\n\n\t\tcci: cci@fd000000 {\n\t\t\tcompatible = \"arm,cci-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd000000 0 0x10000>;\n\t\t\tranges = <0 0 0xfd000000 0xa0000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcci_pmu: pmu@10000 {\n\t\t\t\tcompatible = \"arm,cci-500-pmu,r0\";\n\t\t\t\treg = <0x10000 0x90000>;\n\t\t\t\tinterrupts = <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>,\n\t\t\t\t\t <0 106 4>;\n\t\t\t};\n\t\t};\n\n\t\tlpd_dma_chan0: dma-controller@ffa80000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa80000 0 0x1000>;\n\t\t\tinterrupts = <0 60 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x210>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan1: dma-controller@ffa90000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffa90000 0 0x1000>;\n\t\t\tinterrupts = <0 61 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x212>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan2: dma-controller@ffaa0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaa0000 0 0x1000>;\n\t\t\tinterrupts = <0 62 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x214>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\n\t\tlpd_dma_chan3: dma-controller@ffab0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffab0000 0 0x1000>;\n\t\t\tinterrupts = <0 63 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x216>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan4: dma-controller@ffac0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffac0000 0 0x1000>;\n\t\t\tinterrupts = <0 64 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x218>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan5: dma-controller@ffad0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffad0000 0 0x1000>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x21a>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan6: dma-controller@ffae0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffae0000 0 0x1000>;\n\t\t\tinterrupts = <0 66 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x21c>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tlpd_dma_chan7: dma-controller@ffaf0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xffaf0000 0 0x1000>;\n\t\t\tinterrupts = <0 67 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t/* iommus = <&smmu 0x21e>; */\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tgem0: ethernet@ff0c0000 {\n compatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0c0000 0 0x1000>;\n\t\t\tinterrupts = <0 56 4>, <0 56 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t/* iommus = <&smmu 0x234>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0d0000 {\n compatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0d0000 0 0x1000>;\n\t\t\tinterrupts = <0 58 4>, <0 58 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t/* iommus = <&smmu 0x235>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tgpio0: gpio@ff0b0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff0b0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff020000 0 0x1000>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\tclock-frequency = <100000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff030000 0 0x1000>;\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tclock-frequency = <100000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c2: i2c@f1000000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1000000 0 0x1000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tclock-frequency = <100000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tmc0: memory-controller@f6150000\t{\n\t\t\tcompatible = \"xlnx,versal-ddrmc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;\n\t\t\treg-names = \"base\", \"noc\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t};\n\n\t\tmc1: memory-controller@f62c0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>;\n\t\t\treg-names = \"base\", \"noc\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t};\n\n\t\tmc2: memory-controller@f6430000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>;\n\t\t\treg-names = \"base\", \"noc\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t};\n\n\t\tmc3: memory-controller@f65a0000 {\n\t\t\tcompatible = \"xlnx,versal-ddrmc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>;\n\t\t\treg-names = \"base\", \"noc\";\n\t\t\tinterrupts = <0 147 4>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tinterrupts = <0 142 4>, <0 143 4>;\n\t\t\tcalibration = <0x7FFF>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\t/* iommus = <&smmu 0x242>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\t/* iommus = <&smmu 0x243>; */\n\t\t\t/* dma-coherent; */\n\t\t};\n\n\t\tserial0: serial@ff000000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff000000 0 0x1000>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tbootph-all;\n\t\t};\n\n\t\tserial1: serial@ff010000 {\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff010000 0 0x1000>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t\tbootph-all;\n\t\t};\n\n\t\tsmmu: iommu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd800000 0 0x40000>;\n\t\t\tstream-match-mask = <0x7c00>;\n\t\t\t#iommu-cells = <1>;\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupts = <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,\n\t\t\t\t <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cadence,qspi\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,trigger-address = <0xC0000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t/* iommus = <&smmu 0x244>; */\n\t\t\t/* dma-coherent; */\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff040000 0 0x1000>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff050000 0 0x1000>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsysmon0: sysmon@f1270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\treg = <0x0 0xf1270000 0x0 0x4000>;\n\t\t\tinterrupts = <0 144 4>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tsysmon1: sysmon@109270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x09270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tsysmon2: sysmon@111270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x11270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tsysmon3: sysmon@119270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x1 0x19270000 0x0 0x4000>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tttc0: timer@ff0e0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff0f0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 40 4>, <0 41 4>, <0 42 4>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff100000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 46 4>, <0 47 4>, <0 48 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tusb0: usb@ff9d0000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff9d0000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_0: usb@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0 0xfe200000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"host\", \"peripheral\", \"otg\", \"wakeup\";\n\t\t\t\tinterrupts = <0 0x16 4>, <0 0x16 4>, <0 0x1a 4>, <0x0 0x4a 0x4>;\n\t\t\t\t/* iommus = <&smmu 0x230>; */\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\tcpm_pciea: pci@fca10000 {\n\t\t\tdevice_type = \"pci\";\n\t\t\t#address-cells = <3>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"xlnx,versal-cpm-host-1.00\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc_0 0>,\n\t\t\t\t\t<0 0 0 2 &pcie_intc_0 1>,\n\t\t\t\t\t<0 0 0 3 &pcie_intc_0 2>,\n\t\t\t\t\t<0 0 0 4 &pcie_intc_0 3>;\n\t\t\tinterrupt-map-mask = <0 0 0 7>;\n\t\t\tinterrupt-names = \"misc\";\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>,\n\t\t\t\t <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>;\n\t\t\tmsi-map = <0x0 &gic_its 0x0 0x10000>;\n\t\t\treg = <0x0 0xfca10000 0x0 0x1000>,\n\t\t\t <0x6 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"cpm_slcr\", \"cfg\";\n\t\t\tpcie_intc_0: interrupt-controller {\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\tinterrupt-controller ;\n\t\t\t};\n\t\t};\n\n\t\tcpm5_pcie: pcie@fcdd0000 {\n\t\t\tdevice_type = \"pci\";\n\t\t\t#address-cells = <3>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"xlnx,versal-cpm5-host\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc_1 0>,\n\t\t\t\t\t<0 0 0 2 &pcie_intc_1 1>,\n\t\t\t\t\t<0 0 0 3 &pcie_intc_1 2>,\n\t\t\t\t\t<0 0 0 4 &pcie_intc_1 3>;\n\t\t\tinterrupt-map-mask = <0 0 0 7>;\n\t\t\tinterrupt-names = \"misc\";\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,\n\t\t\t\t <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;\n\t\t\tmsi-map = <0x0 &gic_its 0x0 0x10000>;\n\t\t\treg = <0x00 0xfcdd0000 0x00 0x1000>,\n\t\t\t <0x06 0x00000000 0x00 0x1000000>,\n\t\t\t <0x00 0xfce20000 0x00 0x1000000>;\n\t\t\treg-names = \"cpm_slcr\", \"cfg\", \"cpm_csr\";\n\t\t\tpcie_intc_1: interrupt-controller {\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\tinterrupt-controller;\n\t\t\t};\n\t\t};\n\n\t\twatchdog: watchdog@fd4d0000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xfd4d0000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\t\twatchdog1: watchdog@ff120000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xff120000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\t\txilsem_edac: edac@f2014050 {\n\t\t\tcompatible = \"xlnx,versal-xilsem-edac\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf2014050 0x0 0xc4>;\n\t\t};\n\t};\n\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/versal-net/versal-net-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal with PM\n *\n * Copyright (C) 2022, Xilinx, Inc.\n * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/clock/xlnx-versal-net-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-net-power.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tref_clk: ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tcan0_clk: can0-clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_net_clk CAN0_REF_2X>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tcan1_clk: can1-clk {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-factor-clock\";\n\t\tclocks = <&versal_net_clk CAN1_REF_2X>;\n\t\tclock-div = <2>;\n\t\tclock-mult = <1>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\", \"xlnx,versal-firmware\";\n\t\t\tbootph-all;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <1>;\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tversal_net_clk: clock-controller {\n\t\t\t\tbootph-all;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-net-clk\", \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tversal_net_power: zynqmp-power { /* untested */\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 57 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tversal_sec_cfg: versal-sec-cfg { /* untested */\n\t\t\t\tcompatible = \"xlnx,versal-sec-cfg\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tbbram_zeroize: bbram-zeroize@4 {\n\t\t\t\t\treg = <0x04 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_key: bbram-key@10 {\n\t\t\t\t\treg = <0x10 0x20>;\n\t\t\t\t};\n\n\t\t\t\tbbram_usr: bbram-usr@30 {\n\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t};\n\n\t\t\t\tbbram_lock: bbram-lock@48 {\n\t\t\t\t\treg = <0x48 0x4>;\n\t\t\t\t};\n\n\t\t\t\tuser_key0: user-key@110 {\n\t\t\t\t\treg = <0x110 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key1: user-key@130 {\n\t\t\t\t\treg = <0x130 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key2: user-key@150 {\n\t\t\t\t\treg = <0x150 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key3: user-key@170 {\n\t\t\t\t\treg = <0x170 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key4: user-key@190 {\n\t\t\t\t\treg = <0x190 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key5: user-key@1b0 {\n\t\t\t\t\treg = <0x1b0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key6: user-key@1d0 {\n\t\t\t\t\treg = <0x1d0 0x20>;\n\t\t\t\t};\n\n\t\t\t\tuser_key7: user-key@1f0 {\n\t\t\t\t\treg = <0x1f0 0x20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tzynqmp-ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 57 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@eb3f0440 {\n\t\t\treg = <0 0xeb3f0440 0 0x20>,\n\t\t\t <0 0xeb3f0460 0 0x20>,\n\t\t\t <0 0xeb3f0280 0 0x20>,\n\t\t\t <0 0xeb3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu100 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu200 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu300 {\n\tclocks = <&versal_net_clk ACPU_0>;\n};\n\n&cpu10000 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu10100 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu10200 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu10300 {\n\tclocks = <&versal_net_clk ACPU_1>;\n};\n\n&cpu20000 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu20100 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu20200 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu20300 {\n\tclocks = <&versal_net_clk ACPU_2>;\n};\n\n&cpu30000 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&cpu30100 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&cpu30200 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&cpu30300 {\n\tclocks = <&versal_net_clk ACPU_3>;\n};\n\n&can0 {\n\tclocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>;\n};\n\n&can1 {\n\tclocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>;\n};\n\n&gem0 {\n\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>,\n\t\t <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GEM_0>;\n};\n\n&gem1 {\n\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>,\n\t\t <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GEM_1>;\n};\n\n&gpio0 {\n\tclocks = <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GPIO>;\n};\n\n&gpio1 {\n\tclocks = <&versal_net_clk PMC_LSBUS_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>;\n};\n\n&i2c0 {\n\tclocks = <&versal_net_clk I3C0_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n};\n\n&i2c1 {\n\tclocks = <&versal_net_clk I3C1_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n};\n\n&i3c0 {\n\tclocks = <&versal_net_clk I3C0_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n};\n\n&i3c1 {\n\tclocks = <&versal_net_clk I3C1_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n};\n\n&adma0 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_0>;\n};\n\n&adma1 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_1>;\n};\n\n&adma2 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_2>;\n};\n\n&adma3 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_3>;\n};\n\n&adma4 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_4>;\n};\n\n&adma5 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_5>;\n};\n\n&adma6 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_6>;\n};\n\n&adma7 {\n\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_7>;\n};\n\n&qspi {\n\tclocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_QSPI>;\n};\n\n&ospi {\n\tclocks = <&versal_net_clk OSPI_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_OSPI>;\n\tresets = <&versal_net_reset VERSAL_RST_OSPI>;\n};\n\n&rtc {\n\tpower-domains = <&versal_net_firmware PM_DEV_RTC>;\n};\n\n&serial0 {\n\tclocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_UART_0>;\n};\n\n&serial1 {\n\tclocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_UART_1>;\n};\n\n&sdhci0 {\n\tclocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>,\n\t\t<&versal_net_clk SD_DLL_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_0>;\n};\n\n&sdhci1 {\n\tclocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>,\n\t\t<&versal_net_clk SD_DLL_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_1>;\n};\n\n&spi0 {\n\tclocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SPI_0>;\n};\n\n&spi1 {\n\tclocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_SPI_1>;\n};\n\n&ttc0 {\n\tclocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_0>;\n};\n\n&ttc1 {\n\tclocks = <&versal_net_clk TTC1>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_1>;\n};\n\n&ttc2 {\n\tclocks = <&versal_net_clk TTC2>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_2>;\n};\n\n&ttc3 {\n\tclocks = <&versal_net_clk TTC3>, <&versal_net_clk LPD_LSBUS>;\n\tpower-domains = <&versal_net_firmware PM_DEV_TTC_3>;\n};\n\n&usb0 {\n\tclocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_USB_0>;\n\tresets = <&versal_net_reset VERSAL_RST_USB_0>;\n};\n\n&dwc3_0 {\n\tclocks = <&versal_net_clk USB0_BUS_REF>;\n};\n\n&usb1 {\n\tclocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>;\n\tpower-domains = <&versal_net_firmware PM_DEV_USB_1>;\n\tresets = <&versal_net_reset VERSAL_RST_USB_1>;\n};\n\n&dwc3_1 {\n\tclocks = <&versal_net_clk USB1_BUS_REF>;\n};\n\n&wwdt0 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>;\n};\n\n&wwdt1 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>;\n};\n\n&wwdt2 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>;\n};\n\n&wwdt3 {\n\tclocks = <&versal_net_clk FPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>;\n};\n\n&lpd_wwdt0 {\n\tclocks = <&versal_net_clk LPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_0>;\n};\n\n&lpd_wwdt1 {\n\tclocks = <&versal_net_clk LPD_WWDT>;\n\tpower-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_1>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/versal-net/versal-net-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET fixed clock\n *\n * (C) Copyright 2022-2024, Xilinx, Inc.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tclk60: clk60 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <60000000>;\n\t};\n\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk150: clk150 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <150000000>;\n\t};\n\n\tclk160: clk160 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <160000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk450: clk450 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <450000000>;\n\t};\n\n\tclk1200: clk1200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <1200000000>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\", \"xlnx,versal-firmware\";\n\t\t\tbootph-all;\n\t\t\tmethod = \"smc\";\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&adma0 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma1 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma2 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma3 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma4 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma5 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma6 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&adma7 {\n\tclocks = <&clk450>, <&clk450>;\n};\n\n&can0 {\n\tclocks = <&clk160>, <&clk160>;\n};\n\n&can1 {\n\tclocks = <&clk160>, <&clk160>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;\n};\n\n\n&gpio0 {\n\tclocks = <&clk100>;\n};\n\n&gpio1 {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&i3c0 {\n\tclocks = <&clk100>;\n};\n\n&i3c1 {\n\tclocks = <&clk100>;\n};\n\n&ospi {\n\tclocks = <&clk200>;\n\tresets = <&versal_net_reset VERSAL_RST_OSPI>;\n};\n\n&qspi {\n\tclocks = <&clk300>, <&clk300>;\n};\n\n&rtc {\n\t/* Nothing */\n};\n\n&sdhci0 {\n\tclocks = <&clk200>, <&clk200>, <&clk1200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200>, <&clk200>, <&clk1200>;\n};\n\n&serial0 {\n\tclocks = <&clk100>, <&clk100>;\n\tclock = <1000000>;\n};\n\n&serial1 {\n\tclocks = <&clk100>, <&clk100>;\n\tclock = <100000000>;\n};\n\n&spi0 {\n\tclocks = <&clk200>, <&clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200>, <&clk200>;\n};\n\n&ttc0 {\n\tclocks = <&clk150>;\n};\n\n&usb0 {\n\tclocks = <&clk60>, <&clk60>;\n};\n\n&dwc3_0 {\n\t/* Nothing */\n};\n\n&usb1 {\n\tclocks = <&clk60>, <&clk60>;\n};\n\n&dwc3_1 {\n\t/* Nothing */\n};\n\n&wwdt0 {\n\tclocks = <&clk150>;\n};\n\n&wwdt1 {\n\tclocks = <&clk150>;\n};\n\n&wwdt2 {\n\tclocks = <&clk150>;\n};\n\n&wwdt3 {\n\tclocks = <&clk150>;\n};\n\n&lpd_wwdt0 {\n\tclocks = <&clk150>;\n};\n\n&lpd_wwdt1 {\n\tclocks = <&clk150>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/versal-net/versal-net-ipp-rev1.9.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * (C) Copyright 2021-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/clock/xlnx-versal-net-clk.h\"\n#include \"include/dt-bindings/power/xlnx-versal-net-power.h\"\n#include \"include/dt-bindings/reset/xlnx-versal-net-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,versal-net-ipp-1.9\", \"xlnx,versal-net-spp-5.0\", \"xlnx,versal-net-spp\", \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal NET SPP 5.0/IPP 1.9\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t};\n\t};\n\n\tmemory: memory@0 {\n\t\treg = <0 0 0 0x80000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tserial2 = &dcc;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tbootph-all;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1\";\n\t\tstdout-path = \"serial0:115200\";\n\t};\n\n\tref_clk: ref_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\tbootph-all;\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tfirmware {\n\t\tversal_net_firmware: versal-net-firmware {\n\t\t\tcompatible = \"xlnx,versal-net-firmware\", \"xlnx,versal-firmware\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tbootph-all;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x01>;\n\n\t\t\tversal_net_clk: clock-controller {\n\t\t\t\tbootph-all;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,versal-net-clk\", \"xlnx,versal-clk\";\n\t\t\t\tclocks = <&ref_clk>, <&ref_clk>;\n\t\t\t\tclock-names = \"ref_clk\", \"pl_alt_ref_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupts = <0 57 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>,\n\t\t\t\t\t<&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tversal_net_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,versal-net-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tzynqmp-ipi {\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupts = <0 57 4>;\n\t\txlnx,ipi-id = <2>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@eb3f0440 {\n\t\t\treg = <0 0xeb3f0440 0 0x20>,\n\t\t\t <0 0xeb3f0460 0 0x20>,\n\t\t\t <0 0xeb3f0280 0 0x20>,\n\t\t\t <0 0xeb3f02a0 0 0x20>;\n\t\t\treg-names = \"local_request_region\", \"local_response_region\",\n\t\t\t\t \"remote_request_region\", \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <1>;\n\t\t};\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tbootph-all;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tadma0: dma-controller@ebd00000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd00000 0 0x1000>;\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_0>;\n\t\t};\n\n\t\tadma1: dma-controller@ebd10000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd10000 0 0x1000>;\n\t\t\tinterrupts = <0 73 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_1>;\n\t\t};\n\n\t\tadma2: dma-controller@ebd20000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd20000 0 0x1000>;\n\t\t\tinterrupts = <0 74 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_2>;\n\t\t};\n\n\t\tadma3: dma-controller@ebd30000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd30000 0 0x1000>;\n\t\t\tinterrupts = <0 75 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_3>;\n\t\t};\n\n\t\tadma4: dma-controller@ebd40000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd40000 0 0x1000>;\n\t\t\tinterrupts = <0 76 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_4>;\n\t\t};\n\n\t\tadma5: dma-controller@ebd50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd50000 0 0x1000>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_5>;\n\t\t};\n\n\t\tadma6: dma-controller@ebd60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd60000 0 0x1000>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_6>;\n\t\t};\n\n\t\tadma7: dma-controller@ebd70000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0 0xebd70000 0 0x1000>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t\tclocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_ADMA_7>;\n\t\t};\n\n\t\tcan0: can@f1980000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1980000 0 0x6000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>;\n\t\t};\n\n\t\tcan1: can@f1990000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\treg = <0 0xf1990000 0 0x6000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t\tclocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>;\n\t\t};\n\n\t\tgem0: ethernet@f19e0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19e0000 0 0x1000>;\n\t\t\tinterrupts = <0 39 4>, <0 39 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>,\n\t\t\t\t <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_0>;\n\t\t\tmdio0: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\t\t#phy-cells = <1>;\n\t\t\t\t\tcompatible = \"ethernet-phy-id2000.a231\";\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t\tti,rx-internal-delay = <11>;\n\t\t\t\t\tti,tx-internal-delay = <10>;\n\t\t\t\t\tti,fifo-depth = <1>;\n\t\t\t\t\tti,dp83867-rxctrl-strap-quirk;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgem1: ethernet@f19f0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,versal-gem\", \"cdns,gem\";\n\t\t\treg = <0 0xf19f0000 0 0x1000>;\n\t\t\tinterrupts = <0 41 4>, <0 41 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-handle = <&phy2>;\n\t\t\tphy-mode = \"rmii\";\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>,\n\t\t\t\t <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>,\n\t\t\t\t <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GEM_1>;\n\t\t\tmdio1: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\t\tcompatible = \"ethernet-phy-id0007.0762\"; /* Vitesse VSC8540 */\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tmax-speed = <100>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t};\n\n\t\tgpio0: gpio@f19d0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\treg = <0 0xf19d0000 0 0x1000>;\n\t\t\tinterrupts = <0 13 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO>;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\tclocks = <&versal_net_clk PMC_LSBUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>;\n\t\t};\n\n\t\ti2c0: i2c@f1940000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1940000 0 0x1000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C0_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@f1950000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1950000 0 0x1000>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk I3C1_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_1>;\n\t\t};\n\n\t\ti3c: i3c-master@f1948000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\treg = <0 0xf1948000 0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclocks = <&versal_net_clk I2C_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_I2C_PMC>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 182 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>;\n\t\t\tcdns,trigger-address = <0xc0000000>;\n\t\t\tclocks = <&versal_net_clk OSPI_REF>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_OSPI>;\n\t\t\treset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>;\n\n\t\t\tmt35xu02g: flash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tcdns,read-delay = <0>;\n\t\t\t\tcdns,tshsl-ns = <0>;\n\t\t\t\tcdns,tsd2d-ns = <0>;\n\t\t\t\tcdns,tchsh-ns = <1>;\n\t\t\t\tcdns,tslch-ns = <1>;\n\t\t\t\tspi-tx-bus-width = <8>;\n\t\t\t\tspi-rx-bus-width = <8>;\n\t\t\t\tspi-max-frequency = <20000000>;\n\t\t\t\tbroken-flash-reset;\n\t\t\t\tno-wp;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"ospi-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"ospi-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\treg = <0 0xf1030000 0 0x1000>;\n\t\t\tinterrupts = <0 183 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tnum-cs = <2>;\n\t\t\tspi-rx-bus-width = <4>;\n\t\t\tspi-tx-bus-width = <4>;\n\t\t\tclocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_QSPI>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"micron,m25p80\", \"jedec,spi-nor\";\n\t\t\t\treg = <0>, <1>;\n\t\t\t\tparallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tspi-tx-bus-width = <1>;\n\t\t\t\tspi-rx-bus-width = <4>;\n\t\t\t\tspi-max-frequency = <10000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"qspi0-flash0\";\n\t\t\t\t\t\treg = <0 0x200000>;\n\t\t\t\t\t};\n\t\t\t\t\tpartition@1 {\n\t\t\t\t\t\tlabel = \"qspi0-flash1\";\n\t\t\t\t\t\treg = <0x200000 0x7E00000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupts = <0 200 4>, <0 201 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 184 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_1>;\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 186 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tno-1-8-v;\n\t\t\tclocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SDIO_0>;\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_UART_0>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tserial1: serial@f1930000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\treg = <0 0xf1930000 0 0x1000>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tclocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_UART_1>;\n\t\t\tclock = <1000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t\tskip-init;\n\t\t};\n\n\t\tsmmu: smmu@ec000000 {\n\t\t\tcompatible = \"arm,smmu-v3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xec000000 0 0x40000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tinterrupt-names = \"combined\";\n\t\t\tinterrupts = <0 169 4>;\n\t\t};\n\n\t\tspi0: spi@f1960000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupts = <0 23 4>;\n\t\t\treg = <0 0xf1960000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_0>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi0-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tspi1: spi@f1970000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0 0xf1970000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tclocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_SPI_1>;\n\t\t\tnum-cs = <1>;\n\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"m25p80\";\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"spi1-flash0\";\n\t\t\t\t\t\treg = <0 0x80000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tttc0: timer@f1dc0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dc0000 0x0 0x1000>;\n\t\t\tclocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_TTC_0>;\n\t\t};\n\n\t\tusb0: usb@f1e00000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0 0xf1e00000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\t/* clocks = <&clk60>, <&clk60>; */\n\t\t\tclocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_0>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_0>;\n\n\t\t\tdwc3_0: usb@f1b00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0 0xf1b00000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 29 4>, <0 33 4>, <0 98 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"peripheral\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@f1e10000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\treg = <0x0 0xf1e10000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tclocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_USB_1>;\n\t\t\tresets = <&versal_net_reset VERSAL_RST_USB_1>;\n\n\t\t\tdwc3_1: usb@f1c00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\treg = <0x0 0xf1c00000 0x0 0x10000>;\n\t\t\t\tinterrupt-names = \"dwc_usb3\",\"otg\",\"usb-wakeup\";\n\t\t\t\tinterrupts = <0 34 4>, <0 38 4>, <0 99 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tphy-names = \"usb3-phy\";\n\t\t\t};\n\t\t};\n\n\t\twwdt0: watchdog@ecc10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecc10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>;\n\t\t};\n\n\t\twwdt1: watchdog@ecd10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecd10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>;\n\t\t};\n\n\t\twwdt2: watchdog@ece10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xece10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>;\n\t\t};\n\n\t\twwdt3: watchdog@ecf10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\treg = <0 0xecf10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t\tclocks = <&versal_net_clk FPD_WWDT>;\n\t\t\tpower-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/versal-net/versal-net.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * dts file for Xilinx Versal NET\n *\n * Copyright (C) 2022, Xilinx, Inc.\n * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.\n *\n * Michal Simek \n */\n\n/ {\n\tcompatible = \"xlnx,versal-net\";\n\tmodel = \"Xilinx Versal NET\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&gic>;\n\n\toptions {\n\t\tu-boot {\n\t\t\tcompatible = \"u-boot,config\";\n\t\t\tbootscr-address = /bits/ 64 <0x20000000>;\n\t\t};\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcpu-map {\n\t\t\tcluster0 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu0>;\n\t\t\t\t};\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu100>;\n\t\t\t\t};\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu200>;\n\t\t\t\t};\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcluster1 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu10000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu10100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu10200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu10300>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tcluster2 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu20000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu20100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu20200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu20300>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tcluster3 {\n\t\t\t\tcore0 {\n\t\t\t\t\tcpu = <&cpu30000>;\n\t\t\t\t};\n\n\t\t\t\tcore1 {\n\t\t\t\t\tcpu = <&cpu30100>;\n\t\t\t\t};\n\n\t\t\t\tcore2 {\n\t\t\t\t\tcpu = <&cpu30200>;\n\t\t\t\t};\n\n\t\t\t\tcore3 {\n\t\t\t\t\tcpu = <&cpu30300>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t};\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu100: cpu@100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x100>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu200: cpu@200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x200>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu300: cpu@300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x300>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu10000: cpu@10000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10000>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu10100: cpu@10100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10100>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu10200: cpu@10200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10200>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu10300: cpu@10300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x10300>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu20000: cpu@20000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20000>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu20100: cpu@20100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20100>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu20200: cpu@20200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20200>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu20300: cpu@20300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x20300>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu30000: cpu@30000 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30000>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu30100: cpu@30100 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30100>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu30200: cpu@30200 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30200>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tcpu30300: cpu@30300 {\n\t\t\tcompatible = \"arm,cortex-a78\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x30300>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-1066000000 {\n\t\t\topp-hz = /bits/ 64 <1066000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-1866000000 {\n\t\t\topp-hz = /bits/ 64 <1866000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-1900000000 {\n\t\t\topp-hz = /bits/ 64 <1900000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-1999000000 {\n\t\t\topp-hz = /bits/ 64 <1999000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2050000000 {\n\t\t\topp-hz = /bits/ 64 <2050000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2100000000 {\n\t\t\topp-hz = /bits/ 64 <2100000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2200000000 {\n\t\t\topp-hz = /bits/ 64 <2200000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp-2400000000 {\n\t\t\topp-hz = /bits/ 64 <2400000000>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n };\n };\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tserial2 = &dcc;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\trtc = &rtc;\n\t\tusb0 = &usb0;\n\t\tusb1 = &usb1;\n\t\tspi0 = &ospi;\n\t\tspi1 = &qspi;\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tbootph-all;\n\t};\n\n\tfirmware {\n\t\tpsci {\n\t\t\tcompatible = \"arm,psci-1.0\";\n\t\t\tmethod = \"smc\";\n\t\t};\n\t};\n\n\tfpga: fpga {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&versal_fpga>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t};\n\n\ttimer: timer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */\n\t};\n\n\tversal_fpga: versal-fpga {\n\t\tcompatible = \"xlnx,versal-fpga\";\n\t};\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tbootph-all;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tadma0: dma-controller@ebd00000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd00000 0 0x1000>;\n\t\t\tinterrupts = <0 72 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma1: dma-controller@ebd10000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd10000 0 0x1000>;\n\t\t\tinterrupts = <0 73 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma2: dma-controller@ebd20000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd20000 0 0x1000>;\n\t\t\tinterrupts = <0 74 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma3: dma-controller@ebd30000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd30000 0 0x1000>;\n\t\t\tinterrupts = <0 75 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma4: dma-controller@ebd40000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd40000 0 0x1000>;\n\t\t\tinterrupts = <0 76 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma5: dma-controller@ebd50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd50000 0 0x1000>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma6: dma-controller@ebd60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd60000 0 0x1000>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tadma7: dma-controller@ebd70000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xebd70000 0 0x1000>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tcan0: can@f1980000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1980000 0 0x6000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t};\n\n\t\tcan1: can@f1990000 {\n\t\t\tcompatible = \"xlnx,canfd-2.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1990000 0 0x6000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tclock-names = \"can_clk\", \"s_axi_aclk\";\n\t\t\trx-fifo-depth = <64>;\n\t\t\ttx-mailbox-count = <32>;\n\t\t};\n\n\t\tgem0: ethernet@f19e0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf19e0000 0 0x1000>;\n\t\t\tinterrupts = <0 39 4>, <0 39 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\",\n\t\t\t \"tsu_clk\";\n\t\t};\n\n\t\tgem1: ethernet@f19f0000 {\n\t\t\tcompatible = \"xlnx,versal-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf19f0000 0 0x1000>;\n\t\t\tinterrupts = <0 41 4>, <0 41 4>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\",\n\t\t\t\t \"tsu_clk\";\n\t\t};\n\n\t\tgic: interrupt-controller@e2000000 {\n\t\t\tcompatible = \"arm,gic-v3\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0 0xe2000000 0 0x10000>,\n\t\t\t <0 0xe2060000 0 0x200000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupts = <1 9 4>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\t\t\tits: msi-controller@e2040000 {\n\t\t\t\tcompatible = \"arm,gic-v3-its\";\n\t\t\t\tmsi-controller;\n\t\t\t\t#msi-cells = <1>;\n\t\t\t\treg = <0 0xe2040000 0 0x20000>;\n\t\t\t};\n\t\t};\n\n\t\tgpio0: gpio@f19d0000 {\n\t\t\tcompatible = \"xlnx,versal-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf19d0000 0 0x1000>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio1: gpio@f1020000 {\n\t\t\tcompatible = \"xlnx,pmc-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1020000 0 0x1000>;\n\t\t\tinterrupts = <0 180 4>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\ti2c0: i2c@f1940000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1940000 0 0x1000>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@f1950000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1950000 0 0x1000>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti3c0: i3c-master@f1948000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1948000 0 0x1000>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t};\n\n\t\ti3c1: i3c-master@f1958000 {\n\t\t\tcompatible = \"snps,dw-i3c-master-1.00a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1958000 0 0x1000>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t};\n\n\t\tospi: spi@f1010000 {\n\t\t\tcompatible = \"xlnx,versal-ospi-1.0\", \"cdns,qspi-nor\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1010000 0 0x10000>,\n\t\t\t <0 0xc0000000 0 0x20000000>;\n\t\t\tinterrupts = <0 182 4>;\n\t\t\tcdns,fifo-depth = <256>;\n\t\t\tcdns,fifo-width = <4>;\n\t\t\tcdns,is-dma = <1>; /* u-boot specific */\n\t\t\t/* cdns,is-stig-pgm = <1>; - unused - checking with Sai */\n\t\t\tcdns,trigger-address = <0xc0000000>;\n\t\t};\n\n\t\tqspi: spi@f1030000 {\n\t\t\tcompatible = \"xlnx,versal-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1030000 0 0x1000>; /* missing one more reg range - checking with Sai */\n\t\t\tinterrupts = <0 183 4>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t};\n\n\t\trtc: rtc@f12a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf12a0000 0 0x100>;\n\t\t\tinterrupts = <0 200 4>, <0 201 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsdhci0: mmc@f1040000 {\n\t\t\tcompatible = \"xlnx,versal-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1040000 0 0x10000>;\n\t\t\tinterrupts = <0 184 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t};\n\n\t\tsdhci1: mmc@f1050000 {\n\t\t\tcompatible = \"xlnx,versal-net-emmc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1050000 0 0x10000>;\n\t\t\tinterrupts = <0 186 4>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\", \"gate\";\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t};\n\n\t\tserial0: serial@f1920000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1920000 0 0x1000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tserial1: serial@f1930000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1930000 0 0x1000>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\treg-io-width = <4>;\n\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tsmmu: iommu@ec000000 {\n\t\t\tcompatible = \"arm,smmu-v3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xec000000 0 0x40000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tinterrupt-names = \"combined\";\n\t\t\tinterrupts = <0 169 4>;\n\t\t\tdma-coherent;\n\t\t};\n\n\t\tspi0: spi@f1960000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 23 4>;\n\t\t\treg = <0 0xf1960000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t};\n\n\t\tspi1: spi@f1970000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0 0xf1970000 0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t};\n\n\t\tsysmon0: sysmon@f1270000 {\n\t\t\tcompatible = \"xlnx,versal-sysmon\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf1270000 0x0 0x4000>;\n\t\t\tinterrupts = <0 202 4>;\n\t\t\txlnx,numchannels = /bits/8 <0>;\n\t\t};\n\n\t\tttc0: timer@f1dc0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 43 4>, <0 44 4>, <0 45 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dc0000 0x0 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f1dd0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 46 4>, <0 47 4>, <0 48 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1dd0000 0x0 0x1000>;\n\t\t};\n\n\t\tttc2: timer@f1de0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 49 4>, <0 50 4>, <0 51 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1de0000 0x0 0x1000>;\n\t\t};\n\n\t\tttc3: timer@f1df0000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 52 4>, <0 53 4>, <0 54 4>;\n\t\t\ttimer-width = <32>;\n\t\t\treg = <0x0 0xf1df0000 0x0 0x1000>;\n\t\t};\n\n\t\tusb0: usb@f1e00000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xf1e00000 0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_0: usb@f1b00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0 0xf1b00000 0 0x10000>;\n\t\t\t\tinterrupt-names = \"host\", \"peripheral\", \"otg\", \"wakeup\";\n\t\t\t\tinterrupts = <0 29 4>, <0 29 4>, <0 33 4>, <0 98 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"peripheral\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\t/*phy-names = \"usb3-phy\";- checking with Pyiush */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@f1e10000 {\n\t\t\tcompatible = \"xlnx,versal-dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xf1e10000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tranges;\n\t\t\tinterrupt-names = \"usb-wakeup\";\n\t\t\tinterrupts = <0 99 4>;\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdwc3_1: usb@f1c00000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xf1c00000 0x0 0x10000>;\n\t\t\t\tinterrupt-names = \"host\", \"peripheral\", \"otg\", \"wakeup\";\n\t\t\t\tinterrupts = <0 34 4>, <0 34 4>, <0 38 4>, <0 99 4>;\n\t\t\t\tsnps,dis_u2_susphy_quirk;\n\t\t\t\tsnps,dis_u3_susphy_quirk;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tdr_mode = \"host\";\n\t\t\t\tmaximum-speed = \"high-speed\";\n\t\t\t\tsnps,usb3_lpm_capable;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\t/* phy-names = \"usb3-phy\"; - checking with Pyiush */\n\t\t\t};\n\t\t};\n\n\t\twwdt0: watchdog@ecc10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xecc10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\twwdt1: watchdog@ecd10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xecd10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\twwdt2: watchdog@ece10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xece10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\twwdt3: watchdog@ecf10000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xecf10000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\tlpd_wwdt0: watchdog@ea420000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xea420000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\tlpd_wwdt1: watchdog@ea430000 {\n\t\t\tcompatible = \"xlnx,versal-wwdt\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0 0xea430000 0 0x10000>;\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/zynq/skeleton.dtsi", "content": "/*\n * Skeleton device tree; the bare minimum needed to boot; just include and\n * add a compatible value. The bootloader will typically populate the memory\n * node.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tchosen { };\n\taliases { };\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/zynq/zynq-7000.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n */\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"xlnx,zynq-7000\";\n\n\toptions {\n\t\tu-boot {\n\t\t\tcompatible = \"u-boot,config\";\n\t\t\tbootscr-address = /bits/ 64 <0x3000000>;\n\t\t};\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t\tclocks = <&clkc 3>;\n\t\t\tclock-latency = <1000>;\n\t\t\tcpu0-supply = <®ulator_vccpint>;\n\t\t\toperating-points = <\n\t\t\t\t/* kHz uV */\n\t\t\t\t666667 1000000\n\t\t\t\t333334 1000000\n\t\t\t>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a9\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t\tclocks = <&clkc 3>;\n\t\t};\n\t};\n\n\tfpga_full: fpga-region {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&devcfg>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t};\n\n\tpmu@f8891000 {\n\t\tcompatible = \"arm,cortex-a9-pmu\";\n\t\tinterrupts = <0 5 4>, <0 6 4>;\n\t\tinterrupt-parent = <&intc>;\n\t\treg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;\n\t};\n\n\tregulator_vccpint: fixedregulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"VCCPINT\";\n\t\tregulator-min-microvolt = <1000000>;\n\t\tregulator-max-microvolt = <1000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\treplicator {\n\t\tcompatible = \"arm,coresight-static-replicator\";\n\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\tout-ports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\t/* replicator output ports */\n\t\t\tport@0 {\n\t\t\t\treg = <0>;\n\t\t\t\treplicator_out_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&tpiu_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tport@1 {\n\t\t\t\treg = <1>;\n\t\t\t\treplicator_out_port1: endpoint {\n\t\t\t\t\tremote-endpoint = <&etb_in_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tin-ports {\n\t\t\t/* replicator input port */\n\t\t\tport {\n\t\t\t\treplicator_in_port0: endpoint {\n\t\t\t\t\tremote-endpoint = <&funnel_out_port>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tamba: axi {\n\t\tbootph-all;\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tinterrupt-parent = <&intc>;\n\t\tranges;\n\n\t\tadc: adc@f8007100 {\n\t\t\tcompatible = \"xlnx,zynq-xadc-1.00.a\";\n\t\t\treg = <0xf8007100 0x20>;\n\t\t\tinterrupts = <0 7 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 12>;\n\t\t};\n\n\t\tcan0: can@e0008000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 19>, <&clkc 36>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0008000 0x1000>;\n\t\t\tinterrupts = <0 28 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@e0009000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 20>, <&clkc 37>;\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0xe0009000 0x1000>;\n\t\t\tinterrupts = <0 51 4>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tgpio0: gpio@e000a000 {\n\t\t\tcompatible = \"xlnx,zynq-gpio-1.0\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tclocks = <&clkc 42>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0xe000a000 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@e0004000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 38>;\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\treg = <0xe0004000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@e0005000 {\n\t\t\tcompatible = \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 39>;\n\t\t\tclock-frequency = <400000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0xe0005000 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tintc: interrupt-controller@f8f01000 {\n\t\t\tcompatible = \"arm,cortex-a9-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0xF8F01000 0x1000>,\n\t\t\t <0xF8F00100 0x100>;\n\t\t};\n\n\t\tL2: cache-controller@f8f02000 {\n\t\t\tcompatible = \"arm,pl310-cache\";\n\t\t\treg = <0xF8F02000 0x1000>;\n\t\t\tinterrupts = <0 2 4>;\n\t\t\tarm,data-latency = <3 2 2>;\n\t\t\tarm,tag-latency = <2 2 2>;\n\t\t\tcache-unified;\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tmc: memory-controller@f8006000 {\n\t\t\tcompatible = \"xlnx,zynq-ddrc-a05\";\n\t\t\treg = <0xf8006000 0x1000>;\n\t\t};\n\n\t\tocm: sram@fffc0000 {\n\t\t\tcompatible = \"mmio-sram\";\n\t\t\treg = <0xfffc0000 0x10000>;\n\t\t};\n\n\t\tuart0: serial@e0000000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 23>, <&clkc 40>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0000000 0x1000>;\n\t\t\tinterrupts = <0 27 4>;\n\t\t};\n\n\t\tuart1: serial@e0001000 {\n\t\t\tcompatible = \"xlnx,xuartps\", \"cdns,uart-r1p8\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 24>, <&clkc 41>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\treg = <0xE0001000 0x1000>;\n\t\t\tinterrupts = <0 50 4>;\n\t\t};\n\n\t\tspi0: spi@e0006000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0006000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 26 4>;\n\t\t\tclocks = <&clkc 25>, <&clkc 34>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@e0007000 {\n\t\t\tcompatible = \"xlnx,zynq-spi-r1p6\";\n\t\t\treg = <0xe0007000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\tclocks = <&clkc 26>, <&clkc 35>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tqspi: spi@e000d000 {\n\t\t\tcompatible = \"xlnx,zynq-qspi-1.0\";\n\t\t\treg = <0xe000d000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\tclocks = <&clkc 10>, <&clkc 43>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem0: ethernet@e000b000 {\n compatible = \"xlnx,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000b000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 22 4>;\n\t\t\tclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@e000c000 {\n compatible = \"xlnx,zynq-gem\", \"cdns,gem\";\n\t\t\treg = <0xe000c000 0x1000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupts = <0 45 4>;\n\t\t\tclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tsmcc: memory-controller@e000e000 {\n\t\t\tcompatible = \"arm,pl353-smc-r2p1\", \"arm,primecell\";\n\t\t\treg = <0xe000e000 0x0001000>;\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"memclk\", \"apb_pclk\";\n\t\t\tclocks = <&clkc 11>, <&clkc 44>;\n\t\t\tranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */\n\t\t\t\t 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */\n\t\t\t\t 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tnfc0: nand-controller@0,0 {\n\t\t\t\tcompatible = \"arm,pl353-nand-r2p1\";\n\t\t\t\treg = <0 0 0x1000000>;\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\t#address-cells = <0x1>;\n\t\t\t\t#size-cells = <0x0>;\n\t\t\t};\n\t\t\tnor0: flash@1,0 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\treg = <1 0 0x2000000>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tsdhci0: mmc@e0100000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 21>, <&clkc 32>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\treg = <0xe0100000 0x1000>;\n\t\t};\n\n\t\tsdhci1: mmc@e0101000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tclocks = <&clkc 22>, <&clkc 33>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 47 4>;\n\t\t\treg = <0xe0101000 0x1000>;\n\t\t};\n\n\t\tslcr: slcr@f8000000 {\n\t\t\tbootph-all;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"xlnx,zynq-slcr\", \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xF8000000 0x1000>;\n\t\t\tranges;\n\t\t\tclkc: clkc@100 {\n\t\t\t\tbootph-all;\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tcompatible = \"xlnx,ps7-clkc\";\n\t\t\t\tfclk-enable = <0xf>;\n\t\t\t\tclock-output-names = \"armpll\", \"ddrpll\", \"iopll\", \"cpu_6or4x\",\n\t\t\t\t\t\t\"cpu_3or2x\", \"cpu_2x\", \"cpu_1x\", \"ddr2x\", \"ddr3x\",\n\t\t\t\t\t\t\"dci\", \"lqspi\", \"smc\", \"pcap\", \"gem0\", \"gem1\",\n\t\t\t\t\t\t\"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\", \"can0\", \"can1\",\n\t\t\t\t\t\t\"sdio0\", \"sdio1\", \"uart0\", \"uart1\", \"spi0\", \"spi1\",\n\t\t\t\t\t\t\"dma\", \"usb0_aper\", \"usb1_aper\", \"gem0_aper\",\n\t\t\t\t\t\t\"gem1_aper\", \"sdio0_aper\", \"sdio1_aper\",\n\t\t\t\t\t\t\"spi0_aper\", \"spi1_aper\", \"can0_aper\", \"can1_aper\",\n\t\t\t\t\t\t\"i2c0_aper\", \"i2c1_aper\", \"uart0_aper\", \"uart1_aper\",\n\t\t\t\t\t\t\"gpio_aper\", \"lqspi_aper\", \"smc_aper\", \"swdt\",\n\t\t\t\t\t\t\"dbg_trc\", \"dbg_apb\";\n\t\t\t\treg = <0x100 0x100>;\n\t\t\t};\n\n\t\t\trstc: rstc@200 {\n\t\t\t\tcompatible = \"xlnx,zynq-reset\";\n\t\t\t\treg = <0x200 0x48>;\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl@700 {\n\t\t\t\tcompatible = \"xlnx,pinctrl-zynq\";\n\t\t\t\treg = <0x700 0x200>;\n\t\t\t\tsyscon = <&slcr>;\n\t\t\t};\n\t\t};\n\n dmac_s: dma-controller@f8003000 {\n\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n\t\t\treg = <0xf8003000 0x1000>;\n\t\t\tinterrupt-parent = <&intc>;\n /*\n\t\t\t * interrupt-names = \"abort\", \"dma0\", \"dma1\", \"dma2\", \"dma3\",\n\t\t\t * \"dma4\", \"dma5\", \"dma6\", \"dma7\";\n\t\t\t */\n\t\t\tinterrupts = <0 13 4>,\n\t\t\t <0 14 4>, <0 15 4>,\n\t\t\t <0 16 4>, <0 17 4>,\n\t\t\t <0 40 4>, <0 41 4>,\n\t\t\t <0 42 4>, <0 43 4>;\n\t\t\t#dma-cells = <1>;\n\t\t\tclocks = <&clkc 27>;\n\t\t\tclock-names = \"apb_pclk\";\n\t\t};\n\n\t\tdevcfg: devcfg@f8007000 {\n\t\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n\t\t\treg = <0xf8007000 0x100>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 8 4>;\n\t\t\tclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;\n\t\t\tclock-names = \"ref_clk\", \"fclk0\", \"fclk1\", \"fclk2\", \"fclk3\";\n\t\t\tsyscon = <&slcr>;\n\t\t};\n\n\t\tefuse: efuse@f800d000 {\n\t\t\tcompatible = \"xlnx,zynq-efuse\";\n\t\t\treg = <0xf800d000 0x20>;\n\t\t};\n\n\t\tglobal_timer: timer@f8f00200 {\n\t\t\tcompatible = \"arm,cortex-a9-global-timer\";\n\t\t\treg = <0xf8f00200 0x20>;\n\t\t\tinterrupts = <1 11 0x301>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tttc0: timer@f8001000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8001000 0x1000>;\n\t\t};\n\n\t\tttc1: timer@f8002000 {\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tclocks = <&clkc 6>;\n\t\t\treg = <0xF8002000 0x1000>;\n\t\t};\n\n\t\tscutimer: timer@f8f00600 {\n\t\t\tbootph-all;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1 13 0x301>;\n\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n\t\t\treg = <0xf8f00600 0x20>;\n\t\t\tclocks = <&clkc 4>;\n\t\t};\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 28>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0xe0002000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\tusb1: usb@e0003000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclocks = <&clkc 29>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 44 4>;\n\t\t\treg = <0xe0003000 0x1000>;\n\t\t\tphy_type = \"ulpi\";\n\t\t};\n\n\t\twatchdog0: watchdog@f8005000 {\n\t\t\tclocks = <&clkc 45>;\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <0 9 1>;\n\t\t\treg = <0xf8005000 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\tetb@f8801000 {\n\t\t\tcompatible = \"arm,coresight-etb10\", \"arm,primecell\";\n\t\t\treg = <0xf8801000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\tetb_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ttpiu@f8803000 {\n\t\t\tcompatible = \"arm,coresight-tpiu\", \"arm,primecell\";\n\t\t\treg = <0xf8803000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tin-ports {\n\t\t\t\tport {\n\t\t\t\t\ttpiu_in_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&replicator_out_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tfunnel@f8804000 {\n\t\t\tcompatible = \"arm,coresight-static-funnel\", \"arm,primecell\";\n\t\t\treg = <0xf8804000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\n\t\t\t/* funnel output ports */\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tfunnel_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint =\n\t\t\t\t\t\t\t<&replicator_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tin-ports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\t/* funnel input ports */\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tfunnel0_in_port0: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm0_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tfunnel0_in_port1: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&ptm1_out_port>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tfunnel0_in_port2: endpoint {\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\t/* The other input ports are not connect to anything */\n\t\t\t};\n\t\t};\n\n\t\tptm@f889c000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889c000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu0>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm0_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port0>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tptm@f889d000 {\n\t\t\tcompatible = \"arm,coresight-etm3x\", \"arm,primecell\";\n\t\t\treg = <0xf889d000 0x1000>;\n\t\t\tclocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;\n\t\t\tclock-names = \"apb_pclk\", \"dbg_trc\", \"dbg_apb\";\n\t\t\tcpu = <&cpu1>;\n\t\t\tout-ports {\n\t\t\t\tport {\n\t\t\t\t\tptm1_out_port: endpoint {\n\t\t\t\t\t\tremote-endpoint = <&funnel0_in_port1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/zynqmp/zynqmp-clk-ccf.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n#include \"include/dt-bindings/clock/xlnx-zynqmp-clk.h\"\n\n/ {\n\tpss_ref_clk: pss_ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <33333333>;\n\t};\n\n\tvideo_clk: video_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n\n\tpss_alt_ref_clk: pss_alt_ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <0>;\n\t};\n\n\tgt_crx_ref_clk: gt_crx_ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <108000000>;\n\t};\n\n\taux_ref_clk: aux_ref_clk {\n\t\tbootph-all;\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <27000000>;\n\t};\n};\n\n&zynqmp_firmware {\n\tzynqmp_clk: clock-controller {\n\t\tbootph-all;\n\t\t#clock-cells = <1>;\n\t\tcompatible = \"xlnx,zynqmp-clk\";\n\t\tclocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,\n\t\t\t <&aux_ref_clk>, <>_crx_ref_clk>;\n\t\tclock-names = \"pss_ref_clk\", \"video_clk\", \"pss_alt_ref_clk\",\n\t\t\t \"aux_ref_clk\", \"gt_crx_ref_clk\";\n\t};\n};\n\n&can0 {\n\tclocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&can1 {\n\tclocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&cpu0 {\n\tclocks = <&zynqmp_clk ACPU>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gpu {\n\tclocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&nand0 {\n\tclocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&gem0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>,\n\t\t <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>;\n\tassigned-clocks = <&zynqmp_clk GEM_TSU>;\n};\n\n&gem1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>,\n\t\t <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>;\n\tassigned-clocks = <&zynqmp_clk GEM_TSU>;\n};\n\n&gem2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>,\n\t\t <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>;\n\tassigned-clocks = <&zynqmp_clk GEM_TSU>;\n};\n\n&gem3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>,\n\t\t <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>;\n\tassigned-clocks = <&zynqmp_clk GEM_TSU>;\n};\n\n&gpio {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&i2c0 {\n\tclocks = <&zynqmp_clk I2C0_REF>;\n};\n\n&i2c1 {\n\tclocks = <&zynqmp_clk I2C1_REF>;\n};\n\n&perf_monitor_ocm {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&perf_monitor_ddr {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_cci {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>;\n};\n\n&perf_monitor_lpd {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&pcie {\n\tclocks = <&zynqmp_clk PCIE_REF>;\n};\n\n&qspi {\n\tclocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&sata {\n\tclocks = <&zynqmp_clk SATA_REF>;\n};\n\n&sdhci0 {\n\tclocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;\n\tassigned-clocks = <&zynqmp_clk SDIO0_REF>;\n};\n\n&sdhci1 {\n\tclocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;\n\tassigned-clocks = <&zynqmp_clk SDIO1_REF>;\n};\n\n&spi0 {\n\tclocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&spi1 {\n\tclocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc0 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc1 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc2 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&ttc3 {\n\tclocks = <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart0 {\n\tclocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&uart1 {\n\tclocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;\n};\n\n&usb0 {\n\tclocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n\tassigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&dwc3_0 {\n\tclocks = <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&usb1 {\n\tclocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n\tassigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&dwc3_1 {\n\tclocks = <&zynqmp_clk USB3_DUAL_REF>;\n};\n\n&watchdog0 {\n\tclocks = <&zynqmp_clk WDT>;\n};\n\n&lpd_watchdog {\n\tclocks = <&zynqmp_clk LPD_WDT>;\n};\n\n&xilinx_ams {\n\tclocks = <&zynqmp_clk AMS_REF>;\n};\n\n&zynqmp_dpdma {\n\tclocks = <&zynqmp_clk DPDMA_REF>;\n\tassigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */\n};\n\n&zynqmp_dpsub {\n\tclocks = <&zynqmp_clk TOPSW_LSBUS>,\n\t\t<&zynqmp_clk DP_AUDIO_REF>,\n\t\t<&zynqmp_clk DP_VIDEO_REF>;\n\tassigned-clocks = <&zynqmp_clk DP_STC_REF>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */\n};\n\n&zynqmp_dp_snd_codec0 {\n\tclocks = <&zynqmp_clk DP_AUDIO_REF>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/2024.2/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n#include \"include/dt-bindings/dma/xlnx-zynqmp-dpdma.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n#include \"include/dt-bindings/power/xlnx-zynqmp-power.h\"\n#include \"include/dt-bindings/reset/xlnx-zynqmp-resets.h\"\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\toptions {\n\t\tu-boot {\n\t\t\tcompatible = \"u-boot,config\";\n\t\t\tbootscr-address = /bits/ 64 <0x20000000>;\n\t\t};\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t\tnext-level-cache = <&L2>;\n\t\t};\n\n\t\tL2: l2-cache {\n\t\t\tcompatible = \"cache\";\n\t\t\tcache-level = <2>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: opp-table-cpu {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tzynqmp_ipi: zynqmp-ipi {\n\t\tbootph-all;\n\t\tcompatible = \"xlnx,zynqmp-ipi-mailbox\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 35 4>;\n\t\txlnx,ipi-id = <0>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tipi_mailbox_pmu1: mailbox@ff9905c0 {\n\t\t\tbootph-all;\n\t\t\treg = <0x0 0xff9905c0 0x0 0x20>,\n\t\t\t <0x0 0xff9905e0 0x0 0x20>,\n\t\t\t <0x0 0xff990e80 0x0 0x20>,\n\t\t\t <0x0 0xff990ea0 0x0 0x20>;\n\t\t\treg-names = \"local_request_region\",\n\t\t\t\t \"local_response_region\",\n\t\t\t\t \"remote_request_region\",\n\t\t\t\t \"remote_response_region\";\n\t\t\t#mbox-cells = <1>;\n\t\t\txlnx,ipi-id = <4>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t\tbootph-all;\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t\tinterrupt-affinity = <&cpu0>,\n\t\t\t\t <&cpu1>,\n\t\t\t\t <&cpu2>,\n\t\t\t\t <&cpu3>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\tfirmware {\n\t\tzynqmp_firmware: zynqmp-firmware {\n\t\t\tcompatible = \"xlnx,zynqmp-firmware\";\n\t\t\tbootph-all;\n\t\t\tmethod = \"smc\";\n\t\t\t#power-domain-cells = <0x1>;\n\n\t\t\tzynqmp_power: zynqmp-power {\n\t\t\t\tbootph-all;\n\t\t\t\tcompatible = \"xlnx,zynqmp-power\";\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 35 4>;\n\t\t\t\tmboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;\n\t\t\t\tmbox-names = \"tx\", \"rx\";\n\t\t\t};\n\n\t\t\tsoc-nvmem {\n\t\t\t\tcompatible = \"xlnx,zynqmp-nvmem-fw\";\n\t\t\t\tnvmem-layout {\n\t\t\t\t\tcompatible = \"fixed-layout\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tsoc_revision: soc-revision@0 {\n\t\t\t\t\t\treg = <0x0 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\t/* efuse access */\n\t\t\t\t\tefuse_dna: efuse-dna@c {\n\t\t\t\t\t\treg = <0xc 0xc>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr0: efuse-usr0@20 {\n\t\t\t\t\t\treg = <0x20 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr1: efuse-usr1@24 {\n\t\t\t\t\t\treg = <0x24 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr2: efuse-usr2@28 {\n\t\t\t\t\t\treg = <0x28 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr3: efuse-usr3@2c {\n\t\t\t\t\t\treg = <0x2c 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr4: efuse-usr4@30 {\n\t\t\t\t\t\treg = <0x30 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr5: efuse-usr5@34 {\n\t\t\t\t\t\treg = <0x34 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr6: efuse-usr6@38 {\n\t\t\t\t\t\treg = <0x38 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_usr7: efuse-usr7@3c {\n\t\t\t\t\t\treg = <0x3c 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_miscusr: efuse-miscusr@40 {\n\t\t\t\t\t\treg = <0x40 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_chash: efuse-chash@50 {\n\t\t\t\t\t\treg = <0x50 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_pufmisc: efuse-pufmisc@54 {\n\t\t\t\t\t\treg = <0x54 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_sec: efuse-sec@58 {\n\t\t\t\t\t\treg = <0x58 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_spkid: efuse-spkid@5c {\n\t\t\t\t\t\treg = <0x5c 0x4>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_aeskey: efuse-aeskey@60 {\n\t\t\t\t\t\treg = <0x60 0x20>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_ppk0hash: efuse-ppk0hash@a0 {\n\t\t\t\t\t\treg = <0xa0 0x30>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_ppk1hash: efuse-ppk1hash@d0 {\n\t\t\t\t\t\treg = <0xd0 0x30>;\n\t\t\t\t\t};\n\t\t\t\t\tefuse_pufuser: efuse-pufuser@100 {\n\t\t\t\t\t\treg = <0x100 0x7F>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tzynqmp_pcap: pcap {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pcap-fpga\";\n\t\t\t};\n\n\t\t\tzynqmp_reset: reset-controller {\n\t\t\t\tcompatible = \"xlnx,zynqmp-reset\";\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpinctrl0: pinctrl {\n\t\t\t\tcompatible = \"xlnx,zynqmp-pinctrl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\tmodepin_gpio: gpio {\n\t\t\t\tcompatible = \"xlnx,zynqmp-gpio-modepin\";\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\t\t};\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\n\tfpga_full: fpga-region {\n\t\tcompatible = \"fpga-region\";\n\t\tfpga-mgr = <&zynqmp_pcap>;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t};\n\n\n\n\tamba: axi {\n\t\tcompatible = \"simple-bus\";\n\t\tbootph-all;\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_CAN0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_0>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_CAN1>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_CAN_1>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma-controller@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14e8>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma-controller@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14e9>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma-controller@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ea>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma-controller@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14eb>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma-controller@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ec>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma-controller@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ed>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma-controller@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ee>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma-controller@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <128>;\n\t\t\tiommus = <&smmu 0x14ef>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GDMA>;\n\t\t};\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x0 0x10000>,\n\t\t\t <0x0 0xf9020000 0x0 0x20000>,\n\t\t\t <0x0 0xf9040000 0x0 0x20000>,\n\t\t\t <0x0 0xf9060000 0x0 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\n\t\tgpu: gpu@fd4b0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-mali\", \"arm,mali-400\";\n\t\t\treg = <0x0 0xfd4b0000 0x0 0x10000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;\n\t\t\tinterrupt-names = \"gp\", \"gpmmu\", \"pp0\", \"ppmmu0\", \"pp1\", \"ppmmu1\";\n\t\t\tclock-names = \"bus\", \"core\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPU>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma-controller@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x868>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma-controller@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x869>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma-controller@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86a>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma-controller@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86b>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma-controller@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86c>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma-controller@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86d>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma-controller@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86e>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma-controller@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\t#dma-cells = <1>;\n\t\t\txlnx,bus-width = <64>;\n\t\t/*\tiommus = <&smmu 0x86f>; */\n\t\t\tpower-domains = <&zynqmp_firmware PD_ADMA>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tnand0: nand-controller@ff100000 {\n\t\t\tcompatible = \"xlnx,zynqmp-nand-controller\", \"arasan,nfc-v3p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xff100000 0x0 0x1000>;\n\t\t\tclock-names = \"controller\", \"bus\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 14 4>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x872>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_NAND>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x874>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_0>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;\n\t\t\treset-names = \"gem0_rst\";\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x875>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_1>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;\n\t\t\treset-names = \"gem1_rst\";\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x876>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_2>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;\n\t\t\treset-names = \"gem2_rst\";\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n compatible = \"xlnx,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"rx_clk\", \"tsu_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x877>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_ETH_3>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;\n\t\t\treset-names = \"gem3_rst\";\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_GPIO>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\tclock-frequency = <400000>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_I2C_1>;\n\t\t};\n\n\t\tocm: memory-controller@ff960000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ocmc-1.0\";\n\t\t\treg = <0x0 0xff960000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 10 4>;\n\t\t};\n\n\t\tperf_monitor_ocm: perf-monitor@ffa00000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa00000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_ddr: perf-monitor@fd0b0000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd0b0000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <6>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <10>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_cci: perf-monitor@fd490000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xfd490000 0x0 0x10000>;\n\t\t\tinterrupts = <0 123 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <0>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tperf_monitor_lpd: perf-monitor@ffa10000 {\n\t\t\tcompatible = \"xlnx,axi-perf-monitor\";\n\t\t\treg = <0x0 0xffa10000 0x0 0x10000>;\n\t\t\tinterrupts = <0 25 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\txlnx,enable-profile = <0>;\n\t\t\txlnx,enable-trace = <0>;\n\t\t\txlnx,num-monitor-slots = <1>;\n\t\t\txlnx,enable-event-count = <1>;\n\t\t\txlnx,enable-event-log = <1>;\n\t\t\txlnx,have-sampled-metric-cnt = <1>;\n\t\t\txlnx,num-of-counters = <8>;\n\t\t\txlnx,metric-count-width = <32>;\n\t\t\txlnx,metrics-sample-count-width = <32>;\n\t\t\txlnx,global-count-width = <32>;\n\t\t\txlnx,metric-count-scale = <1>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x10000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tiommus = <&smmu 0x4d0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_PCIE>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tqspi: spi@ff0f0000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"xlnx,zynqmp-qspi-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\tinterrupts = <0 15 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tnum-cs = <1>;\n\t\t\treg = <0x0 0xff0f0000 0x0 0x1000>,\n\t\t\t <0x0 0xc0000000 0x0 0x8000000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tiommus = <&smmu 0x873>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_QSPI>;\n\t\t};\n\n\t\tpsgtr: phy@fd400000 {\n\t\t\tcompatible = \"xlnx,zynqmp-psgtr-v1.1\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd400000 0x0 0x40000>,\n\t\t\t <0x0 0xfd3d0000 0x0 0x1000>;\n\t\t\treg-names = \"serdes\", \"siou\";\n\t\t\t#phy-cells = <4>;\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x7FFF>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SATA>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SATA>;\n\t\t/*\tiommus = <&smmu 0x4c0>, <&smmu 0x4c1>,\n\t\t\t\t <&smmu 0x4c2>, <&smmu 0x4c3>;*/\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tiommus = <&smmu 0x870>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_0>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd0\", \"clk_in_sd0\";\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"xlnx,zynqmp-8.9a\", \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t\tiommus = <&smmu 0x871>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SD_1>;\n\t\t\t#clock-cells = <1>;\n\t\t\tclock-output-names = \"clk_out_sd1\", \"clk_in_sd1\";\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\t#iommu-cells = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_SPI_1>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_0>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_1>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_2>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t\tpower-domains = <&zynqmp_firmware PD_TTC_3>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"xlnx,zynqmp-uart\", \"cdns,uart-r1p12\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_0>;\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"xlnx,zynqmp-uart\", \"cdns,uart-r1p12\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_UART_1>;\n\t\t};\n\n\t\tusb0: usb@ff9d0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9d0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_0>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\t\t\treset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tranges;\n\n\t\t\tdwc3_0: usb@fe200000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"host\", \"peripheral\", \"otg\", \"wakeup\";\n\t\t\t\tinterrupts = <0 65 4>, <0 65 4>, <0 69 4>, <0 75 4>;\n\t\t\t\tiommus = <&smmu 0x860>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\tsnps,resume-hs-terminations;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@ff9e0000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dwc3\";\n\t\t\treg = <0x0 0xff9e0000 0x0 0x100>;\n\t\t\tclock-names = \"bus_clk\", \"ref_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_USB_1>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,\n\t\t\t\t <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;\n\t\t\treset-names = \"usb_crst\", \"usb_hibrst\", \"usb_apbrst\";\n\n\t\t\tranges;\n\n\t\t\tdwc3_1: usb@fe300000 {\n\t\t\t\tcompatible = \"snps,dwc3\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupt-names = \"host\", \"peripheral\", \"otg\", \"wakeup\";\n\t\t\t\tinterrupts = <0 70 4>, <0 70 4>, <0 74 4>, <0 76 4>;\n\t\t\t\tiommus = <&smmu 0x861>;\n\t\t\t\tsnps,quirk-frame-length-adjustment = <0x20>;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\tsnps,resume-hs-terminations;\n\t\t\t\t/* dma-coherent; */\n\t\t\t};\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <60>;\n\t\t\treset-on-timeout;\n\t\t};\n\n\t\tlpd_watchdog: watchdog@ff150000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 52 1>;\n\t\t\treg = <0x0 0xff150000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\n\t\txilinx_ams: ams@ffa50000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ams\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 56 4>;\n\t\t\treg = <0x0 0xffa50000 0x0 0x800>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\t#io-channel-cells = <1>;\n\t\t\tranges = <0 0 0xffa50800 0x800>;\n\n\t\t\tams_ps: ams-ps@0 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-ps\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x0 0x400>;\n\t\t\t};\n\n\t\t\tams_pl: ams-pl@400 {\n\t\t\t\tcompatible = \"xlnx,zynqmp-ams-pl\";\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\treg = <0x400 0x400>;\n\t\t\t};\n\t\t};\n\n\t\tzynqmp_dpdma: dma-controller@fd4c0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpdma\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4c0000 0x0 0x1000>;\n\t\t\tinterrupts = <0 122 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tclock-names = \"axi_clk\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tdma-channels = <6>;\n\t\t\tiommus = <&smmu 0xce4>;\n\t\t\t#dma-cells = <1>;\n\t\t};\n\n\t\tzynqmp_dpaud_setting: dp-aud@fd4ac000 {\n\t\t\tcompatible = \"xlnx,zynqmp-dpaud-setting\", \"syscon\";\n\t\t\treg = <0x0 0xfd4ac000 0x0 0x1000>;\n\t\t};\n\n\t\tzynqmp_dpsub: display@fd4a0000 {\n\t\t\tbootph-all;\n\t\t\tcompatible = \"xlnx,zynqmp-dpsub-1.7\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd4a0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4aa000 0x0 0x1000>,\n\t\t\t <0x0 0xfd4ab000 0x0 0x1000>;\n\t\t\treg-names = \"dp\", \"blend\", \"av_buf\";\n\t\t\txlnx,dpaud-reg = <&zynqmp_dpaud_setting>;\n\t\t\tinterrupts = <0 119 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tiommus = <&smmu 0xce3>;\n\t\t\tclock-names = \"dp_apb_clk\", \"dp_aud_clk\", \"dp_vtc_pixel_clk_in\";\n\t\t\tpower-domains = <&zynqmp_firmware PD_DP>;\n\t\t\tresets = <&zynqmp_reset ZYNQMP_RESET_DP>;\n\t\t\tdma-names = \"vid0\", \"vid1\", \"vid2\", \"gfx0\";\n\t\t\tdmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,\n\t\t\t\t<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;\n\n\t\t\t/* dummy node to to indicate there's no child i2c device */\n\t\t\ti2c-bus {\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_codec0: zynqmp-dp-snd-codec0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-codec\";\n\t\t\t\tclock-names = \"aud_clk\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm0: zynqmp-dp-snd-pcm0 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm0\";\n\t\t\t\tdmas = <&zynqmp_dpdma 4>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_pcm1: zynqmp-dp-snd-pcm1 {\n\t\t\t\tcompatible = \"xlnx,dp-snd-pcm1\";\n\t\t\t\tdmas = <&zynqmp_dpdma 5>;\n\t\t\t\tdma-names = \"tx\";\n\t\t\t};\n\n\t\t\tzynqmp_dp_snd_card0: zynqmp-dp-snd-card {\n\t\t\t\tcompatible = \"xlnx,dp-snd-card\";\n\t\t\t\txlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,\n\t\t\t\t\t\t <&zynqmp_dp_snd_pcm1>;\n\t\t\t\txlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;\n\t\t\t};\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zc1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revA\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t};\n};\n\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tstatus = \"okay\";\n\tbus-width = <8>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\tethernet0 = &gem2;\n\t\ti2c0 = &i2c0;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t};\n};\n\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi0_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi1_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc3.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm017-dc3\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm017-dc3 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 { /* VSC8211 */\n\t\treg = <0>;\n\t};\n};\n\n/* just eeprom here */\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n/* eeprom24c02 and SE98A temp chip pca9306 */\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc4.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm018-dc4\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm018-dc4\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tethernet2 = &gem2;\n\t\tethernet3 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy0>;\n\tethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */\n\t\treg = <0>;\n\t};\n\tethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */\n\t\treg = <7>;\n\t};\n\tethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */\n\t\treg = <3>;\n\t};\n\tethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */\n\t\treg = <8>;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy7>;\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy3>;\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy8>;\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc5.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm019-dc5\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Siva Durga Prasad \n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm019-dc5 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zcep108.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ep108 development board\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tmodel = \"ZynqMP EP108\";\n\n\taliases {\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\tserial0 = &uart0;\n\t};\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t\tmax-speed = <100>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom@54 {\n\t\tcompatible = \"atmel,24c64\";\n\t\treg = <0x54>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\teeprom@55 {\n\t\tcompatible = \"atmel,24c64\";\n\t\treg = <0x55>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\tceva,broken-gen2;\n\t/* SATA Phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;\n\tceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;\n\tceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;\n\tceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;\n\tceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;\n\tceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tbus-width = <8>;\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\tspi0_flash0: spi0_flash0@0 {\n\t\tcompatible = \"m25p80\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tspi0_flash0@0 {\n\t\t\tlabel = \"spi0_flash0\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\tspi1_flash0: spi1_flash0@0 {\n\t\tcompatible = \"m25p80\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tspi1_flash0@0 {\n\t\t\tlabel = \"spi1_flash0\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tdr_mode = \"peripheral\";\n\tmaximum-speed = \"high-speed\";\n};\n\n&usb1 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tmaximum-speed = \"high-speed\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\ti2c0 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart1;\n\t\tserial1 = &uart0;\n\t\tserial2 = &dcc;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 1>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 0>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 0>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 0>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tbt_power {\n\t\t\tlabel = \"bt_power\";\n\t\t\tgpios = <&gpio 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 1>; /* WIFI_EN */\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t\t \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 1>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"HS-SPI1\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n phy-handle = <&phyc>;\n phyc: phy@c {\n reg = <0xc>;\n ti,rx-internal-delay = <0x8>;\n ti,tx-internal-delay = <0xa>;\n ti,fifo-depth = <0x1>;\n };\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\t\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/board/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps54012@44 { /* IRPS5401 - u55 */\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps54012@45 { /* IRPS5401 - u57 */\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 { /* SI5328 - u48 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/zynqmp/zynqmp-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm_clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&watchdog0 {\n\tclocks = <&clk250>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.17/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"arm,psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tamba_apu: amba_apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t};\n\n\t\tsdhci0: sdhci@ff160000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsdhci1: sdhci@ff170000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tusb0: usb@fe200000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tusb1: usb@fe300000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 70 4>;\n\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/board/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/board/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/board/zc1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revA\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t};\n\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tstatus = \"okay\";\n\tbus-width = <8>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\tethernet0 = &gem2;\n\t\ti2c0 = &i2c0;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t};\n\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi0_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi1_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc3.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm017-dc3\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm017-dc3 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 { /* VSC8211 */\n\t\treg = <0>;\n\t};\n};\n\n/* just eeprom here */\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n/* eeprom24c02 and SE98A temp chip pca9306 */\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc4.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm018-dc4\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm018-dc4\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tethernet2 = &gem2;\n\t\tethernet3 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy0>;\n\tethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */\n\t\treg = <0>;\n\t};\n\tethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */\n\t\treg = <7>;\n\t};\n\tethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */\n\t\treg = <3>;\n\t};\n\tethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */\n\t\treg = <8>;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy7>;\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy3>;\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy8>;\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc5.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm019-dc5\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Siva Durga Prasad \n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm019-dc5 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/board/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\ti2c0 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart1;\n\t\tserial1 = &uart0;\n\t\tserial2 = &dcc;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t\t \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"HS-SPI1\";\n};\n\n&uart0 {\n\tstatus = \"okay\";\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/board/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n phy-handle = <&phyc>;\n phyc: phy@c {\n reg = <0xc>;\n ti,rx-internal-delay = <0x8>;\n ti,tx-internal-delay = <0xa>;\n ti,fifo-depth = <0x1>;\n };\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/board/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr-sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr-sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr-sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr-sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/board/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\t\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/board/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/board/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/board/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps54012@44 { /* IRPS5401 - u55 */\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps54012@45 { /* IRPS5401 - u57 */\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 { /* SI5328 - u48 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/zynqmp/zynqmp-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm_clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&watchdog0 {\n\tclocks = <&clk250>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.18/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"arm,psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tamba_apu: amba_apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t};\n\n\t\tsdhci0: sdhci@ff160000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsdhci1: sdhci@ff170000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tusb0: usb@fe200000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tusb1: usb@fe300000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 70 4>;\n\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n\tbroken-cd; /* CD has to be enabled by default */\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n status = \"okay\";\n label = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n status = \"okay\";\n label = \"HS-SPI1\";\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/zc1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revA\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t};\n\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tstatus = \"okay\";\n\tbus-width = <8>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\tethernet0 = &gem2;\n\t\ti2c0 = &i2c0;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t};\n\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi0_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi1_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc3.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm017-dc3\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm017-dc3 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 { /* VSC8211 */\n\t\treg = <0>;\n\t};\n};\n\n/* just eeprom here */\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n/* eeprom24c02 and SE98A temp chip pca9306 */\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc4.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm018-dc4\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm018-dc4\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tethernet2 = &gem2;\n\t\tethernet3 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy0>;\n\tethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */\n\t\treg = <0>;\n\t};\n\tethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */\n\t\treg = <7>;\n\t};\n\tethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */\n\t\treg = <3>;\n\t};\n\tethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */\n\t\treg = <8>;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy7>;\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy3>;\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy8>;\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc5.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm019-dc5\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Siva Durga Prasad \n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm019-dc5 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\ti2c0 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart1;\n\t\tserial1 = &uart0;\n\t\tserial2 = &dcc;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t\t \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"HS-SPI1\";\n};\n\n&uart0 {\n\tstatus = \"okay\";\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n phy-handle = <&phyc>;\n phyc: phy@c {\n reg = <0xc>;\n ti,rx-internal-delay = <0x8>;\n ti,tx-internal-delay = <0xa>;\n ti,fifo-depth = <0x1>;\n };\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr-sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr-sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr-sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr-sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\t\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/board/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps54012@44 { /* IRPS5401 - u55 */\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps54012@45 { /* IRPS5401 - u57 */\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 { /* SI5328 - u48 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/zynqmp/zynqmp-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma-clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm-clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&watchdog0 {\n\tclocks = <&clk250>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.19/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu-opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tamba_apu: amba-apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t};\n\n\t\tsdhci0: sdhci@ff160000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsdhci1: sdhci@ff170000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tusb0: usb@fe200000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tusb1: usb@fe300000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 70 4>;\n\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n\tbroken-cd; /* CD has to be enabled by default */\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n status = \"okay\";\n label = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n status = \"okay\";\n label = \"HS-SPI1\";\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/zc1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revA\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t};\n\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tstatus = \"okay\";\n\tbus-width = <8>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\tethernet0 = &gem2;\n\t\ti2c0 = &i2c0;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t};\n\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi0_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi1_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc3.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm017-dc3\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm017-dc3 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 { /* VSC8211 */\n\t\treg = <0>;\n\t};\n};\n\n/* just eeprom here */\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n/* eeprom24c02 and SE98A temp chip pca9306 */\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc4.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm018-dc4\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm018-dc4\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tethernet2 = &gem2;\n\t\tethernet3 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy0>;\n\tethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */\n\t\treg = <0>;\n\t};\n\tethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */\n\t\treg = <7>;\n\t};\n\tethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */\n\t\treg = <3>;\n\t};\n\tethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */\n\t\treg = <8>;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy7>;\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy3>;\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy8>;\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc5.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm019-dc5\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Siva Durga Prasad \n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm019-dc5 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\ti2c0 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart1;\n\t\tserial1 = &uart0;\n\t\tserial2 = &dcc;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t\t \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"HS-SPI1\";\n};\n\n&uart0 {\n\tstatus = \"okay\";\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n phy-handle = <&phyc>;\n phyc: phy@c {\n reg = <0xc>;\n ti,rx-internal-delay = <0x8>;\n ti,tx-internal-delay = <0xa>;\n ti,fifo-depth = <0x1>;\n };\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr-sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr-sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr-sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr-sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\t\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/board/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps54012@44 { /* IRPS5401 - u55 */\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps54012@45 { /* IRPS5401 - u57 */\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 { /* SI5328 - u48 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/zynqmp/zynqmp-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm_clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&watchdog0 {\n\tclocks = <&clk250>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v4.20/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu_opp_table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tamba_apu: amba_apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t};\n\n\t\tsdhci0: sdhci@ff160000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsdhci1: sdhci@ff170000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tusb0: usb@fe200000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tusb1: usb@fe300000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 70 4>;\n\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n\tbroken-cd; /* CD has to be enabled by default */\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n status = \"okay\";\n label = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n status = \"okay\";\n label = \"HS-SPI1\";\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/zc1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revA\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t};\n\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tstatus = \"okay\";\n\tbus-width = <8>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\tethernet0 = &gem2;\n\t\ti2c0 = &i2c0;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t};\n\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi0_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi1_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc3.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm017-dc3\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm017-dc3 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 { /* VSC8211 */\n\t\treg = <0>;\n\t};\n};\n\n/* just eeprom here */\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n/* eeprom24c02 and SE98A temp chip pca9306 */\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc4.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm018-dc4\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm018-dc4\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tethernet2 = &gem2;\n\t\tethernet3 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy0>;\n\tethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */\n\t\treg = <0>;\n\t};\n\tethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */\n\t\treg = <7>;\n\t};\n\tethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */\n\t\treg = <3>;\n\t};\n\tethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */\n\t\treg = <8>;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy7>;\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy3>;\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy8>;\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc5.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm019-dc5\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Siva Durga Prasad \n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm019-dc5 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \n#include \n#include \n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\ti2c0 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart1;\n\t\tserial1 = &uart0;\n\t\tserial2 = &dcc;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t\t \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"HS-SPI1\";\n};\n\n&uart0 {\n\tstatus = \"okay\";\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n phy-handle = <&phyc>;\n phyc: phy@c {\n reg = <0xc>;\n ti,rx-internal-delay = <0x8>;\n ti,tx-internal-delay = <0xa>;\n ti,fifo-depth = <0x1>;\n };\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\t\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/board/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps54012@44 { /* IRPS5401 - u55 */\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps54012@45 { /* IRPS5401 - u57 */\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 { /* SI5328 - u48 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/zynqmp/zynqmp-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma-clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm-clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&watchdog0 {\n\tclocks = <&clk250>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.0/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu-opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tamba_apu: amba-apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tusb0: usb@fe200000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tusb1: usb@fe300000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 70 4>;\n\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n\tbroken-cd; /* CD has to be enabled by default */\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n status = \"okay\";\n label = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n status = \"okay\";\n label = \"HS-SPI1\";\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/zc1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revA\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t};\n\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tstatus = \"okay\";\n\tbus-width = <8>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\tethernet0 = &gem2;\n\t\ti2c0 = &i2c0;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t};\n\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi0_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi1_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc3.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm017-dc3\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm017-dc3 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 { /* VSC8211 */\n\t\treg = <0>;\n\t};\n};\n\n/* just eeprom here */\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n/* eeprom24c02 and SE98A temp chip pca9306 */\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc4.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm018-dc4\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm018-dc4\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tethernet2 = &gem2;\n\t\tethernet3 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy0>;\n\tethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */\n\t\treg = <0>;\n\t};\n\tethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */\n\t\treg = <7>;\n\t};\n\tethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */\n\t\treg = <3>;\n\t};\n\tethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */\n\t\treg = <8>;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy7>;\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy3>;\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy8>;\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc5.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm019-dc5\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Siva Durga Prasad \n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm019-dc5 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\ti2c0 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart1;\n\t\tserial1 = &uart0;\n\t\tserial2 = &dcc;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t\t \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"HS-SPI1\";\n};\n\n&uart0 {\n\tstatus = \"okay\";\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n phy-handle = <&phyc>;\n phyc: phy@c {\n reg = <0xc>;\n ti,rx-internal-delay = <0x8>;\n ti,tx-internal-delay = <0xa>;\n ti,fifo-depth = <0x1>;\n };\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr-sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr-sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr-sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr-sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\t\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/board/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps54012@44 { /* IRPS5401 - u55 */\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps54012@45 { /* IRPS5401 - u57 */\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 { /* SI5328 - u48 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/zynqmp/zynqmp-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma-clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm-clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&watchdog0 {\n\tclocks = <&clk250>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.1/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu-opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tamba_apu: amba-apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tusb0: usb@fe200000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tusb1: usb@fe300000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 70 4>;\n\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n\tbroken-cd; /* CD has to be enabled by default */\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n status = \"okay\";\n label = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n status = \"okay\";\n label = \"HS-SPI1\";\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/zc1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revA\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t};\n\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tstatus = \"okay\";\n\tbus-width = <8>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\tethernet0 = &gem2;\n\t\ti2c0 = &i2c0;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t};\n\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi0_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi1_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc3.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm017-dc3\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm017-dc3 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 { /* VSC8211 */\n\t\treg = <0>;\n\t};\n};\n\n/* just eeprom here */\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n/* eeprom24c02 and SE98A temp chip pca9306 */\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc4.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm018-dc4\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm018-dc4\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tethernet2 = &gem2;\n\t\tethernet3 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy0>;\n\tethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */\n\t\treg = <0>;\n\t};\n\tethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */\n\t\treg = <7>;\n\t};\n\tethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */\n\t\treg = <3>;\n\t};\n\tethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */\n\t\treg = <8>;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy7>;\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy3>;\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy8>;\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc5.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm019-dc5\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Siva Durga Prasad \n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm019-dc5 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\ti2c0 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart1;\n\t\tserial1 = &uart0;\n\t\tserial2 = &dcc;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t\t \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"HS-SPI1\";\n};\n\n&uart0 {\n\tstatus = \"okay\";\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n phy-handle = <&phyc>;\n phyc: phy@c {\n reg = <0xc>;\n ti,rx-internal-delay = <0x8>;\n ti,tx-internal-delay = <0xa>;\n ti,fifo-depth = <0x1>;\n };\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\t\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/board/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps54012@44 { /* IRPS5401 - u55 */\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps54012@45 { /* IRPS5401 - u57 */\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 { /* SI5328 - u48 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/zynqmp/zynqmp-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma-clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm-clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&watchdog0 {\n\tclocks = <&clk250>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.2/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu-opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tamba_apu: amba-apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tusb0: usb@fe200000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tusb1: usb@fe300000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 70 4>;\n\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n\tbroken-cd; /* CD has to be enabled by default */\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n status = \"okay\";\n label = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n status = \"okay\";\n label = \"HS-SPI1\";\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/zc1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revA\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t};\n\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tstatus = \"okay\";\n\tbus-width = <8>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\tethernet0 = &gem2;\n\t\ti2c0 = &i2c0;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t};\n\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi0_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi1_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc3.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm017-dc3\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm017-dc3 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 { /* VSC8211 */\n\t\treg = <0>;\n\t};\n};\n\n/* just eeprom here */\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n/* eeprom24c02 and SE98A temp chip pca9306 */\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc4.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm018-dc4\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm018-dc4\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tethernet2 = &gem2;\n\t\tethernet3 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy0>;\n\tethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */\n\t\treg = <0>;\n\t};\n\tethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */\n\t\treg = <7>;\n\t};\n\tethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */\n\t\treg = <3>;\n\t};\n\tethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */\n\t\treg = <8>;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy7>;\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy3>;\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy8>;\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc5.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm019-dc5\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Siva Durga Prasad \n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm019-dc5 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \n#include \n#include \n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\ti2c0 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart1;\n\t\tserial1 = &uart0;\n\t\tserial2 = &dcc;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t\t \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"HS-SPI1\";\n};\n\n&uart0 {\n\tstatus = \"okay\";\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n phy-handle = <&phyc>;\n phyc: phy@c {\n reg = <0xc>;\n ti,rx-internal-delay = <0x8>;\n ti,tx-internal-delay = <0xa>;\n ti,fifo-depth = <0x1>;\n };\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\t\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/board/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps54012@44 { /* IRPS5401 - u55 */\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps54012@45 { /* IRPS5401 - u57 */\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 { /* SI5328 - u48 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/zynqmp/zynqmp-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma-clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm-clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&watchdog0 {\n\tclocks = <&clk250>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.3/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu-opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tamba_apu: amba-apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tusb0: usb@fe200000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tusb1: usb@fe300000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 70 4>;\n\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/avnet-ultra96-rev1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Avnet Ultra96 rev1\n *\n * (C) Copyright 2018-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"Avnet Ultra96 Rev1\";\n\tcompatible = \"avnet,ultra96-rev1\", \"avnet,ultra96\",\n\t\t \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\",\n\t\t \"xlnx,zynqmp\";\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ; /* down */\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus_det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio_pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t};\n};\n\n&gpio {\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C0\n\t\t\t */\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/*\n\t\t\t * LSEXP_I2C1\n\t\t\t */\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C2\n\t\t\t */\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/*\n\t\t\t * HSEXP_I2C3\n\t\t\t */\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tno-1-8-v;\n\tdisable-wp;\n\tbroken-cd; /* CD has to be enabled by default */\n};\n\n&sdhci1 {\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n status = \"okay\";\n label = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n status = \"okay\";\n label = \"HS-SPI1\";\n};\n\n&uart0 {\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/zc1232-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1232 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1232-revA\", \"xlnx,zynqmp-zc1232\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/zc1254-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1254 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1254-revA\", \"xlnx,zynqmp-zc1254\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/zc1275-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Siva Durga Prasad Paladugu \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZC1275 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1275-revA\", \"xlnx,zynqmp-zc1275\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc1.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm015-dc1 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t};\n\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\teeprom: eeprom@55 {\n\t\tcompatible = \"atmel,24c64\"; /* 24AA64 */\n\t\treg = <0x55>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* eMMC */\n&sdhci0 {\n\tstatus = \"okay\";\n\tbus-width = <8>;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc2.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tcan0 = &can0;\n\t\tcan1 = &can1;\n\t\tethernet0 = &gem2;\n\t\ti2c0 = &i2c0;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t};\n\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@5 {\n\t\treg = <5>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi0_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"sst,sst25wf080\", \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tspi1_flash0: flash0@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"atmel,at45db041e\", \"atmel,at45\", \"atmel,dataflash\";\n\t\tspi-max-frequency = <20000000>;\n\t\treg = <0>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x0 0x84000>;\n\t\t};\n\t};\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc3.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm017-dc3\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm017-dc3 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 { /* VSC8211 */\n\t\treg = <0>;\n\t};\n};\n\n/* just eeprom here */\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u26: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/* IRQ not connected */\n\t};\n\n\trtc@68 {\n\t\tcompatible = \"dallas,ds1339\";\n\t\treg = <0x68>;\n\t};\n};\n\n/* eeprom24c02 and SE98A temp chip pca9306 */\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA phy OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n\n/* ULPI SMSC USB3320 */\n&usb1 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc4.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm018-dc4\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm018-dc4\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem0;\n\t\tethernet1 = &gem1;\n\t\tethernet2 = &gem2;\n\t\tethernet3 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem0 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy0>;\n\tethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */\n\t\treg = <0>;\n\t};\n\tethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */\n\t\treg = <7>;\n\t};\n\tethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */\n\t\treg = <3>;\n\t};\n\tethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */\n\t\treg = <8>;\n\t};\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy7>;\n};\n\n&gem2 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy3>;\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <ðernet_phy8>;\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n&i2c1 {\n\tclock-frequency = <400000>;\n\tstatus = \"okay\";\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc5.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm019-dc5\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Siva Durga Prasad \n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP zc1751-xm019-dc5 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem1;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci0;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t};\n\n};\n\n&gem1 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/zcu100-revc.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n * Nathalie Chan King Choy\n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/interrupt-controller/irq.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU100 RevC\";\n\tcompatible = \"xlnx,zynqmp-zcu100-revC\", \"xlnx,zynqmp-zcu100\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\ti2c0 = &i2c1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart1;\n\t\tserial1 = &uart0;\n\t\tserial2 = &dcc;\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tmmc0 = &sdhci0;\n\t\tmmc1 = &sdhci1;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw4 {\n\t\t\tlabel = \"sw4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tds2 {\n\t\t\tlabel = \"ds2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tds3 {\n\t\t\tlabel = \"ds3\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tx\"; /* WLAN tx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds4 {\n\t\t\tlabel = \"ds4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0rx\"; /* WLAN rx */\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tds5 {\n\t\t\tlabel = \"ds5\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"bluetooth-power\";\n\t\t};\n\n\t\tvbus-det { /* U5 USB5744 VBUS detection via MIO25 */\n\t\t\tlabel = \"vbus_det\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\twmmcsdio_fixed: fixedregulator-mmcsdio {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"wmmcsdio_fixed\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t};\n\n\tsdio_pwrseq: sdio-pwrseq {\n\t\tcompatible = \"mmc-pwrseq-simple\";\n\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */\n\t\tpost-power-on-delay-ms = <10>;\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gpio {\n\tstatus = \"okay\";\n\tgpio-line-names = \"UART1_TX\", \"UART1_RX\", \"UART0_RX\", \"UART0_TX\", \"I2C1_SCL\",\n\t\t\t \"I2C1_SDA\", \"SPI1_SCLK\", \"WLAN_EN\", \"BT_EN\", \"SPI1_CS\",\n\t\t\t \"SPI1_MISO\", \"SPI1_MOSI\", \"I2C_MUX_RESET\", \"SD0_DAT0\", \"SD0_DAT1\",\n\t\t\t \"SD0_DAT2\", \"SD0_DAT3\", \"PS_LED3\", \"PS_LED2\", \"PS_LED1\",\n\t\t\t \"PS_LED0\", \"SD0_CMD\", \"SD0_CLK\", \"GPIO_PB\", \"SD0_DETECT\",\n\t\t\t \"VBUS_DET\", \"POWER_INT\", \"DP_AUX\", \"DP_HPD\", \"DP_OE\",\n\t\t\t \"DP_AUX_IN\", \"INA226_ALERT\", \"PS_FP_PWR_EN\", \"PL_PWR_EN\", \"POWER_KILL\",\n\t\t\t \"\", \"GPIO-A\", \"GPIO-B\", \"SPI0_SCLK\", \"GPIO-C\",\n\t\t\t \"GPIO-D\", \"SPI0_CS\", \"SPI0_MISO\", \"SPI_MOSI\", \"GPIO-E\",\n\t\t\t \"GPIO-F\", \"SD1_D0\", \"SD1_D1\", \"SD1_D2\", \"SD1_D3\",\n\t\t\t \"SD1_CMD\", \"SD1_CLK\", \"USB0_CLK\", \"USB0_DIR\", \"USB0_DATA2\",\n\t\t\t \"USB0_NXT\", \"USB0_DATA0\", \"USB0_DATA1\", \"USB0_STP\", \"USB0_DATA3\",\n\t\t\t \"USB0_DATA4\", \"USB0_DATA5\", \"USB0_DATA6\", \"USB0_DATA7\", \"USB1_CLK\",\n\t\t\t \"USB1_DIR\", \"USB1_DATA2\", \"USB1_NXT\", \"USB1_DATA0\", \"USB1_DATA1\",\n\t\t\t \"USB1_STP\", \"USB1_DATA3\", \"USB1_DATA4\", \"USB1_DATA5\", \"USB1_DATA6\",\n\t\t\t \"USB_DATA7\", \"WLAN_IRQ\", \"PMIC_IRQ\", /* MIO end and EMIO start */\n\t\t\t \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n\t\t\t \"\", \"\", \"\", \"\";\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <100000>;\n\ti2c-mux@75 { /* u11 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2csw_0: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\tlabel = \"LS-I2C0\";\n\t\t};\n\t\ti2csw_1: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tlabel = \"LS-I2C1\";\n\t\t};\n\t\ti2csw_2: i2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tlabel = \"HS-I2C2\";\n\t\t};\n\t\ti2csw_3: i2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tlabel = \"HS-I2C3\";\n\t\t};\n\t\ti2csw_4: i2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x4>;\n\n\t\t\tpmic: pmic@5e { /* Custom TI PMIC u33 */\n\t\t\t\tcompatible = \"ti,tps65086\";\n\t\t\t\treg = <0x5e>;\n\t\t\t\tinterrupt-parent = <&gpio>;\n\t\t\t\tinterrupts = <77 GPIO_ACTIVE_LOW>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t};\n\t\t};\n\t\ti2csw_5: i2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u35 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <10000>;\n\t\t\t\t/* MIO31 is alert which should be routed to PMUFW */\n\t\t\t};\n\t\t};\n\t\ti2csw_6: i2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/*\n\t\t\t * Not Connected\n\t\t\t */\n\t\t};\n\t\ti2csw_7: i2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/*\n\t\t\t * usb5744 (DNP) - U5\n\t\t\t * 100kHz - this is default freq for us\n\t\t\t */\n\t\t};\n\t};\n};\n\n/* SD0 only supports 3.3V, no level shifter */\n&sdhci0 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tbroken-cd; /* CD has to be enabled by default */\n\tdisable-wp;\n};\n\n&sdhci1 {\n\tstatus = \"okay\";\n\tbus-width = <0x4>;\n\tnon-removable;\n\tdisable-wp;\n\tcap-power-off-card;\n\tmmc-pwrseq = <&sdio_pwrseq>;\n\tvqmmc-supply = <&wmmcsdio_fixed>;\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\twlcore: wifi@2 {\n\t\tcompatible = \"ti,wl1831\";\n\t\treg = <2>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */\n\t};\n};\n\n&spi0 { /* Low Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"LS-SPI0\";\n};\n\n&spi1 { /* High Speed connector */\n\tstatus = \"okay\";\n\tlabel = \"HS-SPI1\";\n};\n\n&uart0 {\n\tstatus = \"okay\";\n\tbluetooth {\n\t\tcompatible = \"ti,wl1831-st\";\n\t\tenable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/zcu102-rev1.0.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 Rev1.0\";\n\tcompatible = \"xlnx,zynqmp-zcu102-rev1.0\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n phy-handle = <&phyc>;\n phyc: phy@c {\n reg = <0xc>;\n ti,rx-internal-delay = <0x8>;\n ti,tx-internal-delay = <0xa>;\n ti,fifo-depth = <0x1>;\n };\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&eeprom {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tboard_sn: board-sn@0 {\n\t\treg = <0x0 0x14>;\n\t};\n\n\teth_mac: eth-mac@20 {\n\t\treg = <0x20 0x6>;\n\t};\n\n\tboard_name: board-name@d0 {\n\t\treg = <0xd0 0x6>;\n\t};\n\n\tboard_revision: board-revision@e0 {\n\t\treg = <0xe0 0x3>;\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/zcu102-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revA\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@21 {\n\t\treg = <21>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/zcu102-revb.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tmodel = \"ZynqMP ZCU102 RevB\";\n\tcompatible = \"xlnx,zynqmp-zcu102-revB\", \"xlnx,zynqmp-zcu102\", \"xlnx,zynqmp\";\n\t\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\t\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 0>;\n\t\t\tlinux,code = <108>;\n\t\t\tgpio-key,wakeup;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat_led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 0>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tphy-handle = <&phyc>;\n\tphyc: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - PS_GTR_LAN_SEL0\n\t\t * 1 - PS_GTR_LAN_SEL1\n\t\t * 2 - PS_GTR_LAN_SEL2\n\t\t * 3 - PS_GTR_LAN_SEL3\n\t\t * 4 - PCI_CLK_DIR_SEL\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 7, 10 - 17 - not connected\n\t\t */\n\n\t\tgtr_sel0 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <0 0>;\n\t\t\toutput-low; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel0\";\n\t\t};\n\t\tgtr_sel1 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <1 0>;\n\t\t\toutput-high; /* PCIE = 0, DP = 1 */\n\t\t\tline-name = \"sel1\";\n\t\t};\n\t\tgtr_sel2 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <2 0>;\n\t\t\toutput-high; /* PCIE = 0, USB0 = 1 */\n\t\t\tline-name = \"sel2\";\n\t\t};\n\t\tgtr_sel3 {\n\t\t\tgpio-hog;\n\t\t\tgpios = <3 0>;\n\t\t\toutput-high; /* PCIE = 0, SATA = 1 */\n\t\t\tline-name = \"sel3\";\n\t\t};\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\t\t\tmax15303@20 { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\tstatus = \"disabled\"; /* unreachable */\n\t\t\t\treg = <0x20>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t\t/*\n\t\t\t\t * Chip has interrupt present connected to PL\n\t\t\t\t * interrupt-parent = <&>;\n\t\t\t\t * interrupts = <>;\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t\t/* 5 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/zcu104-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU104 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu104-revA\", \"xlnx,zynqmp-zcu104\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* Another connection to this bus via PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tclock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */\n\t\t\t\treg = <0x6c>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u175 */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_4d: irps54012@4d { /* IRPS5401 - u180 */\n\t\t\t\treg = <0x4d>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\ttca6416_u97: gpio@21 {\n\t\t\t\tcompatible = \"ti,tca6416\";\n\t\t\t\treg = <0x21>;\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\t/*\n\t\t\t\t * IRQ not connected\n\t\t\t\t * Lines:\n\t\t\t\t * 0 - IRPS5401_ALERT_B\n\t\t\t\t * 1 - HDMI_8T49N241_INT_ALM\n\t\t\t\t * 2 - MAX6643_OT_B\n\t\t\t\t * 3 - MAX6643_FANFAIL_B\n\t\t\t\t * 5 - IIC_MUX_RESET_B\n\t\t\t\t * 6 - GEM3_EXP_RESET_B\n\t\t\t\t * 7 - FMC_LPC_PRSNT_M2C_B\n\t\t\t\t * 4, 10 - 17 - not connected\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t};\n\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t};\n\n\t\t/* 3, 6 not connected */\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n\tdisable-wp;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/zcu106-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU106 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu106-revA\", \"xlnx,zynqmp-zcu106\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tserial2 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u97: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - SFP_SI5328_INT_ALM\n\t\t * 1 - HDMI_SI5328_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMC_HPC0_PRSNT_M2C_B\n\t\t * 11 - FMC_HPC1_PRSNT_M2C_B\n\t\t * 2-4, 7, 12-17 - not connected\n\t\t */\n\t};\n\n\ttca6416_u61: gpio@21 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x21>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - VCCPSPLL_EN\n\t\t * 1 - MGTRAVCC_EN\n\t\t * 2 - MGTRAVTT_EN\n\t\t * 3 - VCCPSDDRPLL_EN\n\t\t * 4 - MIO26_PMU_INPUT_LS\n\t\t * 5 - PL_PMBUS_ALERT\n\t\t * 6 - PS_PMBUS_ALERT\n\t\t * 7 - MAXIM_PMBUS_ALERT\n\t\t * 10 - PL_DDR4_VTERM_EN\n\t\t * 11 - PL_DDR4_VPP_2V5_EN\n\t\t * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON\n\t\t * 13 - PS_DIMM_SUSPEND_EN\n\t\t * 14 - PS_DDR4_VTERM_EN\n\t\t * 15 - PS_DDR4_VPP_2V5_EN\n\t\t * 16 - 17 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u60 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\tina226@40 { /* u76 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@41 { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u78 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u87 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u85 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u86 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u93 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u88 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u15 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u92 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* PL_PMBUS */\n\t\t\tina226@40 { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u81 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u80 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u84 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@44 { /* u16 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u74 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@47 { /* u75 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* MAXIM_PMBUS - 00 */\n\t\t\tmax15301@a { /* u46 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0xa>;\n\t\t\t};\n\t\t\tmax15303@b { /* u4 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0xb>;\n\t\t\t};\n\t\t\tmax15303@10 { /* u13 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x10>;\n\t\t\t};\n\t\t\tmax15301@13 { /* u47 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tmax15303@14 { /* u7 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t\tmax15303@15 { /* u6 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x15>;\n\t\t\t};\n\t\t\tmax15303@16 { /* u10 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x16>;\n\t\t\t};\n\t\t\tmax15303@17 { /* u9 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x17>;\n\t\t\t};\n\t\t\tmax15301@18 { /* u63 */\n\t\t\t\tcompatible = \"maxim,max15301\";\n\t\t\t\treg = <0x18>;\n\t\t\t};\n\t\t\tmax15303@1a { /* u49 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1a>;\n\t\t\t};\n\t\t\tmax15303@1b { /* u8 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1b>;\n\t\t\t};\n\t\t\tmax15303@1d { /* u18 */\n\t\t\t\tcompatible = \"maxim,max15303\";\n\t\t\t\treg = <0x1d>;\n\t\t\t};\n\n\t\t\tmax20751@72 { /* u95 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x72>;\n\t\t\t};\n\t\t\tmax20751@73 { /* u96 */\n\t\t\t\tcompatible = \"maxim,max20751\";\n\t\t\t\treg = <0x73>;\n\t\t\t};\n\t\t};\n\t\t/* Bus 3 is not connected */\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\t/* PL i2c via PCA9306 - u45 */\n\ti2c-mux@74 { /* u34 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u23 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u69 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u42 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u56 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>; /* copy from zc702 */\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 {/* SI5328 - u20 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>; /* FAN controller */\n\t\t\ttemp@4c {/* lm96163 - u128 */\n\t\t\t\tcompatible = \"national,lm96163\";\n\t\t\t\treg = <0x4c>;\n\t\t\t};\n\t\t};\n\t\t/* 6 - 7 unconnected */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u135 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* HPC0_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* HPC1_IIC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SEP 3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SEP 2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SEP 1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SEP 0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/board/zcu111-reva.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU111\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n#include \"include/dt-bindings/input/input.h\"\n#include \"include/dt-bindings/gpio/gpio.h\"\n\n/ {\n\tmodel = \"ZynqMP ZCU111 RevA\";\n\tcompatible = \"xlnx,zynqmp-zcu111-revA\", \"xlnx,zynqmp-zcu111\", \"xlnx,zynqmp\";\n\n\taliases {\n\t\tethernet0 = &gem3;\n\t\ti2c0 = &i2c0;\n\t\ti2c1 = &i2c1;\n\t\tmmc0 = &sdhci1;\n\t\trtc0 = &rtc;\n\t\tserial0 = &uart0;\n\t\tserial1 = &dcc;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tsw19 {\n\t\t\tlabel = \"sw19\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = ;\n\t\t\twakeup-source;\n\t\t\tautorepeat;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\theartbeat-led {\n\t\t\tlabel = \"heartbeat\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\t};\n};\n\n&dcc {\n\tstatus = \"okay\";\n};\n\n&gem3 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\tphy0: phy@c {\n\t\treg = <0xc>;\n\t\tti,rx-internal-delay = <0x8>;\n\t\tti,tx-internal-delay = <0xa>;\n\t\tti,fifo-depth = <0x1>;\n\t\tti,dp83867-rxctrl-strap-quirk;\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ttca6416_u22: gpio@20 {\n\t\tcompatible = \"ti,tca6416\";\n\t\treg = <0x20>;\n\t\tgpio-controller; /* interrupt not connected */\n\t\t#gpio-cells = <2>;\n\t\t/*\n\t\t * IRQ not connected\n\t\t * Lines:\n\t\t * 0 - MAX6643_OT_B\n\t\t * 1 - MAX6643_FANFAIL_B\n\t\t * 2 - MIO26_PMU_INPUT_LS\n\t\t * 4 - SFP_SI5382_INT_ALM\n\t\t * 5 - IIC_MUX_RESET_B\n\t\t * 6 - GEM3_EXP_RESET_B\n\t\t * 10 - FMCP_HSPC_PRSNT_M2C_B\n\t\t * 11 - CLK_SPI_MUX_SEL0\n\t\t * 12 - CLK_SPI_MUX_SEL1\n\t\t * 16 - IRPS5401_ALERT_B\n\t\t * 17 - INA226_PMBUS_ALERT\n\t\t * 3, 7, 13-15 - not connected\n\t\t */\n\t};\n\n\ti2c-mux@75 { /* u23 */\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* PS_PMBUS */\n\t\t\t/* PMBUS_ALERT done via pca9544 */\n\t\t\tina226@40 { /* u67 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@41 { /* u59 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x41>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@42 { /* u61 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x42>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@43 { /* u60 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x43>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@45 { /* u64 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x45>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@46 { /* u69 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x46>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t\tina226@47 { /* u66 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x47>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@48 { /* u65 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x48>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@49 { /* u63 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x49>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4a { /* u3 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4a>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4b { /* u71 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4b>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4c { /* u77 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4c>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4d { /* u73 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4d>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t\tina226@4e { /* u79 */\n\t\t\t\tcompatible = \"ti,ina226\";\n\t\t\t\treg = <0x4e>;\n\t\t\t\tshunt-resistor = <5000>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tirps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */\n\t\t\t\treg = <0x43>;\n\t\t\t};\n\t\t\tirps5401_44: irps54012@44 { /* IRPS5401 - u55 */\n\t\t\t\treg = <0x44>;\n\t\t\t};\n\t\t\tirps5401_45: irps54012@45 { /* IRPS5401 - u57 */\n\t\t\t\treg = <0x45>;\n\t\t\t};\n\t\t\t/* u68 IR38064 +0 */\n\t\t\t/* u70 IR38060 +1 */\n\t\t\t/* u74 IR38060 +2 */\n\t\t\t/* u75 IR38060 +6 */\n\t\t\t/* J19 header too */\n\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* SYSMON */\n\t\t};\n\t};\n};\n\n&i2c1 {\n\tstatus = \"okay\";\n\tclock-frequency = <400000>;\n\n\ti2c-mux@74 { /* u26 */\n\t\tcompatible = \"nxp,pca9548\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x74>;\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/*\n\t\t\t * IIC_EEPROM 1kB memory which uses 256B blocks\n\t\t\t * where every block has different address.\n\t\t\t * 0 - 256B address 0x54\n\t\t\t * 256B - 512B address 0x55\n\t\t\t * 512B - 768B address 0x56\n\t\t\t * 768B - 1024B address 0x57\n\t\t\t */\n\t\t\teeprom: eeprom@54 { /* u88 */\n\t\t\t\tcompatible = \"atmel,24c08\";\n\t\t\t\treg = <0x54>;\n\t\t\t};\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\tsi5341: clock-generator@36 { /* SI5341 - u46 */\n\t\t\t\treg = <0x36>;\n\t\t\t};\n\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\tsi570_1: clock-generator@5d { /* USER SI570 - u47 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <300000000>;\n\t\t\t\tclock-frequency = <300000000>;\n\t\t\t};\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\tsi570_2: clock-generator@5d { /* USER MGT SI570 - u49 */\n\t\t\t\t#clock-cells = <0>;\n\t\t\t\tcompatible = \"silabs,si570\";\n\t\t\t\treg = <0x5d>;\n\t\t\t\ttemperature-stability = <50>;\n\t\t\t\tfactory-fout = <156250000>;\n\t\t\t\tclock-frequency = <148500000>;\n\t\t\t};\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\tsi5328: clock-generator@69 { /* SI5328 - u48 */\n\t\t\t\treg = <0x69>;\n\t\t\t};\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t\tsc18is603@2f { /* sc18is602 - u93 */\n\t\t\t\t\tcompatible = \"nxp,sc18is603\";\n\t\t\t\t\treg = <0x2f>;\n\t\t\t\t\t/* 4 gpios for CS not handled by driver */\n\t\t\t\t\t/*\n\t\t\t\t\t * USB2ANY cable or\n\t\t\t\t\t * LMK04208 - u90 or\n\t\t\t\t\t * LMX2594 - u102 or\n\t\t\t\t\t * LMX2594 - u103 or\n\t\t\t\t\t * LMX2594 - u104\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* FMC connector */\n\t\t};\n\t\t/* 7 NC */\n\t};\n\n\ti2c-mux@75 {\n\t\tcompatible = \"nxp,pca9548\"; /* u27 */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x75>;\n\n\t\ti2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t\t/* FMCP_HSPC_IIC */\n\t\t};\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* NC */\n\t\t};\n\t\ti2c@2 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <2>;\n\t\t\t/* SYSMON */\n\t\t};\n\t\ti2c@3 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <3>;\n\t\t\t/* DDR4 SODIMM */\n\t\t};\n\t\ti2c@4 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <4>;\n\t\t\t/* SFP3 */\n\t\t};\n\t\ti2c@5 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <5>;\n\t\t\t/* SFP2 */\n\t\t};\n\t\ti2c@6 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <6>;\n\t\t\t/* SFP1 */\n\t\t};\n\t\ti2c@7 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <7>;\n\t\t\t/* SFP0 */\n\t\t};\n\t};\n};\n\n&sata {\n\tstatus = \"okay\";\n\t/* SATA OOB timing settings */\n\tceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n\tceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;\n\tceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;\n\tceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;\n\tceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;\n};\n\n/* SD1 with level shifter */\n&sdhci1 {\n\tstatus = \"okay\";\n\tno-1-8-v;\n};\n\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/zynqmp/zynqmp-clk.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n */\n\n/ {\n\tclk100: clk100 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t};\n\n\tclk125: clk125 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tclk200: clk200 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tclk250: clk250 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <250000000>;\n\t};\n\n\tclk300: clk300 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <300000000>;\n\t};\n\n\tclk600: clk600 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <600000000>;\n\t};\n\n\tdp_aclk: clock0 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <100000000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdp_aud_clk: clock1 {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <24576000>;\n\t\tclock-accuracy = <100>;\n\t};\n\n\tdpdma_clk: dpdma-clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <533000000>;\n\t};\n\n\tdrm_clock: drm-clock {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0x0>;\n\t\tclock-frequency = <262750000>;\n\t\tclock-accuracy = <0x64>;\n\t};\n};\n\n&can0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&can1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&fpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&fpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan1 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan2 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan3 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan4 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan5 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan6 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan7 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&lpd_dma_chan8 {\n\tclocks = <&clk600>, <&clk100>;\n};\n\n&gem0 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem1 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem2 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gem3 {\n\tclocks = <&clk125>, <&clk125>, <&clk125>;\n};\n\n&gpio {\n\tclocks = <&clk100>;\n};\n\n&i2c0 {\n\tclocks = <&clk100>;\n};\n\n&i2c1 {\n\tclocks = <&clk100>;\n};\n\n&sata {\n\tclocks = <&clk250>;\n};\n\n&sdhci0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&sdhci1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi0 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&spi1 {\n\tclocks = <&clk200 &clk200>;\n};\n\n&uart0 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&uart1 {\n\tclocks = <&clk100 &clk100>;\n};\n\n&usb0 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&usb1 {\n\tclocks = <&clk250>, <&clk250>;\n};\n\n&watchdog0 {\n\tclocks = <&clk250>;\n};\n" }, { "path": "device_tree/data/kernel_dtsi/v5.4/zynqmp/zynqmp.dtsi", "content": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n * Michal Simek \n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n */\n\n/ {\n\tcompatible = \"xlnx,zynqmp\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu0: cpu@0 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\treg = <0x0>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu1: cpu@1 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x1>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu2: cpu@2 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x2>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tcpu3: cpu@3 {\n\t\t\tcompatible = \"arm,cortex-a53\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\tenable-method = \"psci\";\n\t\t\treg = <0x3>;\n\t\t\toperating-points-v2 = <&cpu_opp_table>;\n\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n\t\t};\n\n\t\tidle-states {\n\t\t\tentry-method = \"psci\";\n\n\t\t\tCPU_SLEEP_0: cpu-sleep-0 {\n\t\t\t\tcompatible = \"arm,idle-state\";\n\t\t\t\tarm,psci-suspend-param = <0x40000000>;\n\t\t\t\tlocal-timer-stop;\n\t\t\t\tentry-latency-us = <300>;\n\t\t\t\texit-latency-us = <600>;\n\t\t\t\tmin-residency-us = <10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tcpu_opp_table: cpu-opp-table {\n\t\tcompatible = \"operating-points-v2\";\n\t\topp-shared;\n\t\topp00 {\n\t\t\topp-hz = /bits/ 64 <1199999988>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp01 {\n\t\t\topp-hz = /bits/ 64 <599999994>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp02 {\n\t\t\topp-hz = /bits/ 64 <399999996>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t\topp03 {\n\t\t\topp-hz = /bits/ 64 <299999997>;\n\t\t\topp-microvolt = <1000000>;\n\t\t\tclock-latency-ns = <500000>;\n\t\t};\n\t};\n\n\tdcc: dcc {\n\t\tcompatible = \"arm,dcc\";\n\t\tstatus = \"disabled\";\n\t};\n\n\tpmu {\n\t\tcompatible = \"arm,armv8-pmuv3\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <0 143 4>,\n\t\t\t <0 144 4>,\n\t\t\t <0 145 4>,\n\t\t\t <0 146 4>;\n\t};\n\n\tpsci {\n\t\tcompatible = \"arm,psci-0.2\";\n\t\tmethod = \"smc\";\n\t};\n\n\ttimer {\n\t\tcompatible = \"arm,armv8-timer\";\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <1 13 0xf08>,\n\t\t\t <1 14 0xf08>,\n\t\t\t <1 11 0xf08>,\n\t\t\t <1 10 0xf08>;\n\t};\n\n\tamba_apu: amba-apu@0 {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges = <0 0 0 0 0xffffffff>;\n\n\t\tgic: interrupt-controller@f9010000 {\n\t\t\tcompatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n\t\t\t#interrupt-cells = <3>;\n\t\t\treg = <0x0 0xf9010000 0x10000>,\n\t\t\t <0x0 0xf9020000 0x20000>,\n\t\t\t <0x0 0xf9040000 0x20000>,\n\t\t\t <0x0 0xf9060000 0x20000>;\n\t\t\tinterrupt-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <1 9 0xf04>;\n\t\t};\n\t};\n\n\tamba: amba {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tcan0: can@ff060000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff060000 0x0 0x1000>;\n\t\t\tinterrupts = <0 23 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcan1: can@ff070000 {\n\t\t\tcompatible = \"xlnx,zynq-can-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\tclock-names = \"can_clk\", \"pclk\";\n\t\t\treg = <0x0 0xff070000 0x0 0x1000>;\n\t\t\tinterrupts = <0 24 4>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\ttx-fifo-depth = <0x40>;\n\t\t\trx-fifo-depth = <0x40>;\n\t\t};\n\n\t\tcci: cci@fd6e0000 {\n\t\t\tcompatible = \"arm,cci-400\";\n\t\t\treg = <0x0 0xfd6e0000 0x0 0x9000>;\n\t\t\tranges = <0x0 0x0 0xfd6e0000 0x10000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpmu@9000 {\n\t\t\t\tcompatible = \"arm,cci-400-pmu,r1\";\n\t\t\t\treg = <0x9000 0x5000>;\n\t\t\t\tinterrupt-parent = <&gic>;\n\t\t\t\tinterrupts = <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>,\n\t\t\t\t\t <0 123 4>;\n\t\t\t};\n\t\t};\n\n\t\t/* GDMA */\n\t\tfpd_dma_chan1: dma@fd500000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd500000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 124 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan2: dma@fd510000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd510000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 125 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan3: dma@fd520000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd520000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 126 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan4: dma@fd530000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd530000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 127 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan5: dma@fd540000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd540000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 128 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan6: dma@fd550000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd550000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 129 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan7: dma@fd560000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd560000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 130 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\tfpd_dma_chan8: dma@fd570000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xfd570000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 131 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <128>;\n\t\t};\n\n\t\t/* LPDDMA default allows only secured access. inorder to enable\n\t\t * These dma channels, Users should ensure that these dma\n\t\t * Channels are allowed for non secure access.\n\t\t */\n\t\tlpd_dma_chan1: dma@ffa80000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa80000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 77 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan2: dma@ffa90000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffa90000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 78 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan3: dma@ffaa0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaa0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 79 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan4: dma@ffab0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffab0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 80 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan5: dma@ffac0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffac0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 81 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan6: dma@ffad0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffad0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 82 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan7: dma@ffae0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffae0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 83 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tlpd_dma_chan8: dma@ffaf0000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"xlnx,zynqmp-dma-1.0\";\n\t\t\treg = <0x0 0xffaf0000 0x0 0x1000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 84 4>;\n\t\t\tclock-names = \"clk_main\", \"clk_apb\";\n\t\t\txlnx,bus-width = <64>;\n\t\t};\n\n\t\tmc: memory-controller@fd070000 {\n\t\t\tcompatible = \"xlnx,zynqmp-ddrc-2.40a\";\n\t\t\treg = <0x0 0xfd070000 0x0 0x30000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 112 4>;\n\t\t};\n\n\t\tgem0: ethernet@ff0b0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 57 4>, <0 57 4>;\n\t\t\treg = <0x0 0xff0b0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem1: ethernet@ff0c0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 59 4>, <0 59 4>;\n\t\t\treg = <0x0 0xff0c0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem2: ethernet@ff0d0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 61 4>, <0 61 4>;\n\t\t\treg = <0x0 0xff0d0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgem3: ethernet@ff0e0000 {\n\t\t\tcompatible = \"cdns,zynqmp-gem\", \"cdns,gem\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 63 4>, <0 63 4>;\n\t\t\treg = <0x0 0xff0e0000 0x0 0x1000>;\n\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tgpio: gpio@ff0a0000 {\n\t\t\tcompatible = \"xlnx,zynqmp-gpio-1.0\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#gpio-cells = <0x2>;\n\t\t\tgpio-controller;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 16 4>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\treg = <0x0 0xff0a0000 0x0 0x1000>;\n\t\t};\n\n\t\ti2c0: i2c@ff020000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 17 4>;\n\t\t\treg = <0x0 0xff020000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\ti2c1: i2c@ff030000 {\n\t\t\tcompatible = \"cdns,i2c-r1p14\", \"cdns,i2c-r1p10\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 18 4>;\n\t\t\treg = <0x0 0xff030000 0x0 0x1000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tpcie: pcie@fd0e0000 {\n\t\t\tcompatible = \"xlnx,nwl-pcie-2.11\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tmsi-controller;\n\t\t\tdevice_type = \"pci\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 118 4>,\n\t\t\t\t <0 117 4>,\n\t\t\t\t <0 116 4>,\n\t\t\t\t <0 115 4>,\t/* MSI_1 [63...32] */\n\t\t\t\t <0 114 4>;\t/* MSI_0 [31...0] */\n\t\t\tinterrupt-names = \"misc\", \"dummy\", \"intx\",\n\t\t\t\t\t \"msi1\", \"msi0\";\n\t\t\tmsi-parent = <&pcie>;\n\t\t\treg = <0x0 0xfd0e0000 0x0 0x1000>,\n\t\t\t <0x0 0xfd480000 0x0 0x1000>,\n\t\t\t <0x80 0x00000000 0x0 0x1000000>;\n\t\t\treg-names = \"breg\", \"pcireg\", \"cfg\";\n\t\t\tranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000\t/* non-prefetchable memory */\n\t\t\t\t 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */\n\t\t\tbus-range = <0x00 0xff>;\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,\n\t\t\t\t\t<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,\n\t\t\t\t\t<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,\n\t\t\t\t\t<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;\n\t\t\tpcie_intc: legacy-interrupt-controller {\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\trtc: rtc@ffa60000 {\n\t\t\tcompatible = \"xlnx,zynqmp-rtc\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xffa60000 0x0 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 26 4>, <0 27 4>;\n\t\t\tinterrupt-names = \"alarm\", \"sec\";\n\t\t\tcalibration = <0x8000>;\n\t\t};\n\n\t\tsata: ahci@fd0c0000 {\n\t\t\tcompatible = \"ceva,ahci-1v84\";\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0x0 0xfd0c0000 0x0 0x2000>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 133 4>;\n\t\t};\n\n\t\tsdhci0: mmc@ff160000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 48 4>;\n\t\t\treg = <0x0 0xff160000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsdhci1: mmc@ff170000 {\n\t\t\tcompatible = \"arasan,sdhci-8.9a\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 49 4>;\n\t\t\treg = <0x0 0xff170000 0x0 0x1000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tsmmu: smmu@fd800000 {\n\t\t\tcompatible = \"arm,mmu-500\";\n\t\t\treg = <0x0 0xfd800000 0x0 0x20000>;\n\t\t\tstatus = \"disabled\";\n\t\t\t#global-interrupts = <1>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,\n\t\t\t\t<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;\n\t\t};\n\n\t\tspi0: spi@ff040000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 19 4>;\n\t\t\treg = <0x0 0xff040000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi1: spi@ff050000 {\n\t\t\tcompatible = \"cdns,spi-r1p6\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 20 4>;\n\t\t\treg = <0x0 0xff050000 0x0 0x1000>;\n\t\t\tclock-names = \"ref_clk\", \"pclk\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tttc0: timer@ff110000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 36 4>, <0 37 4>, <0 38 4>;\n\t\t\treg = <0x0 0xff110000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc1: timer@ff120000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 39 4>, <0 40 4>, <0 41 4>;\n\t\t\treg = <0x0 0xff120000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc2: timer@ff130000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 42 4>, <0 43 4>, <0 44 4>;\n\t\t\treg = <0x0 0xff130000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tttc3: timer@ff140000 {\n\t\t\tcompatible = \"cdns,ttc\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 45 4>, <0 46 4>, <0 47 4>;\n\t\t\treg = <0x0 0xff140000 0x0 0x1000>;\n\t\t\ttimer-width = <32>;\n\t\t};\n\n\t\tuart0: serial@ff000000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 21 4>;\n\t\t\treg = <0x0 0xff000000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tuart1: serial@ff010000 {\n\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 22 4>;\n\t\t\treg = <0x0 0xff010000 0x0 0x1000>;\n\t\t\tclock-names = \"uart_clk\", \"pclk\";\n\t\t};\n\n\t\tusb0: usb@fe200000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 65 4>;\n\t\t\treg = <0x0 0xfe200000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\tusb1: usb@fe300000 {\n\t\t\tcompatible = \"snps,dwc3\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 70 4>;\n\t\t\treg = <0x0 0xfe300000 0x0 0x40000>;\n\t\t\tclock-names = \"clk_xin\", \"clk_ahb\";\n\t\t};\n\n\t\twatchdog0: watchdog@fd4d0000 {\n\t\t\tcompatible = \"cdns,wdt-r1p2\";\n\t\t\tstatus = \"disabled\";\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 113 1>;\n\t\t\treg = <0x0 0xfd4d0000 0x0 0x1000>;\n\t\t\ttimeout-sec = <10>;\n\t\t};\n\t};\n};\n" }, { "path": "dfx_axi_shutdown_manager/data/dfx_axi_shutdown_manager.mdd", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver dfx_axi_shutdown_manager\n OPTION supported_peripherals = (dfx_axi_shutdown_manager);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = dfx_axi_shutdown_manager;\nEND driver\n" }, { "path": "dfx_axi_shutdown_manager/data/dfx_axi_shutdown_manager.tcl", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n set compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,dfx-axi-shutdown-manager\"]\n set_drv_prop $drv_handle compatible \"$compatible\" stringlist\n}\n" }, { "path": "dmaps/data/dmaps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver dmaps\n\n OPTION supported_peripherals = (ps7_dma psu_adma psu_gdma psu_csudma psv_adma psv_gdma psv_csudma psx_pmcdma);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = dmaps;\n\nEND driver\n" }, { "path": "dmaps/data/dmaps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n set ip [get_cells -hier $drv_handle]\n\n #disabling non-secure dma\n if { [string match -nocase $ip \"ps7_dma_ns\"] } {\n set_property NAME none $drv_handle\n }\n}\n" }, { "path": "dp/data/dp.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver dp\n\n OPTION supported_peripherals = (psu_dp psv_dp);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = dp;\n\nEND driver\n" }, { "path": "dp/data/dp.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tgenerate_dp_param $drv_handle\n}\n\nproc generate_dp_param {drv_handle} {\n\tset periph_list [get_cells -hier]\n\tforeach periph $periph_list {\n\tset zynq_ultra_ps [get_property IP_NAME $periph]\n\t\tif {[string match -nocase $zynq_ultra_ps \"zynq_ultra_ps_e\"] } {\n\t\t\tset dp_sel [get_property CONFIG.PSU__DP__LANE_SEL [get_cells -hier $periph]]\n\t\t\tset mode [lindex $dp_sel 0]\n\t\t\tset lan_sel [lindex $dp_sel 1]\n\t\t\tset dp_freq [get_property CONFIG.PSU__DP__REF_CLK_FREQ [get_cells -hier $periph]]\n\t\t\tset dp_freq \"${dp_freq}000000\"\n\t\t\tset ref_clk_list [get_property CONFIG.PSU__DP__REF_CLK_SEL [get_cells -hier $periph]]\n\t\t\tregsub -all {[^0-9]} [lindex $ref_clk_list 1] \"\" val\n\t\t\tif {[string match -nocase $mode \"Single\"]} {\n\t\t\t\tif {[string match -nocase $lan_sel \"Lower\"]} {\n\t\t\t\t\tset lan_name \"dp-phy0\"\n\t\t\t\t\tset lan_phy_type \"psgtr 1 6 0 $val\"\n\t\t\t\t\tset_drv_prop $drv_handle phy-names \"$lan_name\" stringlist\n\t\t\t\t\tset_drv_prop $drv_handle phys \"$lan_phy_type\" reference\n\t\t\t\t} else {\n\t\t\t\t\tset lan_name \"dp-phy0\"\n\t\t\t\t\tset lan_phy_type \"psgtr 3 6 0 $val\"\n\t\t\t\t\tset_drv_prop $drv_handle phy-names \"$lan_name\" stringlist\n\t\t\t\t\tset_drv_prop $drv_handle phys \"$lan_phy_type\" reference\n\t\t\t\t}\n\t\t\t\tset_drv_prop $drv_handle xlnx,max-lanes 1 int\n\t\t\t} elseif {[string match -nocase $mode \"Dual\"]} {\n\t\t\t\tif {[string match -nocase $lan_sel \"Lower\"]} {\n\t\t\t\t\tset lan0_phy_type \"psgtr 1 6 0 $val\"\n\t\t\t\t\tset lan1_phy_type \"psgtr 0 6 1 $val\"\n\t\t\t\t\tset_drv_prop $drv_handle phy-names \"dp-phy0\\\",\\\"dp-phy1\" stringlist\n\t\t\t\t\tset phy_ids \"$lan0_phy_type>, <&$lan1_phy_type\"\n\t\t\t\t\tset_drv_prop $drv_handle phys \"$phy_ids\" reference\n\t\t\t\t} else {\n\t\t\t\t\tset lan0_phy_type \"psgtr 3 6 0 $val\"\n\t\t\t\t\tset lan1_phy_type \"psgtr 2 6 1 $val\"\n\t\t\t\t\tset_drv_prop $drv_handle phy-names \"dp-phy0\\\",\\\"dp-phy1\" stringlist\n\t\t\t\t\tset phy_ids \"$lan0_phy_type>, <&$lan1_phy_type\"\n\t\t\t\t\tset_drv_prop $drv_handle phys \"$phy_ids\" reference\n\t\t\t\t}\n\t\t\t\tset_drv_prop $drv_handle xlnx,max-lanes 2 int\n\t\t\t}\n\t\t}\n\t}\n\tset mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n\tif {[string match -nocase $mainline_ker \"none\"]} {\n\t\tset dp_list \"zynqmp_dp_snd_pcm0 zynqmp_dp_snd_pcm1 zynqmp_dp_snd_card0 zynqmp_dp_snd_codec0\"\n\t\tset dts_file [get_property CONFIG.pcw_dts [get_os]]\n\t\tforeach dp_name ${dp_list} {\n\t\t\tset dp_node [add_or_get_dt_node -n \"&${dp_name}\" -d $dts_file]\n\t\t\thsi::utils::add_new_dts_param \"${dp_node}\" \"status\" \"okay\" string\n\t\t}\n\t}\n}\n" }, { "path": "dp_rx/data/dp_rx.mdd", "content": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver dp_rx\n\n OPTION supported_peripherals = (v_dp_rxss1);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = dp_rx;\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "dp_rx/data/dp_rx.tcl", "content": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tlappend compatible \"xlnx,v-dp-rxss-3.0\" \"xlnx,v-dp-rxss-3.1\"\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset audio_channels [get_property CONFIG.AUDIO_CHANNELS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,audio-channels\" $audio_channels int\n\tset audio_enable [get_property CONFIG.AUDIO_ENABLE [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,audio-enable\" $audio_enable int\n\tset bits_per_color [get_property CONFIG.BITS_PER_COLOR [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,bpc\" $bits_per_color int\n\tset hdcp22_enable [get_property CONFIG.HDCP22_ENABLE [get_cells -hier $drv_handle]]\n\tif {$hdcp22_enable == 1} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,hdcp22-enable\" \"\" boolean\n\t}\n\tset hdcp_enable [get_property CONFIG.HDCP_ENABLE [get_cells -hier $drv_handle]]\n\tif {$hdcp_enable == 1} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,hdcp-enable\" \"\" boolean\n\t}\n\tset include_fec_ports [get_property CONFIG.INCLUDE_FEC_PORTS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,include-fec-ports\" $include_fec_ports int\n\tset edid_ip [get_cells -hier -filter IP_NAME==vid_edid]\n\tif {[llength $edid_ip]} {\n\t\tset baseaddr_dp_rx [get_property CONFIG.C_BASEADDR [get_cells -hier $drv_handle]]\n\t\tset highaddr_dp_rx [get_property CONFIG.C_HIGHADDR [get_cells -hier $drv_handle]]\n\t\tset baseaddr [get_property CONFIG.C_BASEADDR [get_cells -hier $edid_ip]]\n\t\tset highaddr [get_property CONFIG.C_HIGHADDR [get_cells -hier $edid_ip]]\n\t\tset reg_val_0 [generate_reg_property $baseaddr_dp_rx $highaddr_dp_rx]\n\t\tset updat [lappend updat $reg_val_0]\n\t\tset reg_val_1 [generate_reg_property $baseaddr $highaddr]\n\t\tset updat [lappend updat $reg_val_1]\n\t\tset reg_val [lindex $updat 0]\n\t\tappend reg_val \">, <[lindex $updat 1]\"\n\t\tset_drv_prop $drv_handle reg \"$reg_val\" hexintlist\n\t}\n\tlappend reg_names \"dp_base\" \"edid_base\"\n\thsi::utils::add_new_dts_param \"${node}\" \"reg-names\" $reg_names stringlist\n\tlappend phy_names \"dp-phy0\" \"dp-phy1\" \"dp-phy2\" \"dp-phy3\"\n\thsi::utils::add_new_dts_param \"${node}\" \"phy-names\" $phy_names stringlist\n\tset lane_count [get_property CONFIG.LANE_COUNT [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,lane-count\" $lane_count int\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,dp-retimer\" \"xfmc\" reference\n\tset i 0\n\tset updat \"\"\n\twhile {$i < $lane_count} {\n\t\tset rxpinname \"s_axis_lnk_rx_lane$i\"\n\t\tset channelip [get_connected_stream_ip [get_cells -hier $drv_handle] $rxpinname]\n\t\tif {[llength $channelip] && [llength [hsi::utils::get_ip_mem_ranges $channelip]]} {\n\t\t\tset phy_s \"${channelip}rxphy_lane${i} 0 1 1 1\"\n\t\t\tset clocks [lappend clocks $phy_s]\n\t\t\tset updat [lappend updat $phy_s]\n\t\t}\n\t\tincr i\n\t}\n\tset len [llength $updat]\n\tswitch $len {\n\t\t\"1\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"phys\" \"$refs\" reference\n\t\t}\n\t\t\"2\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]\"\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"phys\" \"$refs\" reference\n\t\t}\n\t\t\"3\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]\"\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"phys\" \"$refs\" reference\n\t\t}\n\t\t\"4\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]\"\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"phys\" \"$refs\" reference\n\t\t}\n\t}\n\tset mode [get_property CONFIG.MODE [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mode\" $mode int\n\tset num_streams [get_property CONFIG.NUM_STREAMS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,num-streams\" $num_streams int\n\tset phy_data_width [get_property CONFIG.PHY_DATA_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,phy-data-width\" $phy_data_width int\n\tset pixel_mode [get_property CONFIG.PIXEL_MODE [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,pixel-mode\" $pixel_mode int\n\tset sim_mode [get_property CONFIG.SIM_MODE [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,sim-mode\" $sim_mode string\n\tset video_interface [get_property CONFIG.VIDEO_INTERFACE [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,video-interface\" $video_interface int\n\tset vid_phy_ctlr [get_cells -hier -filter IP_NAME==vid_phy_controller]\n\tif {[llength $vid_phy_ctlr]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,vidphy\" $vid_phy_ctlr reference\n\t}\n\tset ports_node [add_or_get_dt_node -n \"ports\" -l dprx_ports$drv_handle -p ${node}]\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\tset port0_node [add_or_get_dt_node -n \"port\" -u 0 -l dprx_port$drv_handle -p $ports_node]\n\thsi::utils::add_new_dts_param \"$port0_node\" \"reg\" 0 int\n\tset dprxip [get_connected_stream_ip [get_cells -hier $drv_handle] \"m_axis_video_stream1\"]\n\tforeach ip $dprxip {\n\t\tif {[string match -nocase [get_property IP_NAME $ip] \"system_ila\"]} {\n\t\t\tcontinue\n\t\t}\n\t\tset intfpins [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip]\n\t\tif {[llength $ip_mem_handles]} {\n\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\tset dp_rx_node [add_or_get_dt_node -n \"endpoint\" -l dprx_out$drv_handle -p $port0_node]\n\t\t\tgen_endpoint $drv_handle \"dprx_out$drv_handle\"\n\t\t\thsi::utils::add_new_dts_param \"$dp_rx_node\" \"remote-endpoint\" $ip$drv_handle reference\n\t\t\tgen_remoteendpoint $drv_handle $ip$drv_handle\n\t\t\tif {[string match -nocase [get_property IP_NAME $ip] \"v_frmbuf_wr\"]} {\n\t\t\t\tgen_frmbuf_wr_node $ip $drv_handle\n\t\t\t}\n\t\t} else {\n\t\t\tset connectip [get_connect_ip $ip $intfpins]\n\t\t\tif {[llength $connectip]} {\n\t\t\t\tset sdi_rx_node [add_or_get_dt_node -n \"endpoint\" -l dprx_out$drv_handle -p $port0_node]\n\t\t\t\tgen_endpoint $drv_handle \"dprx_out$drv_handle\"\n\t\t\t\thsi::utils::add_new_dts_param \"$dp_rx_node\" \"remote-endpoint\" $connectip$drv_handle reference\n\t\t\t\tgen_remoteendpoint $drv_handle $connectip$drv_handle\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"axi_vdma\"] || [string match -nocase [get_property IP_NAME $connectip] \"v_frmbuf_wr\"]} {\n\t\t\t\t\tgen_frmbuf_wr_node $connectip $drv_handle\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc gen_frmbuf_wr_node {outip drv_handle} {\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n set vcap [add_or_get_dt_node -n \"vcap_dprx$drv_handle\" -p $bus_node]\n hsi::utils::add_new_dts_param $vcap \"compatible\" \"xlnx,video\" string\n hsi::utils::add_new_dts_param $vcap \"dmas\" \"$outip 0\" reference\n hsi::utils::add_new_dts_param $vcap \"dma-names\" \"port0\" string\n set vcap_ports_node [add_or_get_dt_node -n \"ports\" -l vcap_ports$drv_handle -p $vcap]\n hsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#address-cells\" 1 int\n hsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#size-cells\" 0 int\n set vcap_port_node [add_or_get_dt_node -n \"port\" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node]\n hsi::utils::add_new_dts_param \"$vcap_port_node\" \"reg\" 0 int\n hsi::utils::add_new_dts_param \"$vcap_port_node\" \"direction\" input string\n set vcap_in_node [add_or_get_dt_node -n \"endpoint\" -l $outip$drv_handle -p $vcap_port_node]\n hsi::utils::add_new_dts_param \"$vcap_in_node\" \"remote-endpoint\" dprx_out$drv_handle reference\n}\n\n" }, { "path": "dp_tx/data/dp_tx.mdd", "content": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver dp_tx\n\n OPTION supported_peripherals = (v_dp_txss1);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = dp_tx;\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "dp_tx/data/dp_tx.tcl", "content": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tlappend compatible \"xlnx,v-dp-txss-3.1\"\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset num_audio_channels [get_property CONFIG.Number_of_Audio_Channels [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,num-audio-channels\" $num_audio_channels int\n\tset audio_enable [get_property CONFIG.AUDIO_ENABLE [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,audio-enable\" $audio_enable int\n\tset bits_per_color [get_property CONFIG.BITS_PER_COLOR [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,bpc\" $bits_per_color int\n\tset hdcp22_enable [get_property CONFIG.HDCP22_ENABLE [get_cells -hier $drv_handle]]\n\tif {$hdcp22_enable == 1} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,hdcp22-enable\" \"\" boolean\n\t}\n\tset hdcp_enable [get_property CONFIG.HDCP_ENABLE [get_cells -hier $drv_handle]]\n\tif {$hdcp_enable == 1} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,hdcp-enable\" \"\" boolean\n\t}\n\tset include_fec_ports [get_property CONFIG.INCLUDE_FEC_PORTS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,include-fec-ports\" $include_fec_ports int\n\tlappend reg_names \"dp_base\"\n\thsi::utils::add_new_dts_param \"${node}\" \"reg-names\" $reg_names stringlist\n\tlappend phy_names \"dp-phy0\" \"dp-phy1\" \"dp-phy2\" \"dp-phy3\"\n\thsi::utils::add_new_dts_param \"${node}\" \"phy-names\" $phy_names stringlist\n\tset lane_count [get_property CONFIG.LANE_COUNT [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,max-lanes\" $lane_count int\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,dp-retimer\" \"xfmc\" reference\n\tset hdcp_keymngmt [get_cells -hier -filter IP_NAME==hdcp_keymngmt_blk]\n\tif {[llength $hdcp_keymngmt]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,hdcp1x-keymgmt\" [lindex $hdcp_keymngmt 1] reference\n\t}\n\tset clknames \"s_axi_aclk tx_vid_clk\"\n\toverwrite_clknames $clknames $drv_handle\n\tset i 0\n\tset updat \"\"\n\twhile {$i < $lane_count} {\n\t\tset txpinname \"m_axis_lnk_tx_lane$i\"\n\t\tset channelip [get_connected_stream_ip [get_cells -hier $drv_handle] $txpinname]\n\t\tif {[llength $channelip] && [llength [hsi::utils::get_ip_mem_ranges $channelip]]} {\n\t\t\tset phy_s \"${channelip}txphy_lane${i} 0 1 1 1\"\n\t\t\tset clocks [lappend clocks $phy_s]\n\t\t\tset updat [lappend updat $phy_s]\n\t\t}\n\t\tincr i\n\t}\n\tset len [llength $updat]\n\tswitch $len {\n\t\t\"1\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"phys\" \"$refs\" reference\n\t\t}\n\t\t\"2\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]\"\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"phys\" \"$refs\" reference\n\t\t}\n\t\t\"3\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]\"\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"phys\" \"$refs\" reference\n\t\t}\n\t\t\"4\" {\n\t\t\tset refs [lindex $updat 0]\n\t\t\tappend refs \">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]\"\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"phys\" \"$refs\" reference\n\t\t}\n\t}\n\tset link_rate [get_property CONFIG.LINK_RATE [get_cells -hier $drv_handle]]\n\tset link_rate [expr {${link_rate} * 100000}]\n\tset link_rate [expr int ($link_rate)]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,max-link-rate\" $link_rate int\n\tset mode [get_property CONFIG.MODE [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mode\" $mode int\n\tset num_streams [get_property CONFIG.NUM_STREAMS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,num-streams\" $num_streams int\n\tset phy_data_width [get_property CONFIG.PHY_DATA_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,phy-data-width\" $phy_data_width int\n\tset pixel_mode [get_property CONFIG.PIXEL_MODE [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,pixel-mode\" $pixel_mode int\n\tset sim_mode [get_property CONFIG.SIM_MODE [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,sim-mode\" $sim_mode string\n\tset video_interface [get_property CONFIG.VIDEO_INTERFACE [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,video-interface\" $video_interface int\n\tset vtcip [get_cells -hier -filter {IP_NAME == \"v_tc\"}]\n\tif {[llength $vtcip]} {\n\t\tset baseaddr [get_property CONFIG.C_BASEADDR [get_cells -hier $vtcip]]\n\t\tif {[llength $baseaddr]} {\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,vtc-offset\" \"$baseaddr\" int\n\t\t}\n\t}\n\tset ports_node [add_or_get_dt_node -n \"ports\" -l dptx_ports$drv_handle -p ${node}]\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\tset port0_node [add_or_get_dt_node -n \"port\" -u 0 -l dptx_port$drv_handle -p $ports_node]\n\thsi::utils::add_new_dts_param \"$port0_node\" \"reg\" 0 int\n\tset dptxip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video_stream1\"]\n\tforeach ip $dptxip {\n\t\tif {[string match -nocase [get_property IP_NAME $ip] \"system_ila\"]} {\n\t\t\tcontinue\n\t\t}\n\t\tset intfpins [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip]\n\t\tif {[llength $ip_mem_handles]} {\n\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\tset dp_tx_node [add_or_get_dt_node -n \"endpoint\" -l dptx_out$drv_handle -p $port0_node]\n\t\t\tgen_endpoint $drv_handle \"dptx_out$drv_handle\"\n\t\t\tif {[string match -nocase [get_property IP_NAME $ip] \"v_mix\"]} {\n\t\t\t\thsi::utils::add_new_dts_param \"$dp_tx_node\" \"remote-endpoint\" \"mixer_crtc$ip\" reference\n\t\t\t\tgen_remoteendpoint $drv_handle \"mixer_crtc$ip\"\n\t\t\t} else {\n\t\t\t\thsi::utils::add_new_dts_param \"$dp_tx_node\" \"remote-endpoint\" $ip$drv_handle reference\n\t\t\t\tgen_remoteendpoint $drv_handle $ip$drv_handle\n\t\t\t}\n\t\t\tif {[string match -nocase [get_property IP_NAME $ip] \"v_frmbuf_rd\"]} {\n\t\t\t\tgen_pl_disp_node $ip $drv_handle\n\t\t\t}\n\t\t} else {\n\t\t\tset connectip [get_connect_ip $ip $intfpins]\n\t\t\tif {[llength $connectip]} {\n\t\t\t\tset dp_tx_node [add_or_get_dt_node -n \"endpoint\" -l dptx_out$drv_handle -p $port0_node]\n\t\t\t\tgen_endpoint $drv_handle \"dptx_out$drv_handle\"\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $ip] \"v_mix\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$dp_tx_node\" \"remote-endpoint\" \"mixer_crtc$connectip\" reference\n\t\t\t\t\tgen_remoteendpoint $drv_handle \"mixer_crtc$connectip\"\n\t\t\t\t} else {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$dp_tx_node\" \"remote-endpoint\" $connectip$drv_handle reference\n\t\t\t\t\tgen_remoteendpoint $drv_handle $connectip$drv_handle\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"axi_vdma\"] || [string match -nocase [get_property IP_NAME $connectip] \"v_frmbuf_rd\"]} {\n\t\t\t\t\tgen_pl_disp_node $connectip $drv_handle\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tgen_xfmc_node\n\t}\n}\n\nproc gen_pl_disp_node {outip drv_handle} {\n set dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n if {$dt_overlay} {\n set bus_node \"amba\"\n } else {\n set bus_node \"amba_pl\"\n }\n set pl_disp [add_or_get_dt_node -n \"drm-pl-disp-drv\" -l \"v_pl_disp\" -p $bus_node]\n hsi::utils::add_new_dts_param $pl_disp \"compatible\" \"xlnx,pl-disp\" string\n hsi::utils::add_new_dts_param $pl_disp \"dmas\" \"$outip 0\" reference\n hsi::utils::add_new_dts_param $pl_disp \"dma-names\" \"dma0\" string\n hsi::utils::add_new_dts_param $pl_disp \"xlnx,vformat\" \"YUYV\" string\n set pl_port [add_or_get_dt_node -n \"port\" -l \"pl_disp_port\" -u 0 -p $pl_disp]\n hsi::utils::add_new_dts_param \"$pl_port\" \"reg\" 0 int\n set pl_disp_crtc [add_or_get_dt_node -n \"endpoint\" -l $outip$drv_handle -p $pl_port]\n hsi::utils::add_new_dts_param \"$pl_disp_crtc\" \"remote-endpoint\" dptx_out$drv_handle reference\n}\n\n#generate fmc card node as this is required when display port exits\nproc gen_xfmc_node {} {\n set dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n if {$dt_overlay} {\n set bus_node \"amba\"\n } else {\n set bus_node \"amba_pl\"\n }\n set pl_disp [add_or_get_dt_node -n \"xv_fmc\" -l \"xfmc\" -p $bus_node]\n hsi::utils::add_new_dts_param $pl_disp \"compatible\" \"xilinx-vfmc\" string\n}\n" }, { "path": "dpu_eu/data/dpu_eu.mdd", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver dpu_eu\n\n OPTION supported_peripherals = (dpu_eu);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = dpu_eu;\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "dpu_eu/data/dpu_eu.tcl", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"deephi,dpu\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n}\n" }, { "path": "emaclite/data/emaclite.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver emaclite\n\n OPTION supported_peripherals = (axi_ethernetlite);\n OPTION driver_state = ACTIVE;\n OPTION NAME = emaclite;\n OPTION supported_os_types = (DTS);\n PARAMETER name = system.dts, default = \"local-mac-address\", type = stringlist;\n PARAMETER name = dev_type, default = ethernet, type = string;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,xps-ethernetlite-1.00.a\";\n DTGPARAM name = device_type, type = string, default = network;\n DTGPARAM name = dtg.alias, type = string, default = ethernet;\n DTGPARAM name = local-mac-address, default = \"00 0a 35 00 00 00\", type = bytelist;\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "emaclite/data/emaclite.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n set compatible [get_comp_str $drv_handle]\n set compatible [append compatible \" \" \"xlnx,xps-ethernetlite-1.00.a\"]\n set_drv_prop $drv_handle compatible \"$compatible\" stringlist\n update_eth_mac_addr $drv_handle\n set node [gen_peripheral_nodes $drv_handle]\n gen_mdio_node $drv_handle $node\n}\n\n" }, { "path": "emacps/data/emacps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver emacps\n\n OPTION supported_peripherals = (ps7_ethernet psu_ethernet psv_ethernet psx_ethernet);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = emacps;\n PARAMETER name = dev_type, default = ethernet, type = string;\n PARAMETER name = system.dts, default = \"local-mac-address\", type = stringlist;\n\n DTGPARAM name = local-mac-address, default = \"00 0a 35 00 00 00\", type = bytelist\n DTGPARAM name = dtg.alias, type = string, default = ethernet;\n DTGPARAM name = phy-mode, default = gmii\n DTGPARAM name = \"xlnx,ptp-enet-clock\"\n\nEND driver\n" }, { "path": "emacps/data/emacps.tcl", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\n##############################################################################\nvariable phy_count 0\n##############################################################################\n\nproc is_gmii2rgmii_conv_present {slave} {\n set phy_addr -1\n set ipconv 0\n\n set ips [get_cells -hier -filter {IP_NAME == \"gmii_to_rgmii\"}]\n set ip_name [get_property NAME $slave]\n set slave_pins [get_pins -of_objects [get_cells -hier $slave]]\n\n foreach ip $ips {\n set ipconv2eth_pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $ip \"gmii_txd\"]]]\n if {[regexp -nocase {(enet[0-3])} \"$ipconv2eth_pins\" match]} {\n set number [regexp -all -inline -- {[0-3]+} $ipconv2eth_pins]\n if {[string match -nocase $slave \"psu_ethernet_$number\"] || [string match -nocase $slave \"ps7_ethernet_$number\"]} {\n set ipconv $ip\n set phy_addr [get_property \"CONFIG.C_PHYADDR\" $ipconv]\n break\n }\n }\n foreach gmii_pin ${ipconv2eth_pins} {\n # check if it is connected to the slave IP\n if { [lsearch ${slave_pins} $gmii_pin] >= 0 } {\n set ipconv $ip\n set phy_addr [get_property \"CONFIG.C_PHYADDR\" $ipconv]\n break\n }\n }\n if { $phy_addr >= 0 } {\n break\n }\n }\n return \"$phy_addr $ipconv\"\n}\n\nproc gen_phy_node args {\n set mdio_node [lindex $args 0]\n set phy_name [lindex $args 1]\n set phya [lindex $args 2]\n\n set default_dts [get_property CONFIG.pcw_dts [get_os]]\n set rgmii_node [add_or_get_dt_node -l $phy_name -n $phy_name -u $phya -d $default_dts -p $mdio_node]\n hsi::utils::add_new_dts_param \"${rgmii_node}\" \"reg\" $phya int\n hsi::utils::add_new_dts_param \"${rgmii_node}\" \"compatible\" \"xlnx,gmii-to-rgmii-1.0\" string\n hsi::utils::add_new_dts_param \"${rgmii_node}\" \"phy-handle\" phy1 reference\n}\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n\n update_eth_mac_addr $drv_handle\n\n set slave [get_cells -hier $drv_handle]\n set phymode [hsi::utils::get_ip_param_value $slave \"C_ETH_MODE\"]\n if { $phymode == 0 } {\n set_property CONFIG.phy-mode \"gmii\" $drv_handle\n } elseif { $phymode == 2 } {\n set_property CONFIG.phy-mode \"sgmii\" $drv_handle\n } else {\n set_property CONFIG.phy-mode \"rgmii-id\" $drv_handle\n }\n\n set hwproc [get_cells -hier [get_sw_processor]]\n if { [llength [get_sw_processor] ] && [llength $hwproc] } {\n set ps7_cortexa9_1x_clk [hsi::utils::get_ip_param_value $hwproc \"C_CPU_1X_CLK_FREQ_HZ\"]\n set_property CONFIG.xlnx,ptp-enet-clock \"$ps7_cortexa9_1x_clk\" $drv_handle\n }\n ps7_reset_handle $drv_handle CONFIG.C_ENET_RESET CONFIG.enet-reset\n\n # only generate the mdio node if it has mdio\n set has_mdio [get_property CONFIG.C_HAS_MDIO $slave]\n if { $has_mdio == \"0\" } {\n return 0\n }\n\n # node must be created before child node\n set node [gen_peripheral_nodes $drv_handle]\n set proc_type [get_sw_proc_prop IP_NAME]\n if {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n set zynq_periph [get_cells -hier -filter {IP_NAME == zynq_ultra_ps_e}]\n set avail_param [list_property [get_cells -hier $zynq_periph]]\n if {[lsearch -nocase $avail_param \"CONFIG.PSU__GEM__TSU__ENABLE\"] >= 0} {\n set val [get_property CONFIG.PSU__GEM__TSU__ENABLE [get_cells -hier $zynq_periph]]\n if {$val == 1} {\n set default_dts [get_property CONFIG.pcw_dts [get_os]]\n set root_node [add_or_get_dt_node -n / -d ${default_dts}]\n set tsu_node [add_or_get_dt_node -n \"tsu_ext_clk\" -l \"tsu_ext_clk\" -d $default_dts -p $root_node]\n hsi::utils::add_new_dts_param \"${tsu_node}\" \"compatible\" \"fixed-clock\" stringlist\n hsi::utils::add_new_dts_param \"${tsu_node}\" \"#clock-cells\" 0 int\n set tsu-clk-freq [get_property CONFIG.C_ENET_TSU_CLK_FREQ_HZ [get_cells -hier $drv_handle]]\n hsi::utils::add_new_dts_param \"${tsu_node}\" \"clock-frequency\" ${tsu-clk-freq} int\n set_drv_prop_if_empty $drv_handle \"clock-names\" \"pclk hclk tx_clk rx_clk tsu_clk\" stringlist\n\t\tif {[string match -nocase $node \"&gem3\"]} {\n\t\t\tset_drv_prop_if_empty $drv_handle \"clocks\" \"zynqmp_clk 31>, <&zynqmp_clk 107>, <&zynqmp_clk 48>, <&zynqmp_clk 52>, <&tsu_ext_clk\" reference\n\t\t} elseif {[string match -nocase $node \"&gem2\"]} {\n\t\t\tset_drv_prop_if_empty $drv_handle \"clocks\" \"zynqmp_clk 31>, <&zynqmp_clk 106>, <&zynqmp_clk 47>, <&zynqmp_clk 51>, <&tsu_ext_clk\" reference\n\t\t} elseif {[string match -nocase $node \"&gem1\"]} {\n\t\t\tset_drv_prop_if_empty $drv_handle \"clocks\" \"zynqmp_clk 31>, <&zynqmp_clk 105>, <&zynqmp_clk 46>, <&zynqmp_clk 50>, <&tsu_ext_clk\" reference\n\t\t} elseif {[string match -nocase $node \"&gem0\"]} {\n\t\t\tset_drv_prop_if_empty $drv_handle \"clocks\" \"zynqmp_clk 31>, <&zynqmp_clk 104>, <&zynqmp_clk 45>, <&zynqmp_clk 49>, <&tsu_ext_clk\" reference\n\t\t}\n\t}\n }\n }\n\n if {[string match -nocase $proc_type \"psv_cortexa72\"] } {\n\tset versal_periph [get_cells -hier -filter {IP_NAME == versal_cips || IP_NAME == ps_wizard}]\n\tif {[llength $versal_periph]} {\n\t\tset avail_param [list_property [get_cells -hier $versal_periph]]\n\t\tif {[lsearch -nocase $avail_param \"CONFIG.PS_GEM_TSU_ENABLE\"] >= 0} {\n\t\t\tset val [get_property CONFIG.PS_GEM_TSU_ENABLE [get_cells -hier $versal_periph]]\n\t\t\tif {$val == 1} {\n\t\t\t\tset default_dts [get_property CONFIG.pcw_dts [get_os]]\n\t\t\t\tset root_node [add_or_get_dt_node -n / -d ${default_dts}]\n\t\t\t\tset tsu_node [add_or_get_dt_node -n \"tsu_ext_clk\" -l \"tsu_ext_clk\" -d $default_dts -p $root_node]\n\t\t\t\thsi::utils::add_new_dts_param \"${tsu_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t\t\t\thsi::utils::add_new_dts_param \"${tsu_node}\" \"#clock-cells\" 0 int\n\t\t\t\tset tsu-clk-freq [get_property CONFIG.C_ENET_TSU_CLK_FREQ_HZ [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"${tsu_node}\" \"clock-frequency\" ${tsu-clk-freq} int\n\t\t\t\tset_drv_prop_if_empty $drv_handle \"clock-names\" \"pclk hclk tx_clk rx_clk tsu_clk\" stringlist\n\t\t\t\tif {[string match -nocase $node \"&gem0\"]} {\n\t\t\t\t\tset_drv_prop_if_empty $drv_handle \"clocks\" \"versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&tsu_ext_clk\" reference\n\t\t\t\t} elseif {[string match -nocase $node \"&gem1\"]} {\n\t\t\t\t\tset_drv_prop_if_empty $drv_handle \"clocks\" \"versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&tsu_ext_clk\" reference\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\tif {[string match -nocase $proc_type \"psx_cortexa78\"] } {\n\t\tset versalnet_periph [get_cells -hier -filter {IP_NAME == psx_wizard}]\n\t\tset psx_pmcx_params [get_property CONFIG.PSX_PMCX_CONFIG [get_cells -hier $versalnet_periph]]\n\t\tset psx_gem_tsu_enable \"\"\n\t\tif {[llength $psx_pmcx_params]} {\n\t\t\tset psx_gem_tsu \"\"\n\t\t\tif {[dict exists $psx_pmcx_params \"PSX_GEM_TSU\"]} {\n\t\t\t\tset psx_gem_tsu [dict get $psx_pmcx_params \"PSX_GEM_TSU\"]\n\t\t\t\tif {[dict exists $psx_gem_tsu \"ENABLE\"]} {\n\t\t\t\t\tset psx_gem_tsu_enable [dict get $psx_gem_tsu \"ENABLE\"]\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {$psx_gem_tsu_enable == 1} {\n\t\t\tset default_dts [get_property CONFIG.pcw_dts [get_os]]\n\t\t\tset root_node [add_or_get_dt_node -n / -d ${default_dts}]\n\t\t\tset tsu_node [add_or_get_dt_node -n \"tsu_ext_clk\" -l \"tsu_ext_clk\" -d $default_dts -p $root_node]\n\t\t\thsi::utils::add_new_dts_param \"${tsu_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t\t\thsi::utils::add_new_dts_param \"${tsu_node}\" \"#clock-cells\" 0 int\n\t\t\tset tsu-clk-freq [get_property CONFIG.C_ENET_TSU_CLK_FREQ_HZ [get_cells -hier $drv_handle]]\n\t\t\thsi::utils::add_new_dts_param \"${tsu_node}\" \"clock-frequency\" ${tsu-clk-freq} int\n\t\t\tset_drv_prop_if_empty $drv_handle \"clock-names\" \"pclk hclk tx_clk rx_clk tsu_clk\" stringlist\n\t\t\tif {[string match -nocase $node \"&gem0\"]} {\n\t\t\t\tset_drv_prop_if_empty $drv_handle \"clocks\" \"versal_net_clk 82>, <&versal_net_clk 88>, <&versal_net_clk 49>, <&versal_net_clk 48>, <&tsu_ext_clk\" reference\n\t\t\t} elseif {[string match -nocase $node \"&gem1\"]} {\n\t\t\t\tset_drv_prop_if_empty $drv_handle \"clocks\" \"versal_net_clk 82>, <&versal_net_clk 89>, <&versal_net_clk 51>, <&versal_net_clk 50>, <&tsu_ext_clk\" reference\n\t\t\t}\n\t\t}\n\n\t}\n\n # check if gmii2rgmii converter is used.\n set conv_data [is_gmii2rgmii_conv_present $slave]\n set phya [lindex $conv_data 0]\n if { $phya != \"-1\" } {\n set phy_name \"[lindex $conv_data 1]\"\n set_drv_prop $drv_handle phy-handle \"phy1\" reference\n set mdio_node [gen_mdio1_node $drv_handle $node]\n gen_phy_node $mdio_node $phy_name $phya\n }\n set ip_name \" \"\n if {[string match -nocase $proc_type \"ps7_cortexa9\"] } {\n if {[string match -nocase $node \"&gem1\"]} {\n set zynq_periph [get_cells -hier -filter {IP_NAME == processing_system7}]\n set port0_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $zynq_periph] \"ENET1_MDIO_O\"]]\n set sink_periph \"\"\n if {[llength $port0_pins]} {\n set sink_periph [::hsi::get_cells -of_objects $port0_pins]\n }\n if {[llength $sink_periph]} {\n set ip_name [get_property IP_NAME $sink_periph]\n }\n if {[llength $ip_name] && [string match -nocase $ip_name \"gig_ethernet_pcs_pma\"]} {\n set pin [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $sink_periph] \"phyaddr\"]]\n if {[llength $pin]} {\n set periph [::hsi::get_cells -of_objects $pin]\n }\n if {[llength $periph]} {\n set val [get_property CONFIG.CONST_VAL $periph]\n set inhex [format %x $val]\n set_drv_prop $drv_handle phy-handle \"phy$inhex\" reference\n set pcspma_phy_node [add_or_get_dt_node -l phy$inhex -n phy -u $inhex -p $node]\n hsi::utils::add_new_dts_param \"${pcspma_phy_node}\" \"reg\" $val int\n set phy_type [get_property CONFIG.Standard $sink_periph]\n set is_sgmii [get_property CONFIG.c_is_sgmii $sink_periph]\n if {$phy_type == \"1000BASEX\"} {\n hsi::utils::add_new_dts_param \"${pcspma_phy_node}\" \"xlnx,phy-type\" 0x5 int\n } elseif { $is_sgmii == \"true\"} {\n hsi::utils::add_new_dts_param \"${pcspma_phy_node}\" \"xlnx,phy-type\" 0x4 int\n } else {\n dtg_warning \"unsupported phytype:$phy_type\"\n }\n }\n }\n }\n }\n\n\tif {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n\t\tset sink_periph \"\"\n\t\tif {[string match -nocase $node \"&gem0\"]} {\n\t\t\tset connected_ip [hsi::utils::get_connected_stream_ip $zynq_periph \"MDIO_ENET0\"]\n\t\t\tif {[llength $connected_ip]} {\n\t\t\t\tset ip_name [get_property IP_NAME $connected_ip]\n\t\t\t}\n\t\t\tif {[llength $ip_name] && [string match -nocase $ip_name \"gig_ethernet_pcs_pma\"]} {\n\t\t\t\tset intf_pins [::hsi::get_intf_pins -of_objects [get_cells $zynq_periph] \"MDIO_ENET0\"]\n\t\t\t\tset connected_pin \"\"\n\t\t\t\tset intf_nets \"\"\n\t\t\t\tif {[llength $intf_pins]} {\n\t\t\t\t\tset intf_nets [::hsi::get_intf_nets -of_objects $intf_pins]\n\t\t\t\t}\n\t\t\t\tif {[llength $intf_nets]} {\n\t\t\t\t\tset connected_pin [::hsi::get_intf_pins -of_objects $intf_nets -filter {TYPE==SLAVE || TYPE==TARGET}]\n\t\t\t\t}\n\t\t\t\tset phyaddr_suffix \"\"\n\t\t\t\tif {[llength $connected_pin]} {\n\t\t\t\t\tset phyaddr_suffix [string trim $connected_pin \"mdio_pcs_pma\"]\n\t\t\t\t}\n\t\t\t\tset phyaddr \"phyaddr\"\n\t\t\t\tif {[llength $phyaddr_suffix]} {\n\t\t\t\t\tappend phyaddr \"_$phyaddr_suffix\"\n\t\t\t\t}\n\t\t\t\tset pin [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $connected_ip] $phyaddr]]\n\t\t\t\tif {[llength $pin]} {\n\t\t\t\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t}\n\t\t\t\tif {[llength $sink_periph]} {\n\t\t\t\t\tset val [get_property CONFIG.CONST_VAL $sink_periph]\n\t\t\t\t\tset inhex [format %x $val]\n\t\t\t\t\tset_drv_prop $drv_handle phy-handle \"phy$inhex\" reference\n\t\t\t\t\tset pcspma_phy_node [add_or_get_dt_node -l phy$inhex -n phy -u $inhex -p $node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${pcspma_phy_node}\" \"reg\" $val int\n\t\t\t\t\tset phy_type [get_property CONFIG.Standard $connected_ip]\n\t\t\t\t\tset is_sgmii [get_property CONFIG.c_is_sgmii $connected_ip]\n\t\t\t\t\tif {$phy_type == \"1000BASEX\"} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${pcspma_phy_node}\" \"xlnx,phy-type\" 0x5 int\n\t\t\t\t\t} elseif { $is_sgmii == \"true\"} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${pcspma_phy_node}\" \"xlnx,phy-type\" 0x4 int\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"unsupported phytype:$phy_type\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $node \"&gem1\"]} {\n\t\t\tset connected_ip [hsi::utils::get_connected_stream_ip $zynq_periph \"MDIO_ENET1\"]\n\t\t\tif {[llength $connected_ip]} {\n\t\t\t\tset ip_name [get_property IP_NAME $connected_ip]\n\t\t\t}\n\t\t\tif {[llength $ip_name] && [string match -nocase $ip_name \"gig_ethernet_pcs_pma\"]} {\n\t\t\t\tset intf_pins [::hsi::get_intf_pins -of_objects [get_cells $zynq_periph] \"MDIO_ENET1\"]\n\t\t\t\tset connected_pin \"\"\n\t\t\t\tset intf_nets \"\"\n\t\t\t\tif {[llength $intf_pins]} {\n\t\t\t\t\tset intf_nets [::hsi::get_intf_nets -of_objects $intf_pins]\n\t\t\t\t}\n\t\t\t\tif {[llength $intf_nets]} {\n\t\t\t\t\tset connected_pin [::hsi::get_intf_pins -of_objects $intf_nets -filter {TYPE==SLAVE || TYPE==TARGET}]\n\t\t\t\t}\n\t\t\t\tset phyaddr_suffix \"\"\n\t\t\t\tif {[llength $connected_pin]} {\n\t\t\t\t\tset phyaddr_suffix [string trim $connected_pin \"mdio_pcs_pma\"]\n\t\t\t\t}\n\t\t\t\tset phyaddr \"phyaddr\"\n\t\t\t\tif {[llength $phyaddr_suffix]} {\n\t\t\t\t\tappend phyaddr \"_$phyaddr_suffix\"\n\t\t\t\t}\n\t\t\t\tset pin [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $connected_ip] $phyaddr]]\n\t\t\t\tif {[llength $pin]} {\n\t\t\t\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t}\n\t\t\t\tif {[llength $sink_periph]} {\n\t\t\t\t\tset val [get_property CONFIG.CONST_VAL $sink_periph]\n\t\t\t\t\tset inhex [format %x $val]\n\t\t\t\t\tset_drv_prop $drv_handle phy-handle \"phy$inhex\" reference\n\t\t\t\t\tset pcspma_phy_node [add_or_get_dt_node -l phy$inhex -n phy -u $inhex -p $node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${pcspma_phy_node}\" \"reg\" $val int\n\t\t\t\t\tset phy_type [get_property CONFIG.Standard $connected_ip]\n\t\t\t\t\tset is_sgmii [get_property CONFIG.c_is_sgmii $connected_ip]\n\t\t\t\t\tif {$phy_type == \"1000BASEX\"} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${pcspma_phy_node}\" \"xlnx,phy-type\" 0x5 int\n\t\t\t\t\t} elseif { $is_sgmii == \"true\"} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${pcspma_phy_node}\" \"xlnx,phy-type\" 0x4 int\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"unsupported phytype:$phy_type\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $node \"&gem2\"]} {\n\t\t\tset connected_ip [hsi::utils::get_connected_stream_ip $zynq_periph \"MDIO_ENET2\"]\n\t\t\tif {[llength $connected_ip]} {\n\t\t\t\tset ip_name [get_property IP_NAME $connected_ip]\n\t\t\t}\n\t\t\tif {[llength $ip_name] && [string match -nocase $ip_name \"gig_ethernet_pcs_pma\"]} {\n\t\t\t\tset intf_pins [::hsi::get_intf_pins -of_objects [get_cells $zynq_periph] \"MDIO_ENET2\"]\n\t\t\t\tset connected_pin \"\"\n\t\t\t\tset intf_nets \"\"\n\t\t\t\tif {[llength $intf_pins]} {\n\t\t\t\t\tset intf_nets [::hsi::get_intf_nets -of_objects $intf_pins]\n\t\t\t\t}\n\t\t\t\tif {[llength $intf_nets]} {\n\t\t\t\t\tset connected_pin [::hsi::get_intf_pins -of_objects $intf_nets -filter {TYPE==SLAVE || TYPE==TARGET}]\n\t\t\t\t}\n\t\t\t\tset phyaddr_suffix \"\"\n\t\t\t\tif {[llength $connected_pin]} {\n\t\t\t\t\tset phyaddr_suffix [string trim $connected_pin \"mdio_pcs_pma\"]\n\t\t\t\t}\n\t\t\t\tset phyaddr \"phyaddr\"\n\t\t\t\tif {[llength $phyaddr_suffix]} {\n\t\t\t\t\tappend phyaddr \"_$phyaddr_suffix\"\n\t\t\t\t}\n\t\t\t\tset pin [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $connected_ip] $phyaddr]]\n\t\t\t\tif {[llength $pin]} {\n\t\t\t\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t}\n\t\t\t\tif {[llength $sink_periph]} {\n\t\t\t\t\tset val [get_property CONFIG.CONST_VAL $sink_periph]\n\t\t\t\t\tset inhex [format %x $val]\n\t\t\t\t\tset_drv_prop $drv_handle phy-handle \"phy$inhex\" reference\n\t\t\t\t\tset pcspma_phy_node [add_or_get_dt_node -l phy$inhex -n phy -u $inhex -p $node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${pcspma_phy_node}\" \"reg\" $val int\n\t\t\t\t\tset phy_type [get_property CONFIG.Standard $connected_ip]\n\t\t\t\t\tset is_sgmii [get_property CONFIG.c_is_sgmii $connected_ip]\n\t\t\t\t\tif {$phy_type == \"1000BASEX\"} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${pcspma_phy_node}\" \"xlnx,phy-type\" 0x5 int\n\t\t\t\t\t} elseif { $is_sgmii == \"true\"} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${pcspma_phy_node}\" \"xlnx,phy-type\" 0x4 int\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"unsupported phytype:$phy_type\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $node \"&gem3\"]} {\n\t\t\tset connected_ip [hsi::utils::get_connected_stream_ip $zynq_periph \"MDIO_ENET3\"]\n\t\t\tif {[llength $connected_ip]} {\n\t\t\t\tset ip_name [get_property IP_NAME $connected_ip]\n\t\t\t}\n\t\t\tif {[llength $ip_name] && [string match -nocase $ip_name \"gig_ethernet_pcs_pma\"]} {\n\t\t\t\tset intf_pins [::hsi::get_intf_pins -of_objects [get_cells $zynq_periph] \"MDIO_ENET3\"]\n\t\t\t\tset connected_pin \"\"\n\t\t\t\tset intf_nets \"\"\n\t\t\t\tif {[llength $intf_pins]} {\n\t\t\t\t\tset intf_nets [::hsi::get_intf_nets -of_objects $intf_pins]\n\t\t\t\t}\n\t\t\t\tif {[llength $intf_nets]} {\n\t\t\t\t\tset connected_pin [::hsi::get_intf_pins -of_objects $intf_nets -filter {TYPE==SLAVE || TYPE==TARGET}]\n\t\t\t\t}\n\t\t\t\tset phyaddr_suffix \"\"\n\t\t\t\tif {[llength $connected_pin]} {\n\t\t\t\t\tset phyaddr_suffix [string trim $connected_pin \"mdio_pcs_pma\"]\n\t\t\t\t}\n\t\t\t\tset phyaddr \"phyaddr\"\n\t\t\t\tif {[llength $phyaddr_suffix]} {\n\t\t\t\t\tappend phyaddr \"_$phyaddr_suffix\"\n\t\t\t\t}\n\t\t\t\tset pin [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $connected_ip] $phyaddr]]\n\t\t\t\tif {[llength $pin]} {\n\t\t\t\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t}\n\t\t\t\tif {[llength $sink_periph]} {\n\t\t\t\t\tset val [get_property CONFIG.CONST_VAL $sink_periph]\n\t\t\t\t\tset inhex [format %x $val]\n\t\t\t\t\tset_drv_prop $drv_handle phy-handle \"phy$inhex\" reference\n\t\t\t\t\tset pcspma_phy_node [add_or_get_dt_node -l phy$inhex -n phy -u $inhex -p $node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${pcspma_phy_node}\" \"reg\" $val int\n\t\t\t\t\tset phy_type [get_property CONFIG.Standard $connected_ip]\n\t\t\t\t\tset is_sgmii [get_property CONFIG.c_is_sgmii $connected_ip]\n\t\t\t\t\tif {$phy_type == \"1000BASEX\"} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${pcspma_phy_node}\" \"xlnx,phy-type\" 0x5 int\n\t\t\t\t\t} elseif { $is_sgmii == \"true\"} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${pcspma_phy_node}\" \"xlnx,phy-type\" 0x4 int\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"unsupported phytype:$phy_type\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tset is_pcspma [get_cells -hier -filter {IP_NAME == gig_ethernet_pcs_pma}]\n\tif {![string_is_empty ${is_pcspma}] && $phymode == 2} {\n\t\t# if eth mode is sgmii and no external pcs/pma found\n\t\thsi::utils::add_new_property $drv_handle \"is-internal-pcspma\" boolean \"\"\n\t}\n}\n\nproc gen_mdio1_node {drv_handle parent_node} {\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tif {[is_pl_ip $drv_handle] && $remove_pl} {\n\t\treturn\n\t}\n set default_dts [get_property CONFIG.pcw_dts [get_os]]\n\tset mdio_node [add_or_get_dt_node -l ${drv_handle}_mdio -n mdio -d $default_dts -p $parent_node]\n\thsi::utils::add_new_dts_param \"${mdio_node}\" \"#address-cells\" 1 int \"\"\n\thsi::utils::add_new_dts_param \"${mdio_node}\" \"#size-cells\" 0 int \"\"\n\treturn $mdio_node\n}\n" }, { "path": "ernic/data/ernic.mdd", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver ernic\n\n OPTION supported_peripherals = (ernic);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = ernic;\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "ernic/data/ernic.tcl", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset proc_type [get_sw_proc_prop IP_NAME]\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset ernic_ip [get_cells -hier $drv_handle]\n\tset ip_name [get_property IP_NAME $ernic_ip]\n\n\tset ethip [get_connected_ip $drv_handle \"rx_pkt_hndler_s_axis\"]\n\tif {[llength $ethip]} {\n\t\tset_drv_property $drv_handle eth-handle \"$ethip\" reference\n\t}\n}\n\nproc get_connected_ip {drv_handle dma_pin} {\n\tglobal connected_ip\n\tset intf [::hsi::get_intf_pins -of_objects [get_cells -hier $drv_handle] $dma_pin]\n\tset valid_eth_list \"l_ethernet\"\n\tif {[string_is_empty ${intf}]} {\n\t\treturn 0\n\t}\n\tset connected_ip [::hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] $intf]\n\tif {[string_is_empty ${connected_ip}]} {\n\t\tdtg_warning \"$drv_handle connected ip is NULL for the pin $intf\"\n\t\treturn 0\n\t}\n\tset iptype [get_property IP_NAME [get_cells -hier $connected_ip]]\n\tif {[string match -nocase $iptype \"axis_data_fifo\"] } {\n\t\tset dma_pin \"M_AXIS\"\n\t\tget_connected_ip $connected_ip $dma_pin\n\t} elseif {[lsearch -nocase $valid_eth_list $iptype] >= 0 } {\n\t\treturn $connected_ip\n\t} else {\n\t\tset dma_pin \"S_AXIS\"\n\t\tget_connected_ip $connected_ip $dma_pin\n\t}\n}\n" }, { "path": "framebuf_rd/data/framebuf_rd.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver framebuf_rd\n\n OPTION supported_peripherals = (v_frmbuf_rd);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = framebuf_rd;\n\nEND driver\n" }, { "path": "framebuf_rd/data/framebuf_rd.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,axi-frmbuf-rd-v2.2\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset ip [get_cells -hier $drv_handle]\n\tset_drv_conf_prop $drv_handle C_S_AXI_CTRL_ADDR_WIDTH xlnx,s-axi-ctrl-addr-width\n\tset_drv_conf_prop $drv_handle C_S_AXI_CTRL_DATA_WIDTH xlnx,s-axi-ctrl-data-width\n\tset vid_formats \"\"\n\tset has_bgr8 [get_property CONFIG.HAS_BGR8 [get_cells -hier $drv_handle]]\n\tif {$has_bgr8 == 1} {\n\t\tappend vid_formats \" \" \"rgb888\"\n\t}\n\tset has_rgbx8 [get_property CONFIG.HAS_RGBX8 [get_cells -hier $drv_handle]]\n\tif {$has_rgbx8 == 1} {\n\t\tappend vid_formats \" \" \"xbgr8888\"\n\t}\n\tset has_bgra8 [get_property CONFIG.HAS_BGRA8 [get_cells -hier $drv_handle]]\n\tif {$has_bgra8 == 1} {\n\t\tappend vid_formats \" \" \"argb8888\"\n\t}\n\tset has_bgrx8 [get_property CONFIG.HAS_BGRX8 [get_cells -hier $drv_handle]]\n\tif {$has_bgrx8 == 1} {\n\t\tappend vid_formats \" \" \"xrgb8888\"\n\t}\n\tset has_rgb8 [get_property CONFIG.HAS_RGB8 [get_cells -hier $drv_handle]]\n\tif {$has_rgb8 == 1} {\n\t\tappend vid_formats \" \" \"bgr888\"\n\t}\n\tset has_rgba8 [get_property CONFIG.HAS_RGBA8 [get_cells -hier $drv_handle]]\n\tif {$has_rgba8 == 1} {\n\t\tappend vid_formats \" \" \"abgr8888\"\n\t}\n\tset has_bgrx10 [get_property CONFIG.HAS_RGBX10 [get_cells -hier $drv_handle]]\n\tif {$has_bgrx10 == 1} {\n\t\tappend vid_formats \" \" \"xbgr2101010\"\n\t}\n\tset has_uyvy8 [get_property CONFIG.HAS_UYVY8 [get_cells -hier $drv_handle]]\n\tif {$has_uyvy8 == 1} {\n\t\tappend vid_formats \" \" \"uyvy\"\n\t}\n\tset has_y8 [get_property CONFIG.HAS_Y8 [get_cells -hier $drv_handle]]\n\tif {$has_y8 == 1} {\n\t\tappend vid_formats \" \" \"y8\"\n\t}\n\tset has_y10 [get_property CONFIG.HAS_Y10 [get_cells -hier $drv_handle]]\n\tif {$has_y10 == 1} {\n\t\tappend vid_formats \" \" \"y10\"\n\t}\n\tset has_yuv8 [get_property CONFIG.HAS_YUV8 [get_cells -hier $drv_handle]]\n\tif {$has_yuv8 == 1} {\n\t\tappend vid_formats \" \" \"vuy888\"\n\t}\n\tset has_yuvx8 [get_property CONFIG.HAS_YUVX8 [get_cells -hier $drv_handle]]\n\tif {$has_yuvx8 == 1} {\n\t\tappend vid_formats \" \" \"xvuy8888\"\n\t}\n\tset has_yuvx10 [get_property CONFIG.HAS_YUVX10 [get_cells -hier $drv_handle]]\n\tif {$has_yuvx10 == 1} {\n\t\tappend vid_formats \" \" \"yuvx2101010\"\n\t}\n\tset has_yuyv8 [get_property CONFIG.HAS_YUYV8 [get_cells -hier $drv_handle]]\n\tif {$has_yuyv8 == 1} {\n\t\tappend vid_formats \" \" \"yuyv\"\n\t}\n\tset has_y_uv8_420 [get_property CONFIG.HAS_Y_UV8_420 [get_cells -hier $drv_handle]]\n\tif {$has_y_uv8_420 == 1} {\n\t\tappend vid_formats \" \" \"nv12\"\n\t}\n\tset has_y_uv8 [get_property CONFIG.HAS_Y_UV8 [get_cells -hier $drv_handle]]\n\tif {$has_y_uv8 == 1} {\n\t\tappend vid_formats \" \" \"nv16\"\n\t}\n\tset has_y_uv10 [get_property CONFIG.HAS_Y_UV10 [get_cells -hier $drv_handle]]\n\tif {$has_y_uv10 == 1} {\n\t\tappend vid_formats \" \" \"xv20\"\n\t}\n\tset has_y_uv10_420 [get_property CONFIG.HAS_Y_UV10_420 [get_cells -hier $drv_handle]]\n\tif {$has_y_uv10_420 == 1} {\n\t\tappend vid_formats \" \" \"xv15\"\n\t}\n\tset has_y_u_v8 [get_property CONFIG.HAS_Y_U_V8 [get_cells -hier $drv_handle]]\n\tif {$has_y_u_v8 == 1} {\n\t\tappend vid_formats \" \" \"y_u_v8\"\n\t}\n\tif {![string match $vid_formats \"\"]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,vid-formats\" $vid_formats stringlist\n\t}\n\tset samples_per_clk [get_property CONFIG.SAMPLES_PER_CLOCK [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,pixels-per-clock\" $samples_per_clk int\n\tset dma_align [expr $samples_per_clk * 8]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,dma-align\" $dma_align int\n\tset has_interlaced [get_property CONFIG.HAS_INTERLACED [get_cells -hier $drv_handle]]\n\tif {$has_interlaced == 1} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,fid\" \"\" boolean\n\t}\n\tset dma_addr_width [get_property CONFIG.AXIMM_ADDR_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,dma-addr-width\" $dma_addr_width int\n\thsi::utils::add_new_dts_param \"$node\" \"#dma-cells\" 1 int\n\tset max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,video-width\" $max_data_width int\n\tset max_rows [get_property CONFIG.MAX_ROWS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,max-height\" $max_rows int\n\tset max_cols [get_property CONFIG.MAX_COLS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,max-width\" $max_cols int\n\tgen_gpio_reset $drv_handle $node\n}\n\nproc gen_gpio_reset {drv_handle node} {\n\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] \"ap_rst_n\"]]\n\tforeach pin $pins {\n\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tif {[llength $sink_periph]} {\n\t\t\tset sink_ip [get_property IP_NAME $sink_periph]\n\t\t\tif {[string match -nocase $sink_ip \"xlslice\"]} {\n\t\t\t\tset gpio [get_property CONFIG.DIN_FROM $sink_periph]\n\t\t\t\tset pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph \"Din\"]]]\n\t\t\t\tforeach pin $pins {\n\t\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t\tif {[llength $periph]} {\n\t\t\t\t\t\tset ip [get_property IP_NAME $periph]\n\t\t\t\t\t\tset proc_type [get_sw_proc_prop IP_NAME]\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psv_cortexa72\"] } {\n\t\t\t\t\t\t\tif { $ip in { \"versal_cips\" \"ps_wizard\" }} {\n\t\t\t\t\t\t\t\t# As versal has only bank0 for MIOs\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 26]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio0 $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n\t\t\t\t\t\t\tif {[string match -nocase $ip \"zynq_ultra_ps_e\"]} {\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 78]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $ip \"axi_gpio\"]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"$periph $gpio 1\" reference\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"$drv_handle peripheral is NULL for the $pin $periph\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle peripheral is NULL for the $pin $sink_periph\"\n\t\t}\n\t}\n}\n" }, { "path": "framebuf_wr/data/framebuf_wr.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver framebuf_wr\n\n OPTION supported_peripherals = (v_frmbuf_wr);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = framebuf_wr;\n\nEND driver\n" }, { "path": "framebuf_wr/data/framebuf_wr.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,axi-frmbuf-wr-v2.2\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset ip [get_cells -hier $drv_handle]\n\tset_drv_conf_prop $drv_handle C_S_AXI_CTRL_ADDR_WIDTH xlnx,s-axi-ctrl-addr-width\n\tset_drv_conf_prop $drv_handle C_S_AXI_CTRL_DATA_WIDTH xlnx,s-axi-ctrl-data-width\n\tset vid_formats \"\"\n\tset has_bgr8 [get_property CONFIG.HAS_BGR8 [get_cells -hier $drv_handle]]\n\tif {$has_bgr8 == 1} {\n\t\tappend vid_formats \" \" \"rgb888\"\n\t}\n\tset has_rgb8 [get_property CONFIG.HAS_RGB8 [get_cells -hier $drv_handle]]\n\tif {$has_rgb8 == 1} {\n\t\tappend vid_formats \" \" \"bgr888\"\n\t}\n\tset has_rgbx8 [get_property CONFIG.HAS_RGBX8 [get_cells -hier $drv_handle]]\n\tif {$has_rgbx8 == 1} {\n\t\tappend vid_formats \" \" \"xbgr8888\"\n\t}\n\tset has_bgrx8 [get_property CONFIG.HAS_BGRX8 [get_cells -hier $drv_handle]]\n\tif {$has_bgrx8 == 1} {\n\t\tappend vid_formats \" \" \"xrgb8888\"\n\t}\n\tset has_bgrx10 [get_property CONFIG.HAS_RGBX10 [get_cells -hier $drv_handle]]\n\tif {$has_bgrx10 == 1} {\n\t\tappend vid_formats \" \" \"xbgr2101010\"\n\t}\n\tset has_uyvy8 [get_property CONFIG.HAS_UYVY8 [get_cells -hier $drv_handle]]\n\tif {$has_uyvy8 == 1} {\n\t\tappend vid_formats \" \" \"uyvy\"\n\t}\n\tset has_y8 [get_property CONFIG.HAS_Y8 [get_cells -hier $drv_handle]]\n\tif {$has_y8 == 1} {\n\t\tappend vid_formats \" \" \"y8\"\n\t}\n\tset has_y10 [get_property CONFIG.HAS_Y10 [get_cells -hier $drv_handle]]\n\tif {$has_y10 == 1} {\n\t\tappend vid_formats \" \" \"y10\"\n\t}\n\tset has_yuv8 [get_property CONFIG.HAS_YUV8 [get_cells -hier $drv_handle]]\n\tif {$has_yuv8 == 1} {\n\t\tappend vid_formats \" \" \"vuy888\"\n\t}\n\tset has_yuvx8 [get_property CONFIG.HAS_YUVX8 [get_cells -hier $drv_handle]]\n\tif {$has_yuvx8 == 1} {\n\t\tappend vid_formats \" \" \"xvuy8888\"\n\t}\n\tset has_yuvx10 [get_property CONFIG.HAS_YUVX10 [get_cells -hier $drv_handle]]\n\tif {$has_yuvx10 == 1} {\n\t\tappend vid_formats \" \" \"yuvx2101010\"\n\t}\n\tset has_yuyv8 [get_property CONFIG.HAS_YUYV8 [get_cells -hier $drv_handle]]\n\tif {$has_yuyv8 == 1} {\n\t\tappend vid_formats \" \" \"yuyv\"\n\t}\n\tset has_y_uv8_420 [get_property CONFIG.HAS_Y_UV8_420 [get_cells -hier $drv_handle]]\n\tif {$has_y_uv8_420 == 1} {\n\t\tappend vid_formats \" \" \"nv12\"\n\t}\n\tset has_y_uv8 [get_property CONFIG.HAS_Y_UV8 [get_cells -hier $drv_handle]]\n\tif {$has_y_uv8 == 1} {\n\t\tappend vid_formats \" \" \"nv16\"\n\t}\n\tset has_y_uv10 [get_property CONFIG.HAS_Y_UV10 [get_cells -hier $drv_handle]]\n\tif {$has_y_uv10 == 1} {\n\t\tappend vid_formats \" \" \"xv20\"\n\t}\n\tset has_y_uv10_420 [get_property CONFIG.HAS_Y_UV10_420 [get_cells -hier $drv_handle]]\n\tif {$has_y_uv10_420 == 1} {\n\t\tappend vid_formats \" \" \"xv15\"\n\t}\n\tset has_y_u_v8 [get_property CONFIG.HAS_Y_U_V8 [get_cells -hier $drv_handle]]\n\tif {$has_y_u_v8 == 1} {\n\t\tappend vid_formats \" \" \"y_u_v8\"\n\t}\n\tif {![string match $vid_formats \"\"]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,vid-formats\" $vid_formats stringlist\n\t}\n\tset samples_per_clk [get_property CONFIG.SAMPLES_PER_CLOCK [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,pixels-per-clock\" $samples_per_clk int\n\tset dma_align [expr $samples_per_clk * 8]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,dma-align\" $dma_align int\n\tset has_interlaced [get_property CONFIG.HAS_INTERLACED [get_cells -hier $drv_handle]]\n\tif {$has_interlaced == 1} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,fid\" \"\" boolean\n\t}\n\tset dma_addr_width [get_property CONFIG.AXIMM_ADDR_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,dma-addr-width\" $dma_addr_width int\n\thsi::utils::add_new_dts_param \"$node\" \"#dma-cells\" 1 int\n\tset max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,video-width\" $max_data_width int\n\tset max_rows [get_property CONFIG.MAX_ROWS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,max-height\" $max_rows int\n\tset max_cols [get_property CONFIG.MAX_COLS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,max-width\" $max_cols int\n\tgen_gpio_reset $drv_handle $node\n\n\tset frmbuf_inips [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video\"]\n\tforeach inip $frmbuf_inips {\n\t\tif {[string match -nocase [get_property IP_NAME $inip] \"v_mix\"] } {\n\t\t\tset ports_node [add_or_get_dt_node -n \"ports\" -l frmbuf_wr_ports$drv_handle -p $node]\n\t\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\t\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\t\t\tset port0_node [add_or_get_dt_node -n \"port\" -l frmbuf_wr$drv_handle -u 0 -p $ports_node]\n\t\t\thsi::utils::add_new_dts_param \"$port0_node\" \"reg\" 0 int\n\t\t\tset frmbuf_crtc [add_or_get_dt_node -n \"endpoint\" -l v_frmbuf_wr$drv_handle -p $port0_node]\n\t\t\thsi::utils::add_new_dts_param \"$frmbuf_crtc\" \"remote-endpoint\" \"mixer_out$inip\" reference\n\t\t}\n\t}\n}\n\nproc gen_gpio_reset {drv_handle node} {\n\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] \"ap_rst_n\"]]\n\tforeach pin $pins {\n\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tif {[llength $sink_periph]} {\n\t\t\tset sink_ip [get_property IP_NAME $sink_periph]\n\t\t\tif {[string match -nocase $sink_ip \"xlslice\"]} {\n\t\t\t\tset gpio [get_property CONFIG.DIN_FROM $sink_periph]\n\t\t\t\tset pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph \"Din\"]]]\n\t\t\t\tforeach pin $pins {\n\t\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t\tif {[llength $periph]} {\n\t\t\t\t\t\tset ip [get_property IP_NAME $periph]\n\t\t\t\t\t\tset proc_type [get_sw_proc_prop IP_NAME]\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psv_cortexa72\"] } {\n\t\t\t\t\t\t\tif { $ip in { \"versal_cips\" \"ps_wizard\" }} {\n\t\t\t\t\t\t\t\t# As versal has only bank0 for MIOs\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 26]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio0 $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n\t\t\t\t\t\t\tif {[string match -nocase $ip \"zynq_ultra_ps_e\"]} {\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 78]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $ip \"axi_gpio\"]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"$periph $gpio 1\" reference\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"$drv_handle peripheral is NULL for the $pin $periph\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle peripheral is NULL for the $pin $sink_periph\"\n\t\t}\n\t}\n}\n" }, { "path": "gamma_lut/data/gamma_lut.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver gamma_lut\n\n OPTION supported_peripherals = (v_gamma_lut);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = gamma_lut;\n\nEND driver\n" }, { "path": "gamma_lut/data/gamma_lut.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,v-gamma-lut\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset gamma_ip [get_cells -hier $drv_handle]\n\tset s_axi_ctrl_addr_width [get_property CONFIG.C_S_AXI_CTRL_ADDR_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,s-axi-ctrl-addr-width\" $s_axi_ctrl_addr_width int\n\tset s_axi_ctrl_data_width [get_property CONFIG.C_S_AXI_CTRL_DATA_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,s-axi-ctrl-data-width\" $s_axi_ctrl_data_width int\n\tset max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]]\n\tset max_rows [get_property CONFIG.MAX_ROWS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,max-height\" $max_rows int\n\tset max_cols [get_property CONFIG.MAX_COLS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,max-width\" $max_cols int\n\n\tset ports_node [add_or_get_dt_node -n \"ports\" -l gamma_ports$drv_handle -p $node]\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\tset port1_node [add_or_get_dt_node -n \"port\" -l gamma_port1$drv_handle -u 1 -p $ports_node]\n\thsi::utils::add_new_dts_param \"$port1_node\" \"reg\" 1 int\n\thsi::utils::add_new_dts_param \"$port1_node\" \"xlnx,video-width\" $max_data_width int\n\n\tset gammaoutip [get_connected_stream_ip [get_cells -hier $drv_handle] \"m_axis_video\"]\n\tforeach outip $gammaoutip {\n\t\tif {[llength $outip]} {\n\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $outip] -filter { TYPE==MASTER || TYPE == INITIATOR}]\n\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $outip]\n\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\t\tset gammanode [add_or_get_dt_node -n \"endpoint\" -l gamma_out$drv_handle -p $port1_node]\n\t\t\t\thsi::utils::add_new_dts_param \"$gammanode\" \"remote-endpoint\" $outip$drv_handle reference\n\t\t\t\tgen_endpoint $drv_handle \"gamma_out$drv_handle\"\n\t\t\t\tgen_remoteendpoint $drv_handle \"$outip$drv_handle\"\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $outip] \"v_frmbuf_wr\"]} {\n\t\t\t\t\tgen_frmbuf_wr_node $outip $drv_handle\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $outip] \"system_ila\"]} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\tset connectip [get_connect_ip $outip $master_intf]\n\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\tset gammanode [add_or_get_dt_node -n \"endpoint\" -l gamma_out$drv_handle -p $port1_node]\n\t\t\t\t\tgen_endpoint $drv_handle \"gamma_out$drv_handle\"\n\t\t\t\t\thsi::utils::add_new_dts_param \"$gammanode\" \"remote-endpoint\" $connectip$drv_handle reference\n\t\t\t\t\tgen_remoteendpoint $drv_handle \"$connectip$drv_handle\"\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"v_frmbuf_wr\"]} {\n\t\t\t\t\t\tgen_frmbuf_wr_node $connectip $drv_handle\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle pin m_axis_video is not connected..check your design\"\n\t\t}\n\t}\n\tgen_gpio_reset $drv_handle $node\n}\n\nproc gen_frmbuf_wr_node {outip drv_handle} {\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n set vcap [add_or_get_dt_node -n \"vcap_$drv_handle\" -p $bus_node]\n hsi::utils::add_new_dts_param $vcap \"compatible\" \"xlnx,video\" string\n hsi::utils::add_new_dts_param $vcap \"dmas\" \"$outip 0\" reference\n hsi::utils::add_new_dts_param $vcap \"dma-names\" \"port0\" string\n set vcap_ports_node [add_or_get_dt_node -n \"ports\" -l vcap_ports$drv_handle -p $vcap]\n hsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#address-cells\" 1 int\n hsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#size-cells\" 0 int\n set vcap_port_node [add_or_get_dt_node -n \"port\" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node]\n hsi::utils::add_new_dts_param \"$vcap_port_node\" \"reg\" 0 int\n hsi::utils::add_new_dts_param \"$vcap_port_node\" \"direction\" input string\n set vcap_in_node [add_or_get_dt_node -n \"endpoint\" -l $outip$drv_handle -p $vcap_port_node]\n hsi::utils::add_new_dts_param \"$vcap_in_node\" \"remote-endpoint\" gamma_out$drv_handle reference\n}\n\nproc gen_gpio_reset {drv_handle node} {\n\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] \"ap_rst_n\"]]\n\tset proc_type [get_sw_proc_prop IP_NAME]\n\tforeach pin $pins {\n\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tif {[llength $sink_periph]} {\n\t\t\tset sink_ip [get_property IP_NAME $sink_periph]\n\t\t\tif {[string match -nocase $sink_ip \"xlslice\"]} {\n\t\t\t\tset gpio [get_property CONFIG.DIN_FROM $sink_periph]\n\t\t\t\tset pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph \"Din\"]]]\n\t\t\t\tforeach pin $pins {\n\t\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t\tif {[llength $periph]} {\n\t\t\t\t\t\tset ip [get_property IP_NAME $periph]\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psv_cortexa72\"] } {\n\t\t\t\t\t\t\tif { $ip in { \"versal_cips\" \"ps_wizard\" }} {\n\t\t\t\t\t\t\t\t# As versal has only bank0 for MIOs\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 26]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio0 $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n\t\t\t\t\t\t\tif {[string match -nocase $ip \"zynq_ultra_ps_e\"]} {\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 78]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $ip \"axi_gpio\"]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"$periph $gpio 1\" reference\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"$drv_handle: peripheral is NULL for the $pin $periph\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle: peripheral is NULL for the $pin $sink_periph\"\n\t\t}\n\t}\n}\n" }, { "path": "generic/data/generic.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver generic\n\n OPTION NAME = generic;\n OPTION supported_os_types = (DTS);\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "generic/data/generic.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\n\tset hsi_version [get_hsi_version]\n\tset ver [split $hsi_version \".\"]\n\tset value [lindex $ver 0]\n\tif {$value >= 2018} {\n\t\tset generic_node [gen_peripheral_nodes $drv_handle]\n\t\tset last [string last \"@\" $generic_node]\n\t\tif {$last != -1} {\n\t\t\thsi::utils::add_new_dts_param \"${generic_node}\" \"/* This is a place holder node for a custom IP, user may need to update the entries */\" \"\" comment\n\t\t}\n\t}\n}\n" }, { "path": "globaltimerps/data/globaltimerps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver globaltimerps\n OPTION supported_peripherals = (ps7_globaltimer);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = globaltimerps;\nEND driver\n" }, { "path": "globaltimerps/data/globaltimerps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n" }, { "path": "gpiops/data/gpiops.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver gpiops\n\n OPTION supported_peripherals = (ps7_gpio psu_gpio psv_gpio);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = gpiops;\n DTGPARAM name = emio-gpio-width, type = int;\n DTGPARAM name = gpio-mask-high, type = hexint;\n DTGPARAM name = gpio-mask-low, type = hexint;\n\nEND driver\n" }, { "path": "gpiops/data/gpiops.tcl", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\n\nproc generate {drv_handle} {\n set count 32\n set ip [get_cells -hier $drv_handle]\n set_property CONFIG.emio-gpio-width \"[hsi::utils::get_ip_param_value $ip C_EMIO_GPIO_WIDTH]\" $drv_handle\n set gpiomask [hsi::utils::get_ip_param_value $ip \"C_MIO_GPIO_MASK\"]\n if {[llength $gpiomask]} {\n set mask [expr {$gpiomask & 0xffffffff}]\n set_property CONFIG.gpio-mask-low \"$mask\" $drv_handle\n set mask [expr {$gpiomask>>$count}]\n set mask [expr {$mask & 0xffffffff}]\n set_property CONFIG.gpio-mask-high \"$mask\" $drv_handle\n }\n}\n\n\n" }, { "path": "hdmi_ctrl/data/hdmi_ctrl.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver hdmi_ctrl\n\n OPTION supported_peripherals = (hdmi_acr_ctrl);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = hdmi_ctrl;\n\nEND driver\n" }, { "path": "hdmi_ctrl/data/hdmi_ctrl.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,hdmi_act_ctrl\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n}\n" }, { "path": "hdmi_gt_ctrl/data/hdmi_gt_ctrl.mdd", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver hdmi_gt_ctrl\n\n OPTION supported_peripherals = (hdmi_gt_controller);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = hdmi_gt_ctrl;\n\nEND driver\n" }, { "path": "hdmi_gt_ctrl/data/hdmi_gt_ctrl.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset err_irq_en [get_property CONFIG.C_Err_Irq_En [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,err-irq-en\" $err_irq_en int\n\tset tx_frl_refclk_sel [get_property CONFIG.C_TX_FRL_REFCLK_SEL [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,tx-frl-refclk-sel\" $tx_frl_refclk_sel int\n\tset rx_frl_refclk_sel [get_property CONFIG.C_RX_FRL_REFCLK_SEL [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,rx-frl-refclk-sel\" $rx_frl_refclk_sel int\n\tset input_pixels_per_clock [get_property CONFIG.C_INPUT_PIXELS_PER_CLOCK [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,input-pixels-per-clock\" $input_pixels_per_clock int\n\tset nidru [get_property CONFIG.C_NIDRU [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,nidru\" $nidru int\n\tset use_gt_ch4_hdmi [get_property CONFIG.C_Use_GT_CH4_HDMI [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,use-gt-ch4-hdmi\" $use_gt_ch4_hdmi int\n\tset nidru_refclk_sel [get_property CONFIG.C_NIDRU_REFCLK_SEL [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,nidru-refclk-sel\" $nidru_refclk_sel int\n\tset Rx_No_Of_Channels [get_property CONFIG.C_Rx_No_Of_Channels [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,rx-no-of-channels\" $Rx_No_Of_Channels int\n\tset rx_pll_selection [get_property CONFIG.C_RX_PLL_SELECTION [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,rx-pll-selection\" $rx_pll_selection int\n\tset rx_protocol [get_property CONFIG.C_Rx_Protocol [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,rx-protocol\" $rx_protocol int\n\tset rx_refclk_sel [get_property CONFIG.C_RX_REFCLK_SEL [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,rx-refclk-sel\" $rx_refclk_sel int\n\tset tx_pll_selection [get_property CONFIG.C_TX_PLL_SELECTION [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,tx-pll-selection\" $tx_pll_selection int\n\tset tx_protocol [get_property CONFIG.C_Tx_Protocol [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,tx-protocol\" $tx_protocol int\n\tset tx_refclk_sel [get_property CONFIG.C_TX_REFCLK_SEL [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,tx-refclk-sel\" $tx_refclk_sel int\n\tset tx_no_of_channels [get_property CONFIG.C_Tx_No_Of_Channels [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,tx-no-of-channels\" $tx_no_of_channels int\n\tset tx_buffer_bypass [get_property CONFIG.Tx_Buffer_Bypass [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,tx-buffer-bypass\" $tx_buffer_bypass int\n\tset transceiver_width [get_property CONFIG.Transceiver_Width [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,transceiver-width\" $transceiver_width int\n\tset hdmi_fast_switch [get_property CONFIG.C_Hdmi_Fast_Switch [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,hdmi-fast-switch\" $hdmi_fast_switch int\n\tfor {set ch 0} {$ch < $tx_no_of_channels} {incr ch} {\n\t\tset txpinname \"tx_axi4s_ch$ch\"\n\t\tset channelip [get_connected_stream_ip [get_cells -hier $drv_handle] $txpinname]\n\t\tif {[llength $channelip] && [llength [hsi::utils::get_ip_mem_ranges $channelip]]} {\n\t\t\tset phy_node [add_or_get_dt_node -n \"${txpinname}${channelip}\" -l ${drv_handle}txphy_lane${ch} -p $node]\n\t\t\thsi::utils::add_new_dts_param \"$phy_node\" \"#phy-cells\" 4 int\n\t\t}\n\t}\n\tset transceiver [get_property CONFIG.Transceiver [get_cells -hier $drv_handle]]\n\tswitch $transceiver {\n\t\t\t\"GTXE2\" {\n\t\t\t hsi::utils::add_new_dts_param \"${node}\" \"xlnx,transceiver-type\" 1 int\n\t\t\t}\n\t\t\t\"GTHE2\" {\n\t\t\t hsi::utils::add_new_dts_param \"${node}\" \"xlnx,transceiver-type\" 2 int\n\t\t\t}\n\t\t\t\"GTPE2\" {\n\t\t\t hsi::utils::add_new_dts_param \"${node}\" \"xlnx,transceiver-type\" 3 int\n\t\t\t}\n\t\t\t\"GTHE3\" {\n\t\t\t hsi::utils::add_new_dts_param \"${node}\" \"xlnx,transceiver-type\" 4 int\n\t\t\t}\n\t\t\t\"GTHE4\" {\n\t\t\t hsi::utils::add_new_dts_param \"${node}\" \"xlnx,transceiver-type\" 5 int\n\t\t\t}\n\t\t\t\"GTYE4\" {\n\t\t\t hsi::utils::add_new_dts_param \"${node}\" \"xlnx,transceiver-type\" 6 int\n\t\t\t}\n\t\t\t\"GTYE5\" {\n\t\t\t hsi::utils::add_new_dts_param \"${node}\" \"xlnx,transceiver-type\" 7 int\n\t\t\t}\n\t}\n\tset gt_direction [get_property CONFIG.C_GT_DIRECTION [get_cells -hier $drv_handle]]\n\tswitch $gt_direction {\n\t\t\t\"SIMPLEX_TX\" {\n\t\t\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,gt-direction\" 1 int\n\t\t\t}\n\t\t\t\"SIMPLEX_RX\" {\n\t\t\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,gt-direction\" 2 int\n\t\t\t}\n\t\t\t\"DUPLEX\" {\n\t\t\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,gt-direction\" 3 int\n\t\t\t}\n\t}\n}\n" }, { "path": "hdmi_rx_ss/data/hdmi_rx_ss.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver hdmi_rx_ss\n\n OPTION supported_peripherals = (v_hdmi_rx_ss v_hdmi_rxss1);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = hdmi_rx_ss;\n\nEND driver\n" }, { "path": "hdmi_rx_ss/data/hdmi_rx_ss.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,v-hdmi-rx-ss-3.1\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset ports_node [add_or_get_dt_node -n \"ports\" -l hdmirx_ports$drv_handle -p $node]\n hsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n hsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n set port_node [add_or_get_dt_node -n \"port\" -l hdmirx_port$drv_handle -u 0 -p $ports_node]\n hsi::utils::add_new_dts_param \"${port_node}\" \"/* Fill the fields xlnx,video-format and xlnx,video-width based on user requirement */\" \"\" comment\n hsi::utils::add_new_dts_param \"$port_node\" \"xlnx,video-format\" 0 int\n hsi::utils::add_new_dts_param \"$port_node\" \"xlnx,video-width\" 10 int\n hsi::utils::add_new_dts_param \"$port_node\" \"reg\" 0 int\n\tset outip [get_connected_stream_ip [get_cells -hier $drv_handle] \"VIDEO_OUT\"]\n\tforeach ip $outip {\n\t\tif {[llength $ip]} {\n\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip]\n\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\tset hdmi_rx_node [add_or_get_dt_node -n \"endpoint\" -l hdmirx_out$drv_handle -p $port_node]\n\t\t\t\tgen_endpoint $drv_handle \"hdmirx_out$drv_handle\"\n\t\t\t\thsi::utils::add_new_dts_param \"$hdmi_rx_node\" \"remote-endpoint\" $ip$drv_handle reference\n\t\t\t\tgen_remoteendpoint $drv_handle $ip$drv_handle\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $ip] \"v_frmbuf_wr\"]} {\n\t\t\t\t\tgen_frmbuf_node $ip $drv_handle\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $ip] \"system_ila\"]} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\tset connectip [get_connect_ip $ip $master_intf]\n\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\tset hdmi_rx_node [add_or_get_dt_node -n \"endpoint\" -l hdmirx_out$drv_handle -p $port_node]\n\t\t\t\t\tgen_endpoint $drv_handle \"hdmirx_out$drv_handle\"\n\t\t\t\t\thsi::utils::add_new_dts_param \"$hdmi_rx_node\" \"remote-endpoint\" $connectip$drv_handle reference\n\t\t\t\t\tgen_remoteendpoint $drv_handle $connectip$drv_handle\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"v_frmbuf_wr\"]} {\n\t\t\t\t\t\tgen_frmbuf_node $connectip $drv_handle\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tset phy_names \"\"\n\tset phys \"\"\n\tset link_data0 [get_connected_stream_ip [get_cells -hier $drv_handle] \"LINK_DATA0_IN\"]\n\tif {[llength $link_data0]} {\n\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $link_data0]\n\t\tif {[llength $ip_mem_handles]} {\n\t\t\tset link_data0_inst $link_data0\n\t\t\tset link_data0 [get_property IP_NAME $link_data0]\n\t\t\tif {[string match -nocase $link_data0 \"vid_phy_controller\"] || [string match -nocase $link_data0 \"hdmi_gt_controller\"]} {\n\t\t\t\tappend phy_names \" \" \"hdmi-phy0\"\n\t\t\t\tappend phys \"${link_data0_inst}rxphy_lane0 0 1 1 0>,\"\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"connected stream of LINK_DATA0_IN is NULL...check the design\"\n\t\t}\n\t}\n\tset link_data1 [get_connected_stream_ip [get_cells -hier $drv_handle] \"LINK_DATA1_IN\"]\n\tif {[llength $link_data1]} {\n\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $link_data1]\n\t\tif {[llength $ip_mem_handles]} {\n\t\t\tset link_data1_inst $link_data1\n\t\t\tset link_data1 [get_property IP_NAME $link_data1]\n\t\t\tif {[string match -nocase $link_data1 \"vid_phy_controller\"] || [string match -nocase $link_data1 \"hdmi_gt_controller\"]} {\n\t\t\t\tappend phy_names \" \" \"hdmi-phy1\"\n\t\t\t\tappend phys \" <&${link_data1_inst}rxphy_lane1 0 1 1 0>,\"\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"Connected stream of LINK_DATA1_IN is NULL...check the design\"\n\t\t}\n\t}\n\tset link_data2 [get_connected_stream_ip [get_cells -hier $drv_handle] \"LINK_DATA2_IN\"]\n\tif {[llength $link_data2]} {\n\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $link_data2]\n\t\tif {[llength $ip_mem_handles]} {\n\t\t\tset link_data2_inst $link_data2\n\t\t\tset link_data2 [get_property IP_NAME $link_data2]\n\t\t\tif {[string match -nocase $link_data2 \"vid_phy_controller\"] || [string match -nocase $link_data2 \"hdmi_gt_controller\"]} {\n\t\t\t\tappend phy_names \" \" \"hdmi-phy2\"\n\t\t\t\tappend phys \" <&${link_data2_inst}rxphy_lane2 0 1 1 0\"\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"Connected stream of LINK_DATA2_IN is NULL...check the design\"\n\t\t}\n\t}\n\tset link_data3 [get_connected_stream_ip [get_cells -hier $drv_handle] \"LINK_DATA3_IN\"]\n\tif {[llength $link_data3]} {\n\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $link_data3]\n\t\tif {[llength $ip_mem_handles]} {\n\t\t\tset link_data3_inst $link_data3\n\t\t\tset link_data3 [get_property IP_NAME $link_data3]\n\t\t\tif {[string match -nocase $link_data3 \"vid_phy_controller\"] || [string match -nocase $link_data3 \"hdmi_gt_controller\"]} {\n\t\t\t\tappend phy_names \" \" \"hdmi-phy3\"\n\t\t\t\tappend phys \" <&${link_data3_inst}rxphy_lane3 0 1 1 0\"\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"Connected stream of LINK_DATA3_IN is NULL...check the design\"\n\t\t}\n\t}\n\tif {![string match -nocase $phy_names \"\"]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"phy-names\" $phy_names stringlist\n\t}\n\tif {![string match -nocase $phys \"\"]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"phys\" $phys reference\n\t}\n\tset input_pixels_per_clock [get_property CONFIG.C_INPUT_PIXELS_PER_CLOCK [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,input-pixels-per-clock\" $input_pixels_per_clock int\n\tset max_bits_per_component [get_property CONFIG.C_MAX_BITS_PER_COMPONENT [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,max-bits-per-component\" $max_bits_per_component int\n\tset edid_ram_size [get_property CONFIG.C_EDID_RAM_SIZE [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,edid-ram-size\" $edid_ram_size hexint\n\tset include_hdcp_1_4 [get_property CONFIG.C_INCLUDE_HDCP_1_4 [get_cells -hier $drv_handle]]\n\tif {[string match -nocase $include_hdcp_1_4 \"true\"]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,include-hdcp-1-4\" \"\" boolean\n\t}\n\tset include_hdcp_2_2 [get_property CONFIG.C_INCLUDE_HDCP_2_2 [get_cells -hier $drv_handle]]\n\tif {[string match -nocase $include_hdcp_2_2 \"true\"]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,include-hdcp-2-2\" \"\" boolean\n\t}\n\tset audio_out_connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"AUDIO_OUT\"]\n\tif {[llength $audio_out_connect_ip] != 0} {\n\t\tset audio_out_connect_ip_type [get_property IP_NAME $audio_out_connect_ip]\n\t\tif {[string match -nocase $audio_out_connect_ip_type \"axis_switch\"]} {\n\t\t\t set connected_ip [hsi::utils::get_connected_stream_ip $audio_out_connect_ip \"M00_AXIS\"]\n if {[llength $connected_ip] != 0} {\n hsi::utils::add_new_dts_param \"$node\" \"xlnx,snd-pcm\" $connected_ip reference\n\t\t\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,audio-enabled\" \"\" boolean\n }\n\t\t} elseif {[string match -nocase $audio_out_connect_ip_type \"audio_formatter\"]} {\n\t\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,snd-pcm\" $audio_out_connect_ip reference\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,audio-enabled\" \"\" boolean\n\t\t}\n\t} else {\n\t\tdtg_warning \"$drv_handle pin AUDIO_OUT is not connected... check your design\"\n\t}\n}\n\nproc gen_frmbuf_node {ip drv_handle} {\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n\tset vcap [add_or_get_dt_node -n \"vcap_$drv_handle\" -p $bus_node]\n\thsi::utils::add_new_dts_param $vcap \"compatible\" \"xlnx,video\" string\n\thsi::utils::add_new_dts_param $vcap \"dmas\" \"$ip 0\" reference\n\thsi::utils::add_new_dts_param $vcap \"dma-names\" \"port0\" string\n\tset vcap_ports_node [add_or_get_dt_node -n \"ports\" -l vcap_ports$drv_handle -p $vcap]\n\thsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#size-cells\" 0 int\n\tset vcap_port_node [add_or_get_dt_node -n \"port\" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node]\n\thsi::utils::add_new_dts_param \"$vcap_port_node\" \"reg\" 0 int\n\thsi::utils::add_new_dts_param \"$vcap_port_node\" \"direction\" input string\n\tset vcap_in_node [add_or_get_dt_node -n \"endpoint\" -l $ip$drv_handle -p $vcap_port_node]\n\thsi::utils::add_new_dts_param \"$vcap_in_node\" \"remote-endpoint\" hdmirx_out$drv_handle reference\n}\n" }, { "path": "hdmi_tx_ss/data/hdmi_tx_ss.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver hdmi_tx_ss\n\n OPTION supported_peripherals = (v_hdmi_tx_ss v_hdmi_txss1);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = hdmi_tx_ss;\n\nEND driver\n" }, { "path": "hdmi_tx_ss/data/hdmi_tx_ss.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,v-hdmi-tx-ss-3.1\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset input_pixels_per_clock [get_property CONFIG.C_INPUT_PIXELS_PER_CLOCK [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,input-pixels-per-clock\" $input_pixels_per_clock int\n\tset max_bits_per_component [get_property CONFIG.C_MAX_BITS_PER_COMPONENT [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,max-bits-per-component\" $max_bits_per_component int\n\tset vid_interface [get_property CONFIG.C_VID_INTERFACE [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,vid-interface\" $vid_interface int\n set vtcip [get_cells -hier -filter {IP_NAME == \"v_tc\"}]\n\tset base_addr [get_property CONFIG.C_BASEADDR [get_cells -hier $drv_handle]]\n if {[llength $vtcip]} {\n\t\tgenerate_vtc_node $drv_handle $base_addr\n }\n\tset phy_names \"\"\n\tset phys \"\"\n\tset link_data0 [get_connected_stream_ip [get_cells -hier $drv_handle] \"LINK_DATA0_OUT\"]\n\tif {[llength $link_data0]} {\n\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $link_data0]\n\t\tif {[llength $ip_mem_handles]} {\n\t\t\tset link_data0_inst $link_data0\n\t\t\tset link_data0 [get_property IP_NAME $link_data0]\n\t\t\tif {[string match -nocase $link_data0 \"vid_phy_controller\"] || [string match -nocase $link_data0 \"hdmi_gt_controller\"]} {\n\t\t\t\tappend phy_names \" \" \"hdmi-phy0\"\n\t\t\t\tappend phys \"${link_data0_inst}txphy_lane0 0 1 1 1>,\"\n\t\t\t}\n\t\t}\n\t} else {\n\t\tdtg_warning \"connected stream of LINK_DATA0_IN is NULL...check the design\"\n\t}\n\n\tset link_data1 [get_connected_stream_ip [get_cells -hier $drv_handle] \"LINK_DATA1_OUT\"]\n\tif {[llength $link_data1]} {\n\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $link_data1]\n\t\tif {[llength $ip_mem_handles]} {\n\t\t\tset link_data1_inst $link_data1\n\t\t\tset link_data1 [get_property IP_NAME $link_data1]\n\t\t\tif {[string match -nocase $link_data1 \"vid_phy_controller\"] || [string match -nocase $link_data1 \"hdmi_gt_controller\"]} {\n\t\t\t\tappend phy_names \" \" \"hdmi-phy1\"\n\t\t\t\tappend phys \" <&${link_data1_inst}txphy_lane1 0 1 1 1>,\"\n\t\t\t}\n\t\t}\n\t} else {\n\t\tdtg_warning \"Connected stream of LINK_DATA1_IN is NULL...check the design\"\n\t}\n\n\tset link_data2 [get_connected_stream_ip [get_cells -hier $drv_handle] \"LINK_DATA2_OUT\"]\n\tif {[llength $link_data2]} {\n\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $link_data2]\n\t\tif {[llength $ip_mem_handles]} {\n\t\t\tset link_data2_inst $link_data2\n\t\t\tset link_data2 [get_property IP_NAME $link_data2]\n\t\t\tif {[string match -nocase $link_data2 \"vid_phy_controller\"] || [string match -nocase $link_data2 \"hdmi_gt_controller\"]} {\n\t\t\t\tappend phy_names \" \" \"hdmi-phy2\"\n\t\t\t\tappend phys \" <&${link_data2_inst}txphy_lane2 0 1 1 1\"\n\t\t\t}\n\t\t}\n\t} else {\n\t\tdtg_warning \"Connected stream of LINK_DATA2_IN is NULL...check the design\"\n\t}\n\n\tif {![string match -nocase $phy_names \"\"]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"phy-names\" $phy_names stringlist\n\t}\n\tif {![string match -nocase $phys \"\"]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"phys\" $phys reference\n\t}\n\tset include_hdcp_1_4 [get_property CONFIG.C_INCLUDE_HDCP_1_4 [get_cells -hier $drv_handle]]\n\tif {[string match -nocase $include_hdcp_1_4 \"true\"]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,include-hdcp-1-4\" \"\" boolean\n\t}\n\tset include_hdcp_2_2 [get_property CONFIG.C_INCLUDE_HDCP_2_2 [get_cells -hier $drv_handle]]\n\tif {[string match -nocase $include_hdcp_2_2 \"true\"]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,include-hdcp-2-2\" \"\" boolean\n\t}\n\tif {[string match -nocase $include_hdcp_1_4 \"true\"] || [string match -nocase $include_hdcp_2_2 \"true\"]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,hdcp-authenticate\" 0x1 int\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,hdcp-encrypt\" 0x1 int\n\t}\n\tset audio_in_connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"AUDIO_IN\"]\n\tif {[llength $audio_in_connect_ip] != 0} {\n\t\tset audio_in_connect_ip_type [get_property IP_NAME $audio_in_connect_ip]\n\t\tif {[string match -nocase $audio_in_connect_ip_type \"axis_switch\"]} {\n\t\t\tset connected_ip [hsi::utils::get_connected_stream_ip $audio_in_connect_ip \"S00_AXIS\"]\n\t\t\tif {[llength $connected_ip] != 0} {\n\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,snd-pcm\" $connected_ip reference\n\t\t\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,audio-enabled\" \"\" boolean\n\t\t\t}\n\t\t} elseif {[string match -nocase $audio_in_connect_ip_type \"audio_formatter\"]} {\n\t\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,snd-pcm\" $audio_in_connect_ip reference\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,audio-enabled\" \"\" boolean\n\t\t}\n\t} else {\n\t\tdtg_warning \"$drv_handle pin AUDIO_IN is not connected... check your design\"\n\t}\n\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] \"acr_cts\"]]\n\tforeach pin $pins {\n\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tif {[llength $sink_periph]} {\n\t\t\tif {[string match -nocase \"[get_property IP_NAME $sink_periph]\" \"hdmi_acr_ctrl\"]} {\n\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,xlnx-hdmi-acr-ctrl\" $sink_periph reference\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle peripheral is NULL for the $pin $sink_periph\"\n\t\t}\n\t}\n}\n" }, { "path": "i2s_receiver/data/i2s_receiver.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver i2s_receiver\n\n OPTION supported_peripherals = (i2s_receiver);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = i2s_receiver;\n\nEND driver\n" }, { "path": "i2s_receiver/data/i2s_receiver.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,i2s-receiver-1.0\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"M_AXIS_AUD\"]\n\tif {![llength $connect_ip]} {\n\t\tdtg_warning \"$drv_handle pin M_AXIS_AUD is not connected... check your design\"\n\t}\n\tif {[llength $connect_ip]} {\n\t\tset connect_ip_type [get_property IP_NAME $connect_ip]\n\t\tif {[string match -nocase $connect_ip_type \"axis_switch\"]} {\n\t\t\tset connected_ip [hsi::utils::get_connected_stream_ip $connect_ip \"M00_AXIS\"]\n\t\t\tif {![llength $connected_ip]} {\n\t\t\t\tdtg_warning \"$connect_ip pin M00_AXIS is not connected... check your design\"\n\t\t\t}\n\t\t\tif {[llength $connected_ip] != 0} {\n\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,snd-pcm\" $connected_ip reference\n\t\t\t}\n\t\t} elseif {[string match -nocase $connect_ip_type \"audio_formatter\"]} {\n\t\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,snd-pcm\" $connect_ip reference\n\t\t}\n\t}\n\tset dwidth [get_property CONFIG.C_DWIDTH [get_cells -hier $drv_handle]]\n\tif {[llength $dwidth]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,dwidth\" $dwidth hexint\n\t}\n\tset num_channels [get_property CONFIG.C_NUM_CHANNELS [get_cells -hier $drv_handle]]\n\tif {[llength $num_channels]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,num-channels\" $num_channels hexint\n\t}\n\tset depth [get_property CONFIG.C_DEPTH [get_cells -hier $drv_handle]]\n\tif {[llength $depth]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,depth\" $depth hexint\n\t}\n\tset ip [get_cells -hier $drv_handle]\n\tset freq \"\"\n\tset clk [get_pins -of_objects $ip \"aud_mclk\"]\n\tif {[llength $clk] } {\n\t\tset freq [get_property CLK_FREQ $clk]\n\t\thsi::utils::add_new_dts_param $node \"aud_mclk\" \"$freq\" int\n\t}\n}\n" }, { "path": "i2s_transmitter/data/i2s_transmitter.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver i2s_transmitter\n\n OPTION supported_peripherals = (i2s_transmitter);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = i2s_transmitter;\n\nEND driver\n" }, { "path": "i2s_transmitter/data/i2s_transmitter.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,i2s-transmitter-1.0\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"S_AXIS_AUD\"]\n\tif {![llength $connect_ip]} {\n dtg_warning \"$drv_handle pin S_AXIS_AUD is not connected... check your design\"\n }\n\tif {[llength $connect_ip]} {\n\t\tset connect_ip_type [get_property IP_NAME $connect_ip]\n\t\tif {[string match -nocase $connect_ip_type \"axis_switch\"]} {\n\t\t\tset connected_ip [hsi::utils::get_connected_stream_ip $connect_ip \"S00_AXIS\"]\n\t\t\tif {![llength $connected_ip]} {\n\t\t\t\tdtg_warning \"$connect_ip pin S00_AXIS is not connected... check your design\"\n\t\t\t}\n\t\t\tif {[llength $connected_ip] != 0} {\n\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,snd-pcm\" $connected_ip reference\n\t\t\t}\n\t\t} elseif {[string match -nocase $connect_ip_type \"audio_formatter\"]} {\n\t\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,snd-pcm\" $connect_ip reference\n\t\t}\n\t}\n\tset dwidth [get_property CONFIG.C_DWIDTH [get_cells -hier $drv_handle]]\n\tif {[llength $dwidth]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,dwidth\" $dwidth hexint\n\t}\n\tset num_channels [get_property CONFIG.C_NUM_CHANNELS [get_cells -hier $drv_handle]]\n\tif {[llength $num_channels]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,num-channels\" $num_channels hexint\n\t}\n\tset depth [get_property CONFIG.C_DEPTH [get_cells -hier $drv_handle]]\n\tif {[llength $depth]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,depth\" $depth hexint\n\t}\n\tset ip [get_cells -hier $drv_handle]\n\tset freq \"\"\n\tset clk [get_pins -of_objects $ip \"aud_mclk\"]\n\tif {[llength $clk] } {\n\t\tset freq [get_property CLK_FREQ $clk]\n\t\thsi::utils::add_new_dts_param $node \"aud_mclk\" \"$freq\" int\n\t}\n}\n" }, { "path": "i3cpsx/data/i3cpsx.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver i3cpsx\n\n OPTION supported_peripherals = (psx_i3c);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = i3cpsx;\n DTGPARAM name = clock-frequency, type = int , default = 400000;\n\nEND driver\n" }, { "path": "i3cpsx/data/i3cpsx.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n}\n" }, { "path": "iicps/data/iicps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver iicps\n\n OPTION supported_peripherals = (ps7_i2c psu_i2c psv_i2c psx_i2c);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = iicps;\n DTGPARAM name = dtg.alias , type = reference, default = i2c;\n\nEND driver\n" }, { "path": "iicps/data/iicps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n\n ps7_reset_handle $drv_handle CONFIG.C_I2C_RESET CONFIG.i2c-reset\n}\n" }, { "path": "intc/data/intc.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver intc\n\n OPTION DRC = intc_drc;\n OPTION supported_peripherals = (axi_intc);\n OPTION supported_os_types = (DTS);\n OPTION NAME = intc;\n PARAMETER name = dev_type, default = \"interrupt-controller\", type = string;\n DTGPARAM name = \"#interrupt-cells\", default = 2, type = int;\n DTGPARAM name = interrupt-controller, type = boolean;\n DTGPARAM name = compatible, type =stringlist, default = \"xlnx,xps-intc-1.00.a\" ;\n DTGPARAM name = \"xlnx,kind-of-intr\", type = hexint, default = 0x0 ;\n\nEND driver\n" }, { "path": "intc/data/intc.tcl", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n set zocl [get_property CONFIG.dt_zocl [get_os]]\n set compatible [get_comp_str $drv_handle]\n set compatible [append compatible \" \" \"xlnx,xps-intc-1.00.a\"]\n set_drv_prop $drv_handle compatible \"$compatible\" stringlist\n set ip [get_cells -hier $drv_handle]\n set num_intr_inputs [hsi::utils::get_ip_param_value $ip C_NUM_INTR_INPUTS]\n set kind_of_intr [hsi::utils::get_ip_param_value $ip C_KIND_OF_INTR]\n # Pad to 32 bits - num_intr_inputs\n if { $num_intr_inputs != -1 } {\n set count 0\n set par_mask 0\n for { set count 0 } { $count < $num_intr_inputs} { incr count} {\n set mask [expr {1<<$count}]\n set new_mask [expr {$mask | $par_mask}]\n set par_mask $new_mask\n }\n\n set kind_of_intr_32 $kind_of_intr\n set kind_of_intr [expr {$kind_of_intr_32 & $par_mask}]\n } else {\n set kind_of_intr 0\n }\n set_property CONFIG.xlnx,kind-of-intr $kind_of_intr $drv_handle\n if {$zocl} {\n set num_intr_inputs \"0x20\"\n set_drv_prop $drv_handle \"xlnx,num-intr-inputs\" $num_intr_inputs int\n } else {\n set_drv_conf_prop $drv_handle C_NUM_INTR_INPUTS \"xlnx,num-intr-inputs\"\n }\n}\n" }, { "path": "isppipeline/data/ispipeline.mdd", "content": "#\n# (C) Copyright 2023 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver ispipeline\n\n OPTION supported_peripherals = (ISPPipeline_accel);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = ispipeline;\n\nEND driver\n" }, { "path": "isppipeline/data/ispipeline.tcl", "content": "#\n# (C) Copyright 2023 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\nproc gen_reset_gpio {drv_handle node} {\n\tset ip [get_cells -hier $drv_handle]\n\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] \"ap_rst_n\"]]\n\tforeach pin $pins {\n\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tif {[llength $sink_periph]} {\n\t\t\tset sink_ip [get_property IP_NAME $sink_periph]\n\t\t\tif {[string match -nocase $sink_ip \"axi_gpio\"]} {\n\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"$sink_periph 0 1\" reference\n\t\t\t}\n\t\t\tif {[string match -nocase $sink_ip \"xlslice\"]} {\n\t\t\t\tset gpio [get_property CONFIG.DIN_FROM $sink_periph]\n\t\t\t\tset pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph \"Din\"]]]\n\t\t\tforeach pin $pins {\n\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\tif {[llength $periph]} {\n\t\t\t\t\tset ip [get_property IP_NAME $periph]\n\t\t\t\t\tset proc_type [get_sw_proc_prop IP_NAME]\n\t\t\t\t\tif {[string match -nocase $proc_type \"psv_cortexa72\"] } {\n\t\t\t\t\t\tif { $ip in { \"versal_cips\" \"ps_wizard\" }} {\n\t\t\t\t\t\t\t# As in versal there is only bank0 for MIOs\n\t\t\t\t\t\t\tset gpio [expr $gpio + 26]\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio0 $gpio 0\" reference\n\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tif {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n\t\t\t\t\t\tif {[string match -nocase $ip \"zynq_ultra_ps_e\"]} {\n\t\t\t\t\t\t\tset gpio [expr $gpio + 78]\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio $gpio 0\" reference\n\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tif {[string match -nocase $ip \"axi_gpio\"]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"$periph $gpio 0 1\" reference\n\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"periph for the pin:$pin is NULL $periph...check the design\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"peripheral for the pin:$pin is NULL $sink_periph...check the design\"\n\t\t}\n\t}\n}\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\tif {[file exists $common_tcl_file]} {\n\t\tsource $common_tcl_file\n\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n return\n\t}\n\tset ip_name [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,isppipeline-1.0\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\thsi::utils::add_new_dts_param $node \"xlnx,max-height\" \"/bits/ 16 <2160>\" noformating\n\thsi::utils::add_new_dts_param $node \"xlnx,max-width\" \"/bits/ 16 <3840>\" noformating\n\thsi::utils::add_new_dts_param $node \"xlnx,rgain\" \"/bits/ 16 <128>\" noformating\n\thsi::utils::add_new_dts_param $node \"xlnx,bgain\" \"/bits/ 16 <210>\" noformating\n\thsi::utils::add_new_dts_param $node \"xlnx,pawb\" \"/bits/ 16 <350>\" noformating\n\thsi::utils::add_new_dts_param $node \"xlnx,mode-reg\" \"\" boolean\n\tgen_reset_gpio \"$drv_handle\" \"$node\"\n\t# generating ports node for ispipeline ip\n\tset isppipeline_ports_node [add_or_get_dt_node -n \"ports\" -l isppipeline_ports$drv_handle -p $node]\n\thsi::utils::add_new_dts_param \"$isppipeline_ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$isppipeline_ports_node\" \"#size-cells\" 0 int\n\t# find input ip which is connected to s_axis_video\n\tset inip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video\"]\n\tif {[llength $inip]} {\n\t\tif {[string match -nocase [get_property IP_NAME $inip] \"axis_subset_converter\"]} {\n\t\t\tset inip [get_connected_stream_ip [get_cells -hier $inip] \"S_AXIS\"]\n\t\t}\n\t\tif {[string match -nocase [get_property IP_NAME $inip] \"axis_data_fifo\"]} {\n\t\t\tset inip [get_connected_stream_ip [get_cells -hier $inip] \"S_AXIS\"]\n\t\t}\n\t\t# generating port0 node for ispipeline ip\n\t\tset port0_node [add_or_get_dt_node -n \"port\" -l isppipeline_port0$drv_handle -u 0 -p $isppipeline_ports_node]\n\t\thsi::utils::add_new_dts_param \"$port0_node\" \"reg\" 0 int\n\t\tset isppipeline_port_node_endpoint [add_or_get_dt_node -n \"endpoint\" -l $drv_handle$inip -p $port0_node]\n\t\thsi::utils::add_new_dts_param \"$isppipeline_port_node_endpoint\" \"remote-endpoint\" isppipeline_in$drv_handle reference\n\t}\n\t# find scanoutip which is connected to m_axis_video\n\tset scanoutip [get_connected_stream_ip [get_cells -hier $drv_handle] \"m_axis_video\"]\n\tset port1_node [add_or_get_dt_node -n \"port\" -l isppipeline_port1$drv_handle -u 1 -p $isppipeline_ports_node]\n\thsi::utils::add_new_dts_param \"$port1_node\" \"reg\" 1 int\n\tif {[llength $scanoutip]} {\n\t\t# generating port1 node for ispipeline ip\n\t\tif {[string match -nocase [get_property IP_NAME $scanoutip] \"axis_broadcaster\"]} {\n\t\t\tset port1_node_endpoint [add_or_get_dt_node -n \"endpoint\" -l $drv_handle$scanoutip -p $port1_node]\n\t\t\tgen_endpoint $drv_handle \"$drv_handle$scanoutip\"\n\t\t\thsi::utils::add_new_dts_param \"$port1_node_endpoint\" \"remote-endpoint\" $scanoutip$drv_handle reference\n\t\t\tgen_remoteendpoint $drv_handle \"$scanoutip$drv_handle\"\n\t\t}\n\t\tif {[string match -nocase [get_property IP_NAME $scanoutip] \"axis_switch\"]} {\n\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $scanoutip]\n\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\tset port1_node_endpoint [add_or_get_dt_node -n \"endpoint\" -l $drv_handle$scanoutip -p $port1_node]\n\t\t\t\tgen_axis_switch_in_endpoint $drv_handle \"$drv_handle$scanoutip\"\n\t\t\t\thsi::utils::add_new_dts_param \"$port1_node_endpoint\" \"remote-endpoint\" $scanoutip$drv_handle reference\n\t\t\t\tgen_axis_switch_in_remo_endpoint $drv_handle \"$scanoutip$drv_handle\"\n\t\t\t}\n\t\t}\n\t}\n\tforeach outip $scanoutip {\n\t\tif {[llength $outip]} {\n\t\t\tif {[string match -nocase [get_property IP_NAME $outip] \"system_ila\"]} {\n\t\t\t\tcontinue\n\t\t\t}\n\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $outip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $outip]\n\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\tset port1_node_endpoint [add_or_get_dt_node -n \"endpoint\" -l $drv_handle$outip -p $port1_node]\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $outip] \"v_proc_ss\"]} {\n\t\t\t\t\t# generating remote-endpoint only when it is connected to v_proc_ss ip\n\t\t\t\t\thsi::utils::add_new_dts_param \"$port1_node_endpoint\" \"remote-endpoint\" \"v_proc_ss$drv_handle\" reference\n\t\t\t\t} else {\n\t\t\t\t\tgen_endpoint $drv_handle \"$drv_handle$outip\"\n\t\t\t\t\thsi::utils::add_new_dts_param \"$port1_node_endpoint\" \"remote-endpoint\" $outip$drv_handle reference\n\t\t\t\t\tgen_remoteendpoint $drv_handle \"$outip$drv_handle\"\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tset connectip [get_connect_ip $outip $master_intf]\n\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\tset port1_node_endpoint [add_or_get_dt_node -n \"endpoint\" -l ispipeline_out$drv_handle -p $port1_node]\n\t\t\t\t\tgen_endpoint $drv_handle \"$drv_handle$outip\"\n\t\t\t\t\thsi::utils::add_new_dts_param \"$port1_node_endpoint\" \"remote-endpoint\" $connectip$drv_handle reference\n\t\t\t\t\tgen_remoteendpoint $drv_handle \"$connectip$drv_handle\"\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle pin m_axis_video is not connected..check your design\"\n\t\t}\n\t}\n}\n" }, { "path": "mig_7series/data/mig_7series.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver mig_7series\n\n OPTION supported_peripherals = (mig_7series ddr4 ddr3);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = mig_7series;\n\nEND driver\n" }, { "path": "mig_7series/data/mig_7series.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n\tset remove_pl [get_property CONFIG.remove_pl [get_os]]\n\tif {[is_pl_ip $drv_handle] && $remove_pl} {\n\t\treturn 0\n\t}\n\tset ddr_ip \"\"\n\tset slave [get_cells -hier ${drv_handle}]\n\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $slave]\n\tset main_memory [get_property CONFIG.main_memory [get_os]]\n\tif {![string match -nocase $main_memory \"none\"]} {\n\t\tset ddr_ip [get_property IP_NAME [get_cells -hier -nocase $main_memory]]\n\t}\n\tset drv_ip [get_property IP_NAME [get_cells -hier $drv_handle]]\n\n\tif {[regexp $drv_ip $ddr_ip match]} {\n\t\tset master_dts [get_property CONFIG.master_dts [get_os]]\n\t\tset cur_dts [current_dt_tree]\n\t\tset master_dts_obj [get_dt_trees ${master_dts}]\n\t\tset_cur_working_dts $master_dts\n\n\t\tset parent_node [add_or_get_dt_node -n / -d ${master_dts}]\n\t\tset addr [get_property CONFIG.C0_DDR4_MEMORY_MAP_BASEADDR [get_cells -hier $drv_handle]]\n\t\tset base [get_property CONFIG.C0_DDR4_MEMORY_MAP_BASEADDR [get_cells -hier $drv_handle]]\n\t\tset high [get_property CONFIG.C0_DDR4_MEMORY_MAP_HIGHADDR [get_cells -hier $drv_handle]]\n\t\tif {![llength $addr]} {\n\t\t\tset addr [get_property CONFIG.C_BASEADDR [get_cells -hier $drv_handle]]\n\t\t}\n\t\tregsub -all {^0x} $addr {} addr\n\t\tset memory_node [add_or_get_dt_node -n memory -u $addr -p $parent_node]\n\t\tif {![llength $base]} {\n\t\t\tset base [get_property CONFIG.C_BASEADDR [get_cells -hier $drv_handle]]\n\t\t}\n\t\tif {![llength $high]} {\n\t\t\tset high [get_property CONFIG.C_HIGHADDR [get_cells -hier $drv_handle]]\n\t\t}\n\t\tset size [format 0x%x [expr {${high} - ${base} + 1}]]\n\t\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$base\" match]} {\n\t\t\t\tset temp $base\n\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\tset len [string length $temp]\n\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\tset high_base \"0x[string range $temp $rem $len]\"\n\t\t\t\tset low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\tset low_base [format 0x%08x $low_base]\n\t\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$size\" match]} {\n\t\t\t\t\tset temp $size\n\t\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\t\tset len [string length $temp]\n\t\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\t\tset high_size \"0x[string range $temp $rem $len]\"\n\t\t\t\t\tset low_size \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\t\tset low_size [format 0x%08x $low_size]\n\t\t\t\t\tset reg \"$low_base $high_base $low_size $high_size\"\n\t\t\t\t} else {\n\t\t\t\t\tset reg \"$low_base $high_base 0x0 $size\"\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tset reg \"0x0 $base 0x0 $size\"\n\t\t\t}\n\t\t} else {\n\t\t\tset reg \"$base $size\"\n\t\t}\n\n\t\thsi::utils::add_new_dts_param \"${memory_node}\" \"reg\" $reg inthexlist\n\t\tif {[catch {set dev_type [get_property CONFIG.device_type $drv_handle]} msg]} {\n\t\t\tset dev_type memory\n\t\t}\n\t\tif {[string_is_empty $dev_type]} {set dev_type memory}\n\t\thsi::utils::add_new_dts_param \"${memory_node}\" \"device_type\" $dev_type string\n\t}\n\n\tset ip_mem_handle [lindex [hsi::utils::get_ip_mem_ranges [get_cells -hier $slave]] 0]\n\tset addr [string tolower [get_property BASE_VALUE $ip_mem_handle]]\n\tset base [string tolower [get_property BASE_VALUE $ip_mem_handle]]\n\tset high [string tolower [get_property HIGH_VALUE $ip_mem_handle]]\n\tset size [format 0x%x [expr {${high} - ${base} + 1}]]\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$base\" match]} {\n\t\t\tset temp $base\n\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\tset len [string length $temp]\n\t\t\tset rem [expr {${len} - 8}]\n\t\t\tset high_base \"0x[string range $temp $rem $len]\"\n\t\t\tset low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\tset low_base [format 0x%08x $low_base]\n\t\t\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$size\" match]} {\n\t\t\t\tset temp $size\n\t\t\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\t\t\tset len [string length $temp]\n\t\t\t\tset rem [expr {${len} - 8}]\n\t\t\t\tset high_size \"0x[string range $temp $rem $len]\"\n\t\t\t\tset low_size \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\t\t\tset low_size [format 0x%08x $low_size]\n\t\t\t\tset reg \"$low_base $high_base $low_size $high_size\"\n\t\t\t} else {\n\t\t\t\tset reg \"$low_base $high_base 0x0 $size\"\n\t\t\t}\n\t\t} else {\n\t\t\tset reg \"0x0 $base 0x0 $size\"\n\t\t}\n\t} else {\n\t\tset reg \"$base $size\"\n\t}\n\tset_drv_prop_if_empty $drv_handle reg $reg intlist\n}\n" }, { "path": "mipi_csi2_rx/data/mipi_csi2_rx.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver mipi_csi2_rx\n\n OPTION supported_peripherals = (mipi_csi2_rx_subsystem);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = mipi_csi2_rx;\n\nEND driver\n" }, { "path": "mipi_csi2_rx/data/mipi_csi2_rx.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,mipi-csi2-rx-subsystem-5.0\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset dphy_en_reg_if [get_property CONFIG.DPY_EN_REG_IF [get_cells -hier $drv_handle]]\n\tif {[string match -nocase $dphy_en_reg_if \"true\"]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,dphy-present\" \"\" boolean\n\t}\n\tset en_vcx [get_property CONFIG.C_EN_VCX [get_cells -hier $drv_handle]]\n\tif {[string match -nocase $en_vcx \"true\"]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,en-vcx\" \"\" boolean\n\t}\n\tset en_csi_v2_0 [get_property CONFIG.C_EN_CSI_V2_0 [get_cells -hier $drv_handle]]\n\tif {[string match -nocase $en_csi_v2_0 \"true\"]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,en-csi-v2-0\" \"\" boolean\n\t}\n\tset dphy_lanes [get_property CONFIG.C_DPHY_LANES [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,max-lanes\" $dphy_lanes int\n\tfor {set lane 1} {$lane <= $dphy_lanes} {incr lane} {\n\t\tlappend lanes $lane\n\t}\n\tset en_csi_v2_0 [get_property CONFIG.C_EN_CSI_V2_0 [get_cells -hier $drv_handle]]\n\tset en_vcx [get_property CONFIG.C_EN_VCX [get_cells -hier $drv_handle]]\n\tset cmn_vc [get_property CONFIG.CMN_VC [get_cells -hier $drv_handle]]\n\tif {$en_csi_v2_0 == true && $en_vcx == true && [string match -nocase $cmn_vc \"ALL\"]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,vc\" 16 int\n\t} elseif {$en_csi_v2_0 == true && $en_vcx == false && [string match -nocase $cmn_vc \"ALL\"]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,vc\" 4 int\n\t} elseif {$en_csi_v2_0 == false && [string match -nocase $cmn_vc \"ALL\"]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,vc\" 4 int\n\t}\n\tif {[llength $en_csi_v2_0] == 0} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,vc\" $cmn_vc int\n\t}\n\tset cmn_pxl_format [get_property CONFIG.CMN_PXL_FORMAT [get_cells -hier $drv_handle]]\n\tgen_pixel_format $node $cmn_pxl_format\n\tset csi_en_activelanes [get_property CONFIG.C_CSI_EN_ACTIVELANES [get_cells -hier $drv_handle]]\n\tif {[string match -nocase $csi_en_activelanes \"true\"]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,en-active-lanes\" \"\" boolean\n\t}\n\tset cmn_inc_vfb [get_property CONFIG.CMN_INC_VFB [get_cells -hier $drv_handle]]\n\tif {[string match -nocase $cmn_inc_vfb \"true\"]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,vfb\" \"\" boolean\n\t}\n\tset cmn_num_pixels [get_property CONFIG.CMN_NUM_PIXELS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,ppc\" \"$cmn_num_pixels\" int\n\tset axis_tdata_width [get_property CONFIG.AXIS_TDATA_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,axis-tdata-width\" \"$axis_tdata_width\" int\n\n\tset ports_node [add_or_get_dt_node -n \"ports\" -l mipi_csi_ports$drv_handle -p $node]\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\tset port_node [add_or_get_dt_node -n \"port\" -l mipi_csi_port1$drv_handle -u 1 -p $ports_node]\n\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 1 int\n\n\tset port0_node [add_or_get_dt_node -n \"port\" -l mipi_csi_port0$drv_handle -u 0 -p $ports_node]\n\thsi::utils::add_new_dts_param \"$port0_node\" \"reg\" 0 int\n\thsi::utils::add_new_dts_param \"${port0_node}\" \"/* User need to add something like remote-endpoint=<&out> under the node csiss_in:endpoint */\" \"\" comment\n\tset csiss_rx_node [add_or_get_dt_node -n \"endpoint\" -l mipi_csi_in$drv_handle -p $port0_node]\n\tif {[llength $lanes]} {\n\t\thsi::utils::add_new_dts_param \"${csiss_rx_node}\" \"data-lanes\" $lanes int\n\t}\n\n\tset outip [get_connected_stream_ip [get_cells -hier $drv_handle] \"VIDEO_OUT\"]\n\tif {[llength $outip]} {\n\t\tif {[string match -nocase [get_property IP_NAME $outip] \"axis_broadcaster\"]} {\n\t\t\tset mipi_node [add_or_get_dt_node -n \"endpoint\" -l mipi_csirx_out$drv_handle -p $port_node]\n\t\t\tgen_endpoint $drv_handle \"mipi_csirx_out$drv_handle\"\n\t\t\thsi::utils::add_new_dts_param \"$mipi_node\" \"remote-endpoint\" $outip$drv_handle reference\n\t\t\tgen_remoteendpoint $drv_handle \"$outip$drv_handle\"\n\t\t}\n\t\tif {[string match -nocase [get_property IP_NAME $outip] \"axis_switch\"]} {\n\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $outip]\n\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\tset mipi_node [add_or_get_dt_node -n \"endpoint\" -l mipi_csirx_out$drv_handle -p $port_node]\n\t\t\t\tgen_axis_switch_in_endpoint $drv_handle \"mipi_csirx_out$drv_handle\"\n\t\t\t\thsi::utils::add_new_dts_param \"$mipi_node\" \"remote-endpoint\" $outip$drv_handle reference\n\t\t\t\tgen_axis_switch_in_remo_endpoint $drv_handle \"$outip$drv_handle\"\n\t\t\t}\n\t\t}\n\t}\n\tforeach ip $outip {\n\t\tif {[llength $ip]} {\n\t\t\tset intfpins [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip]\n\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\t\tset csi_rx_node [add_or_get_dt_node -n \"endpoint\" -l mipi_csirx_out$drv_handle -p $port_node]\n\t\t\t\tgen_endpoint $drv_handle \"mipi_csirx_out$drv_handle\"\n\t\t\t\thsi::utils::add_new_dts_param \"$csi_rx_node\" \"remote-endpoint\" $ip$drv_handle reference\n\t\t\t\tgen_remoteendpoint $drv_handle $ip$drv_handle\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $ip] \"v_frmbuf_wr\"]} {\n gen_frmbuf_node $ip $drv_handle\n }\n\t\t\t} else {\n\t\t\t\tset connectip [get_connect_ip $ip $intfpins]\n\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"axis_switch\"]} {\n\t\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip]\n\t\t\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\t\t\tset mipi_node [add_or_get_dt_node -n \"endpoint\" -l mipi_csirx_out$drv_handle -p $port_node]\n\t\t\t\t\t\t\tgen_axis_switch_in_endpoint $drv_handle \"mipi_csirx_out$drv_handle\"\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mipi_node\" \"remote-endpoint\" $connectip$drv_handle reference\n\t\t\t\t\t\t\tgen_axis_switch_in_remo_endpoint $drv_handle \"$connectip$drv_handle\"\n\t\t\t\t\t\t}\n\n\t\t\t\t\t} elseif {[string match -nocase [get_property IP_NAME $connectip] \"ISPPipeline_accel\"]} {\n\t\t\t\t\t\tset isppipeline_node [add_or_get_dt_node -n \"endpoint\" -l isppipeline_in$connectip -p $port_node]\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$isppipeline_node\" \"remote-endpoint\" $connectip$drv_handle reference\n\n\t\t\t\t\t} else {\n\t\t\t\t\tset csi_rx_node [add_or_get_dt_node -n \"endpoint\" -l mipi_csirx_out$drv_handle -p $port_node]\n\t\t\t\t\tgen_endpoint $drv_handle \"mipi_csirx_out$drv_handle\"\n\t\t\t\t\thsi::utils::add_new_dts_param \"$csi_rx_node\" \"remote-endpoint\" $connectip$drv_handle reference\n\t\t\t\t\tgen_remoteendpoint $drv_handle $connectip$drv_handle\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"v_frmbuf_wr\"]} {\n\t\t\t\t\t\tgen_frmbuf_node $connectip $drv_handle\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\t}\n\tgen_gpio_reset $drv_handle $node\n}\n\nproc gen_pixel_format {node pxl_format} {\n\tset pixel_format \"\"\n\tswitch $pxl_format {\n\t\t\"YUV422_8bit\" {\n\t\t\tset pixel_format 0x18\n\t\t}\n\t\t\"YUV422_10bit\" {\n\t\t\tset pixel_format 0x1f\n\t\t}\n\t\t\"RGB444\" {\n\t\t\tset pixel_format 0x20\n\t\t}\n\t\t\"RGB555\" {\n\t\t\tset pixel_format 0x21\n\t\t}\n\t\t\"RGB565\" {\n\t\t\tset pixel_format 0x22\n\t\t}\n\t\t\"RGB666\" {\n\t\t\tset pixel_format 0x23\n\t\t}\n\t\t\"RGB888\" {\n\t\t\tset pixel_format 0x24\n\t\t}\n\t\t\"RAW6\" {\n\t\t\tset pixel_format 0x28\n\t\t}\n\t\t\"RAW7\" {\n\t\t\tset pixel_format 0x29\n\t\t}\n\t\t\"RAW8\" {\n\t\t\tset pixel_format 0x2a\n\t\t}\n\t\t\"RAW10\" {\n\t\t\tset pixel_format 0x2b\n\t\t}\n\t\t\"RAW12\" {\n\t\t\tset pixel_format 0x2c\n\t\t}\n\t\t\"RAW14\" {\n\t\t\tset pixel_format 0x2d\n\t\t}\n\t\t\"RAW16\" {\n\t\t\tset pixel_format 0x2e\n\t\t}\n\t\t\"RAW20\" {\n\t\t\tset pixel_format 0x2f\n\t\t}\n\t}\n\tif {[llength $pixel_format]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,csi-pxl-format\" $pixel_format hex\n\t}\n}\n\nproc gen_frmbuf_node {outip drv_handle} {\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n set vcap [add_or_get_dt_node -n \"vcap_$drv_handle\" -p $bus_node]\n hsi::utils::add_new_dts_param $vcap \"compatible\" \"xlnx,video\" string\n hsi::utils::add_new_dts_param $vcap \"dmas\" \"$outip 0\" reference\n hsi::utils::add_new_dts_param $vcap \"dma-names\" \"port0\" string\n set vcap_ports_node [add_or_get_dt_node -n \"ports\" -l vcap_ports$drv_handle -p $vcap]\n hsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#address-cells\" 1 int\n hsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#size-cells\" 0 int\n set vcap_port_node [add_or_get_dt_node -n \"port\" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node]\n hsi::utils::add_new_dts_param \"$vcap_port_node\" \"reg\" 0 int\n hsi::utils::add_new_dts_param \"$vcap_port_node\" \"direction\" input string\n set vcap_in_node [add_or_get_dt_node -n \"endpoint\" -l $outip$drv_handle -p $vcap_port_node]\n hsi::utils::add_new_dts_param \"$vcap_in_node\" \"remote-endpoint\" mipi_csirx_out$drv_handle reference\n}\n\n\nproc gen_gpio_reset {drv_handle node} {\n\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] \"video_aresetn\"]]\n\tforeach pin $pins {\n\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tif {[llength $sink_periph]} {\n\t\t\tset sink_ip [get_property IP_NAME $sink_periph]\n\t\t\tif {[string match -nocase $sink_ip \"xlslice\"]} {\n\t\t\t\tset gpio [get_property CONFIG.DIN_FROM $sink_periph]\n\t\t\t\tset pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph \"Din\"]]]\n\t\t\t\tforeach pin $pins {\n\t\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t\tif {[llength $periph]} {\n\t\t\t\t\t\tset ip [get_property IP_NAME $periph]\n\t\t\t\t\t\tset proc_type [get_sw_proc_prop IP_NAME]\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psv_cortexa72\"] } {\n\t\t\t\t\t\t\tif { $ip in { \"versal_cips\" \"ps_wizard\" }} {\n\t\t\t\t\t\t\t\t# As versal has only bank0 for MIOs\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 26]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"video-reset-gpios\" \"gpio0 $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n\t\t\t\t\t\t\tif {[string match -nocase $ip \"zynq_ultra_ps_e\"]} {\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 78]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"video-reset-gpios\" \"gpio $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $ip \"axi_gpio\"]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"video-reset-gpios\" \"$periph $gpio 1\" reference\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"$drv_handle peripheral is NULL for the $pin $periph\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\t# If no axi-slice connected b/w axi_gpio and reset pin\n\t\t\t\t# add video-reset-gpios property with gpio number 0\n\t\t\t\tif {[string match -nocase $sink_ip \"axi_gpio\"]} {\n\t\t\t\t\tset gpio \"0\"\n\t\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t\tif {[llength $gpio]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"video-reset-gpios\" \"$periph $gpio 1\" reference\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle peripheral is NULL for the $pin $sink_periph\"\n\t\t}\n\t}\n}\n" }, { "path": "mipi_dsi_tx/data/mipi_dsi_tx.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver mipi_dsi_tx\n\n OPTION supported_peripherals = (mipi_dsi_tx_subsystem);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = mipi_dsi_tx;\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "mipi_dsi_tx/data/mipi_dsi_tx.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,dsi\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset dsi_num_lanes [get_property CONFIG.DSI_LANES [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,dsi-num-lanes\" $dsi_num_lanes int\n\tset dsi_pixels_perbeat [get_property CONFIG.DSI_PIXELS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,dsi-pixels-perbeat\" $dsi_pixels_perbeat int\n\tset dsi_datatype [get_property CONFIG.DSI_DATATYPE [get_cells -hier $drv_handle]]\n\tif {[string match -nocase $dsi_datatype \"RGB888\"]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,dsi-data-type\" 0 int\n\t} elseif {[string match -nocase $dsi_datatype \"RGB666_L\"]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,dsi-data-type\" 1 int\n\t} elseif {[string match -nocase $dsi_datatype \"RGB666_P\"]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,dsi-data-type\" 2 int\n\t} elseif {[string match -nocase $dsi_datatype \"RGB565\"]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,dsi-data-type\" 3 int\n\t}\n\tset panel_node [add_or_get_dt_node -n \"simple_panel\" -l simple_panel$drv_handle -u 0 -p $node]\n\thsi::utils::add_new_dts_param \"${panel_node}\" \"/* User needs to add the panel node based on their requirement */\" \"\" comment\n\thsi::utils::add_new_dts_param \"$panel_node\" \"reg\" 0 int\n\thsi::utils::add_new_dts_param \"$panel_node\" \"compatible\" \"auo,b101uan01\" string\n}\n" }, { "path": "mixer/data/mixer.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver mixer\n\n OPTION supported_peripherals = (v_mix);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = mixer;\n\nEND driver\n" }, { "path": "mixer/data/mixer.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,mixer-3.0 xlnx,mixer-4.0 xlnx,mixer-5.0\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset mixer_ip [get_cells -hier $drv_handle]\n\tset num_layers [get_property CONFIG.NR_LAYERS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,num-layers\" $num_layers int\n\tset samples_per_clock [get_property CONFIG.SAMPLES_PER_CLOCK [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,ppc\" $samples_per_clock int\n\tset dma_addr_width [get_property CONFIG.AXIMM_ADDR_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,dma-addr-width\" $dma_addr_width int\n\tset max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,bpc\" $max_data_width int\n\tset logo_layer [get_property CONFIG.LOGO_LAYER [get_cells -hier $drv_handle]]\n\tif {[string match -nocase $logo_layer \"true\"]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,logo-layer\" \"\" boolean\n\t}\n\tset vtcip [get_cells -hier -filter {IP_NAME == \"v_tc\"}]\n\tset mix_outip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] \"m_axis_video\"]\n\tif {![llength $mix_outip]} {\n\t\tdtg_warning \"$drv_handle pin m_axis_video is not connected ...check your design\"\n\t}\n\tset enable_csc_coefficient_registers [get_property CONFIG.ENABLE_CSC_COEFFICIENT_REGISTERS [get_cells -hier $drv_handle]]\n\tif {$enable_csc_coefficient_registers == 1} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,enable-csc-coefficient-register\" \"\" boolean\n\t}\n\n\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $mix_outip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\tforeach outip $mix_outip {\n\t\tif {[llength $outip] != 0} {\n\t\t\tif {[string match -nocase [get_property IP_NAME $outip] \"v_hdmi_tx_ss\"] || [string match -nocase [get_property IP_NAME $outip] \"v_hdmi_txss1\"]} {\n\t\t\t\tif {[llength $vtcip]} {\n\t\t\t\t\t# Adding bridge param when v_tc ip connected as subcore\n\t\t\t\t\t# in the subsystem core by appending subsystem name.\n\t\t\t\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,bridge\" \"v_tc_$outip\" reference\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {![string match -nocase [get_property IP_NAME $outip] \"v_frmbuf_wr\"]} {\n\t\t\t\tset mixer_port_node [add_or_get_dt_node -n \"port\" -l crtc_mixer_port$drv_handle -u 0 -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_port_node\" \"reg\" 0 int\n\t\t\t\tset mixer_crtc [add_or_get_dt_node -n \"endpoint\" -l mixer_crtc$drv_handle -p $mixer_port_node]\n\t\t\t} else {\n\t\t\t\tset ports_node [add_or_get_dt_node -n \"ports\" -l crtc_mixer_ports$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\t\t\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\t\t\t\tset mixer_port0 [add_or_get_dt_node -n \"port\" -l crtc_mixer_port$drv_handle -u 0 -p $ports_node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_port0\" \"reg\" 0 int\n\t\t\t\tset mixer0_endpoint [add_or_get_dt_node -n \"endpoint\" -l mixer_crtc$drv_handle -p $mixer_port0]\n\t\t\t\tset mixer_port1 [add_or_get_dt_node -n \"port\" -l crtc_mixer_port1$drv_handle -u 1 -p $ports_node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_port1\" \"reg\" 1 int\n\t\t\t\tset mixer1_endpoint [add_or_get_dt_node -n \"endpoint\" -l mixer_out$drv_handle -p $mixer_port1]\n\t\t\t}\n\n\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $outip]\n\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\tgen_endpoint $drv_handle \"mixer_crtc$drv_handle\"\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $outip] \"v_dp_txss1\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_crtc\" \"remote-endpoint\" \"dptx_out$outip\" reference\n\t\t\t\t\tgen_remoteendpoint $drv_handle \"dptx_out$outip\"\n\t\t\t\t} elseif {[string match -nocase [get_property IP_NAME $outip] \"v_frmbuf_wr\"]} {\n\t\t\t\t\tset mix_inip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video\"]\n\t\t\t\t\tif {[llength $mix_inip]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer0_endpoint\" \"remote-endpoint\" \"sca_out$mix_inip\" reference\n\t\t\t\t\t}\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer1_endpoint\" \"remote-endpoint\" \"v_frmbuf_wr$outip\" reference\n\t\t\t\t} else {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_crtc\" \"remote-endpoint\" $outip$drv_handle reference\n\t\t\t\t\tgen_remoteendpoint $drv_handle \"$outip$drv_handle\"\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $outip] \"system_ila\"]} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\tset connectip [get_connect_ip $outip $master_intf]\n\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"v_hdmi_tx_ss\"] || [string match -nocase [get_property IP_NAME $connectip] \"v_hdmi_txss1\"]} {\n\t\t\t\t\t\tif {[llength $vtcip]} {\n\t\t\t\t\t\t\t# Adding bridge param when v_tc ip connected as subcore\n\t\t\t\t\t\t\t# in the subsystem core by appending subsystem name.\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,bridge\" \"v_tc_$connectip\" reference\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tgen_endpoint $drv_handle \"mixer_crtc$drv_handle\"\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $outip] \"v_dp_txss1\"]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_crtc\" \"remote-endpoint\" \"dptx_out$outip\" reference\n\t\t\t\t\t\tgen_remoteendpoint $drv_handle \"dptx_out$outip\"\n\t\t\t\t\t} else {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_crtc\" \"remote-endpoint\" $connectip$drv_handle reference\n\t\t\t\t\t\tgen_remoteendpoint $drv_handle \"$connectip$drv_handle\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle pin m_axis_video is not connected ...check your design\"\n\t\t}\n\t}\n\tfor {set layer 0} {$layer < $num_layers} {incr layer} {\n\t\tswitch $layer {\n\t\t\t\"0\" {\n\t\t\t\tset mixer_node0 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_master$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node0\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset maxwidth [get_property CONFIG.MAX_COLS [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node0\" \"xlnx,layer-max-width\" $maxwidth int\n\t\t\t\tset maxheight [get_property CONFIG.MAX_ROWS [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node0\" \"xlnx,layer-max-height\" $maxheight int\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node0\" \"xlnx,layer-primary\" \"\" boolean\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip] != 0} {\n\t\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_ip]\n\t\t\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node0 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node0 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node0\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\t\t\t\tset inip [get_in_connect_ip $connected_ip $master_intf]\n\t\t\t\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node0 \"dmas\" \"$inip 0\" reference\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node0 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node0\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset layer0_video_format [get_property CONFIG.VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer0_video_format $mixer_node0 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"1\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer1_alpha [get_property CONFIG.LAYER1_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer1_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer1_maxwidth [get_property CONFIG.LAYER1_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer1_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video1\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_ip]\n\t\t\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\t\t\t\tset inip [get_in_connect_ip $connected_ip $master_intf]\n\t\t\t\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$inip 0\" reference\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER1_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer1_video_format [get_property CONFIG.LAYER1_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer1_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"2\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer2_alpha [get_property CONFIG.LAYER2_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer2_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer2_maxwidth [get_property CONFIG.LAYER2_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer2_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video2\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_ip]\n\t\t\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\t\t\t\tset inip [get_in_connect_ip $connected_ip $master_intf]\n\t\t\t\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$inip 0\" reference\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER2_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer2_video_format [get_property CONFIG.LAYER2_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer2_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"3\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer3_alpha [get_property CONFIG.LAYER3_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer3_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer3_maxwidth [get_property CONFIG.LAYER3_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer3_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video3\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_ip]\n\t\t\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\t\t\t\tset inip [get_in_connect_ip $connected_ip $master_intf]\n\t\t\t\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$inip 0\" reference\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER3_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer3_video_format [get_property CONFIG.LAYER3_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer3_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"4\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer4_alpha [get_property CONFIG.LAYER4_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer4_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer4_maxwidth [get_property CONFIG.LAYER4_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer4_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video4\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_ip]\n\t\t\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\t\t\t\tset inip [get_in_connect_ip $connected_ip $master_intf]\n\t\t\t\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$inip 0\" reference\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER4_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer4_video_format [get_property CONFIG.LAYER4_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer4_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"5\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer5_alpha [get_property CONFIG.LAYER5_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer5_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer5_maxwidth [get_property CONFIG.LAYER5_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer5_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video5\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_ip]\n\t\t\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node0 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node0 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node0\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t\t\tset layer0_video_format [get_property CONFIG.VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\t\t\t\tgen_video_format $layer0_video_format $mixer_node0 $drv_handle $max_data_width\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\t\t\t\tset inip [get_in_connect_ip $connected_ip $master_intf]\n\t\t\t\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$inip 0\" reference\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER5_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer5_video_format [get_property CONFIG.LAYER5_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer5_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"6\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer6_alpha [get_property CONFIG.LAYER6_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer6_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer6_maxwidth [get_property CONFIG.LAYER6_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer6_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video6\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_ip]\n\t\t\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node0 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node0 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node0\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t\t\tset layer0_video_format [get_property CONFIG.VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\t\t\t\tgen_video_format $layer0_video_format $mixer_node0 $drv_handle $max_data_width\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}]\n\t\t\t\t\t\t\tset inip [get_in_connect_ip $connected_ip $master_intf]\n\t\t\t\t\t\t\tif {[llength $inip]} {\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$inip 0\" reference\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER6_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer6_video_format [get_property CONFIG.LAYER6_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer6_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"7\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer7_alpha [get_property CONFIG.LAYER7_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer7_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer7_maxwidth [get_property CONFIG.LAYER7_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer7_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video7\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset connected_ip_type [get_property IP_NAME $connected_ip]\n\t\t\t\t\t\tif {[string match -nocase $connected_ip_type \"system_ila\"]} {\n\t\t\t\t\t\t\tcontinue\n\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER7_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer7_video_format [get_property CONFIG.LAYER7_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer7_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"8\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer8_alpha [get_property CONFIG.LAYER8_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer8_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer8_maxwidth [get_property CONFIG.LAYER8_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer8_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video8\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset connected_ip_type [get_property IP_NAME $connected_ip]\n\t\t\t\t\t\tif {[string match -nocase $connected_ip_type \"system_ila\"]} {\n\t\t\t\t\t\t\tcontinue\n\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER8_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer8_video_format [get_property CONFIG.LAYER8_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer8_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"9\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer9_alpha [get_property CONFIG.LAYER9_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer9_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer9_maxwidth [get_property CONFIG.LAYER9_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer9_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video9\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset connected_ip_type [get_property IP_NAME $connected_ip]\n\t\t\t\t\t\tif {[string match -nocase $connected_ip_type \"system_ila\"]} {\n\t\t\t\t\t\t\tcontinue\n\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER9_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer9_video_format [get_property CONFIG.LAYER9_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer9_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"10\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer10_alpha [get_property CONFIG.LAYER10_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer10_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer10_maxwidth [get_property CONFIG.LAYER10_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer10_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video10\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset connected_ip_type [get_property IP_NAME $connected_ip]\n\t\t\t\t\t\tif {[string match -nocase $connected_ip_type \"system_ila\"]} {\n\t\t\t\t\t\t\tcontinue\n\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER10_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer10_video_format [get_property CONFIG.LAYER10_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer10_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"11\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer11_alpha [get_property CONFIG.LAYER11_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer11_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer11_maxwidth [get_property CONFIG.LAYER11_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer11_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video11\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset connected_ip_type [get_property IP_NAME $connected_ip]\n\t\t\t\t\t\tif {[string match -nocase $connected_ip_type \"system_ila\"]} {\n\t\t\t\t\t\t\tcontinue\n\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER11_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer11_video_format [get_property CONFIG.LAYER11_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer11_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"12\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer12_alpha [get_property CONFIG.LAYER12_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer12_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer12_maxwidth [get_property CONFIG.LAYER12_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer12_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video12\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset connected_ip_type [get_property IP_NAME $connected_ip]\n\t\t\t\t\t\tif {[string match -nocase $connected_ip_type \"system_ila\"]} {\n\t\t\t\t\t\t\tcontinue\n\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER12_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer12_video_format [get_property CONFIG.LAYER12_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer12_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"13\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer13_alpha [get_property CONFIG.LAYER13_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer13_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer13_maxwidth [get_property CONFIG.LAYER13_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer13_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video13\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset connected_ip_type [get_property IP_NAME $connected_ip]\n\t\t\t\t\t\tif {[string match -nocase $connected_ip_type \"system_ila\"]} {\n\t\t\t\t\t\t\tcontinue\n\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER13_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer13_video_format [get_property CONFIG.LAYER13_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer13_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"14\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer14_alpha [get_property CONFIG.LAYER14_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer14_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer14_maxwidth [get_property CONFIG.LAYER14_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer14_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video14\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset connected_ip_type [get_property IP_NAME $connected_ip]\n\t\t\t\t\t\tif {[string match -nocase $connected_ip_type \"system_ila\"]} {\n\t\t\t\t\t\t\tcontinue\n\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER14_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer14_video_format [get_property CONFIG.LAYER14_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer14_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"15\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer15_alpha [get_property CONFIG.LAYER15_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer15_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer15_maxwidth [get_property CONFIG.LAYER15_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer15_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video15\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset connected_ip_type [get_property IP_NAME $connected_ip]\n\t\t\t\t\t\tif {[string match -nocase $connected_ip_type \"v_frmbuf_rd\"]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER15_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer15_video_format [get_property CONFIG.LAYER15_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer15_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\t\"16\" {\n\t\t\t\tset mixer_node1 [add_or_get_dt_node -n \"layer_$layer\" -l xx_mix_overlay_$layer$drv_handle -p $node]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\t\t\t\tset layer16_alpha [get_property CONFIG.LAYER16_ALPHA [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $layer16_alpha \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-alpha\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer16_maxwidth [get_property CONFIG.LAYER16_MAX_WIDTH [get_cells -hier $drv_handle]]\n\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-max-width\" $layer16_maxwidth int\n\t\t\t\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"s_axis_video16\"]\n\t\t\t\tforeach connected_ip $connect_ip {\n\t\t\t\t\tif {[llength $connected_ip]} {\n\t\t\t\t\t\tset connected_ip_type [get_property IP_NAME $connected_ip]\n\t\t\t\t\t\tif {[string match -nocase $connected_ip_type \"system_ila\"]} {\n\t\t\t\t\t\t\tcontinue\n\t\t\t\t\t\t}\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dmas\" \"$connected_ip 0\" reference\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param $mixer_node1 \"dma-names\" \"dma0\" string\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-streaming\" \"\" boolean\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset sample [get_property CONFIG.LAYER16_UPSAMPLE [get_cells -hier $drv_handle]]\n\t\t\t\tif {[string match -nocase $sample \"true\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-scale\" \"\" boolean\n\t\t\t\t}\n\t\t\t\tset layer16_video_format [get_property CONFIG.LAYER16_VIDEO_FORMAT [get_cells -hier $drv_handle]]\n\t\t\t\tgen_video_format $layer16_video_format $mixer_node1 $drv_handle $max_data_width\n\t\t\t}\n\t\t\tdefault {\n\t\t\t}\n\t\t}\n\t}\n\tset mixer_node1 [add_or_get_dt_node -n \"logo\" -l xx_mix_logo$drv_handle -p $node]\n\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,layer-id\" $layer int\n\tset logo_width [get_property CONFIG.MAX_LOGO_COLS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,logo-width\" $logo_width int\n\tset logo_height [get_property CONFIG.MAX_LOGO_ROWS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$mixer_node1\" \"xlnx,logo-height\" $logo_height int\n\tgen_gpio_reset $drv_handle $node\n}\n\nproc gen_video_format {num node drv_handle max_data_width} {\n\tset vid_formats \"\"\n\tswitch $num {\n\t\t\"0\" {\n\t\t\tappend vid_formats \" \" \"BG24\"\n\t\t}\n\t\t\"1\" {\n\t\t\tappend vid_formats \" \" \"YUYV\"\n\t\t}\n\t\t\"2\" {\n\t\t\tif {$max_data_width == 10} {\n\t\t\t\tappend vid_formats \" \" \"XV20\"\n\t\t\t} else {\n\t\t\t\tappend vid_formats \" \" \"NV16\"\n\t\t\t}\n\t\t}\n\t\t\"3\" {\n\t\t\tif {$max_data_width == 10} {\n\t\t\t\tappend vid_formats \" \" \"XV15\"\n\t\t\t} else {\n\t\t\t\tappend vid_formats \" \" \"NV12\"\n\t\t\t}\n\t\t}\n\t\t\"5\" {\n\t\t\tappend vid_formats \" \" \"AB24\"\n\t\t}\n\t\t\"6\" {\n\t\t\tappend vid_formats \" \" \"AVUY\"\n\t\t}\n\t\t\"10\" {\n\t\t\tappend vid_formats \" \" \"XB24\"\n\t\t}\n\t\t\"11\" {\n\t\t\tappend vid_formats \" \" \"XV24\"\n\t\t}\n\t\t\"12\" {\n\t\t\tappend vid_formats \" \" \"YUYV\"\n\t\t}\n\t\t\"13\" {\n\t\t\tappend vid_formats \" \" \"AB24\"\n\t\t}\n\t\t\"14\" {\n\t\t\tappend vid_formats \" \" \"AVUY\"\n\t\t}\n\t\t\"15\" {\n\t\t\tappend vid_formats \" \" \"XB30\"\n\t\t}\n\t\t\"16\" {\n\t\t\tappend vid_formats \" \" \"XV30\"\n\t\t}\n\t\t\"17\" {\n\t\t\tappend vid_formats \" \" \"BG16\"\n\t\t}\n\t\t\"18\" {\n\t\t\tappend vid_formats \" \" \"NV16\"\n\t\t}\n\t\t\"19\" {\n\t\t\tappend vid_formats \" \" \"NV12\"\n\t\t}\n\t\t\"20\" {\n\t\t\tappend vid_formats \" \" \"BG24\"\n\t\t}\n\t\t\"21\" {\n\t\t\tappend vid_formats \" \" \"VU24\"\n\t\t}\n\t\t\"22\" {\n\t\t\tappend vid_formats \" \" \"XV20\"\n\t\t}\n\t\t\"23\" {\n\t\t\tappend vid_formats \" \" \"XV15\"\n\t\t}\n\t\t\"24\" {\n\t\t\tappend vid_formats \" \" \"GREY\"\n\t\t}\n\t\t\"25\" {\n\t\t\tappend vid_formats \" \" \"Y10 \"\n\t\t}\n\t\t\"26\" {\n\t\t\tappend vid_formats \" \" \"AR24\"\n\t\t}\n\t\t\"27\" {\n\t\t\tappend vid_formats \" \" \"XR24\"\n\t\t}\n\t\t\"28\" {\n\t\t\tappend vid_formats \" \" \"UYVY\"\n\t\t}\n\t\t\"29\" {\n\t\t\tappend vid_formats \" \" \"RG24\"\n\t\t}\n\t\tdefault {\n\t\t\tdtg_warning \"Not supported format:$num\"\n\t\t}\n\t}\n\tif {![string match -nocase $vid_formats \"\"]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,vformat\" $vid_formats stringlist\n\t}\n}\n\nproc gen_gpio_reset {drv_handle node} {\n\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] \"ap_rst_n\"]]\n\tforeach pin $pins {\n\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tif {[llength $sink_periph]} {\n\t\t\tset sink_ip [get_property IP_NAME $sink_periph]\n\t\t\tif {[string match -nocase $sink_ip \"xlslice\"]} {\n\t\t\t\tset gpio [get_property CONFIG.DIN_FROM $sink_periph]\n\t\t\t\tset pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph \"Din\"]]]\n\t\t\t\tforeach pin $pins {\n\t\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t\tif {[llength $periph]} {\n\t\t\t\t\t\tset ip [get_property IP_NAME $periph]\n\t\t\t\t\t\tset proc_type [get_sw_proc_prop IP_NAME]\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psv_cortexa72\"] } {\n\t\t\t\t\t\t\tif { $ip in { \"versal_cips\" \"ps_wizard\" }} {\n\t\t\t\t\t\t\t\t# As versal has only one bank0 for MIOs\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 26]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio0 $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n\t\t\t\t\t\t\tif {[string match -nocase $ip \"zynq_ultra_ps_e\"]} {\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 78]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $ip \"axi_gpio\"]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"$periph $gpio 1\" reference\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"$drv_handle:peripheral is NULL for the $pin $periph\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle:peripheral is NULL for the $pin $sink_periph\"\n\t\t}\n\t}\n}\n" }, { "path": "mrmac/data/mrmac.mdd", "content": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver mrmac\n\n OPTION supported_peripherals = (mrmac dcmac);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = mrmac;\n\nEND driver\n" }, { "path": "mrmac/data/mrmac.tcl", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\nproc add_prop_ifexists {drv_handle hsi_prop dt_prop node {dt_prop_type \"string\"}} {\n\tif {[llength $drv_handle] && [llength $hsi_prop] && [llength $dt_prop] && [llength $node]} {\n\t\tset value [get_property $hsi_prop [get_cells -hier $drv_handle]]\n\t\tif {[llength $value]} {\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"$dt_prop\" $value $dt_prop_type\n\t\t}\n\t}\n}\n\nproc fix_clockprop {s_clk rx_clk} {\n\tregsub -all \"\\<&\" $s_clk {} s_clk\n\tregsub -all \"\\<&\" $s_clk {} s_clk\n\tregsub -all \" \" $s_clk \"\" s_clk\n\t# if s_clk and rx_clk not matches and clock not starts\n\t# with <& add it.\n\tset rx_clk [string trim $rx_clk]\n\tif {![string match -nocase \"$s_clk\" $rx_clk] && \\\n\t\t![string match -nocase \"<&*\" \"$rx_clk\"]} {\n\t\tset rx_clk \"<&$rx_clk\"\n\t}\n\treturn \"$s_clk $rx_clk\"\n}\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"mrmac\"]} {\n\t\tset compatible [append compatible \" \" \"xlnx,mrmac-ethernet-1.0\"]\n\t}\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset mrmac_ip [get_cells -hier $drv_handle]\n\tgen_mrmac_clk_property $drv_handle\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n\tset dts_file [current_dt_tree]\n\tset mem_ranges [hsi::utils::get_ip_mem_ranges [get_cells -hier $drv_handle]]\n\tdtg_verbose \"mem_ranges:$mem_ranges\"\n\tforeach mem_range $mem_ranges {\n\t\tset base_addr [string tolower [get_property BASE_VALUE $mem_range]]\n\t\tset base [format %x $base_addr]\n\t\tset high_addr [string tolower [get_property HIGH_VALUE $mem_range]]\n\t\tset slave_intf [get_property SLAVE_INTERFACE $mem_range]\n\t\tdtg_verbose \"slave_intf:$slave_intf\"\n\t\tset ptp_comp \"xlnx,timer-syncer-1588-1.0\"\n\t\tif {[string match -nocase $slave_intf \"ptp_0_s_axi\"]} {\n\t\t\tset ptp_0_node [add_or_get_dt_node -n \"ptp_timer\" -l \"$slave_intf\" -u $base -d $dts_file -p $bus_node]\n\t\t\thsi::utils::add_new_dts_param \"$ptp_0_node\" \"compatible\" \"$ptp_comp\" stringlist\n\t\t\tset reg [generate_reg_property $base_addr $high_addr]\n\t\t\thsi::utils::add_new_dts_param \"$ptp_0_node\" \"reg\" $reg inthexlist\n\t\t}\n\t\tif {[string match -nocase $slave_intf \"ptp_1_s_axi\"]} {\n\t\t\tset ptp_1_node [add_or_get_dt_node -n \"ptp_timer\" -l \"$slave_intf\" -u $base -d $dts_file -p $bus_node]\n\t\t\thsi::utils::add_new_dts_param \"$ptp_1_node\" \"compatible\" \"$ptp_comp\" stringlist\n\t\t\tset reg [generate_reg_property $base_addr $high_addr]\n\t\t\thsi::utils::add_new_dts_param \"$ptp_1_node\" \"reg\" $reg inthexlist\n\t\t}\n\t\tif {[string match -nocase $slave_intf \"ptp_2_s_axi\"]} {\n\t\t\tset ptp_2_node [add_or_get_dt_node -n \"ptp_timer\" -l \"$slave_intf\" -u $base -d $dts_file -p $bus_node]\n\t\t\thsi::utils::add_new_dts_param \"$ptp_2_node\" \"compatible\" \"$ptp_comp\" stringlist\n\t\t\tset reg [generate_reg_property $base_addr $high_addr]\n\t\t\thsi::utils::add_new_dts_param \"$ptp_2_node\" \"reg\" $reg inthexlist\n\t\t}\n\t\tif {[string match -nocase $slave_intf \"ptp_3_s_axi\"]} {\n\t\t\tset ptp_3_node [add_or_get_dt_node -n \"ptp_timer\" -l \"$slave_intf\" -u $base -d $dts_file -p $bus_node]\n\t\t\thsi::utils::add_new_dts_param \"$ptp_3_node\" \"compatible\" \"$ptp_comp\" stringlist\n\t\t\tset reg [generate_reg_property $base_addr $high_addr]\n\t\t\thsi::utils::add_new_dts_param \"$ptp_3_node\" \"reg\" $reg inthexlist\n\t\t}\n\t\tif {[string match -nocase $slave_intf \"s_axi\"]} {\n\t\t\tset mrmac0_highaddr_hex [format 0x%x [expr $base_addr + 0xFFF]]\n\t\t\tset reg [generate_reg_property $base_addr $mrmac0_highaddr_hex]\n\t\t\thsi::utils::add_new_dts_param \"$node\" \"reg\" $reg inthexlist\n\t\t}\n\t}\n\tset connected_ip [get_connected_stream_ip $mrmac_ip \"tx_axis_tdata0\"]\n\n\tadd_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE0_CFG_C0 \"xlnx,flex-slice0-cfg-c0\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE0_CFG_C1 \"xlnx,flex-slice0-cfg-c1\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT0_DATA_RATE_C0 \"xlnx,flex-port0-data-rate-c0\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT0_DATA_RATE_C1 \"xlnx,flex-port0-data-rate-c1\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT0_ENABLE_TIME_STAMPING_C0 \"xlnx,flex-port0-enable-time-stamping-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT0_ENABLE_TIME_STAMPING_C1 \"xlnx,flex-port0-enable-time-stamping-c1\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT0_MODE_C0 \"xlnx,flex-port0-mode-c0\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT0_MODE_C1 \"xlnx,flex-port0-mode-c1\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT0_1588v2_Clocking_C0 \"xlnx,port0-1588v2-clocking-c0\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT0_1588v2_Clocking_C1 \"xlnx,port0-1588v2-clocking-c1\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT0_1588v2_Operation_MODE_C0 \"xlnx,port0-1588v2-operation-mode-c0\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT0_1588v2_Operation_MODE_C1 \"xlnx,port0-1588v2-operation-mode-c1\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_ENABLE_TIME_STAMPING_C0 \"xlnx,mac-port0-enable-time-stamping-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_ENABLE_TIME_STAMPING_C1 \"xlnx,mac-port0-enable-time-stamping-c1\" ${node} int\n\tset MAC_PORT0_RATE_C0 [get_property CONFIG.MAC_PORT0_RATE_C0 [get_cells -hier $drv_handle]]\n\tif { [llength $MAC_PORT0_RATE_C0] } {\n\t\tif {[string match -nocase $MAC_PORT0_RATE_C0 \"10GE\"]} {\n\t\t\tset number 10000\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mrmac-rate\" $number int\n\t\t} else {\n\t\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mrmac-rate\" $MAC_PORT0_RATE_C0 string\n\t\t}\n\t}\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RATE_C1 \"xlnx,mac-port0-rate-c1\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_GCP_C0 \"xlnx,mac-port0-rx-etype-gcp-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_GCP_C1 \"xlnx,mac-port0-rx-etype-gcp-c1\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_GPP_C0 \"xlnx,mac-port0-rx-etype-gpp-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_GPP_C1 \"xlnx,mac-port0-rx-etype-gpp-c1\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_PCP_C0 \"xlnx,mac-port0-rx-etype-pcp-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_PCP_C1 \"xlnx,mac-port0-rx-etype-pcp-c1\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_PPP_C0 \"xlnx,mac-port0-rx-etype-ppp-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_PPP_C1 \"xlnx,mac-port0-rx-etype-ppp-c1\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_FLOW_C0 \"xlnx,mac-port0-rx-flow-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_FLOW_C1 \"xlnx,mac-port0-rx-flow-c1\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_GPP_C0 \"xlnx,mac-port0-rx-opcode-gpp-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_GPP_C1 \"xlnx,mac-port0-rx-opcode-gpp-c1\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MAX_GCP_C0 \"xlnx,mac-port0-rx-opcode-max-gcp-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MAX_GCP_C1 \"xlnx,mac-port0-rx-opcode-max-gcp-c1\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MAX_PCP_C0 \"xlnx,mac-port0-rx-opcode-max-pcp-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MAX_PCP_C1 \"xlnx,mac-port0-rx-opcode-max-pcp-c1\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MIN_GCP_C0 \"xlnx,mac-port0-rx-opcode-min-gcp-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MIN_GCP_C1 \"xlnx,mac-port0-rx-opcode-min-gcp-c1\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MIN_PCP_C0 \"xlnx,mac-port0-rx-opcode-min-pcp-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MIN_PCP_C1 \"xlnx,mac-port0-rx-opcode-min-pcp-c1\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_PPP_C0 \"xlnx,mac-port0-rx-opcode-ppp-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_PPP_C1 \"xlnx,mac-port0-rx-opcode-ppp-c1\" ${node} int\n\tset MAC_PORT0_RX_PAUSE_DA_MCAST_C0 [get_property CONFIG.MAC_PORT0_RX_PAUSE_DA_MCAST_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT0_RX_PAUSE_DA_MCAST_C0 [check_size $MAC_PORT0_RX_PAUSE_DA_MCAST_C0 $node]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mac-port0-rx-pause-da-mcast-c0\" $MAC_PORT0_RX_PAUSE_DA_MCAST_C0 int\n\tset MAC_PORT0_RX_PAUSE_DA_MCAST_C1 [get_property CONFIG.MAC_PORT0_RX_PAUSE_DA_MCAST_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT0_RX_PAUSE_DA_MCAST_C1 [check_size $MAC_PORT0_RX_PAUSE_DA_MCAST_C1 $node]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mac-port0-rx-pause-da-mcast-c1\" $MAC_PORT0_RX_PAUSE_DA_MCAST_C1 int\n\tset MAC_PORT0_RX_PAUSE_DA_UCAST_C0 [get_property CONFIG.MAC_PORT0_RX_PAUSE_DA_UCAST_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT0_RX_PAUSE_DA_UCAST_C0 [check_size $MAC_PORT0_RX_PAUSE_DA_UCAST_C0 $node]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mac-port0-rx-pause-da-ucast-c0\" $MAC_PORT0_RX_PAUSE_DA_UCAST_C0 int\n\tset MAC_PORT0_RX_PAUSE_DA_UCAST_C1 [get_property CONFIG.MAC_PORT0_RX_PAUSE_DA_UCAST_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT0_RX_PAUSE_DA_UCAST_C1 [check_size $MAC_PORT0_RX_PAUSE_DA_UCAST_C1 $node]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mac-port0-rx-pause-da-ucast-c1\" $MAC_PORT0_RX_PAUSE_DA_UCAST_C1 int\n\tset MAC_PORT0_RX_PAUSE_SA_C0 [get_property CONFIG.MAC_PORT0_RX_PAUSE_SA_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT0_RX_PAUSE_SA_C0 [check_size $MAC_PORT0_RX_PAUSE_SA_C0 $node]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mac-port0-rx-pause-sa-c0\" $MAC_PORT0_RX_PAUSE_SA_C0 int\n\tset MAC_PORT0_RX_PAUSE_SA_C1 [get_property CONFIG.MAC_PORT0_RX_PAUSE_SA_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT0_RX_PAUSE_SA_C1 [check_size $MAC_PORT0_RX_PAUSE_SA_C1 $node]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mac-port0-rx-pause-sa-c1\" $MAC_PORT0_RX_PAUSE_SA_C1 int\n\tset MAC_PORT0_TX_DA_GPP_C0 [get_property CONFIG.MAC_PORT0_TX_DA_GPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT0_TX_DA_GPP_C0 [check_size $MAC_PORT0_TX_DA_GPP_C0 $node]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mac-port0-tx-da-gpp-c0\" $MAC_PORT0_TX_DA_GPP_C0 int\n\tset MAC_PORT0_TX_DA_GPP_C1 [get_property CONFIG.MAC_PORT0_TX_DA_GPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT0_TX_DA_GPP_C1 [check_size $MAC_PORT0_TX_DA_GPP_C1 $node]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mac-port0-tx-da-gpp-c1\" $MAC_PORT0_TX_DA_GPP_C1 int\n\tset MAC_PORT0_TX_DA_PPP_C0 [get_property CONFIG.MAC_PORT0_TX_DA_PPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT0_TX_DA_PPP_C0 [check_size $MAC_PORT0_TX_DA_PPP_C0 $node]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mac-port0-tx-da-ppp-c0\" $MAC_PORT0_TX_DA_PPP_C0 int\n\tset MAC_PORT0_TX_DA_PPP_C1 [get_property CONFIG.MAC_PORT0_TX_DA_PPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT0_TX_DA_PPP_C1 [check_size $MAC_PORT0_TX_DA_PPP_C1 $node]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mac-port0-tx-da-ppp-c1\" $MAC_PORT0_TX_DA_PPP_C1 int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_ETHERTYPE_GPP_C0 \"xlnx,mac-port0-tx-ethertype-gpp-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_ETHERTYPE_GPP_C1 \"xlnx,mac-port0-tx-ethertype-gpp-c1\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_ETHERTYPE_PPP_C0 \"xlnx,mac-port0-tx-ethertype-ppp-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_ETHERTYPE_PPP_C1 \"xlnx,mac-port0-tx-ethertype-ppp-c1\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_FLOW_C0 \"xlnx,mac-port0-tx-flow-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_FLOW_C1 \"xlnx,mac-port0-tx-flow-c1\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_OPCODE_GPP_C0 \"xlnx,mac-port0-tx-opcode-gpp-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_OPCODE_GPP_C1 \"xlnx,mac-port0-tx-opcode-gpp-c1\" ${node} int\n\tset MAC_PORT0_TX_SA_GPP_C0 [get_property CONFIG.MAC_PORT0_TX_SA_GPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT0_TX_SA_GPP_C0 [check_size $MAC_PORT0_TX_SA_GPP_C0 $node]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mac-port0-tx-sa-gpp-c0\" $MAC_PORT0_TX_SA_GPP_C0 int\n\tset MAC_PORT0_TX_SA_GPP_C1 [get_property CONFIG.MAC_PORT0_TX_SA_GPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT0_TX_SA_GPP_C1 [check_size $MAC_PORT0_TX_SA_GPP_C1 $node]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mac-port0-tx-sa-gpp-c1\" $MAC_PORT0_TX_SA_GPP_C1 int\n\tset MAC_PORT0_TX_SA_PPP_C0 [get_property CONFIG.MAC_PORT0_TX_SA_PPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT0_TX_SA_PPP_C0 [check_size $MAC_PORT0_TX_SA_PPP_C0 $node]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mac-port0-tx-sa-ppp-c0\" $MAC_PORT0_TX_SA_PPP_C0 int\n\tset MAC_PORT0_TX_SA_PPP_C1 [get_property CONFIG.MAC_PORT0_TX_SA_PPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT0_TX_SA_PPP_C1 [check_size $MAC_PORT0_TX_SA_PPP_C1 $node]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,mac-port0-tx-sa-ppp-c1\" $MAC_PORT0_TX_SA_PPP_C1 int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RXPROGDIV_FREQ_ENABLE_C0 \"xlnx,gt-ch0-rxprogdiv-freq-enable-c0\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RXPROGDIV_FREQ_ENABLE_C1 \"xlnx,gt-ch0-rxprogdiv-freq-enable-c1\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RXPROGDIV_FREQ_SOURCE_C0 \"xlnx,gt-ch0-rxprogdiv-freq-source-c0\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RXPROGDIV_FREQ_SOURCE_C1 \"xlnx,gt-ch0-rxprogdiv-freq-source-c1\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RXPROGDIV_FREQ_VAL_C0 \"xlnx,gt-ch0-rxprogdiv-freq-val-c0\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RXPROGDIV_FREQ_VAL_C1 \"xlnx,gt-ch0-rxprogdiv-freq-val-c1\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_BUFFER_MODE_C0 \"xlnx,gt-ch0-rx-buffer-mode-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_BUFFER_MODE_C1 \"xlnx,gt-ch0-rx-buffer-mode-c1\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_DATA_DECODING_C0 \"xlnx,gt-ch0-rx-data-decoding-c0\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_DATA_DECODING_C1 \"xlnx,gt-ch0-rx-data-decoding-c1\" ${node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_INT_DATA_WIDTH_C0 \"xlnx,gt-ch0-rx-int-data-width-c0\" ${node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_INT_DATA_WIDTH_C1 \"xlnx,gt-ch0-rx-int-data-width-c1\" ${node} int\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_LINE_RATE_C0 \"xlnx,gt-ch0-rx-line-rate-c0\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_LINE_RATE_C1 \"xlnx,gt-ch0-rx-line-rate-c1\" ${node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_OUTCLK_SOURCE_C0 \"xlnx,gt-ch0-rx-outclk-source-c0\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_OUTCLK_SOURCE_C1 \"xlnx,gt-ch0-rx-outclk-source-c1\" ${node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_REFCLK_FREQUENCY_C0 \"xlnx,gt-ch0-rx-refclk-frequency-c0\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_REFCLK_FREQUENCY_C1 \"xlnx,gt-ch0-rx-refclk-frequency-c1\" ${node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_USER_DATA_WIDTH_C0 \"xlnx,gt-ch0-rx-user-data-width-c0\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_USER_DATA_WIDTH_C1 \"xlnx,gt-ch0-rx-user-data-width-c1\" ${node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_TXPROGDIV_FREQ_ENABLE_C0 \"xlnx,gt-ch0-txprogdiv-freq-enable-c0\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_TXPROGDIV_FREQ_ENABLE_C1 \"xlnx,gt-ch0-txprogdiv-freq-enable-c1\" ${node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_TXPROGDIV_FREQ_SOURCE_C0 \"xlnx,gt-ch0-txprogdiv-freq-source-c0\" ${node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH0_TXPROGDIV_FREQ_SOURCE_C1 \"xlnx,gt-ch0-txprogdiv-freq-source-c1\" ${node}\n\n\tset mrmac_clk_names [get_property CONFIG.zclock-names1 $drv_handle]\n\tset mrmac_clks [get_property CONFIG.zclocks1 $drv_handle]\n\tset mrmac_clkname_len [llength $mrmac_clk_names]\n\tset mrmac_clk_len [expr {[llength [split $mrmac_clks \",\"]]}]\n\tset clk_list [split $mrmac_clks \",\"]\n\tset null \"\"\n\tset_drv_prop $drv_handle \"zclock-names1\" $null stringlist\n\tset refs \"\"\n\tset_drv_prop $drv_handle \"zclocks1\" \"$refs\" stringlist\n\n\tset i 0\n\twhile {$i < $mrmac_clkname_len} {\n\t\tset clkname [lindex $mrmac_clk_names $i]\n\t\tif {[string match -nocase $clkname \"s_axi_aclk\"]} {\n\t\t\tset s_axi_aclk \"s_axi_aclk\"\n\t\t\tset s_axi_aclk_index0 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"rx_macif_clk\"]} {\n\t\t\tset rx_macif_clk \"rx_macif_clk\"\n\t\t\tset rx_macif_clk_index0 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_macif_clk\"]} {\n\t\t\tset tx_macif_clk \"tx_macif_clk\"\n\t\t\tset tx_macif_clk_index0 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"ts_clk0\"]} {\n\t\t\tset ts_clk0 \"ts_clk\"\n\t\t\tset ts_clk_index0 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"ts_clk1\"]} {\n\t\t\tset ts_clk1 \"ts_clk\"\n\t\t\tset ts_clk_index1 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"ts_clk2\"]} {\n\t\t\tset ts_clk2 \"ts_clk\"\n\t\t\tset ts_clk_index2 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"ts_clk3\"]} {\n\t\t\tset ts_clk3 \"ts_clk\"\n\t\t\tset ts_clk_index3 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_serdes_clk0\"]} {\n\t\t\tset tx_serdes_clk0 \"tx_serdes_clk\"\n\t\t\tset tx_serdes_clk_index0 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_serdes_clk1\"]} {\n\t\t\tset tx_serdes_clk1 \"tx_serdes_clk\"\n\t\t\tset tx_serdes_clk_index1 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_serdes_clk2\"]} {\n\t\t\tset tx_serdes_clk2 \"tx_serdes_clk\"\n\t\t\tset tx_serdes_clk_index2 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_serdes_clk3\"]} {\n\t\t\tset tx_serdes_clk3 \"tx_serdes_clk\"\n\t\t\tset tx_serdes_clk_index3 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"rx_axi_clk0\"] || [string match -nocase $clkname \"rx_axi_clk\"]} {\n\t\t\tset rx_axi_clk0 \"rx_axi_clk\"\n\t\t\tset rx_axi_clk_index0 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"rx_axi_clk1\"]} {\n\t\t\tset rx_axi_clk1 \"rx_axi_clk\"\n\t\t\tset rx_axi_clk_index1 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"rx_axi_clk2\"]} {\n\t\t\tset rx_axi_clk2 \"rx_axi_clk\"\n\t\t\tset rx_axi_clk_index2 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"rx_axi_clk3\"]} {\n\t\t\tset rx_axi_clk3 \"rx_axi_clk\"\n\t\t\tset rx_axi_clk_index3 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"rx_flexif_clk0\"]} {\n\t\t\tset rx_flexif_clk0 \"rx_flexif_clk\"\n\t\t\tset rx_flexif_clk_index0 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"rx_flexif_clk1\"]} {\n\t\t\tset rx_flexif_clk1 \"rx_flexif_clk\"\n\t\t\tset rx_flexif_clk_index1 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"rx_flexif_clk2\"]} {\n\t\t\tset rx_flexif_clk2 \"rx_flexif_clk\"\n\t\t\tset rx_flexif_clk_index2 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"rx_flexif_clk3\"]} {\n\t\t\tset rx_flexif_clk3 \"rx_flexif_clk\"\n\t\t\tset rx_flexif_clk_index3 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"rx_ts_clk0\"]} {\n\t\t\tset rx_ts_clk0 \"rx_ts_clk\"\n\t\t\tset rx_ts_clk0_index0 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"rx_ts_clk1\"]} {\n\t\t\tset rx_ts_clk1 \"rx_ts_clk\"\n\t\t\tset rx_ts_clk1_index1 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"rx_ts_clk2\"]} {\n\t\t\tset rx_ts_clk2 \"rx_ts_clk\"\n\t\t\tset rx_ts_clk2_index2 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"rx_ts_clk3\"]} {\n\t\t\tset rx_ts_clk3 \"rx_ts_clk\"\n\t\t\tset rx_ts_clk3_index3 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_axi_clk0\"] || [string match -nocase $clkname \"tx_axi_clk\"] } {\n\t\t\tset tx_axi_clk0 \"tx_axi_clk\"\n\t\t\tset tx_axi_clk_index0 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_axi_clk1\"]} {\n\t\t\tset tx_axi_clk1 \"tx_axi_clk\"\n\t\t\tset tx_axi_clk_index1 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_axi_clk2\"]} {\n\t\t\tset tx_axi_clk2 \"tx_axi_clk\"\n\t\t\tset tx_axi_clk_index2 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_axi_clk3\"]} {\n\t\t\tset tx_axi_clk3 \"tx_axi_clk\"\n\t\t\tset tx_axi_clk_index3 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_flexif_clk0\"]} {\n\t\t\tset tx_flexif_clk0 \"tx_flexif_clk\"\n\t\t\tset tx_flexif_clk_index0 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_flexif_clk1\"]} {\n\t\t\tset tx_flexif_clk1 \"tx_flexif_clk\"\n\t\t\tset tx_flexif_clk_index1 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_flexif_clk2\"]} {\n\t\t\tset tx_flexif_clk2 \"tx_flexif_clk\"\n\t\t\tset tx_flexif_clk_index2 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_flexif_clk3\"]} {\n\t\t\tset tx_flexif_clk3 \"tx_flexif_clk\"\n\t\t\tset tx_flexif_clk_index3 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_ts_clk0\"]} {\n\t\t\tset tx_ts_clk0 \"tx_ts_clk\"\n\t\t\tset tx_ts_clk_index0 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_ts_clk1\"]} {\n\t\t\tset tx_ts_clk1 \"tx_ts_clk\"\n\t\t\tset tx_ts_clk_index1 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_ts_clk2\"]} {\n\t\t\tset tx_ts_clk2 \"tx_ts_clk\"\n\t\t\tset tx_ts_clk_index2 $i\n\t\t}\n\t\tif {[string match -nocase $clkname \"tx_ts_clk3\"]} {\n\t\t\tset tx_ts_clk3 \"tx_ts_clk\"\n\t\t\tset tx_ts_clk_index3 $i\n\t\t}\n\t\tincr i\n\t}\n\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"mrmac\"]} {\n\t\tlappend clknames \"$s_axi_aclk\" \"$rx_axi_clk0\" \"$rx_flexif_clk0\" \"$rx_ts_clk0\" \"$tx_axi_clk0\" \"$tx_flexif_clk0\" \"$tx_ts_clk0\"\n\t\tset tmpclks0 [fix_clockprop \"[lindex $clk_list $s_axi_aclk_index0]\" \"[lindex $clk_list $rx_axi_clk_index0]\"]\n\t\tset txindex0 [lindex $clk_list $tx_ts_clk_index0]\n\t\tregsub -all \"\\>\" $txindex0 {} txindex0\n\t\tappend clkvals0 \"[lindex $tmpclks0 0], [lindex $tmpclks0 1], [lindex $clk_list $rx_flexif_clk_index0], [lindex $clk_list $rx_ts_clk0_index0], [lindex $clk_list $tx_axi_clk_index0], [lindex $clk_list $tx_flexif_clk_index0], $txindex0\"\n\t\thsi::utils::add_new_dts_param \"${node}\" \"clocks\" $clkvals0 reference\n\t\thsi::utils::add_new_dts_param \"${node}\" \"clock-names\" $clknames stringlist\n\t}\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"dcmac\"]} {\n\t\tlappend clknames \"$s_axi_aclk\" \"$rx_axi_clk0\" \"$rx_flexif_clk0\" \"$tx_axi_clk0\" \"$tx_flexif_clk0\" \"$rx_macif_clk\" \"$ts_clk0\" \"$tx_macif_clk\" \"$tx_serdes_clk0\"\n\t\tset tmpclks0 [fix_clockprop \"[lindex $clk_list $s_axi_aclk_index0]\" \"[lindex $clk_list $rx_axi_clk_index0]\"]\n\t\tset txindex0 [lindex $clk_list $tx_serdes_clk_index0]\n\t\tregsub -all \"\\>\" $txindex0 {} txindex0\n\t\tappend clkvals0 \"[lindex $tmpclks0 0], [lindex $tmpclks0 1], [lindex $clk_list $rx_flexif_clk_index0], [lindex $clk_list $tx_axi_clk_index0], [lindex $clk_list $tx_flexif_clk_index0], [lindex $clk_list $rx_macif_clk_index0], [lindex $clk_list $ts_clk_index0], [lindex $clk_list $tx_macif_clk_index0], $txindex0\"\n\t\thsi::utils::add_new_dts_param \"${node}\" \"clocks\" $clkvals0 reference\n\t\thsi::utils::add_new_dts_param \"${node}\" \"clock-names\" $clknames stringlist\n\t}\n\tset port0_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"rx_axis_tdata0\"]]\n\tdtg_verbose \"port0_pins:$port0_pins\"\n\tforeach pin $port0_pins {\n\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tset mux_ip \"\"\n\t\tset fifo_ip \"\"\n\t\tif {[llength $sink_periph]} {\n\t\t\tif {[string match -nocase [get_property IP_NAME $sink_periph] \"dcmac_intf_rx\"]} {\n\t\t\t\tset sink_periph [hsi::utils::get_connected_stream_ip [get_cells -hier $sink_periph] \"M_AXIS\"]\n\t\t\t}\n\t\t\tif {[string match -nocase [get_property IP_NAME $sink_periph] \"axis_data_fifo\"]} {\n\t\t\t\tset fifo_width_bytes [get_property CONFIG.TDATA_NUM_BYTES $sink_periph]\n\t\t\t\tif {[string_is_empty $fifo_width_bytes]} {\n\t\t\t\t\tset fifo_width_bytes 1\n\t\t\t\t}\n\t\t\t\tset rxethmem [get_property CONFIG.FIFO_DEPTH $sink_periph]\n\t\t\t\t# FIFO can be other than 8 bits, and we need the rxmem in bytes\n\t\t\t\tset rxethmem [expr $rxethmem * $fifo_width_bytes]\n\t\t\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,rxmem\" $rxethmem int\n\t\t\t\tset fifo_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $sink_periph] \"m_axis_tdata\"]]\n\t\t\t\tset mux_per [::hsi::get_cells -of_objects $fifo_pin]\n\t\t\t\tset fiforx_connect_ip \"\"\n\t\t\t\tif {[llength $mux_per] && [string match -nocase [get_property IP_NAME $mux_per] \"mrmac_10g_mux\"]} {\n\t\t\t\t\tset data_fifo_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mux_per] \"rx_m_axis_tdata\"]]\n\t\t\t\t\tset data_fifo_per [::hsi::get_cells -of_objects $data_fifo_pin]\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $data_fifo_per] \"axis_data_fifo\"]} {\n\t\t\t\t\t\tset fiforx_connect_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $data_fifo_per] \"M_AXIS\"]\n\t\t\t\t\t\tdtg_verbose \"fiforx_connect_ip:$fiforx_connect_ip\"\n\t\t\t\t\t\tset fiforx_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $data_fifo_per] \"m_axis_tdata\"]]\n\t\t\t\t\t\tif {[llength $fiforx_pin]} {\n\t\t\t\t\t\t\tset fiforx_per [::hsi::get_cells -of_objects $fiforx_pin]\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[llength $fiforx_per]} {\n\t\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $fiforx_per] \"RX_PTP_PKT_DETECT_TS_PREPEND\"]} {\n\t\t\t\t\t\t\t\tset fiforx_connect_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $fiforx_per] \"M_AXIS\"]\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $mux_per] \"axi_mcdma\"]} {\n\t\t\t\t\tset fiforx_connect_ip $mux_per\n\t\t\t\t}\n\t\t\t\tif {[llength $fiforx_connect_ip]} {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $fiforx_connect_ip] \"axi_mcdma\"]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"axistream-connected\" \"$fiforx_connect_ip\" reference\n\t\t\t\t\t\tset num_queues [get_property CONFIG.c_num_mm2s_channels $fiforx_connect_ip]\n\t\t\t\t\t\tset inhex [format %x $num_queues]\n\t\t\t\t\t\tappend numqueues \"/bits/ 16 <0x$inhex>\"\n\t\t\t\t\t\thsi::utils::add_new_dts_param $node \"xlnx,num-queues\" $numqueues noformating\n\t\t\t\t\t\tset id 1\n\t\t\t\t\t\tfor {set i 2} {$i <= $num_queues} {incr i} {\n\t\t\t\t\t\t\tset i [format \"%\" $i]\n\t\t\t\t\t\t\tappend id \"\\\"\"\n\t\t\t\t\t\t\tappend id \",\\\"\" $i\n\t\t\t\t\t\t\tset i [expr 0x$i]\n\t\t\t\t\t\t}\n\t\t\t\t\t\thsi::utils::add_new_dts_param $node \"xlnx,num-queues\" $numqueues noformating\n\t\t\t\t\t\thsi::utils::add_new_dts_param $node \"xlnx,channel-ids\" $id stringlist\n\t\t\t\t\t\tgenerate_intr_info $drv_handle $node $fiforx_connect_ip\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t#set port0_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"tx_timestamp_tod_0\"]]\n\tset port0_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"tx_ptp_tstamp_tag_out_0\"]]\n\tdtg_verbose \"port0_pins:$port0_pins\"\n\n\tif {[llength $port0_pins]} {\n\t\tset sink_periph [::hsi::get_cells -of_objects $port0_pins]\n\t\tif {[llength $sink_periph]} {\n\t\t\tif {[string match -nocase [get_property IP_NAME $sink_periph] \"mrmac_ptp_timestamp_if\"]} {\n\t\t\t\tset port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $sink_periph] \"tx_timestamp_tod\"]]\n\t\t\t\tset sink_periph [::hsi::get_cells -of_objects $port_pins]\n\t\t\t}\n\t\t}\n\t\tif {[llength $sink_periph] && [string match -nocase [get_property IP_NAME $sink_periph] \"xlconcat\"]} {\n\t\t\tset intf \"dout\"\n\t\t\tset intr1_pin [::hsi::get_pins -of_objects $sink_periph -filter \"NAME==$intf\"]\n\t\t\tset sink_pins [::hsi::utils::get_sink_pins $intr1_pin]\n\t\t\tset xl_per \"\"\n\t\t\tif {[llength $sink_pins]} {\n\t\t\t\tset xl_per [::hsi::get_cells -of_objects $sink_pins]\n\t\t\t}\n\t\t\tif {[llength $xl_per] && [string match -nocase [get_property IP_NAME $xl_per] \"axis_dwidth_converter\"]} {\n\t\t\t\tset port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $xl_per] \"m_axis_tdata\"]]\n\t\t\t\tset axis_per [::hsi::get_cells -of_objects $port_pins]\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $axis_per] \"axis_clock_converter\"]} {\n\t\t\t\t\tset tx_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $axis_per] \"M_AXIS\"]\n\t\t\t\t\tif {[llength $tx_ip]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"axififo-connected\" $tx_ip reference\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else {\n\t\tdtg_warning \"tx_timestamp_tod_0 connected pins are NULL...please check the design...\"\n\t}\n\n\t#set rxtod_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"rx_timestamp_tod_0\"]]\n\tset rxtod_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"rx_ptp_tstamp_out_0\"]]\n\tdtg_verbose \"rxtod_pins:$rxtod_pins\"\n\tif {[llength $rxtod_pins]} {\n\t\tset rx_periph [::hsi::get_cells -of_objects $rxtod_pins]\n\t\tif {[llength $rx_periph]} {\n\t\t\tif {[string match -nocase [get_property IP_NAME $rx_periph] \"mrmac_ptp_timestamp_if\"]} {\n\t\t\t\tset port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rx_periph] \"rx_timestamp_tod\"]]\n\t\t\t\tset rx_periph [::hsi::get_cells -of_objects $port_pins]\n\t\t\t}\n\t\t}\n\t\tif {[llength $rx_periph] && [string match -nocase [get_property IP_NAME $rx_periph] \"xlconcat\"]} {\n\t\t\tset intf \"dout\"\n\t\t\tset in1_pin [::hsi::get_pins -of_objects $rx_periph -filter \"NAME==$intf\"]\n\t\t\tset sink_pins [::hsi::utils::get_sink_pins $in1_pin]\n\t\t\tset rxxl_per \"\"\n\t\t\tif {[llength $sink_pins]} {\n\t\t\t\tset rxxl_per [::hsi::get_cells -of_objects $sink_pins]\n\t\t\t}\n\t\t\tif {[llength $rxxl_per] && [string match -nocase [get_property IP_NAME $rxxl_per] \"axis_dwidth_converter\"]} {\n\t\t\t\tset port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rxxl_per] \"m_axis_tdata\"]]\n\t\t\t\tset rx_axis_per [::hsi::get_cells -of_objects $port_pins]\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $rx_axis_per] \"axis_clock_converter\"]} {\n\t\t\t\t\tset rx_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $rx_axis_per] \"M_AXIS\"]\n\t\t\t\t\tif {[llength $rx_ip]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,rxtsfifo\" $rx_ip reference\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else {\n\t\tdtg_warning \"rx_timestamp_tod_0 connected pins are NULL...please check the design...\"\n\t}\n\n\tset handle \"\"\n\tset mask_handle \"\"\n\tset ips [get_cells -hier -filter {IP_NAME == \"axi_gpio\"}]\n\tforeach ip $ips {\n\t\tset mem_ranges [hsi::utils::get_ip_mem_ranges [get_cells -hier $ip]]\n\t\tforeach mem_range $mem_ranges {\n\t\t\tset base [string tolower [get_property BASE_VALUE $mem_range]]\n\t\t\tif {[string match -nocase $base \"0xa4010000\"]} {\n\t\t\t\tset handle $ip\n\t\t\t\tbreak\n\t\t\t}\n\t\t}\n\t}\n\tif {[llength $handle]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,gtctrl\" $handle reference\n\t}\n\t# Workaround: For gtpll we might need to add the below code for v0.1 version.\n\t# We can remove this workaround for later versions.\n\tforeach ip $ips {\n\t\tset mem_ranges [hsi::utils::get_ip_mem_ranges [get_cells -hier $ip]]\n\t\tforeach mem_range $mem_ranges {\n\t\t\tset base [string tolower [get_property BASE_VALUE $mem_range]]\n\t\t\tif {[string match -nocase $base \"0xa4000000\"]} {\n\t\t\t\tset mask_handle $ip\n\t\t\t\tbreak\n\t\t\t}\n\t\t}\n\t}\n\tif {[llength $mask_handle]} {\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,gtpll\" $mask_handle reference\n\t}\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,phcindex\" 0 int\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,gtlane\" 0 int\n\n\tset gt_reset_pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"gt_reset_all_in\"]]\n\tdtg_verbose \"gt_reset_pins:$gt_reset_pins\"\n\tset gt_reset_per \"\"\n\tif {[llength $gt_reset_pins]} {\n\t\tset gt_reset_periph [::hsi::get_cells -of_objects $gt_reset_pins]\n\t\tif {[llength $gt_reset_periph] && [string match -nocase [get_property IP_NAME $gt_reset_periph] \"xlconcat\"]} {\n\t\t\tset intf \"In0\"\n\t\t\tset in1_pin [::hsi::get_pins -of_objects $gt_reset_periph -filter \"NAME==$intf\"]\n\t\t\tset sink_pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $gt_reset_periph] $in1_pin]]\n\t\t\tset gt_per [::hsi::get_cells -of_objects $sink_pins]\n\t\t\tif {[string match -nocase [get_property IP_NAME $gt_per] \"xlslice\"]} {\n\t\t\t\tset intf \"Din\"\n\t\t\t\tset in1_pin [::hsi::get_pins -of_objects $gt_per -filter \"NAME==$intf\"]\n\t\t\t\tset sink_pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $gt_per] $in1_pin]]\n\t\t\t\tset gt_reset_per [::hsi::get_cells -of_objects $sink_pins]\n\t\t\t\tdtg_verbose \"gt_reset_per:$gt_reset_per\"\n\t\t\t\tif {[llength $gt_reset_per]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,gtctrl\" $gt_reset_per reference\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tset gt_pll_pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"mst_rx_resetdone_in\"]]\n\tdtg_verbose \"gt_pll_pins:$gt_pll_pins\"\n\tset gt_pll_per \"\"\n if {[llength $gt_pll_pins]} {\n set gt_pll_periph [::hsi::get_cells -of_objects $gt_pll_pins]\n if {[llength $gt_pll_periph] && [string match -nocase [get_property IP_NAME $gt_pll_periph] \"xlconcat\"]} {\n set intf \"dout\"\n set in1_pin [::hsi::get_pins -of_objects $gt_pll_periph -filter \"NAME==$intf\"]\n set sink_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $gt_pll_periph] $in1_pin]]\n foreach pin $sink_pins {\n if {[string match -nocase $pin \"In0\"]} {\n set gt_per [::hsi::get_cells -of_objects $sink_pins]\n foreach per $gt_per {\n if {[string match -nocase [get_property IP_NAME $per] \"xlconcat\"]} {\n set intf \"dout\"\n set in1_pin [::hsi::get_pins -of_objects $per -filter \"NAME==$intf\"]\n set sink_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $per] $in1_pin]]\n if {[llength $sink_pins]} {\n set gt_pll_per [::hsi::get_cells -of_objects $sink_pins]\n dtg_verbose \"gt_pll_per:$gt_pll_per\"\n if {[llength $gt_pll_per]} {\n hsi::utils::add_new_dts_param \"$node\" \"xlnx,gtpll\" $gt_pll_per reference\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n\tset dts_file [current_dt_tree]\n\tset mrmac1_base [format 0x%x [expr $base_addr + 0x1000]]\n\tset mrmac1_base_hex [format %x $mrmac1_base]\n\tset mrmac1_highaddr_hex [format 0x%x [expr $mrmac1_base + 0xFFF]]\n\tset port1 1\n\tappend new_label $drv_handle \"_\" $port1\n\tset node_prefix [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tset mrmac1_node [add_or_get_dt_node -n $node_prefix -l \"$new_label\" -u $mrmac1_base_hex -d $dts_file -p $bus_node]\n\thsi::utils::add_new_dts_param \"$mrmac1_node\" \"compatible\" \"$compatible\" stringlist\n\tset mrmac1_reg [generate_reg_property $mrmac1_base $mrmac1_highaddr_hex]\n\thsi::utils::add_new_dts_param \"$mrmac1_node\" \"reg\" $mrmac1_reg inthexlist\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"mrmac\"]} {\n\t\tlappend clknames1 \"$s_axi_aclk\" \"$rx_axi_clk1\" \"$rx_flexif_clk1\" \"$rx_ts_clk1\" \"$tx_axi_clk1\" \"$tx_flexif_clk1\" \"$tx_ts_clk1\"\n\t\tset tmpclks1 [fix_clockprop \"[lindex $clk_list $s_axi_aclk_index0]\" \"[lindex $clk_list $rx_axi_clk_index1]\"]\n\t\tset txindex1 [lindex $clk_list $tx_ts_clk_index1]\n\t\tregsub -all \"\\>\" $txindex1 {} txindex1\n\t\tappend clkvals \"[lindex $tmpclks1 0], [lindex $tmpclks1 1], [lindex $clk_list $rx_flexif_clk_index1], [lindex $clk_list $rx_ts_clk1_index1], [lindex $clk_list $tx_axi_clk_index1], [lindex $clk_list $tx_flexif_clk_index1], $txindex1\"\n\t\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"clocks\" $clkvals reference\n\t\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"clock-names\" $clknames1 stringlist\n\t}\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"dcmac\"]} {\n\t\tlappend clknames1 \"$s_axi_aclk\" \"$rx_axi_clk0\" \"$rx_flexif_clk1\" \"$tx_axi_clk0\" \"$tx_flexif_clk1\" \"$rx_macif_clk\" \"$ts_clk1\" \"$tx_macif_clk\" \"$tx_serdes_clk1\"\n\t\tset tmpclks1 [fix_clockprop \"[lindex $clk_list $s_axi_aclk_index0]\" \"[lindex $clk_list $rx_axi_clk_index0]\"]\n\t\tset txindex1 [lindex $clk_list $tx_serdes_clk_index1]\n\t\tregsub -all \"\\>\" $txindex1 {} txindex1\n\t\tappend clkvals \"[lindex $tmpclks1 0], [lindex $tmpclks1 1], [lindex $clk_list $rx_flexif_clk_index1], [lindex $clk_list $tx_axi_clk_index0], [lindex $clk_list $tx_flexif_clk_index1], [lindex $clk_list $rx_macif_clk_index0], [lindex $clk_list $ts_clk_index1], [lindex $clk_list $tx_macif_clk_index0], $txindex1\"\n\t\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"clocks\" $clkvals reference\n\t\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"clock-names\" $clknames1 stringlist\n\t}\n\tset port1_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"rx_axis_tdata2\"]]\n\tdtg_verbose \"port1_pins:$port1_pins\"\n\tforeach pin $port1_pins {\n\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tset mux_ip \"\"\n\t\tset fifo_ip \"\"\n\t\tif {[llength $sink_periph]} {\n\t\t\tif {[string match -nocase [get_property IP_NAME $sink_periph] \"dcmac_intf_rx\"]} {\n\t\t\t\tset sink_periph [hsi::utils::get_connected_stream_ip [get_cells -hier $sink_periph] \"M_AXIS\"]\n\t\t\t}\n\t\t\tif {[string match -nocase [get_property IP_NAME $sink_periph] \"axis_data_fifo\"]} {\n\t\t\t\tset fifo_width_bytes [get_property CONFIG.TDATA_NUM_BYTES $sink_periph]\n\t\t\t\tif {[string_is_empty $fifo_width_bytes]} {\n\t\t\t\t\tset fifo_width_bytes 1\n\t\t\t\t}\n\t\t\t\tset rxethmem [get_property CONFIG.FIFO_DEPTH $sink_periph]\n\t\t\t\t# FIFO can be other than 8 bits, and we need the rxmem in bytes\n\t\t\t\tset rxethmem [expr $rxethmem * $fifo_width_bytes]\n\t\t\t\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,rxmem\" $rxethmem int\n\t\t\t\tset fifo1_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $sink_periph] \"m_axis_tdata\"]]\n\t\t\t\tset mux_per1 [::hsi::get_cells -of_objects $fifo1_pin]\n\t\t\t\tset fiforx_connect_ip1 \"\"\n\t\t\t\tif {[llength $mux_per1] && [string match -nocase [get_property IP_NAME $mux_per1] \"mrmac_10g_mux\"]} {\n\t\t\t\t\tset data_fifo_pin1 [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mux_per1] \"rx_m_axis_tdata\"]]\n\t\t\t\t\tset data_fifo_per1 [::hsi::get_cells -of_objects $data_fifo_pin1]\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $data_fifo_per1] \"axis_data_fifo\"]} {\n\t\t\t\t\t\tset fiforx_connect_ip1 [hsi::utils::get_connected_stream_ip [get_cells -hier $data_fifo_per1] \"M_AXIS\"]\n\t\t\t\t\t\tset fiforx1_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $data_fifo_per1] \"m_axis_tdata\"]]\n\t\t\t\t\t\tif {[llength $fiforx1_pin]} {\n\t\t\t\t\t\t\tset fiforx1_per [::hsi::get_cells -of_objects $fiforx1_pin]\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[llength $fiforx1_per]} {\n\t\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $fiforx1_per] \"RX_PTP_PKT_DETECT_TS_PREPEND\"]} {\n\t\t\t\t\t\t\t\tset fiforx_connect_ip1 [hsi::utils::get_connected_stream_ip [get_cells -hier $fiforx1_per] \"M_AXIS\"]\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $mux_per1] \"axi_mcdma\"]} {\n\t\t\t\t\tset fiforx_connect_ip1 $mux_per1\n\t\t\t\t}\n\t\t\t\tif {[llength $fiforx_connect_ip1]} {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $fiforx_connect_ip1] \"axi_mcdma\"]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mrmac1_node\" \"axistream-connected\" \"$fiforx_connect_ip1\" reference\n\t\t\t\t\t\tset num_queues [get_property CONFIG.c_num_mm2s_channels $fiforx_connect_ip1]\n\t\t\t\t\t\tset inhex [format %x $num_queues]\n\t\t\t\t\t\tappend numqueues1 \"/bits/ 16 <0x$inhex>\"\n\t\t\t\t\t\thsi::utils::add_new_dts_param $mrmac1_node \"xlnx,num-queues\" $numqueues1 noformating\n\t\t\t\t\t\tset id 1\n\t\t\t\t\t\tfor {set i 2} {$i <= $num_queues} {incr i} {\n\t\t\t\t\t\t\tset i [format \"%\" $i]\n\t\t\t\t\t\t\tappend id \"\\\"\"\n\t\t\t\t\t\t\tappend id \",\\\"\" $i\n\t\t\t\t\t\t\tset i [expr 0x$i]\n\t\t\t\t\t\t}\n\t\t\t\t\t\thsi::utils::add_new_dts_param $mrmac1_node \"xlnx,num-queues\" $numqueues1 noformating\n\t\t\t\t\t\thsi::utils::add_new_dts_param $mrmac1_node \"xlnx,channel-ids\" $id stringlist\n\t\t\t\t\t\tgenerate_intr_info $drv_handle $mrmac1_node $fiforx_connect_ip1\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t#set txtodport1_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"tx_timestamp_tod_1\"]]\n\tset txtodport1_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"tx_ptp_tstamp_tag_out_1\"]]\n\tdtg_verbose \"txtodport1_pins:$txtodport1_pins\"\n\tif {[llength $txtodport1_pins]} {\n\t\tset tod1_sink_periph [::hsi::get_cells -of_objects $txtodport1_pins]\n\t\tif {[llength $tod1_sink_periph]} {\n\t\t\tif {[string match -nocase [get_property IP_NAME $tod1_sink_periph] \"mrmac_ptp_timestamp_if\"]} {\n\t\t\t\tset port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $tod1_sink_periph] \"tx_timestamp_tod\"]]\n\t\t\t\tset tod1_sink_periph [::hsi::get_cells -of_objects $port_pins]\n\t\t\t}\n\t\t}\n\t\tif {[llength $tod1_sink_periph] && [string match -nocase [get_property IP_NAME $tod1_sink_periph] \"xlconcat\"]} {\n\t\t\tset intf \"dout\"\n\t\t\tset in1_pin [::hsi::get_pins -of_objects $tod1_sink_periph -filter \"NAME==$intf\"]\n\t\t\tset in1sink_pins [::hsi::utils::get_sink_pins $in1_pin]\n\t\t\tset xl_per1 \"\"\n\t\t\tif {[llength $in1sink_pins]} {\n\t\t\t\tset xl_per1 [::hsi::get_cells -of_objects $in1sink_pins]\n\t\t\t}\n\t\t\tif {[llength $xl_per1] && [string match -nocase [get_property IP_NAME $xl_per1] \"axis_dwidth_converter\"]} {\n\t\t\t\tset port1_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $xl_per1] \"m_axis_tdata\"]]\n\t\t\t\tset axis_per1 [::hsi::get_cells -of_objects $port1_pins]\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $axis_per1] \"axis_clock_converter\"]} {\n\t\t\t\t\tset tx1_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $axis_per1] \"M_AXIS\"]\n\t\t\t\t\tif {[llength $tx1_ip]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mrmac1_node\" \"axififo-connected\" $tx1_ip reference\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else {\n\t\tdtg_warning \"tx_timestamp_tod_1 connected pins are NULL...please check the design...\"\n\t}\n\n\n\t#set rxtod1_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"rx_timestamp_tod_1\"]]\n\tset rxtod1_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"rx_ptp_tstamp_out_1\"]]\n\tdtg_verbose \"rxtod1_pins:$rxtod1_pins\"\n\tif {[llength $rxtod1_pins]} {\n\t\tset rx_periph1 [::hsi::get_cells -of_objects $rxtod1_pins]\n\t\tif {[llength $rx_periph1]} {\n\t\t\tif {[string match -nocase [get_property IP_NAME $rx_periph1] \"mrmac_ptp_timestamp_if\"]} {\n\t\t\t\tset port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rx_periph1] \"rx_timestamp_tod\"]]\n\t\t\t\tset rx_periph1 [::hsi::get_cells -of_objects $port_pins]\n\t\t\t}\n\t\t}\n\t\tif {[llength $rx_periph1] && [string match -nocase [get_property IP_NAME $rx_periph1] \"xlconcat\"]} {\n\t\t\tset intf \"dout\"\n\t\t\tset inrx1_pin [::hsi::get_pins -of_objects $rx_periph1 -filter \"NAME==$intf\"]\n\t\t\tset rxtodsink_pins [::hsi::utils::get_sink_pins $inrx1_pin]\n\t\t\tset rx_per \"\"\n\t\t\tif {[llength $rxtodsink_pins]} {\n\t\t\t\tset rx_per [::hsi::get_cells -of_objects $rxtodsink_pins]\n\t\t\t}\n\t\t\tif {[llength $rx_per] && [string match -nocase [get_property IP_NAME $rx_per] \"axis_dwidth_converter\"]} {\n\t\t\t\tset port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rx_per] \"m_axis_tdata\"]]\n\t\t\t\tset rx_axis_per [::hsi::get_cells -of_objects $port_pins]\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $rx_axis_per] \"axis_clock_converter\"]} {\n\t\t\t\t\tset rx_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $rx_axis_per] \"M_AXIS\"]\n\t\t\t\t\tif {[llength $rx_ip]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mrmac1_node\" \"xlnx,rxtsfifo\" $rx_ip reference\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else {\n\t\tdtg_warning \"rx_timestamp_tod_1 connected pins are NULL...please check the design...\"\n\t}\n\n\n\tif {[llength $handle]} {\n\t\thsi::utils::add_new_dts_param \"$mrmac1_node\" \"xlnx,gtctrl\" $handle reference\n\t}\n\tif {[llength $mask_handle]} {\n\t\thsi::utils::add_new_dts_param \"$mrmac1_node\" \"xlnx,gtpll\" $mask_handle reference\n\t}\n\tif {[llength $gt_reset_per]} {\n\t\thsi::utils::add_new_dts_param \"$mrmac1_node\" \"xlnx,gtctrl\" $gt_reset_per reference\n\t}\n\tif {[llength $gt_pll_per]} {\n\t\thsi::utils::add_new_dts_param \"$mrmac1_node\" \"xlnx,gtpll\" $gt_pll_per reference\n\t}\n\thsi::utils::add_new_dts_param \"$mrmac1_node\" \"xlnx,phcindex\" 1 int\n\thsi::utils::add_new_dts_param \"$mrmac1_node\" \"xlnx,gtlane\" 1 int\n\n\tadd_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE1_CFG_C0 \"xlnx,flex-slice1-cfg-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE1_CFG_C1 \"xlnx,flex-slice1-cfg-c1\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT1_DATA_RATE_C0 \"xlnx,flex-port1-data-rate-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT1_DATA_RATE_C1 \"xlnx,flex-port1-data-rate-c1\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT1_ENABLE_TIME_STAMPING_C0 \"xlnx,flex-port1-enable-time-stamping-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT1_ENABLE_TIME_STAMPING_C1 \"xlnx,flex-port1-enable-time-stamping-c1\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT1_MODE_C0 \"xlnx,flex-port1-mode-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT1_MODE_C1 \"xlnx,flex-port1-mode-c1\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT1_1588v2_Clocking_C0 \"xlnx,port1-1588v2-clocking-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT1_1588v2_Clocking_C1 \"xlnx,port1-1588v2-clocking-c1\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT1_1588v2_Operation_MODE_C0 \"xlnx,port1-1588v2-operation-mode-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT1_1588v2_Operation_MODE_C1 \"xlnx,port1-1588v2-operation-mode-c1\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_ENABLE_TIME_STAMPING_C0 \"xlnx,mac-port1-enable-time-stamping-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_ENABLE_TIME_STAMPING_C1 \"xlnx,mac-port1-enable-time-stamping-c1\" ${mrmac1_node} int\n\tset MAC_PORT1_RATE_C0 [get_property CONFIG.MAC_PORT1_RATE_C0 [get_cells -hier $drv_handle]]\n\tif {[llength $MAC_PORT1_RATE_C0]} {\n\t\tif {[string match -nocase $MAC_PORT1_RATE_C0 \"10GE\"]} {\n\t\t\tset number 10000\n\t\t\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mrmac-rate\" $number int\n\t\t} else {\n\t\t\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mrmac-rate\" $MAC_PORT1_RATE_C0 string\n\t\t}\n\t}\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RATE_C1 \"xlnx,mac-port1-rate-c1\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_GCP_C0 \"xlnx,mac-port1-rx-etype-gcp-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_GCP_C1 \"xlnx,mac-port1-rx-etype-gcp-c1\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_GPP_C0 \"xlnx,mac-port1-rx-etype-gpp-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_GPP_C1 \"xlnx,mac-port1-rx-etype-gpp-c1\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_PCP_C0 \"xlnx,mac-port1-rx-etype-pcp-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_PCP_C1 \"xlnx,mac-port1-rx-etype-pcp-c1\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_PPP_C0 \"xlnx,mac-port1-rx-etype-ppp-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_PPP_C1 \"xlnx,mac-port1-rx-etype-ppp-c1\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_FLOW_C0 \"xlnx,mac-port1-rx-flow-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_FLOW_C1 \"xlnx,mac-port1-rx-flow-c1\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_GPP_C0 \"xlnx,mac-port1-rx-opcode-gpp-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_GPP_C1 \"xlnx,mac-port1-rx-opcode-gpp-c1\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MAX_GCP_C0 \"xlnx,mac-port1-rx-opcode-max-gcp-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MAX_GCP_C1 \"xlnx,mac-port1-rx-opcode-max-gcp-c1\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MAX_PCP_C0 \"xlnx,mac-port1-rx-opcode-max-pcp-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MAX_PCP_C1 \"xlnx,mac-port1-rx-opcode-max-pcp-c1\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MIN_GCP_C0 \"xlnx,mac-port1-rx-opcode-min-gcp-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MIN_GCP_C1 \"xlnx,mac-port1-rx-opcode-min-gcp-c1\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MIN_PCP_C0 \"xlnx,mac-port1-rx-opcode-min-pcp-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MIN_PCP_C1 \"xlnx,mac-port1-rx-opcode-min-pcp-c1\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_PPP_C0 \"xlnx,mac-port1-rx-opcode-ppp-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_PPP_C1 \"xlnx,mac-port1-rx-opcode-ppp-c1\" ${mrmac1_node} int\n\tset MAC_PORT1_RX_PAUSE_DA_MCAST_C0 [get_property CONFIG.MAC_PORT1_RX_PAUSE_DA_MCAST_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT1_RX_PAUSE_DA_MCAST_C0 [check_size $MAC_PORT1_RX_PAUSE_DA_MCAST_C0 $mrmac1_node]\n\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mac-port1-rx-pause-da-mcast-c0\" $MAC_PORT1_RX_PAUSE_DA_MCAST_C0 int\n\tset MAC_PORT1_RX_PAUSE_DA_MCAST_C1 [get_property CONFIG.MAC_PORT1_RX_PAUSE_DA_MCAST_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT1_RX_PAUSE_DA_MCAST_C1 [check_size $MAC_PORT1_RX_PAUSE_DA_MCAST_C1 $mrmac1_node]\n\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mac-port1-rx-pause-da-mcast-c1\" $MAC_PORT1_RX_PAUSE_DA_MCAST_C1 int\n\tset MAC_PORT1_RX_PAUSE_DA_UCAST_C0 [get_property CONFIG.MAC_PORT1_RX_PAUSE_DA_UCAST_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT1_RX_PAUSE_DA_UCAST_C0 [check_size $MAC_PORT1_RX_PAUSE_DA_UCAST_C0 $mrmac1_node]\n\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mac-port1-rx-pause-da-ucast-c0\" $MAC_PORT1_RX_PAUSE_DA_UCAST_C0 int\n\tset MAC_PORT1_RX_PAUSE_DA_UCAST_C1 [get_property CONFIG.MAC_PORT1_RX_PAUSE_DA_UCAST_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT1_RX_PAUSE_DA_UCAST_C1 [check_size $MAC_PORT1_RX_PAUSE_DA_UCAST_C1 $mrmac1_node]\n\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mac-port1-rx-pause-da-ucast-c1\" $MAC_PORT1_RX_PAUSE_DA_UCAST_C1 int\n\tset MAC_PORT1_RX_PAUSE_SA_C0 [get_property CONFIG.MAC_PORT1_RX_PAUSE_SA_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT1_RX_PAUSE_SA_C0 [check_size $MAC_PORT1_RX_PAUSE_SA_C0 $mrmac1_node]\n\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mac-port1-rx-pause-sa-c0\" $MAC_PORT1_RX_PAUSE_SA_C0 int\n\tset MAC_PORT1_RX_PAUSE_SA_C1 [get_property CONFIG.MAC_PORT1_RX_PAUSE_SA_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT1_RX_PAUSE_SA_C1 [check_size $MAC_PORT1_RX_PAUSE_SA_C1 $mrmac1_node]\n\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mac-port1-rx-pause-sa-c1\" $MAC_PORT1_RX_PAUSE_SA_C1 int\n\tset MAC_PORT1_TX_DA_GPP_C0 [get_property CONFIG.MAC_PORT1_TX_DA_GPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT1_TX_DA_GPP_C0 [check_size $MAC_PORT1_TX_DA_GPP_C0 $mrmac1_node]\n\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mac-port1-tx-da-gpp-c0\" $MAC_PORT1_TX_DA_GPP_C0 int\n\tset MAC_PORT1_TX_DA_GPP_C1 [get_property CONFIG.MAC_PORT1_TX_DA_GPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT1_TX_DA_GPP_C1 [check_size $MAC_PORT1_TX_DA_GPP_C1 $mrmac1_node]\n\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mac-port1-tx-da-gpp-c1\" $MAC_PORT1_TX_DA_GPP_C1 int\n\tset MAC_PORT1_TX_DA_PPP_C0 [get_property CONFIG.MAC_PORT1_TX_DA_PPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT1_TX_DA_PPP_C0 [check_size $MAC_PORT1_TX_DA_PPP_C0 $mrmac1_node]\n\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mac-port1-tx-da-ppp-c0\" $MAC_PORT1_TX_DA_PPP_C0 int\n\tset MAC_PORT1_TX_DA_PPP_C1 [get_property CONFIG.MAC_PORT1_TX_DA_PPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT1_TX_DA_PPP_C1 [check_size $MAC_PORT1_TX_DA_PPP_C1 $mrmac1_node]\n\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mac-port1-tx-da-ppp-c1\" $MAC_PORT1_TX_DA_PPP_C1 int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_ETHERTYPE_GPP_C0 \"xlnx,mac-port1-tx-ethertype-gpp-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_ETHERTYPE_GPP_C1 \"xlnx,mac-port1-tx-ethertype-gpp-c1\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_ETHERTYPE_PPP_C0 \"xlnx,mac-port1-tx-ethertype-ppp-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_ETHERTYPE_PPP_C1 \"xlnx,mac-port1-tx-ethertype-ppp-c1\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_FLOW_C0 \"xlnx,mac-port1-tx-flow-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_FLOW_C1 \"xlnx,mac-port1-tx-flow-c1\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_OPCODE_GPP_C0 \"xlnx,mac-port1-tx-opcode-gpp-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_OPCODE_GPP_C1 \"xlnx,mac-port1-tx-opcode-gpp-c1\" ${mrmac1_node} int\n\tset MAC_PORT1_TX_SA_GPP_C0 [get_property CONFIG.MAC_PORT1_TX_SA_GPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT1_TX_SA_GPP_C0 [check_size $MAC_PORT1_TX_SA_GPP_C0 $mrmac1_node]\n\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mac-port1-tx-sa-gpp-c0\" $MAC_PORT1_TX_SA_GPP_C0 int\n\tset MAC_PORT1_TX_SA_GPP_C1 [get_property CONFIG.MAC_PORT1_TX_SA_GPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT1_TX_SA_GPP_C1 [check_size $MAC_PORT1_TX_SA_GPP_C1 $mrmac1_node]\n\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mac-port1-tx-sa-gpp-c1\" $MAC_PORT1_TX_SA_GPP_C1 int\n\tset MAC_PORT1_TX_SA_PPP_C0 [get_property CONFIG.MAC_PORT1_TX_SA_PPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT1_TX_SA_PPP_C0 [check_size $MAC_PORT1_TX_SA_PPP_C0 $mrmac1_node]\n\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mac-port1-tx-sa-ppp-c0\" $MAC_PORT1_TX_SA_PPP_C0 int\n\tset MAC_PORT1_TX_SA_PPP_C1 [get_property CONFIG.MAC_PORT1_TX_SA_PPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT1_TX_SA_PPP_C1 [check_size $MAC_PORT1_TX_SA_PPP_C1 $mrmac1_node]\n\thsi::utils::add_new_dts_param \"${mrmac1_node}\" \"xlnx,mac-port1-tx-sa-ppp-c1\" $MAC_PORT1_TX_SA_PPP_C1 int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RXPROGDIV_FREQ_ENABLE_C0 \"xlnx,gt-ch1-rxprogdiv-freq-enable-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RXPROGDIV_FREQ_ENABLE_C1 \"xlnx,gt-ch1-rxprogdiv-freq-enable-c1\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RXPROGDIV_FREQ_SOURCE_C0 \"xlnx,gt-ch1-rxprogdiv-freq-source-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RXPROGDIV_FREQ_SOURCE_C1 \"xlnx,gt-ch1-rxprogdiv-freq-source-c1\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RXPROGDIV_FREQ_VAL_C0 \"xlnx,gt-ch1-rxprogdiv-freq-val-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RXPROGDIV_FREQ_VAL_C1 \"xlnx,gt-ch1-rxprogdiv-freq-val-c1\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_BUFFER_MODE_C0 \"xlnx,gt-ch1-rx-buffer-mode-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_BUFFER_MODE_C1 \"xlnx,gt-ch1-rx-buffer-mode-c1\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_DATA_DECODING_C0 \"xlnx,gt-ch1-rx-data-decoding-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_DATA_DECODING_C1 \"xlnx,gt-ch1-rx-data-decoding-c1\" ${mrmac1_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_INT_DATA_WIDTH_C0 \"xlnx,gt-ch1-rx-int-data-width-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_INT_DATA_WIDTH_C1 \"xlnx,gt-ch1-rx-int-data-width-c1\" ${mrmac1_node} int\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_LINE_RATE_C0 \"xlnx,gt-ch1-rx-line-rate-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_LINE_RATE_C1 \"xlnx,gt-ch1-rx-line-rate-c1\" ${mrmac1_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_OUTCLK_SOURCE_C0 \"xlnx,gt-ch1-rx-outclk-source-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_OUTCLK_SOURCE_C1 \"xlnx,gt-ch1-rx-outclk-source-c1\" ${mrmac1_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_REFCLK_FREQUENCY_C0 \"xlnx,gt-ch1-rx-refclk-frequency-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_REFCLK_FREQUENCY_C1 \"xlnx,gt-ch1-rx-refclk-frequency-c1\" ${mrmac1_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_USER_DATA_WIDTH_C0 \"xlnx,gt-ch1-rx-user-data-width-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_USER_DATA_WIDTH_C1 \"xlnx,gt-ch1-rx-user-data-width-c1\" ${mrmac1_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TXPROGDIV_FREQ_ENABLE_C0 \"xlnx,gt-ch1-txprogdiv-freq-enable-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TXPROGDIV_FREQ_ENABLE_C1 \"xlnx,gt-ch1-txprogdiv-freq-enable-c1\" ${mrmac1_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TXPROGDIV_FREQ_SOURCE_C0 \"xlnx,gt-ch1-txprogdiv-freq-source-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TXPROGDIV_FREQ_SOURCE_C1 \"xlnx,gt-ch1-txprogdiv-freq-source-c1\" ${mrmac1_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TXPROGDIV_FREQ_VAL_C0 \"xlnx,gt-ch1-txprogdiv-freq-val-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TXPROGDIV_FREQ_VAL_C1 \"xlnx,gt-ch1-txprogdiv-freq-val-c1\" ${mrmac1_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_BUFFER_MODE_C0 \"xlnx,gt-ch1-tx-buffer-mode-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_BUFFER_MODE_C1 \"xlnx,gt-ch1-tx-buffer-mode-c1\" ${mrmac1_node} int\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_DATA_ENCODING_C0 \"xlnx,gt-ch1-tx-data-encoding-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_DATA_ENCODING_C1 \"xlnx,gt-ch1-tx-data-encoding-c1\" ${mrmac1_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_INT_DATA_WIDTH_C0 \"xlnx,gt-ch1-int-data-width-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_INT_DATA_WIDTH_C1 \"xlnx,gt-ch1-int-data-width-c1\" ${mrmac1_node} int\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_LINE_RATE_C0 \"xlnx,gt-ch1-tx-line-rate-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_LINE_RATE_C1 \"xlnx,gt-ch1-tx-line-rate-c1\" ${mrmac1_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_OUTCLK_SOURCE_C0 \"xlnx,gt-ch1-tx-outclk-source-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_OUTCLK_SOURCE_C1 \"xlnx,gt-ch1-tx-outclk-source-c1\" ${mrmac1_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_PLL_TYPE_C0 \"xlnx,gt-ch1-tx-pll-type-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_PLL_TYPE_C1 \"xlnx,gt-ch1-tx-pll-type-c1\" ${mrmac1_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_REFCLK_FREQUENCY_C0 \"xlnx,gt-ch1-tx-refclk-frequency-c0\" ${mrmac1_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_REFCLK_FREQUENCY_C1 \"xlnx,gt-ch1-tx-refclk-frequency-c1\" ${mrmac1_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_USER_DATA_WIDTH_C0 \"xlnx,gt-ch1-tx-user-data-width-c0\" ${mrmac1_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_USER_DATA_WIDTH_C1 \"xlnx,gt-ch1-tx-user-data-width-c1\" ${mrmac1_node} int\n\n\tset mrmac2_base [format 0x%x [expr $base_addr + 0x2000]]\n\tset mrmac2_base_hex [format %x $mrmac2_base]\n\tset mrmac2_highaddr_hex [format 0x%x [expr $mrmac2_base + 0xFFF]]\n\tset port2 2\n\tappend label2 $drv_handle \"_\" $port2\n\tset node_prefix [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tset mrmac2_node [add_or_get_dt_node -n $node_prefix -l \"$label2\" -u $mrmac2_base_hex -d $dts_file -p $bus_node]\n\thsi::utils::add_new_dts_param \"$mrmac2_node\" \"compatible\" \"$compatible\" stringlist\n\tset mrmac2_reg [generate_reg_property $mrmac2_base $mrmac2_highaddr_hex]\n\thsi::utils::add_new_dts_param \"$mrmac2_node\" \"reg\" $mrmac2_reg inthexlist\n\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"mrmac\"]} {\n\t\tlappend clknames2 \"$s_axi_aclk\" \"$rx_axi_clk2\" \"$rx_flexif_clk2\" \"$rx_ts_clk2\" \"$tx_axi_clk2\" \"$tx_flexif_clk2\" \"$tx_ts_clk2\"\n\t\tset tmpclks2 [fix_clockprop \"[lindex $clk_list $s_axi_aclk_index0]\" \"[lindex $clk_list $rx_axi_clk_index2]\"]\n\t\tset txindex2 [lindex $clk_list $tx_ts_clk_index2]\n\t\tregsub -all \"\\>\" $txindex2 {} txindex2\n\t\tappend clkvals2 \"[lindex $tmpclks2 0], [lindex $tmpclks2 1], [lindex $clk_list $rx_flexif_clk_index2], [lindex $clk_list $rx_ts_clk2_index2], [lindex $clk_list $tx_axi_clk_index2], [lindex $clk_list $tx_flexif_clk_index2], $txindex2\"\n\t\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"clocks\" $clkvals2 reference\n\t\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"clock-names\" $clknames2 stringlist\n\t}\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"dcmac\"]} {\n\t\tlappend clknames2 \"$s_axi_aclk\" \"$rx_axi_clk0\" \"$rx_flexif_clk2\" \"$tx_axi_clk0\" \"$tx_flexif_clk2\" \"$rx_macif_clk\" \"$ts_clk2\" \"$tx_macif_clk\" \"$tx_serdes_clk2\"\n\t\tset tmpclks2 [fix_clockprop \"[lindex $clk_list $s_axi_aclk_index0]\" \"[lindex $clk_list $rx_axi_clk_index0]\"]\n\t\tset txindex2 [lindex $clk_list $tx_serdes_clk_index2]\n\t\tregsub -all \"\\>\" $txindex2 {} txindex2\n\t\tappend clkvals2 \"[lindex $tmpclks2 0], [lindex $tmpclks2 1], [lindex $clk_list $rx_flexif_clk_index2], [lindex $clk_list $tx_axi_clk_index0], [lindex $clk_list $tx_flexif_clk_index2], [lindex $clk_list $rx_macif_clk_index0], [lindex $clk_list $ts_clk_index2], [lindex $clk_list $tx_macif_clk_index0], $txindex2\"\n\t\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"clocks\" $clkvals2 reference\n\t\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"clock-names\" $clknames2 stringlist\n\t}\n\n\tset port2_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"rx_axis_tdata4\"]]\n\tforeach pin $port2_pins {\n\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tset mux_ip \"\"\n\t\tset fifo_ip \"\"\n\t\tif {[llength $sink_periph]} {\n\t\t\tif {[string match -nocase [get_property IP_NAME $sink_periph] \"dcmac_intf_rx\"]} {\n\t\t\t\tset sink_periph [hsi::utils::get_connected_stream_ip [get_cells -hier $sink_periph] \"M_AXIS\"]\n\t\t\t}\n\t\t\tif {[string match -nocase [get_property IP_NAME $sink_periph] \"axis_data_fifo\"]} {\n\t\t\t\tset fifo_width_bytes [get_property CONFIG.TDATA_NUM_BYTES $sink_periph]\n\t\t\t\tif {[string_is_empty $fifo_width_bytes]} {\n\t\t\t\t\tset fifo_width_bytes 1\n\t\t\t\t}\n\t\t\t\tset rxethmem [get_property CONFIG.FIFO_DEPTH $sink_periph]\n\t\t\t\t# FIFO can be other than 8 bits, and we need the rxmem in bytes\n\t\t\t\tset rxethmem [expr $rxethmem * $fifo_width_bytes]\n\t\t\t\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,rxmem\" $rxethmem int\n\t\t\t\tset fifo2_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $sink_periph] \"m_axis_tdata\"]]\n\t\t\t\tset mux_per2 [::hsi::get_cells -of_objects $fifo2_pin]\n\t\t\t\tset fiforx_connect_ip2 \"\"\n\t\t\t\tif {[llength $mux_per2] && [string match -nocase [get_property IP_NAME $mux_per2] \"mrmac_10g_mux\"]} {\n\t\t\t\t\tset data_fifo_pin2 [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mux_per2] \"rx_m_axis_tdata\"]]\n\t\t\t\t\tset data_fifo_per2 [::hsi::get_cells -of_objects $data_fifo_pin2]\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $data_fifo_per2] \"axis_data_fifo\"]} {\n\t\t\t\t\t\tset fiforx_connect_ip2 [hsi::utils::get_connected_stream_ip [get_cells -hier $data_fifo_per2] \"M_AXIS\"]\n\t\t\t\t\t\tset fiforx2_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $data_fifo_per2] \"m_axis_tdata\"]]\n\t\t\t\t\t\tset fiforx2_per [::hsi::get_cells -of_objects $fiforx2_pin]\n\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $fiforx2_per] \"RX_PTP_PKT_DETECT_TS_PREPEND\"]} {\n\t\t\t\t\t\t\tset fiforx_connect_ip2 [hsi::utils::get_connected_stream_ip [get_cells -hier $fiforx2_per] \"M_AXIS\"]\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $mux_per2] \"axi_mcdma\"]} {\n\t\t\t\t\tset fiforx_connect_ip2 $mux_per2\n\t\t\t\t}\n\t\t\t\tif {[llength $fiforx_connect_ip2]} {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $fiforx_connect_ip2] \"axi_mcdma\"]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mrmac2_node\" \"axistream-connected\" \"$fiforx_connect_ip2\" reference\n\t\t\t\t\t\tset num_queues [get_property CONFIG.c_num_mm2s_channels $fiforx_connect_ip2]\n\t\t\t\t\t\tset inhex [format %x $num_queues]\n\t\t\t\t\t\tappend numqueues2 \"/bits/ 16 <0x$inhex>\"\n\t\t\t\t\t\thsi::utils::add_new_dts_param $mrmac2_node \"xlnx,num-queues\" $numqueues2 noformating\n\t\t\t\t\t\tset id 1\n\t\t\t\t\t\tfor {set i 2} {$i <= $num_queues} {incr i} {\n\t\t\t\t\t\t\tset i [format \"%\" $i]\n\t\t\t\t\t\t\tappend id \"\\\"\"\n\t\t\t\t\t\t\tappend id \",\\\"\" $i\n\t\t\t\t\t\t\tset i [expr 0x$i]\n\t\t\t\t\t\t}\n\t\t\t\t\t\thsi::utils::add_new_dts_param $mrmac2_node \"xlnx,num-queues\" $numqueues2 noformating\n\t\t\t\t\t\thsi::utils::add_new_dts_param $mrmac2_node \"xlnx,channel-ids\" $id stringlist\n\t\t\t\t\t\tgenerate_intr_info $drv_handle $mrmac2_node $fiforx_connect_ip2\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t#set txtodport2_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"tx_timestamp_tod_2\"]]\n\tset txtodport2_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"tx_ptp_tstamp_tag_out_2\"]]\n\n\tif {[llength $txtodport2_pins]} {\n\t\tset tod2_sink_periph [::hsi::get_cells -of_objects $txtodport2_pins]\n\t\tif {[string match -nocase [get_property IP_NAME $tod2_sink_periph] \"mrmac_ptp_timestamp_if\"]} {\n\t\t\tset port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $tod2_sink_periph] \"tx_timestamp_tod\"]]\n\t\t\tset tod2_sink_periph [::hsi::get_cells -of_objects $port_pins]\n\t\t}\n\t\tif {[llength $tod2_sink_periph] && [string match -nocase [get_property IP_NAME $tod2_sink_periph] \"xlconcat\"]} {\n\t\t\tset intf \"dout\"\n\t\t\tset in2_pin [::hsi::get_pins -of_objects $tod2_sink_periph -filter \"NAME==$intf\"]\n\t\t\tset in2sink_pins [::hsi::utils::get_sink_pins $in2_pin]\n\t\t\tset xl_per2 \"\"\n\t\t\tif {[llength $in2sink_pins]} {\n\t\t\t\tset xl_per2 [::hsi::get_cells -of_objects $in2sink_pins]\n\t\t\t}\n\t\t\tif {[llength $xl_per2] && [string match -nocase [get_property IP_NAME $xl_per2] \"axis_dwidth_converter\"]} {\n\t\t\t\tset port2pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $xl_per2] \"m_axis_tdata\"]]\n\t\t\t\tset axis_per2 [::hsi::get_cells -of_objects $port2pins]\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $axis_per2] \"axis_clock_converter\"]} {\n\t\t\t\t\tset tx2_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $axis_per2] \"M_AXIS\"]\n\t\t\t\t\tif {[llength $tx2_ip]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mrmac2_node\" \"axififo-connected\" $tx2_ip reference\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else {\n\t\tdtg_warning \"tx_timestamp_tod_2 connected pins are NULL...please check the design...\"\n\t}\n\n\n\t#set rxtod2_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"rx_timestamp_tod_2\"]]\n\tset rxtod2_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"rx_ptp_tstamp_out_2\"]]\n\n\tif {[llength $rxtod2_pins]} {\n\t\tset rx_periph2 [::hsi::get_cells -of_objects $rxtod2_pins]\n\t\tif {[string match -nocase [get_property IP_NAME $rx_periph2] \"mrmac_ptp_timestamp_if\"]} {\n\t\t\tset port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rx_periph2] \"rx_timestamp_tod\"]]\n\t\t\tset rx_periph2 [::hsi::get_cells -of_objects $port_pins]\n\t\t}\n\t\tif {[llength $rx_periph2] && [string match -nocase [get_property IP_NAME $rx_periph2] \"xlconcat\"]} {\n\t\t\tset intf \"dout\"\n\t\t\tset inrx2_pin [::hsi::get_pins -of_objects $rx_periph2 -filter \"NAME==$intf\"]\n\t\t\tset rxtodsink_pins [::hsi::utils::get_sink_pins $inrx2_pin]\n\t\t\tset rx_per2 \"\"\n\t\t\tif {[llength $rxtodsink_pins]} {\n\t\t\t\tset rx_per2 [::hsi::get_cells -of_objects $rxtodsink_pins]\n\t\t\t}\n\t\t\tif {[llength $rx_per2] && [string match -nocase [get_property IP_NAME $rx_per2] \"axis_dwidth_converter\"]} {\n\t\t\t\tset port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rx_per2] \"m_axis_tdata\"]]\n\t\t\t\tset rx_axis_per2 [::hsi::get_cells -of_objects $port_pins]\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $rx_axis_per2] \"axis_clock_converter\"]} {\n\t\t\t\t\tset rx_ip2 [hsi::utils::get_connected_stream_ip [get_cells -hier $rx_axis_per2] \"M_AXIS\"]\n\t\t\t\t\tif {[llength $rx_ip2]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mrmac2_node\" \"xlnx,rxtsfifo\" $rx_ip2 reference\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else {\n\t\tdtg_warning \"rx_timestamp_tod_2 connected pins are NULL...please check the design...\"\n\t}\n\n\tif {[llength $handle]} {\n\t\thsi::utils::add_new_dts_param \"$mrmac2_node\" \"xlnx,gtctrl\" $handle reference\n\t}\n\tif {[llength $mask_handle]} {\n\t\thsi::utils::add_new_dts_param \"$mrmac2_node\" \"xlnx,gtpll\" $mask_handle reference\n\t}\n\tif {[llength $gt_reset_per]} {\n\t\thsi::utils::add_new_dts_param \"$mrmac2_node\" \"xlnx,gtctrl\" $gt_reset_per reference\n\t}\n\tif {[llength $gt_pll_per]} {\n\t\thsi::utils::add_new_dts_param \"$mrmac2_node\" \"xlnx,gtpll\" $gt_pll_per reference\n\t}\n\thsi::utils::add_new_dts_param \"$mrmac2_node\" \"xlnx,phcindex\" 2 int\n\thsi::utils::add_new_dts_param \"$mrmac2_node\" \"xlnx,gtlane\" 2 int\n\n\tadd_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE2_CFG_C0 \"xlnx,flex-slice2-cfg-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE2_CFG_C1 \"xlnx,flex-slice2-cfg-c1\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT2_DATA_RATE_C0 \"xlnx,flex-port2-data-rate-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT2_DATA_RATE_C1 \"xlnx,flex-port2-data-rate-c1\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT2_ENABLE_TIME_STAMPING_C0 \"xlnx,flex-port2-enable-time-stamping-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT2_ENABLE_TIME_STAMPING_C1 \"xlnx,flex-port2-enable-time-stamping-c1\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT2_MODE_C0 \"xlnx,flex-port2-mode-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT2_MODE_C1 \"xlnx,flex-port2-mode-c1\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT2_1588v2_Clocking_C0 \"xlnx,port2-1588v2-clocking-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT2_1588v2_Clocking_C1 \"xlnx,port2-1588v2-clocking-c1\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT2_1588v2_Operation_MODE_C0 \"xlnx,port2-1588v2-operation-mode-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT2_1588v2_Operation_MODE_C1 \"xlnx,port2-1588v2-operation-mode-c1\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_ENABLE_TIME_STAMPING_C0 \"xlnx,mac-port2-enable-time-stamping-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_ENABLE_TIME_STAMPING_C1 \"xlnx,mac-port2-enable-time-stamping-c1\" ${mrmac2_node} int\n\n\tset MAC_PORT2_RATE_C0 [get_property CONFIG.MAC_PORT2_RATE_C0 [get_cells -hier $drv_handle]]\n\tif {[llength ${MAC_PORT2_RATE_C0}]} {\n\t\tif {[string match -nocase $MAC_PORT2_RATE_C0 \"10GE\"]} {\n\t\t\tset number 10000\n\t\t\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mrmac-rate\" $number int\n\t\t} else {\n\t\t\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mrmac-rate\" $MAC_PORT2_RATE_C0 string\n\t\t}\n\t}\n\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RATE_C1 \"xlnx,mac-port2-rate-c1\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_GCP_C0 \"xlnx,mac-port2-rx-etype-gcp-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_GCP_C1 \"xlnx,mac-port2-rx-etype-gcp-c1\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_GPP_C0 \"xlnx,mac-port2-rx-etype-gpp-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_GPP_C1 \"xlnx,mac-port2-rx-etype-gpp-c1\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_PCP_C0 \"xlnx,mac-port2-rx-etype-pcp-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_PCP_C1 \"xlnx,mac-port2-rx-etype-pcp-c1\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_PPP_C0 \"xlnx,mac-port2-rx-etype-ppp-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_PPP_C1 \"xlnx,mac-port2-rx-etype-ppp-c1\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_FLOW_C0 \"xlnx,mac-port2-rx-flow-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_FLOW_C1 \"xlnx,mac-port2-rx-flow-c1\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_GPP_C0 \"xlnx,mac-port2-rx-opcode-gpp-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_GPP_C1 \"xlnx,mac-port2-rx-opcode-gpp-c1\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MAX_GCP_C0 \"xlnx,mac-port2-rx-opcode-max-gcp-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MAX_GCP_C1 \"xlnx,mac-port2-rx-opcode-max-gcp-c1\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MAX_PCP_C0 \"xlnx,mac-port2-rx-opcode-max-pcp-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MAX_PCP_C1 \"xlnx,mac-port2-rx-opcode-max-pcp-c1\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MIN_GCP_C0 \"xlnx,mac-port2-rx-opcode-min-gcp-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MIN_GCP_C1 \"xlnx,mac-port2-rx-opcode-min-gcp-c1\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MIN_PCP_C0 \"xlnx,mac-port2-rx-opcode-min-pcp-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MIN_PCP_C1 \"xlnx,mac-port2-rx-opcode-min-pcp-c1\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_PPP_C0 \"xlnx,mac-port2-rx-opcode-ppp-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_PPP_C1 \"xlnx,mac-port2-rx-opcode-ppp-c1\" ${mrmac2_node} int\n\tset MAC_PORT2_RX_PAUSE_DA_MCAST_C0 [get_property CONFIG.MAC_PORT2_RX_PAUSE_DA_MCAST_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT2_RX_PAUSE_DA_MCAST_C0 [check_size $MAC_PORT2_RX_PAUSE_DA_MCAST_C0 $mrmac2_node]\n\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mac-port2-rx-pause-da-mcast-c0\" $MAC_PORT2_RX_PAUSE_DA_MCAST_C0 int\n\tset MAC_PORT2_RX_PAUSE_DA_MCAST_C1 [get_property CONFIG.MAC_PORT2_RX_PAUSE_DA_MCAST_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT2_RX_PAUSE_DA_MCAST_C1 [check_size $MAC_PORT2_RX_PAUSE_DA_MCAST_C1 $mrmac2_node]\n\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mac-port2-rx-pause-da-mcast-c1\" $MAC_PORT2_RX_PAUSE_DA_MCAST_C1 int\n\tset MAC_PORT2_RX_PAUSE_DA_UCAST_C0 [get_property CONFIG.MAC_PORT2_RX_PAUSE_DA_UCAST_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT2_RX_PAUSE_DA_UCAST_C0 [check_size $MAC_PORT2_RX_PAUSE_DA_UCAST_C0 $mrmac2_node]\n\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mac-port2-rx-pause-da-ucast-c0\" $MAC_PORT2_RX_PAUSE_DA_UCAST_C0 int\n\tset MAC_PORT2_RX_PAUSE_DA_UCAST_C1 [get_property CONFIG.MAC_PORT2_RX_PAUSE_DA_UCAST_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT2_RX_PAUSE_DA_UCAST_C1 [check_size $MAC_PORT2_RX_PAUSE_DA_UCAST_C1 $mrmac2_node]\n\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mac-port2-rx-pause-da-ucast-c1\" $MAC_PORT2_RX_PAUSE_DA_UCAST_C1 int\n\tset MAC_PORT2_RX_PAUSE_SA_C0 [get_property CONFIG.MAC_PORT2_RX_PAUSE_SA_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT2_RX_PAUSE_SA_C0 [check_size $MAC_PORT2_RX_PAUSE_SA_C0 $mrmac2_node]\n\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mac-port2-rx-pause-sa-c0\" $MAC_PORT2_RX_PAUSE_SA_C0 int\n\tset MAC_PORT2_RX_PAUSE_SA_C1 [get_property CONFIG.MAC_PORT2_RX_PAUSE_SA_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT2_RX_PAUSE_SA_C1 [check_size $MAC_PORT2_RX_PAUSE_SA_C1 $mrmac2_node]\n\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mac-port2-rx-pause-sa-c1\" $MAC_PORT2_RX_PAUSE_SA_C1 int\n\tset MAC_PORT2_TX_DA_GPP_C0 [get_property CONFIG.MAC_PORT2_TX_DA_GPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT2_TX_DA_GPP_C0 [check_size $MAC_PORT2_TX_DA_GPP_C0 $mrmac2_node]\n\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mac-port2-tx-da-gpp-c0\" $MAC_PORT2_TX_DA_GPP_C0 int\n\tset MAC_PORT2_TX_DA_GPP_C1 [get_property CONFIG.MAC_PORT2_TX_DA_GPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT2_TX_DA_GPP_C1 [check_size $MAC_PORT2_TX_DA_GPP_C1 $mrmac2_node]\n\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mac-port2-tx-da-gpp-c1\" $MAC_PORT2_TX_DA_GPP_C1 int\n\tset MAC_PORT2_TX_DA_PPP_C0 [get_property CONFIG.MAC_PORT2_TX_DA_PPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT2_TX_DA_PPP_C0 [check_size $MAC_PORT2_TX_DA_PPP_C0 $mrmac2_node]\n\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mac-port2-tx-da-ppp-c0\" $MAC_PORT2_TX_DA_PPP_C0 int\n\tset MAC_PORT2_TX_DA_PPP_C1 [get_property CONFIG.MAC_PORT2_TX_DA_PPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT2_TX_DA_PPP_C1 [check_size $MAC_PORT2_TX_DA_PPP_C1 $mrmac2_node]\n\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mac-port2-tx-da-ppp-c1\" $MAC_PORT2_TX_DA_PPP_C1 int\n\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_ETHERTYPE_GPP_C0 \"xlnx,mac-port2-tx-ethertype-gpp-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_ETHERTYPE_GPP_C1 \"xlnx,mac-port2-tx-ethertype-gpp-c1\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_ETHERTYPE_PPP_C0 \"xlnx,mac-port2-tx-ethertype-ppp-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_ETHERTYPE_PPP_C1 \"xlnx,mac-port2-tx-ethertype-ppp-c1\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_FLOW_C0 \"xlnx,mac-port2-tx-flow-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_FLOW_C1 \"xlnx,mac-port2-tx-flow-c1\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_OPCODE_GPP_C0 \"xlnx,mac-port2-tx-opcode-gpp-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_OPCODE_GPP_C1 \"xlnx,mac-port2-tx-opcode-gpp-c1\" ${mrmac2_node} int\n\n\tset MAC_PORT2_TX_SA_GPP_C0 [get_property CONFIG.MAC_PORT2_TX_SA_GPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT2_TX_SA_GPP_C0 [check_size $MAC_PORT2_TX_SA_GPP_C0 $mrmac2_node]\n\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mac-port2-tx-sa-gpp-c0\" $MAC_PORT2_TX_SA_GPP_C0 int\n\tset MAC_PORT2_TX_SA_GPP_C1 [get_property CONFIG.MAC_PORT2_TX_SA_GPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT2_TX_SA_GPP_C1 [check_size $MAC_PORT2_TX_SA_GPP_C1 $mrmac2_node]\n\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mac-port2-tx-sa-gpp-c1\" $MAC_PORT2_TX_SA_GPP_C1 int\n\tset MAC_PORT2_TX_SA_PPP_C0 [get_property CONFIG.MAC_PORT2_TX_SA_PPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT2_TX_SA_PPP_C0 [check_size $MAC_PORT2_TX_SA_PPP_C0 $mrmac2_node]\n\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mac-port2-tx-sa-ppp-c0\" $MAC_PORT2_TX_SA_PPP_C0 int\n\tset MAC_PORT2_TX_SA_PPP_C1 [get_property CONFIG.MAC_PORT2_TX_SA_PPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT2_TX_SA_PPP_C1 [check_size $MAC_PORT2_TX_SA_PPP_C1 $mrmac2_node]\n\thsi::utils::add_new_dts_param \"${mrmac2_node}\" \"xlnx,mac-port2-tx-sa-ppp-c1\" $MAC_PORT2_TX_SA_PPP_C1 int\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RXPROGDIV_FREQ_ENABLE_C0 \"xlnx,gt-ch2-rxprogdiv-freq-enable-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RXPROGDIV_FREQ_ENABLE_C1 \"xlnx,gt-ch2-rxprogdiv-freq-enable-c1\" ${mrmac2_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RXPROGDIV_FREQ_SOURCE_C0 \"xlnx,gt-ch2-rxprogdiv-freq-source-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RXPROGDIV_FREQ_SOURCE_C1 \"xlnx,gt-ch2-rxprogdiv-freq-source-c1\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RXPROGDIV_FREQ_VAL_C0 \"xlnx,gt-ch2-rxprogdiv-freq-val-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RXPROGDIV_FREQ_VAL_C1 \"xlnx,gt-ch2-rxprogdiv-freq-val-c1\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_BUFFER_MODE_C0 \"xlnx,gt-ch2-rx-buffer-mode-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_BUFFER_MODE_C1 \"xlnx,gt-ch2-rx-buffer-mode-c1\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_DATA_DECODING_C0 \"xlnx,gt-ch2-rx-data-decoding-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_DATA_DECODING_C1 \"xlnx,gt-ch2-rx-data-decoding-c1\" ${mrmac2_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_INT_DATA_WIDTH_C0 \"xlnx,gt-ch2-rx-int-data-width-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_INT_DATA_WIDTH_C1 \"xlnx,gt-ch2-rx-int-data-width-c1\" ${mrmac2_node} int\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_LINE_RATE_C0 \"xlnx,gt-ch2-rx-line-rate-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_LINE_RATE_C1 \"xlnx,gt-ch2-rx-line-rate-c1\" ${mrmac2_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_OUTCLK_SOURCE_C0 \"xlnx,gt-ch2-rx-outclk-source-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_OUTCLK_SOURCE_C1 \"xlnx,gt-ch2-rx-outclk-source-c1\" ${mrmac2_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_REFCLK_FREQUENCY_C0 \"xlnx,gt-ch2-rx-refclk-frequency-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_REFCLK_FREQUENCY_C1 \"xlnx,gt-ch2-rx-refclk-frequency-c1\" ${mrmac2_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_USER_DATA_WIDTH_C0 \"xlnx,gt-ch2-rx-user-data-width-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_USER_DATA_WIDTH_C1 \"xlnx,gt-ch2-rx-user-data-width-c1\" ${mrmac2_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TXPROGDIV_FREQ_ENABLE_C0 \"xlnx,gt-ch2-txprogdiv-freq-enable-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TXPROGDIV_FREQ_ENABLE_C1 \"xlnx,gt-ch2-txprogdiv-freq-enable-c1\" ${mrmac2_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TXPROGDIV_FREQ_SOURCE_C0 \"xlnx,gt-ch2-txprogdiv-freq-source-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TXPROGDIV_FREQ_SOURCE_C1 \"xlnx,gt-ch2-txprogdiv-freq-source-c1\" ${mrmac2_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_BUFFER_MODE_C0 \"xlnx,gt-ch2-tx-buffer-mode-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_BUFFER_MODE_C1 \"xlnx,gt-ch2-tx-buffer-mode-c1\" ${mrmac2_node} int\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_DATA_ENCODING_C0 \"xlnx,gt-ch2-tx-data-encoding-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_DATA_ENCODING_C1 \"xlnx,gt-ch2-tx-data-encoding-c1\" ${mrmac2_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_INT_DATA_WIDTH_C0 \"xlnx,gt-ch2-int-data-width-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_INT_DATA_WIDTH_C1 \"xlnx,gt-ch2-int-data-width-c1\" ${mrmac2_node} int\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_LINE_RATE_C0 \"xlnx,gt-ch2-tx-line-rate-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_LINE_RATE_C1 \"xlnx,gt-ch2-tx-line-rate-c1\" ${mrmac2_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_OUTCLK_SOURCE_C0 \"xlnx,gt-ch2-tx-outclk-source-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_OUTCLK_SOURCE_C1 \"xlnx,gt-ch2-tx-outclk-source-c1\" ${mrmac2_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_PLL_TYPE_C0 \"xlnx,gt-ch2-tx-pll-type-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_PLL_TYPE_C1 \"xlnx,gt-ch2-tx-pll-type-c1\" ${mrmac2_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_REFCLK_FREQUENCY_C0 \"xlnx,gt-ch2-tx-refclk-frequency-c0\" ${mrmac2_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_REFCLK_FREQUENCY_C1 \"xlnx,gt-ch2-tx-refclk-frequency-c1\" ${mrmac2_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_USER_DATA_WIDTH_C0 \"xlnx,gt-ch2-tx-user-data-width-c0\" ${mrmac2_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_USER_DATA_WIDTH_C1 \"xlnx,gt-ch2-tx-user-data-width-c1\" ${mrmac2_node} int\n\n\tset mrmac3_base [format 0x%x [expr $base_addr + 0x3000]]\n\tset mrmac3_base_hex [format %x $mrmac3_base]\n\tset mrmac3_highaddr_hex [format 0x%x [expr $mrmac3_base + 0xFFF]]\n\tset port3 3\n\tappend label3 $drv_handle \"_\" $port3\n\tset node_prefix [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tset mrmac3_node [add_or_get_dt_node -n $node_prefix -l \"$label3\" -u $mrmac3_base_hex -d $dts_file -p $bus_node]\n\thsi::utils::add_new_dts_param \"$mrmac3_node\" \"compatible\" \"$compatible\" stringlist\n\tset mrmac3_reg [generate_reg_property $mrmac3_base $mrmac3_highaddr_hex]\n\thsi::utils::add_new_dts_param \"$mrmac3_node\" \"reg\" $mrmac3_reg inthexlist\n\n\tset port3_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"rx_axis_tdata6\"]]\n\tforeach pin $port3_pins {\n\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tset mux_ip \"\"\n\t\tset fifo_ip \"\"\n\t\tif {[llength $sink_periph]} {\n\t\t\tif {[string match -nocase [get_property IP_NAME $sink_periph] \"dcmac_intf_rx\"]} {\n\t\t\t\tset sink_periph [hsi::utils::get_connected_stream_ip [get_cells -hier $sink_periph] \"M_AXIS\"]\n\t\t\t}\n\t\t\tif {[string match -nocase [get_property IP_NAME $sink_periph] \"axis_data_fifo\"]} {\n\t\t\t\tset fifo_width_bytes [get_property CONFIG.TDATA_NUM_BYTES $sink_periph]\n\t\t\t\tif {[string_is_empty $fifo_width_bytes]} {\n\t\t\t\t\tset fifo_width_bytes 1\n\t\t\t\t}\n\t\t\t\tset rxethmem [get_property CONFIG.FIFO_DEPTH $sink_periph]\n\t\t\t\t# FIFO can be other than 8 bits, and we need the rxmem in bytes\n\t\t\t\tset rxethmem [expr $rxethmem * $fifo_width_bytes]\n\t\t\t\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,rxmem\" $rxethmem int\n\t\t\t\tset fifo3_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $sink_periph] \"m_axis_tdata\"]]\n\t\t\t\tset mux_per3 [::hsi::get_cells -of_objects $fifo3_pin]\n\t\t\t\tset fiforx_connect_ip3 \"\"\n\t\t\t\tif {[llength $mux_per3] && [string match -nocase [get_property IP_NAME $mux_per3] \"mrmac_10g_mux\"]} {\n\t\t\t\t\tset data_fifo_pin3 [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mux_per3] \"rx_m_axis_tdata\"]]\n\t\t\t\t\tset data_fifo_per3 [::hsi::get_cells -of_objects $data_fifo_pin3]\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $data_fifo_per3] \"axis_data_fifo\"]} {\n\t\t\t\t\t\tset fiforx_connect_ip3 [hsi::utils::get_connected_stream_ip [get_cells -hier $data_fifo_per3] \"M_AXIS\"]\n\t\t\t\t\t\tset fiforx3_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $data_fifo_per3] \"m_axis_tdata\"]]\n\t\t\t\t\t\tset fiforx3_per [::hsi::get_cells -of_objects $fiforx3_pin]\n\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $fiforx3_per] \"RX_PTP_PKT_DETECT_TS_PREPEND\"]} {\n\t\t\t\t\t\t\tset fiforx_connect_ip3 [hsi::utils::get_connected_stream_ip [get_cells -hier $fiforx3_per] \"M_AXIS\"]\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $mux_per3] \"axi_mcdma\"]} {\n\t\t\t\t\tset fiforx_connect_ip3 $mux_per3\n\t\t\t\t}\n\t\t\t\tif {[llength $fiforx_connect_ip3]} {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $fiforx_connect_ip3] \"axi_mcdma\"]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mrmac3_node\" \"axistream-connected\" \"$fiforx_connect_ip3\" reference\n\t\t\t\t\t\tset num_queues [get_property CONFIG.c_num_mm2s_channels $fiforx_connect_ip3]\n\t\t\t\t\t\tset inhex [format %x $num_queues]\n\t\t\t\t\t\tappend numqueues3 \"/bits/ 16 <0x$inhex>\"\n\t\t\t\t\t\thsi::utils::add_new_dts_param $mrmac3_node \"xlnx,num-queues\" $numqueues3 noformating\n\t\t\t\t\t\tset id 1\n\t\t\t\t\t\tfor {set i 2} {$i <= $num_queues} {incr i} {\n\t\t\t\t\t\t\tset i [format \"%\" $i]\n\t\t\t\t\t\t\tappend id \"\\\"\"\n\t\t\t\t\t\t\tappend id \",\\\"\" $i\n\t\t\t\t\t\t\tset i [expr 0x$i]\n\t\t\t\t\t\t}\n\t\t\t\t\t\thsi::utils::add_new_dts_param $mrmac3_node \"xlnx,num-queues\" $numqueues3 noformating\n\t\t\t\t\t\thsi::utils::add_new_dts_param $mrmac3_node \"xlnx,channel-ids\" $id stringlist\n\t\t\t\t\t\tgenerate_intr_info $drv_handle $mrmac3_node $fiforx_connect_ip3\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\t#set txtodport3_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"tx_timestamp_tod_3\"]]\n\tset txtodport3_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"tx_ptp_tstamp_tag_out_3\"]]\n\n\tif {[llength $txtodport3_pins]} {\n\t\tset tod3_sink_periph [::hsi::get_cells -of_objects $txtodport3_pins]\n\t\tif {[string match -nocase [get_property IP_NAME $tod3_sink_periph] \"mrmac_ptp_timestamp_if\"]} {\n\t\t\tset port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $tod3_sink_periph] \"tx_timestamp_tod\"]]\n\t\t\tset tod3_sink_periph [::hsi::get_cells -of_objects $port_pins]\n\t\t}\n\t\tif {[llength $tod3_sink_periph] && [string match -nocase [get_property IP_NAME $tod3_sink_periph] \"xlconcat\"]} {\n\t\t\tset intf \"dout\"\n\t\t\tset in3_pin [::hsi::get_pins -of_objects $tod3_sink_periph -filter \"NAME==$intf\"]\n\t\t\tset in3sink_pins [::hsi::utils::get_sink_pins $in3_pin]\n\t\t\tset xl_per3 \"\"\n\t\t\tif {[llength $in3sink_pins]} {\n\t\t\t\tset xl_per3 [::hsi::get_cells -of_objects $in3sink_pins]\n\t\t\t}\n\t\t\tif {[llength $xl_per3] && [string match -nocase [get_property IP_NAME $xl_per3] \"axis_dwidth_converter\"]} {\n\t\t\t\tset port3pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $xl_per3] \"m_axis_tdata\"]]\n\t\t\t\tset axis_per3 [::hsi::get_cells -of_objects $port3pins]\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $axis_per3] \"axis_clock_converter\"]} {\n\t\t\t\t\tset tx3_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $axis_per3] \"M_AXIS\"]\n\t\t\t\t\tif {[llength $tx3_ip]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mrmac3_node\" \"axififo-connected\" $tx3_ip reference\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else {\n\t\tdtg_warning \"tx_timestamp_tod_3 connected pins are NULL...please check the design...\"\n\t}\n\n\t#set rxtod3_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"rx_timestamp_tod_3\"]]\n\tset rxtod3_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] \"rx_ptp_tstamp_out_3\"]]\n\n\tif {[llength $rxtod3_pins]} {\n\t\tset rx_periph3 [::hsi::get_cells -of_objects $rxtod3_pins]\n\t\tif {[string match -nocase [get_property IP_NAME $rx_periph3] \"mrmac_ptp_timestamp_if\"]} {\n\t\t\tset port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rx_periph3] \"rx_timestamp_tod\"]]\n\t\t\tset rx_periph3 [::hsi::get_cells -of_objects $port_pins]\n\t\t}\n\t\tif {[llength $rx_periph3] && [string match -nocase [get_property IP_NAME $rx_periph3] \"xlconcat\"]} {\n\t\t\tset intf \"dout\"\n\t\t\tset inrx3_pin [::hsi::get_pins -of_objects $rx_periph3 -filter \"NAME==$intf\"]\n\t\t\tset rxtodsink_pins [::hsi::utils::get_sink_pins $inrx3_pin]\n\t\t\tset rx_per3 \"\"\n\t\t\tif {[llength $rxtodsink_pins]} {\n\t\t\t\tset rx_per3 [::hsi::get_cells -of_objects $rxtodsink_pins]\n\t\t\t}\n\t\t\tif {[llength $rx_per3] && [string match -nocase [get_property IP_NAME $rx_per3] \"axis_dwidth_converter\"]} {\n\t\t\t\tset port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rx_per3] \"m_axis_tdata\"]]\n\t\t\t\tset rx_axis_per3 [::hsi::get_cells -of_objects $port_pins]\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $rx_axis_per3] \"axis_clock_converter\"]} {\n\t\t\t\t\tset rx_ip3 [hsi::utils::get_connected_stream_ip [get_cells -hier $rx_axis_per3] \"M_AXIS\"]\n\t\t\t\t\tif {[llength $rx_ip3]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$mrmac3_node\" \"xlnx,rxtsfifo\" $rx_ip3 reference\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else {\n\t\tdtg_warning \"rx_timestamp_tod_3 connected pins are NULL...please check the design...\"\n\t}\n\n\n\tif {[llength $handle]} {\n\t\thsi::utils::add_new_dts_param \"$mrmac3_node\" \"xlnx,gtctrl\" $handle reference\n\t}\n\tif {[llength $mask_handle]} {\n\t\thsi::utils::add_new_dts_param \"$mrmac3_node\" \"xlnx,gtpll\" $mask_handle reference\n\t}\n\tif {[llength $gt_reset_per]} {\n\t\thsi::utils::add_new_dts_param \"$mrmac3_node\" \"xlnx,gtctrl\" $gt_reset_per reference\n\t}\n\tif {[llength $gt_pll_per]} {\n\t\thsi::utils::add_new_dts_param \"$mrmac3_node\" \"xlnx,gtpll\" $gt_pll_per reference\n\t}\n\thsi::utils::add_new_dts_param \"$mrmac3_node\" \"xlnx,phcindex\" 3 int\n\thsi::utils::add_new_dts_param \"$mrmac3_node\" \"xlnx,gtlane\" 3 int\n\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"mrmac\"]} {\n\t\tlappend clknames3 \"$s_axi_aclk\" \"$rx_axi_clk3\" \"$rx_flexif_clk3\" \"$rx_ts_clk3\" \"$tx_axi_clk3\" \"$tx_flexif_clk3\" \"$tx_ts_clk3\"\n\t\tset tmpclks3 [fix_clockprop \"[lindex $clk_list $s_axi_aclk_index0]\" \"[lindex $clk_list $rx_axi_clk_index3]\"]\n\t\tset txindex3 [lindex $clk_list $tx_ts_clk_index3]\n\t\tregsub -all \"\\>\" $txindex3 {} txindex3\n\t\tappend clkvals3 \"[lindex $tmpclks3 0], [lindex $tmpclks3 1], [lindex $clk_list $rx_flexif_clk_index3], [lindex $clk_list $rx_ts_clk3_index3], [lindex $clk_list $tx_axi_clk_index3], [lindex $clk_list $tx_flexif_clk_index3], $txindex3\"\n\t\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"clocks\" $clkvals3 reference\n\t\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"clock-names\" $clknames3 stringlist\n\t}\n\tif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] \"dcmac\"]} {\n\t\tlappend clknames3 \"$s_axi_aclk\" \"$rx_axi_clk0\" \"$rx_flexif_clk3\" \"$tx_axi_clk0\" \"$tx_flexif_clk3\" \"$rx_macif_clk\" \"$ts_clk3\" \"$tx_macif_clk\" \"$tx_serdes_clk3\"\n\t\tset tmpclks3 [fix_clockprop \"[lindex $clk_list $s_axi_aclk_index0]\" \"[lindex $clk_list $rx_axi_clk_index0]\"]\n\t\tset txindex3 [lindex $clk_list $tx_serdes_clk_index3]\n\t\tregsub -all \"\\>\" $txindex3 {} txindex3\n\t\tappend clkvals3 \"[lindex $tmpclks3 0], [lindex $tmpclks3 1], [lindex $clk_list $rx_flexif_clk_index3], [lindex $clk_list $tx_axi_clk_index0], [lindex $clk_list $tx_flexif_clk_index3], [lindex $clk_list $rx_macif_clk_index0], [lindex $clk_list $ts_clk_index3], [lindex $clk_list $tx_macif_clk_index0], $txindex3\"\n\t\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"clocks\" $clkvals3 reference\n\t\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"clock-names\" $clknames3 stringlist\n\t}\n\n\tadd_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE3_CFG_C0 \"xlnx,flex-slice3-cfg-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE3_CFG_C1 \"xlnx,flex-slice3-cfg-c1\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT3_DATA_RATE_C0 \"xlnx,flex-port3-data-rate-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT3_DATA_RATE_C1 \"xlnx,flex-port3-data-rate-c1\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT3_ENABLE_TIME_STAMPING_C0 \"xlnx,flex-port3-enable-time-stamping-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT3_ENABLE_TIME_STAMPING_C1 \"xlnx,flex-port3-enable-time-stamping-c1\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT3_MODE_C0 \"xlnx,flex-port3-mode-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT3_MODE_C1 \"xlnx,flex-port3-mode-c1\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT3_1588v2_Clocking_C0 \"xlnx,port3-1588v2-clocking-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT3_1588v2_Clocking_C1 \"xlnx,port3-1588v2-clocking-c1\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT3_1588v2_Operation_MODE_C0 \"xlnx,port3-1588v2-operation-mode-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.PORT3_1588v2_Operation_MODE_C1 \"xlnx,port3-1588v2-operation-mode-c1\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_ENABLE_TIME_STAMPING_C0 \"xlnx,mac-port3-enable-time-stamping-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_ENABLE_TIME_STAMPING_C1 \"xlnx,mac-port3-enable-time-stamping-c1\" ${mrmac3_node} int\n\n\tset MAC_PORT3_RATE_C0 [get_property CONFIG.MAC_PORT3_RATE_C0 [get_cells -hier $drv_handle]]\n\tif {[llength $MAC_PORT3_RATE_C0]} {\n\t\tif {[string match -nocase $MAC_PORT3_RATE_C0 \"10GE\"]} {\n\t\t\tset number 10000\n\t\t\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mrmac-rate\" $number int\n\t\t} else {\n\t\t\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mrmac-rate\" $MAC_PORT3_RATE_C0 string\n\t\t}\n\t}\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RATE_C1 \"xlnx,mac-port3-rate-c1\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_GCP_C0 \"xlnx,mac-port3-rx-etype-gcp-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_GCP_C1 \"xlnx,mac-port3-rx-etype-gcp-c1\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_GPP_C0 \"xlnx,mac-port3-rx-etype-gpp-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_GPP_C1 \"xlnx,mac-port3-rx-etype-gpp-c1\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_PCP_C0 \"xlnx,mac-port3-rx-etype-pcp-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_PCP_C1 \"xlnx,mac-port3-rx-etype-pcp-c1\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_PPP_C0 \"xlnx,mac-port3-rx-etype-ppp-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_PPP_C1 \"xlnx,mac-port3-rx-etype-ppp-c1\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_FLOW_C0 \"xlnx,mac-port3-rx-flow-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_FLOW_C1 \"xlnx,mac-port3-rx-flow-c1\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_GPP_C0 \"xlnx,mac-port3-rx-opcode-gpp-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_GPP_C1 \"xlnx,mac-port3-rx-opcode-gpp-c1\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MAX_GCP_C0 \"xlnx,mac-port3-rx-opcode-max-gcp-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MAX_GCP_C1 \"xlnx,mac-port3-rx-opcode-max-gcp-c1\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MAX_PCP_C0 \"xlnx,mac-port3-rx-opcode-max-pcp-c0\" ${mrmac3_node} int\n\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MAX_PCP_C1 \"xlnx,mac-port3-rx-opcode-max-pcp-c1\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MIN_GCP_C0 \"xlnx,mac-port3-rx-opcode-min-gcp-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MIN_GCP_C1 \"xlnx,mac-port3-rx-opcode-min-gcp-c1\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MIN_PCP_C0 \"xlnx,mac-port3-rx-opcode-min-pcp-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MIN_PCP_C1 \"xlnx,mac-port3-rx-opcode-min-pcp-c1\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_PPP_C0 \"xlnx,mac-port3-rx-opcode-ppp-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_PPP_C1 \"xlnx,mac-port3-rx-opcode-ppp-c1\" ${mrmac3_node} int\n\n\tset MAC_PORT3_RX_PAUSE_DA_MCAST_C0 [get_property CONFIG.MAC_PORT3_RX_PAUSE_DA_MCAST_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT3_RX_PAUSE_DA_MCAST_C0 [check_size $MAC_PORT3_RX_PAUSE_DA_MCAST_C0 $mrmac3_node]\n\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mac-port3-rx-pause-da-mcast-c0\" $MAC_PORT3_RX_PAUSE_DA_MCAST_C0 int\n\tset MAC_PORT3_RX_PAUSE_DA_MCAST_C1 [get_property CONFIG.MAC_PORT3_RX_PAUSE_DA_MCAST_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT3_RX_PAUSE_DA_MCAST_C1 [check_size $MAC_PORT3_RX_PAUSE_DA_MCAST_C1 $mrmac3_node]\n\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mac-port3-rx-pause-da-mcast-c1\" $MAC_PORT3_RX_PAUSE_DA_MCAST_C1 int\n\tset MAC_PORT3_RX_PAUSE_DA_UCAST_C0 [get_property CONFIG.MAC_PORT3_RX_PAUSE_DA_UCAST_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT3_RX_PAUSE_DA_UCAST_C0 [check_size $MAC_PORT3_RX_PAUSE_DA_UCAST_C0 $mrmac3_node]\n\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mac-port3-rx-pause-da-ucast-c0\" $MAC_PORT3_RX_PAUSE_DA_UCAST_C0 int\n\tset MAC_PORT3_RX_PAUSE_DA_UCAST_C1 [get_property CONFIG.MAC_PORT3_RX_PAUSE_DA_UCAST_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT3_RX_PAUSE_DA_UCAST_C1 [check_size $MAC_PORT3_RX_PAUSE_DA_UCAST_C1 $mrmac3_node]\n\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mac-port3-rx-pause-da-ucast-c1\" $MAC_PORT3_RX_PAUSE_DA_UCAST_C1 int\n\tset MAC_PORT3_RX_PAUSE_SA_C0 [get_property CONFIG.MAC_PORT3_RX_PAUSE_SA_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT3_RX_PAUSE_SA_C0 [check_size $MAC_PORT3_RX_PAUSE_SA_C0 $mrmac3_node]\n\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mac-port3-rx-pause-sa-c0\" $MAC_PORT3_RX_PAUSE_SA_C0 int\n\tset MAC_PORT3_RX_PAUSE_SA_C1 [get_property CONFIG.MAC_PORT3_RX_PAUSE_SA_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT3_RX_PAUSE_SA_C1 [check_size $MAC_PORT3_RX_PAUSE_SA_C1 $mrmac3_node]\n\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mac-port3-rx-pause-sa-c1\" $MAC_PORT3_RX_PAUSE_SA_C1 int\n\tset MAC_PORT3_TX_DA_GPP_C0 [get_property CONFIG.MAC_PORT3_TX_DA_GPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT3_TX_DA_GPP_C0 [check_size $MAC_PORT3_TX_DA_GPP_C0 $mrmac3_node]\n\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mac-port3-tx-da-gpp-c0\" $MAC_PORT3_TX_DA_GPP_C0 int\n\tset MAC_PORT3_TX_DA_GPP_C1 [get_property CONFIG.MAC_PORT3_TX_DA_GPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT3_TX_DA_GPP_C1 [check_size $MAC_PORT3_TX_DA_GPP_C1 $mrmac3_node]\n\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mac-port3-tx-da-gpp-c1\" $MAC_PORT3_TX_DA_GPP_C1 int\n\tset MAC_PORT3_TX_DA_PPP_C0 [get_property CONFIG.MAC_PORT3_TX_DA_PPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT3_TX_DA_PPP_C0 [check_size $MAC_PORT3_TX_DA_PPP_C0 $mrmac3_node]\n\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mac-port3-tx-da-ppp-c0\" $MAC_PORT3_TX_DA_PPP_C0 int\n\tset MAC_PORT3_TX_DA_PPP_C1 [get_property CONFIG.MAC_PORT3_TX_DA_PPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT3_TX_DA_PPP_C1 [check_size $MAC_PORT3_TX_DA_PPP_C1 $mrmac3_node]\n\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mac-port3-tx-da-ppp-c1\" $MAC_PORT3_TX_DA_PPP_C1 int\n\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_ETHERTYPE_GPP_C0 \"xlnx,mac-port3-tx-ethertype-gpp-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_ETHERTYPE_GPP_C1 \"xlnx,mac-port3-tx-ethertype-gpp-c1\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_ETHERTYPE_PPP_C0 \"xlnx,mac-port3-tx-ethertype-ppp-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_ETHERTYPE_PPP_C1 \"xlnx,mac-port3-tx-ethertype-ppp-c1\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_FLOW_C0 \"xlnx,mac-port3-tx-flow-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_FLOW_C1 \"xlnx,mac-port3-tx-flow-c1\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_OPCODE_GPP_C0 \"xlnx,mac-port3-tx-opcode-gpp-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_OPCODE_GPP_C1 \"xlnx,mac-port3-tx-opcode-gpp-c1\" ${mrmac3_node} int\n\n\tset MAC_PORT3_TX_SA_GPP_C0 [get_property CONFIG.MAC_PORT3_TX_SA_GPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT3_TX_SA_GPP_C0 [check_size $MAC_PORT3_TX_SA_GPP_C0 $mrmac3_node]\n\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mac-port3-tx-sa-gpp-c0\" $MAC_PORT3_TX_SA_GPP_C0 int\n\tset MAC_PORT3_TX_SA_GPP_C1 [get_property CONFIG.MAC_PORT3_TX_SA_GPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT3_TX_SA_GPP_C1 [check_size $MAC_PORT3_TX_SA_GPP_C1 $mrmac3_node]\n\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mac-port3-tx-sa-gpp-c1\" $MAC_PORT3_TX_SA_GPP_C1 int\n\tset MAC_PORT3_TX_SA_PPP_C0 [get_property CONFIG.MAC_PORT3_TX_SA_PPP_C0 [get_cells -hier $drv_handle]]\n\tset MAC_PORT3_TX_SA_PPP_C0 [check_size $MAC_PORT3_TX_SA_PPP_C0 $mrmac3_node]\n\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mac-port3-tx-sa-ppp-c0\" $MAC_PORT3_TX_SA_PPP_C0 int\n\tset MAC_PORT3_TX_SA_PPP_C1 [get_property CONFIG.MAC_PORT3_TX_SA_PPP_C1 [get_cells -hier $drv_handle]]\n\tset MAC_PORT3_TX_SA_PPP_C1 [check_size $MAC_PORT3_TX_SA_PPP_C1 $mrmac3_node]\n\thsi::utils::add_new_dts_param \"${mrmac3_node}\" \"xlnx,mac-port3-tx-sa-ppp-c1\" $MAC_PORT3_TX_SA_PPP_C1 int\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RXPROGDIV_FREQ_ENABLE_C0 \"xlnx,gt-ch3-rxprogdiv-freq-enable-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RXPROGDIV_FREQ_ENABLE_C1 \"xlnx,gt-ch3-rxprogdiv-freq-enable-c1\" ${mrmac3_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RXPROGDIV_FREQ_SOURCE_C0 \"xlnx,gt-ch3-rxprogdiv-freq-source-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RXPROGDIV_FREQ_SOURCE_C1 \"xlnx,gt-ch3-rxprogdiv-freq-source-c1\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RXPROGDIV_FREQ_VAL_C0 \"xlnx,gt-ch3-rxprogdiv-freq-val-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RXPROGDIV_FREQ_VAL_C1 \"xlnx,gt-ch3-rxprogdiv-freq-val-c1\" ${mrmac3_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_BUFFER_MODE_C0 \"xlnx,gt-ch3-rx-buffer-mode-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_BUFFER_MODE_C1 \"xlnx,gt-ch3-rx-buffer-mode-c1\" ${mrmac3_node} int\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_DATA_DECODING_C0 \"xlnx,gt-ch3-rx-data-decoding-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_DATA_DECODING_C1 \"xlnx,gt-ch3-rx-data-decoding-c1\" ${mrmac3_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_INT_DATA_WIDTH_C0 \"xlnx,gt-ch3-rx-int-data-width-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_INT_DATA_WIDTH_C1 \"xlnx,gt-ch3-rx-int-data-width-c1\" ${mrmac3_node} int\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_LINE_RATE_C0 \"xlnx,gt-ch3-rx-line-rate-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_LINE_RATE_C1 \"xlnx,gt-ch3-rx-line-rate-c1\" ${mrmac3_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_OUTCLK_SOURCE_C0 \"xlnx,gt-ch3-rx-outclk-source-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_OUTCLK_SOURCE_C1 \"xlnx,gt-ch3-rx-outclk-source-c1\" ${mrmac3_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_REFCLK_FREQUENCY_C0 \"xlnx,gt-ch3-rx-refclk-frequency-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_REFCLK_FREQUENCY_C1 \"xlnx,gt-ch3-rx-refclk-frequency-c1\" ${mrmac3_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_USER_DATA_WIDTH_C0 \"xlnx,gt-ch3-rx-user-data-width-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_USER_DATA_WIDTH_C1 \"xlnx,gt-ch3-rx-user-data-width-c1\" ${mrmac3_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TXPROGDIV_FREQ_ENABLE_C0 \"xlnx,gt-ch3-txprogdiv-freq-enable-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TXPROGDIV_FREQ_ENABLE_C1 \"xlnx,gt-ch3-txprogdiv-freq-enable-c1\" ${mrmac3_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TXPROGDIV_FREQ_SOURCE_C0 \"xlnx,gt-ch3-txprogdiv-freq-source-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TXPROGDIV_FREQ_SOURCE_C1 \"xlnx,gt-ch3-txprogdiv-freq-source-c1\" ${mrmac3_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_BUFFER_MODE_C0 \"xlnx,gt-ch3-tx-buffer-mode-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_BUFFER_MODE_C1 \"xlnx,gt-ch3-tx-buffer-mode-c1\" ${mrmac3_node} int\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_DATA_ENCODING_C0 \"xlnx,gt-ch3-tx-data-encoding-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_DATA_ENCODING_C1 \"xlnx,gt-ch3-tx-data-encoding-c1\" ${mrmac3_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_INT_DATA_WIDTH_C0 \"xlnx,gt-ch3-int-data-width-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_INT_DATA_WIDTH_C1 \"xlnx,gt-ch3-int-data-width-c1\" ${mrmac3_node} int\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_LINE_RATE_C0 \"xlnx,gt-ch3-tx-line-rate-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_LINE_RATE_C1 \"xlnx,gt-ch3-tx-line-rate-c1\" ${mrmac3_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_OUTCLK_SOURCE_C0 \"xlnx,gt-ch3-tx-outclk-source-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_OUTCLK_SOURCE_C1 \"xlnx,gt-ch3-tx-outclk-source-c1\" ${mrmac3_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_PLL_TYPE_C0 \"xlnx,gt-ch3-tx-pll-type-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_PLL_TYPE_C1 \"xlnx,gt-ch3-tx-pll-type-c1\" ${mrmac3_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_REFCLK_FREQUENCY_C0 \"xlnx,gt-ch3-tx-refclk-frequency-c0\" ${mrmac3_node}\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_REFCLK_FREQUENCY_C1 \"xlnx,gt-ch3-tx-refclk-frequency-c1\" ${mrmac3_node}\n\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_USER_DATA_WIDTH_C0 \"xlnx,gt-ch3-tx-user-data-width-c0\" ${mrmac3_node} int\n\tadd_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_USER_DATA_WIDTH_C1 \"xlnx,gt-ch3-tx-user-data-width-c1\" ${mrmac3_node} int\n}\n\nproc generate_intr_info {drv_handle node fifo_ip} {\n\tset ips [get_cells -hier $drv_handle]\n\tforeach ip [get_drivers] {\n\t\tif {[string compare -nocase $ip $fifo_ip] == 0} {\n\t\t\tset target_handle $ip\n\t\t}\n\t}\n\tset intr_val [get_property CONFIG.interrupts $target_handle]\n\tset intr_parent [get_property CONFIG.interrupt-parent $target_handle]\n\tset int_names [get_property CONFIG.interrupt-names $target_handle]\n\thsi::utils::add_new_dts_param \"${node}\" \"interrupts\" $intr_val int\n\thsi::utils::add_new_dts_param \"${node}\" \"interrupt-parent\" $intr_parent reference\n\thsi::utils::add_new_dts_param \"${node}\" \"interrupt-names\" $int_names stringlist\n}\n\nproc check_size {base node} {\n\tif {[regexp -nocase {0x([0-9a-f]{9})} \"$base\" match]} {\n\t\tset temp $base\n\t\tset temp [string trimleft [string trimleft $temp 0] x]\n\t\tset len [string length $temp]\n\t\tset rem [expr {${len} - 8}]\n\t\tset high_base \"0x[string range $temp $rem $len]\"\n\t\tset low_base \"0x[string range $temp 0 [expr {${rem} - 1}]]\"\n\t\tset low_base [format 0x%08x $low_base]\n\t\tset reg \"$low_base $high_base\"\n\t} else {\n\t\tset reg \"$base\"\n\t}\n\treturn $reg\n}\n\nproc gen_mrmac_clk_property {drv_handle} {\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tif {[string match -nocase $proctype \"microblaze\"]} {\n\t\treturn\n\t}\n\tset clocks \"\"\n\tset axi 0\n\tset is_clk_wiz 0\n\tset is_pl_clk 0\n\tset updat \"\"\n\tglobal bus_clk_list\n\tset clocknames \"\"\n\tset clk_pins [get_pins -of_objects [get_cells -hier $drv_handle] -filter {TYPE==clk&&DIRECTION==I || TYPE==gt_usrclk&&DIRECTION==I}]\n\tset ip [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tforeach clk $clk_pins {\n\t\tset ip [get_cells -hier $drv_handle]\n\t\tset port_width [::hsi::utils::get_port_width $clk]\n\t\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] $clk]]\n\t\tif {$port_width >= 2} {\n\t\t\tfor {set i 0} { $i < $port_width} {incr i} {\n\t\t\t\tset peri [::hsi::get_cells -of_objects $pins]\n\t\t\t\tset mrclk \"$clk$i\"\n\t\t\t\tif {[llength $peri]} {\n\t\t\t\t\tif {[string match -nocase [common::get_property IP_NAME $peri] \"xlconcat\"]} {\n\t\t\t\t\t\tset pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects [get_cells $peri] In$i]] -filter \"DIRECTION==O\"]\n\t\t\t\t\t\tset clk_peri [::hsi::get_cells -of_objects $pins]\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tset valid_clk_list \"clk_out0 clk_out1 clk_out2 clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 clk_out8 clk_out9\"\n\t\t\t\tset pl_clk \"\"\n\t\t\t\tset clkout \"\"\n\t\t\t\tforeach pin $pins {\n\t\t\t\t\tif {[lsearch $valid_clk_list $pin] >= 0} {\n\t\t\t\t\t\tset clkout $pin\n\t\t\t\t\t\tset is_clk_wiz 1\n\t\t\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {[llength $clkout]} {\n\t\t\t\t\tset number [regexp -all -inline -- {[0-9]+} $clkout]\n\t\t\t\t\tset clk_wiz [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk]\n\t\t\t\t\tset axi_clk \"s_axi_aclk\"\n\t\t\t\t\tforeach clk1 $clk_wiz {\n\t\t\t\t\t\tif {[regexp $axi_clk $clk1 match]} {\n\t\t\t\t\t\t\tset axi 1\n\t\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif {[string match -nocase $axi \"0\"]} {\n\t\t\t\t\tdtg_warning \"no s_axi_aclk for clockwizard\"\n\t\t\t\t\tset pins [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk]\n\t\t\t\t\tset clk_list \"pl_clk*\"\n\t\t\t\t\tset clk_pl \"\"\n\t\t\t\t\tset num \"\"\n\t\t\t\t\tforeach clk_wiz_pin $pins {\n\t\t\t\t\t\t\tset clk_wiz_pins [get_pins -of_objects [get_nets -of_objects $clk_wiz_pin]]\n\t\t\t\t\t\t\tforeach pin $clk_wiz_pins {\n\t\t\t\t\t\t\t\tif {[regexp $clk_list $pin match]} {\n\t\t\t\t\t\t\t\t\tset clk_pl $pin\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tif {[llength $clk_pl]} {\n\t\t\t\t\t\tset num [regexp -all -inline -- {[0-9]+} $clk_pl]\n\t\t\t\t\t}\n\t\t\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\t\t\t\t\tswitch $num {\n\t\t\t\t\t\t\t\t\t\"0\" {\n\t\t\t\t\t\t\t\t\t\tset def_dts [get_property CONFIG.pcw_dts [get_os]]\n\t\t\t\t\t\t\t\t\t\tset fclk_node [add_or_get_dt_node -n \"&fclk0\" -d $def_dts]\n\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${fclk_node}\" \"status\" \"okay\" string\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\"1\" {\n\t\t\t\t\t\t\t\t\t\tset def_dts [get_property CONFIG.pcw_dts [get_os]]\n\t\t\t\t\t\t\t\t\t\t set fclk_node [add_or_get_dt_node -n \"&fclk1\" -d $def_dts]\n\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${fclk_node}\" \"status\" \"okay\" string\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\"2\" {\n\t\t\t\t\t\t\t\t\t\tset def_dts [get_property CONFIG.pcw_dts [get_os]]\n\t\t\t\t\t\t\t\t\t\tset fclk_node [add_or_get_dt_node -n \"&fclk2\" -d $def_dts]\n\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${fclk_node}\" \"status\" \"okay\" string\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\t\"3\" {\n\t\t\t\t\t\t\t\t\t\tset def_dts [get_property CONFIG.pcw_dts [get_os]]\n\t\t\t\t\t\t\t\t\t\tset fclk_node [add_or_get_dt_node -n \"&fclk3\" -d $def_dts]\n\t\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"${fclk_node}\" \"status\" \"okay\" string\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tset dts_file \"pl.dtsi\"\n\t\t\t\t\tset bus_node [add_or_get_bus_node $drv_handle $dts_file]\n\t\t\t\t\tset clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"$clk\"]\n\t\t\t\t\tif {[llength $clk_freq] == 0} {\n\t\t\t\t\t\tdtg_warning \"clock frequency for the $clk is NULL\"\n\t\t\t\t\t\tcontinue\n\t\t\t\t\t}\n\t\t\t\t\tset clk_freq [expr int($clk_freq)]\n\t\t\t\t\tset iptype [get_property IP_NAME [get_cells -hier $drv_handle]]\n\t\t\t\t\tif {![string equal $clk_freq \"\"]} {\n\t\t\t\t\t\tif {[lsearch $bus_clk_list $clk_freq] < 0} {\n\t\t\t\t\t\t\tset bus_clk_list [lappend bus_clk_list $clk_freq]\n\t\t\t\t\t\t}\n\t\t\t\t\t\tset bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]\n\t\t\t\t\t\tset misc_clk_node [add_or_get_dt_node -n \"misc_clk_${bus_clk_cnt}\" -l \"misc_clk_${bus_clk_cnt}\" \\\n\t\t\t\t\t\t-d ${dts_file} -p ${bus_node}]\n\t\t\t\t\t\tset clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]\n\t\t\t\t\t\tset updat [lappend updat misc_clk_${bus_clk_cnt}]\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-frequency\" $clk_freq int\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {![string match -nocase $axi \"0\"]} {\n\t\t\t\t\t\tswitch $number {\n\t\t\t\t\t\t\t\t\"1\" {\n\t\t\t\t\t\t\t\t\tset peri \"$periph 0\"\n\t\t\t\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\"2\" {\n\t\t\t\t\t\t\t\t\tset peri \"$periph 1\"\n\t\t\t\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\"3\" {\n\t\t\t\t\t\t\t\t\tset peri \"$periph 2\"\n\t\t\t\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\"4\" {\n\t\t\t\t\t\t\t\t\tset peri \"$periph 3\"\n\t\t\t\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\"5\" {\n\t\t\t\t\t\t\t\t\tset peri \"$periph 4\"\n\t\t\t\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\"6\" {\n\t\t\t\t\t\t\t\t\tset peri \"$periph 5\"\n\t\t\t\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\"7\" {\n\t\t\t\t\t\t\t\t\tset peri \"$periph 6\"\n\t\t\t\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\t\tset clklist \"pl_clk0 pl_clk1 pl_clk2 pl_clk3\"\n\t\t\t} elseif {[string match -nocase $proctype \"ps7_cortexa9\"]} {\n\t\t\t\tset clklist \"FCLK_CLK0 FCLK_CLK1 FCLK_CLK2 FCLK_CLK3\"\n\t\t\t}\n\t\t\tforeach pin $pins {\n\t\t\t\tif {[lsearch $clklist $pin] >= 0} {\n\t\t\t\t\tset pl_clk $pin\n\t\t\t\t\tset is_pl_clk 1\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[string match -nocase $proctype \"psv_cortexa72\"]} {\n\t\t\t\tswitch $pl_clk {\n\t\t\t\t\t\t\"pl_clk0\" {\n\t\t\t\t\t\t\t\tset pl_clk0 \"versal_clk 65\"\n\t\t\t\t\t\t\t\tset clocks [lappend clocks $pl_clk0]\n\t\t\t\t\t\t\t\tset updat [lappend updat $pl_clk0]\n\t\t\t\t\t\t}\n\t\t\t\t\t\t\"pl_clk1\" {\n\t\t\t\t\t\t\t\tset pl_clk1 \"versal_clk 66\"\n\t\t\t\t\t\t\t\tset clocks [lappend clocks $pl_clk1]\n\t\t\t\t\t\t\t\tset updat [lappend updat $pl_clk1]\n\t\t\t\t\t\t}\n\t\t\t\t\t\t\"pl_clk2\" {\n\t\t\t\t\t\t\t\tset pl_clk2 \"versal_clk 67\"\n\t\t\t\t\t\t\t\tset clocks [lappend clocks $pl_clk2]\n\t\t\t\t\t\t\t\tset updat [lappend updat $pl_clk2]\n\t\t\t\t\t\t}\n\t\t\t\t\t\t\"pl_clk3\" {\n\t\t\t\t\t\t\t\tset pl_clk3 \"versal_clk 68\"\n\t\t\t\t\t\t\t\tset clocks [lappend clocks $pl_clk3]\n\t\t\t\t\t\t\t\tset updat [lappend updat $pl_clk3]\n\t\t\t\t\t\t}\n\t\t\t\t\t\tdefault {\n\t\t\t\t\t\t\t\tdtg_debug \"not supported pl_clk:$pl_clk\"\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t}\n\t\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\t\t\tswitch $pl_clk {\n\t\t\t\t\t\t\t\"pl_clk0\" {\n\t\t\t\t\t\t\t\t\tset pl_clk0 \"zynqmp_clk 71\"\n\t\t\t\t\t\t\t\t\tset clocks [lappend clocks $pl_clk0]\n\t\t\t\t\t\t\t\t\tset updat [lappend updat $pl_clk0]\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\"pl_clk1\" {\n\t\t\t\t\t\t\t\t\tset pl_clk1 \"zynqmp_clk 72\"\n\t\t\t\t\t\t\t\t\tset clocks [lappend clocks $pl_clk1]\n\t\t\t\t\t\t\t\t\tset updat [lappend updat $pl_clk1]\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\"pl_clk2\" {\n\t\t\t\t\t\t\t\t\tset pl_clk2 \"zynqmp_clk 73\"\n\t\t\t\t\t\t\t\t\tset clocks [lappend clocks $pl_clk2]\n\t\t\t\t\t\t\t\t\tset updat [lappend updat $pl_clk2]\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\"pl_clk3\" {\n\t\t\t\t\t\t\t\t\tset pl_clk3 \"zynqmp_clk 74\"\n\t\t\t\t\t\t\t\t\tset clocks [lappend clocks $pl_clk3]\n\t\t\t\t\t\t\t\t\tset updat [lappend updat $pl_clk3]\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tdefault {\n\t\t\t\t\t\t\t\t\tdtg_debug \"not supported pl_clk:$pl_clk\"\n\t\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t}\n\t\t\tif {[string match -nocase $proctype \"ps7_cortexa9\"]} {\n\t\t\t\t\t\tswitch $pl_clk {\n\t\t\t\t\t\t\t\"FCLK_CLK0\" {\n\t\t\t\t\t\t\t\t\tset pl_clk0 \"clkc 15\"\n\t\t\t\t\t\t\t\t\tset clocks [lappend clocks $pl_clk0]\n\t\t\t\t\t\t\t\t\tset updat [lappend updat $pl_clk0]\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\"FCLK_CLK1\" {\n\t\t\t\t\t\t\t\t\tset pl_clk1 \"clkc 16\"\n\t\t\t\t\t\t\t\t\tset clocks [lappend clocks $pl_clk1]\n\t\t\t\t\t\t\t\t\tset updat [lappend updat $pl_clk1]\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\"FCLK_CLK2\" {\n\t\t\t\t\t\t\t\t\tset pl_clk2 \"clkc 17\"\n\t\t\t\t\t\t\t\t\tset clocks [lappend clocks $pl_clk2]\n\t\t\t\t\t\t\t\t\tset updat [lappend updat $pl_clk2]\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\"FCLK_CLK3\" {\n\t\t\t\t\t\t\t\t\tset pl_clk3 \"clkc 18\"\n\t\t\t\t\t\t\t\t\tset clocks [lappend clocks $pl_clk3]\n\t\t\t\t\t\t\t\t\tset updat [lappend updat $pl_clk3]\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tdefault {\n\t\t\t\t\t\t\t\t\tdtg_debug \"not supported pl_clk:$pl_clk\"\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t}\n\t\t\tif {[string match -nocase $is_clk_wiz \"0\"]&& [string match -nocase $is_pl_clk \"0\"]} {\n\t\t\t\t\tset dts_file \"pl.dtsi\"\n\t\t\t\t\tset bus_node [add_or_get_bus_node $drv_handle $dts_file]\n\t\t\t\t\tset clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"$clk\"]\n\t\t\t\t\tif {[llength $clk_freq] == 0} {\n\t\t\t\t\t\tdtg_warning \"clock frequency for the $clk is NULL\"\n\t\t\t\t\t\tcontinue\n\t\t\t\t\t}\n\t\t\t\t\tset clk_freq [expr int($clk_freq)]\n\t\t\t\t\tset iptype [get_property IP_NAME [get_cells -hier $drv_handle]]\n\t\t\t\t\tif {![string equal $clk_freq \"\"]} {\n\t\t\t\t\t\tif {[lsearch $bus_clk_list $clk_freq] < 0} {\n\t\t\t\t\t\t\tset bus_clk_list [lappend bus_clk_list $clk_freq]\n\t\t\t\t\t\t}\n\t\t\t\t\t\tset bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]\n\t\t\t\t\t\tset misc_clk_node [add_or_get_dt_node -n \"misc_clk_${bus_clk_cnt}\" -l \"misc_clk_${bus_clk_cnt}\" \\\n\t\t\t\t\t\t-d ${dts_file} -p ${bus_node}]\n\t\t\t\t\t\tset clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]\n\t\t\t\t\t\tset updat [lappend updat misc_clk_${bus_clk_cnt}]\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-frequency\" $clk_freq int\n\t\t\t\t\t}\n\t\t\t}\n\t\t\tappend clocknames \" \" \"$mrclk\"\n\t\t\tset is_pl_clk 0\n\t\t\tset is_clk_wiz 0\n\t\t\tset axi 0\n\t\t}\n\t} else {\n\t\tset valid_clk_list \"clk_out0 clk_out1 clk_out2 clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 clk_out8 clk_out9\"\n\t\tset pl_clk \"\"\n\t\tset clkout \"\"\n\t\tforeach pin $pins {\n\t\t\tif {[lsearch $valid_clk_list $pin] >= 0} {\n\t\t\t\tset clkout $pin\n\t\t\t\tset is_clk_wiz 1\n\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t}\n\t\t}\n\t\tif {[llength $clkout]} {\n\t\t\tset number [regexp -all -inline -- {[0-9]+} $clkout]\n\t\t\tset clk_wiz [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk]\n\t\t\tset axi_clk \"s_axi_aclk\"\n\t\t\tforeach clk1 $clk_wiz {\n\t\t\t\tif {[regexp $axi_clk $clk1 match]} {\n\t\t\t\t\tset axi 1\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {[string match -nocase $axi \"0\"]} {\n\t\t\t\tdtg_warning \"no s_axi_aclk for clockwizard\"\n\t\t\t\tset pins [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk]\n\t\t\t\tset clk_list \"pl_clk*\"\n\t\t\t\tset clk_pl \"\"\n\t\t\t\tset num \"\"\n\t\t\t\tforeach clk_wiz_pin $pins {\n\t\t\t\t\tset clk_wiz_pins [get_pins -of_objects [get_nets -of_objects $clk_wiz_pin]]\n\t\t\t\t\tforeach pin $clk_wiz_pins {\n\t\t\t\t\t\tif {[regexp $clk_list $pin match]} {\n\t\t\t\t\t\t\tset clk_pl $pin\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {[llength $clk_pl]} {\n\t\t\t\t\tset num [regexp -all -inline -- {[0-9]+} $clk_pl]\n\t\t\t\t}\n\t\t\t\tset dts_file \"pl.dtsi\"\n\t\t\t\tset bus_node [add_or_get_bus_node $drv_handle $dts_file]\n\t\t\t\tset clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"$clk\"]\n\t\t\t\tif {[llength $clk_freq] == 0} {\n\t\t\t\t\tdtg_warning \"clock frequency for the $clk is NULL\"\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\tset clk_freq [expr int($clk_freq)]\n\t\t\t\tset iptype [get_property IP_NAME [get_cells -hier $drv_handle]]\n\t\t\t\tif {![string equal $clk_freq \"\"]} {\n\t\t\t\t\tif {[lsearch $bus_clk_list $clk_freq] < 0} {\n\t\t\t\t\t\tset bus_clk_list [lappend bus_clk_list $clk_freq]\n\t\t\t\t\t}\n\t\t\t\t\tset bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]\n\t\t\t\t\tset misc_clk_node [add_or_get_dt_node -n \"misc_clk_${bus_clk_cnt}\" -l \"misc_clk_${bus_clk_cnt}\" \\\n\t\t\t\t\t-d ${dts_file} -p ${bus_node}]\n\t\t\t\t\tset clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]\n\t\t\t\t\tset updat [lappend updat misc_clk_${bus_clk_cnt}]\n\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"#clock-cells\" 0 int\n\t\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-frequency\" $clk_freq int\n\t\t\t\t}\n\t\t\t}\n\t\t\tif {![string match -nocase $axi \"0\"]} {\n\t\t\t\tswitch $number {\n\t\t\t\t\t\"1\" {\n\t\t\t\t\t\tset peri \"$periph 0\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"2\" {\n\t\t\t\t\t\tset peri \"$periph 1\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"3\" {\n\t\t\t\t\t\tset peri \"$periph 2\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"4\" {\n\t\t\t\t\t\tset peri \"$periph 3\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"5\" {\n\t\t\t\t\t\tset peri \"$periph 4\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"6\" {\n\t\t\t\t\t\tset peri \"$periph 5\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t\t\"7\" {\n\t\t\t\t\t\tset peri \"$periph 6\"\n\t\t\t\t\t\tset clocks [lappend clocks $peri]\n\t\t\t\t\t\tset updat [lappend updat $peri]\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $proctype \"psu_cortexa53\"] || [string match -nocase $proctype \"psv_cortexa72\"]} {\n\t\t\tset clklist \"pl_clk0 pl_clk1 pl_clk2 pl_clk3\"\n\t\t} elseif {[string match -nocase $proctype \"ps7_cortexa9\"]} {\n\t\t\tset clklist \"FCLK_CLK0 FCLK_CLK1 FCLK_CLK2 FCLK_CLK3\"\n\t\t}\n\t\tforeach pin $pins {\n\t\t\tif {[lsearch $clklist $pin] >= 0} {\n\t\t\t\tset pl_clk $pin\n\t\t\t\tset is_pl_clk 1\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $proctype \"psv_cortexa72\"]} {\n\t\t\tswitch $pl_clk {\n\t\t\t\t\"pl_clk0\" {\n\t\t\t\t\t\tset pl_clk0 \"versal_clk 65\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk0]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk0]\n\t\t\t\t}\n\t\t\t\t\"pl_clk1\" {\n\t\t\t\t\t\tset pl_clk1 \"versal_clk 66\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk1]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk1]\n\t\t\t\t}\n\t\t\t\t\"pl_clk2\" {\n\t\t\t\t\t\tset pl_clk2 \"versal_clk 67\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk2]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk2]\n\t\t\t\t}\n\t\t\t\t\"pl_clk3\" {\n\t\t\t\t\t\tset pl_clk3 \"versal_clk 68\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk3]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk3]\n\t\t\t\t}\n\t\t\t\tdefault {\n\t\t\t\t\t\tdtg_warning \"not supported pl_clk:$pl_clk\"\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $proctype \"psu_cortexa53\"]} {\n\t\t\tswitch $pl_clk {\n\t\t\t\t\"pl_clk0\" {\n\t\t\t\t\t\tset pl_clk0 \"zynqmp_clk 71\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk0]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk0]\n\t\t\t\t}\n\t\t\t\t\"pl_clk1\" {\n\t\t\t\t\t\tset pl_clk1 \"zynqmp_clk 72\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk1]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk1]\n\t\t\t\t}\n\t\t\t\t\"pl_clk2\" {\n\t\t\t\t\t\tset pl_clk2 \"zynqmp_clk 73\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk2]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk2]\n\t\t\t\t}\n\t\t\t\t\"pl_clk3\" {\n\t\t\t\t\t\tset pl_clk3 \"zynqmp_clk 74\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk3]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk3]\n\t\t\t\t}\n\t\t\t\tdefault {\n\t\t\t\t\t\tdtg_warning \"not supported pl_clk:$pl_clk\"\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $proctype \"ps7_cortexa9\"]} {\n\t\t\tswitch $pl_clk {\n\t\t\t\t\"FCLK_CLK0\" {\n\t\t\t\t\t\tset pl_clk0 \"clkc 15\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk0]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk0]\n\t\t\t\t}\n\t\t\t\t\"FCLK_CLK1\" {\n\t\t\t\t\t\tset pl_clk1 \"clkc 16\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk1]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk1]\n\t\t\t\t}\n\t\t\t\t\"FCLK_CLK2\" {\n\t\t\t\t\t\tset pl_clk2 \"clkc 17\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk2]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk2]\n\t\t\t\t}\n\t\t\t\t\"FCLK_CLK3\" {\n\t\t\t\t\t\tset pl_clk3 \"clkc 18\"\n\t\t\t\t\t\tset clocks [lappend clocks $pl_clk3]\n\t\t\t\t\t\tset updat [lappend updat $pl_clk3]\n\t\t\t\t}\n\t\t\t\tdefault {\n\t\t\t\t\t\tdtg_warning \"not supported pl_clk:$pl_clk\"\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase $is_clk_wiz \"0\"]&& [string match -nocase $is_pl_clk \"0\"]} {\n\t\t\tset dts_file \"pl.dtsi\"\n\t\t\tset bus_node [add_or_get_bus_node $drv_handle $dts_file]\n\t\t\tset clk_freq [get_clock_frequency [get_cells -hier $drv_handle] \"$clk\"]\n\t\t\tif {[llength $clk_freq] == 0} {\n\t\t\t\tdtg_warning \"clock frequency for the $clk is NULL\"\n\t\t\t\tcontinue\n\t\t\t}\n\t\t\tset clk_freq [expr int($clk_freq)]\n\t\t\tset iptype [get_property IP_NAME [get_cells -hier $drv_handle]]\n\t\t\tif {![string equal $clk_freq \"\"]} {\n\t\t\t\tif {[lsearch $bus_clk_list $clk_freq] < 0} {\n\t\t\t\t\tset bus_clk_list [lappend bus_clk_list $clk_freq]\n\t\t\t\t}\n\t\t\t\tset bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]\n\t\t\t\tset misc_clk_node [add_or_get_dt_node -n \"misc_clk_${bus_clk_cnt}\" -l \"misc_clk_${bus_clk_cnt}\" \\\n\t\t\t\t-d ${dts_file} -p ${bus_node}]\n\t\t\t\tset clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]\n\t\t\t\tset updat [lappend updat misc_clk_${bus_clk_cnt}]\n\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"compatible\" \"fixed-clock\" stringlist\n\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"#clock-cells\" 0 int\n\t\t\t\thsi::utils::add_new_dts_param \"${misc_clk_node}\" \"clock-frequency\" $clk_freq int\n\t\t\t}\n\t\t}\n\t\tappend clocknames \" \" \"$clk\"\n\t\tset is_pl_clk 0\n\t\tset is_clk_wiz 0\n\t\tset axi 0\n\t}\n\t}\n\tset_drv_prop_if_empty $drv_handle \"zclock-names1\" $clocknames stringlist\n\tset ip [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tset refs [lindex $updat 0]\n\tfor {set clk_count 1} {$clk_count < [llength $updat]} {incr clk_count +1} {\n\t\tappend refs \">, <&[lindex $updat $clk_count]\"\n\t}\n\tset_drv_prop $drv_handle \"zclocks1\" \"$refs\" reference\n}\n" }, { "path": "multi_scaler/data/multi_scaler.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver multi_scaler\n\n OPTION supported_peripherals = (v_multi_scaler);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = multi_scaler;\n\nEND driver\n" }, { "path": "multi_scaler/data/multi_scaler.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,v-multi-scaler-v1.0\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset ip [get_cells -hier $drv_handle]\n\tset max_outs [get_property CONFIG.MAX_OUTS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,max-chan\" $max_outs int\n\tset max_cols [get_property CONFIG.MAX_COLS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,max-width\" $max_cols int\n\tset max_rows [get_property CONFIG.MAX_ROWS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,max-height\" $max_rows int\n\tset taps [get_property CONFIG.TAPS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,num-taps\" $taps int\n\tset aximm_addr_width [get_property CONFIG.AXIMM_ADDR_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,dma-addr-width\" $aximm_addr_width hexint\n\tset pixes_per_clock [get_property CONFIG.SAMPLES_PER_CLOCK [get_cells -hier $drv_handle]]\n\tset pixel $pixes_per_clock\n\tappend pixel_per_clock \"/bits/ 8 <$pixel>\"\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,pixels-per-clock\" $pixel_per_clock noformating\n\tset has_bgr8 [get_property CONFIG.HAS_BGR8 [get_cells -hier $drv_handle]]\n\tset vid_formats \"\"\n\tif {$has_bgr8 == 1} {\n\t\tappend vid_formats \" \" \"rgb888\"\n\t}\n\tset has_bgra8 [get_property CONFIG.HAS_BGRA8 [get_cells -hier $drv_handle]]\n\tif {$has_bgra8 == 1} {\n\t\tappend vid_formats \" \" \"argb8888\"\n\t}\n\tset has_bgrx8 [get_property CONFIG.HAS_BGRX8 [get_cells -hier $drv_handle]]\n\tif {$has_bgrx8 == 1} {\n\t\tappend vid_formats \" \" \"xrgb8888\"\n\t}\n\tset has_rgb8 [get_property CONFIG.HAS_RGB8 [get_cells -hier $drv_handle]]\n\tif {$has_rgb8 == 1} {\n\t\tappend vid_formats \" \" \"bgr888\"\n\t}\n\tset has_rgbx8 [get_property CONFIG.HAS_RGBX8 [get_cells -hier $drv_handle]]\n\tif {$has_rgbx8 == 1} {\n\t\tappend vid_formats \" \" \"xbgr8888\"\n\t}\n\tset has_rgba8 [get_property CONFIG.HAS_RGBA8 [get_cells -hier $drv_handle]]\n\tif {$has_rgba8 == 1} {\n\t\tappend vid_formats \" \" \"abgr8888\"\n\t}\n\tset has_rgbx10 [get_property CONFIG.HAS_RGBX10 [get_cells -hier $drv_handle]]\n\tif {$has_rgbx10 == 1} {\n\t\tappend vid_formats \" \" \"xbgr2101010\"\n\t}\n\tset has_uyuy8 [get_property CONFIG.HAS_UYVY8 [get_cells -hier $drv_handle]]\n\tif {$has_uyuy8 == 1} {\n\t\tappend vid_formats \" \" \"uyvy\"\n\t}\n\tset has_y8 [get_property CONFIG.HAS_Y8 [get_cells -hier $drv_handle]]\n\tif {$has_y8 == 1} {\n\t\tappend vid_formats \" \" \"y8\"\n\t}\n\tset has_y10 [get_property CONFIG.HAS_Y10 [get_cells -hier $drv_handle]]\n\tif {$has_y10 == 1} {\n\t\tappend vid_formats \" \" \"y10\"\n\t}\n\tset has_yuv8 [get_property CONFIG.HAS_YUV8 [get_cells -hier $drv_handle]]\n\tif {$has_yuv8 == 1} {\n\t\tappend vid_formats \" \" \"vuy888\"\n\t}\n\tset has_yuvx8 [get_property CONFIG.HAS_YUVX8 [get_cells -hier $drv_handle]]\n\tif {$has_yuvx8 == 1} {\n\t\tappend vid_formats \" \" \"xvuy8888\"\n\t}\n\tset has_yuva8 [get_property CONFIG.HAS_YUVA8 [get_cells -hier $drv_handle]]\n\tif {$has_yuva8 == 1} {\n\t\tappend vid_formats \" \" \"avuy8888\"\n\t}\n\tset has_yuvx10 [get_property CONFIG.HAS_YUVX10 [get_cells -hier $drv_handle]]\n\tif {$has_yuvx10 == 1} {\n\t\tappend vid_formats \" \" \"yuvx2101010\"\n\t}\n\tset has_yuyv8 [get_property CONFIG.HAS_YUYV8 [get_cells -hier $drv_handle]]\n\tif {$has_yuyv8 == 1} {\n\t\tappend vid_formats \" \" \"yuyv\"\n\t}\n\tset has_y_uv8_420 [get_property CONFIG.HAS_Y_UV8_420 [get_cells -hier $drv_handle]]\n\tif {$has_y_uv8_420 == 1} {\n\t\tappend vid_formats \" \" \"nv12\"\n\t}\n\tset has_y_uv8 [get_property CONFIG.HAS_Y_UV8 [get_cells -hier $drv_handle]]\n\tif {$has_y_uv8 == 1} {\n\t\tappend vid_formats \" \" \"nv16\"\n\t}\n\tset has_y_uv10 [get_property CONFIG.HAS_Y_UV10 [get_cells -hier $drv_handle]]\n\tif {$has_y_uv10 == 1} {\n\t\tappend vid_formats \" \" \"xv20\"\n\t}\n\tset has_y_uv10_420 [get_property CONFIG.HAS_Y_UV10_420 [get_cells -hier $drv_handle]]\n\tif {$has_y_uv10_420 == 1} {\n\t\tappend vid_formats \" \" \"xv15\"\n\t}\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,vid-formats\" $vid_formats stringlist\n\tgen_gpio_reset $drv_handle $node\n}\n\nproc gen_gpio_reset {drv_handle node} {\n\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] \"ap_rst_n\"]]\n\tforeach pin $pins {\n\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tif {[llength $sink_periph]} {\n\t\t\tset sink_ip [get_property IP_NAME $sink_periph]\n\t\t\tif {[string match -nocase $sink_ip \"xlslice\"]} {\n\t\t\t\tset gpio [get_property CONFIG.DIN_FROM $sink_periph]\n\t\t\t\tset pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph \"Din\"]]]\n\t\t\t\tforeach pin $pins {\n\t\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t\tif {[llength $periph]} {\n\t\t\t\t\t\tset ip [get_property IP_NAME $periph]\n\t\t\t\t\t\tset proc_type [get_sw_proc_prop IP_NAME]\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psv_cortexa72\"] } {\n\t\t\t\t\t\t\tif { $ip in { \"versal_cips\" \"ps_wizard\" }} {\n\t\t\t\t\t\t\t\t# As versal has only one bank0 for MIOs\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 26]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio0 $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n\t\t\t\t\t\t\tif {[string match -nocase $ip \"zynq_ultra_ps_e\"]} {\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 78]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $ip \"axi_gpio\"]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"$periph $gpio 1\" reference\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"$drv_handle:peripheral is NULL for the $pin $periph\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle:peripheral is NULL for the $pin $sink_periph\"\n\t\t}\n\t}\n}\n" }, { "path": "nandps/data/nandps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver nandps\n\n OPTION supported_peripherals = (ps7_nand psu_nand psv_nand);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = nandps;\n\nEND driver\n" }, { "path": "nandps/data/nandps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc ns_to_cycle {drv_handle prop_name nand_cycle_time} {\n return [expr [get_property CONFIG.$prop_name [get_cells -hier $drv_handle]]/${nand_cycle_time}]\n}\n\nproc generate {drv_handle} {\n # try to source the common tcl procs\n # assuming the order of return is based on repo priority\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n\n set hw_ver [get_hw_version]\n # Parameter name changed in 2014.4\n # TODO: check with 2014.3\n switch -exact $hw_ver {\n \"2014.2\" {\n set nand_par_prefix \"C_NAND_CYCLE_\"\n set nand_cycle_time 1\n } \"2014.4\" -\n default {\n set nand_par_prefix \"NAND-CYCLE-\"\n set nand_cycle_time [expr \"1000000000/[get_property CONFIG.C_NAND_CLK_FREQ_HZ [get_cells -hier $drv_handle]]\"]\n }\n }\n if {![regexp -nocase \"psu_nand*\" $drv_handle match]} {\n\tset_drv_prop $drv_handle \"arm,nand-cycle-t0\" [ns_to_cycle $drv_handle \"${nand_par_prefix}T0\" $nand_cycle_time]\n\tset_drv_prop $drv_handle \"arm,nand-cycle-t1\" [ns_to_cycle $drv_handle \"${nand_par_prefix}T1\" $nand_cycle_time]\n\tset_drv_prop $drv_handle \"arm,nand-cycle-t2\" [ns_to_cycle $drv_handle \"${nand_par_prefix}T2\" $nand_cycle_time]\n\tset_drv_prop $drv_handle \"arm,nand-cycle-t3\" [ns_to_cycle $drv_handle \"${nand_par_prefix}T3\" $nand_cycle_time]\n\tset_drv_prop $drv_handle \"arm,nand-cycle-t4\" [ns_to_cycle $drv_handle \"${nand_par_prefix}T4\" $nand_cycle_time]\n\tset_drv_prop $drv_handle \"arm,nand-cycle-t5\" [ns_to_cycle $drv_handle \"${nand_par_prefix}T5\" $nand_cycle_time]\n\tset_drv_prop $drv_handle \"arm,nand-cycle-t6\" [ns_to_cycle $drv_handle \"${nand_par_prefix}T6\" $nand_cycle_time]\n\tset bus_width [get_property CONFIG.C_NAND_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_property $drv_handle \"nand-bus-width\" int $bus_width\n }\n}\n" }, { "path": "norps/data/norps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver norps\n\n OPTION supported_peripherals = (ps7_sram);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = norps;\n DTGPARAM name = bank-width, type = int, default = 1;\n\nEND driver\n" }, { "path": "norps/data/norps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n\n # TODO: if addr25 is used, should we consider set the reg size to 64MB?\n # enable reg generation for ps ip\n gen_reg_property $drv_handle \"enable_ps_ip\"\n}\n" }, { "path": "nvme_aggr/data/nvme_aggr.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver nvme_aggr\n\n OPTION supported_peripherals = (nvme_subsystem);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = nvme_aggr;\n\nEND driver\n" }, { "path": "nvme_aggr/data/nvme_aggr.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset proc_type [get_sw_proc_prop IP_NAME]\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset nvme_ip [get_cells -hier $drv_handle]\n\tset ip_name [get_property IP_NAME $nvme_ip]\n\n\tif {[string match -nocase $proc_type \"psu_cortexa53\"] ||\n [string match -nocase $proc_type \"psv_cortexa72\"] || [string match -nocase $proc_type \"psx_cortexa78\"]} {\n\t\thsi::utils::add_new_dts_param $node \"#address-cells\" 2 int\n\t\thsi::utils::add_new_dts_param $node \"#size-cells\" 2 int\n\t\thsi::utils::add_new_dts_param \"${node}\" \"ranges\" \"\" boolean\n\t} elseif {[string match -nocase $proc_type \"ps7_cortexa9\"] ||\n [string match -nocase $proc_type \"microblaze\"]} {\n\t\thsi::utils::add_new_dts_param $node \"#address-cells\" 1 int\n\t\thsi::utils::add_new_dts_param $node \"#size-cells\" 1 int\n\t\thsi::utils::add_new_dts_param \"${node}\" \"ranges\" \"\" boolean\n\t}\n\n\tset intr_val [get_property CONFIG.interrupts $drv_handle]\n\tset intr_parent [get_property CONFIG.interrupt-parent $drv_handle]\n\tset intr_names [get_property CONFIG.interrupt-names $drv_handle]\n\n\tset ha_intr \"\"\n\tset tc_intr \"\"\n\tset mapper_intr \"\"\n\tforeach intr1 $intr_names {\n\t\tif {[string match -nocase $intr1 \"hc_interrupt\"]} {\n\t\t\tlappend ha_intr $intr1\n\t\t}\n\t\tif {[string match -nocase $intr1 \"nvme_tc_intr\"]} {\n\t\t\tlappend tc_intr $intr1\n\t\t}\n\t\tif {[string match -nocase $intr1 \"mapper_interrupt\"]} {\n\t\t\tlappend tc_intr $intr1\n\t\t}\n\t}\n\t\n set periph_list [get_cells -hier]\n set nvme_inst_name [get_cells -filter {IP_NAME =~ \"*nvme*\"}]\n\tforeach periph $periph_list {\n\t\tif {[string match -nocase \"${nvme_inst_name}_nvmeha_0\" $periph] } {\n set addr [get_property CONFIG.HA_S_AXI_LITE_OFFSET $nvme_ip]\n set addr [format %0x $addr]\n\t\t\tgen_ha_node $periph $addr $node $drv_handle $proc_type $nvme_ip $intr_parent $ha_intr\n\t\t}\n\t\tif {[string match -nocase \"${nvme_inst_name}_nvme_tc_0\" $periph] } {\n set addr [get_property CONFIG.TC_S_AXI_LITE_OFFSET $nvme_ip]\n set addr [format %0x $addr]\n\t\t\tgen_tc_node $periph $addr $node $drv_handle $proc_type $nvme_ip $intr_parent $tc_intr\n }\n\t\tif {[string match -nocase \"${nvme_inst_name}_nvme_mapper_0\" $periph] } {\n set addr [get_property CONFIG.MAPER_S_AXI_LITE_OFFSET $nvme_ip]\n set addr [format %0x $addr]\n\t\t\tgen_mapper_node $periph $addr $node $drv_handle $proc_type $nvme_ip $intr_parent $mapper_intr\n }\n\t}\n}\n\nproc gen_ha_node {periph addr parent_node drv_handle proc_type nvme_ip intr_parent intr} {\n\tset ha_node [add_or_get_dt_node -n \"nvme_ha\" -l nvme_ha_0 -u $addr -p $parent_node]\n\tset lite_size [get_property CONFIG.HA_S_AXI_LITE_SIZE $nvme_ip]\n\tset full_off [get_property CONFIG.HA_SW_S_AXI_OFFSET $nvme_ip]\n\tset full_size [get_property CONFIG.HA_SW_S_AXI_SIZE $nvme_ip]\n\tset ssd_off [get_property CONFIG.HA_S_AXI_SSD_OFFSET $nvme_ip]\n\tset ssd_size [get_property CONFIG.HA_S_AXI_SSD_SIZE $nvme_ip]\n\tif {[string match -nocase $proc_type \"ps7_cortexa9\"] ||\n [string match -nocase $proc_type \"microblaze\"]} {\n\t\tset ha_reg \"0x$addr $lite_size $full_off $full_size $ssd_off $ssd_size\"\n\t} else {\n\t\tset ha_reg \"0x0 0x$addr 0x0 $lite_size 0x0 $full_off 0x0 $full_size 0x0 $ssd_off 0x0 $ssd_size\"\n\t}\n\thsi::utils::add_new_dts_param \"${ha_node}\" \"reg\" $ha_reg int\n\thsi::utils::add_new_dts_param \"${ha_node}\" \"compatible\" \"xlnx,nvmeha-1.0\" string\n\n set intr_len [llength $intr]\n for {set i 0} {$i < $intr_len} {incr i} {\n\t\tlappend intr_num [get_intr_id $nvme_ip [lindex $intr $i]]\n\t}\n\tregsub -all \"\\{||\\t\" $intr_num {} intr_num\n\tregsub -all \"\\}||\\t\" $intr_num {} intr_num\n\thsi::utils::add_new_dts_param ${ha_node} \"interrupts\" $intr_num intlist\n\thsi::utils::add_new_dts_param \"${ha_node}\" \"interrupt-parent\" $intr_parent reference\n hsi::utils::add_new_dts_param \"${ha_node}\" \"interrupt-names\" $intr stringlist\n\n gen_property \"CONFIG.C_NUM_SQ\" \"xlnx,num-sq\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_0\" \"xlnx,num-sq-hw-0\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_1\" \"xlnx,num-sq-hw-1\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_2\" \"xlnx,num-sq-hw-2\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_3\" \"xlnx,num-sq-hw-3\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_4\" \"xlnx,num-sq-hw-4\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_5\" \"xlnx,num-sq-hw-5\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_6\" \"xlnx,num-sq-hw-6\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_7\" \"xlnx,num-sq-hw-7\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_8\" \"xlnx,num-sq-hw-8\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_9\" \"xlnx,num-sq-hw-9\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_10\" \"xlnx,num-sq-hw-10\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_11\" \"xlnx,num-sq-hw-11\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_12\" \"xlnx,num-sq-hw-12\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_13\" \"xlnx,num-sq-hw-13\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_14\" \"xlnx,num-sq-hw-14\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_15\" \"xlnx,num-sq-hw-15\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_16\" \"xlnx,num-sq-hw-16\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_17\" \"xlnx,num-sq-hw-17\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_18\" \"xlnx,num-sq-hw-18\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_19\" \"xlnx,num-sq-hw-19\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_20\" \"xlnx,num-sq-hw-20\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_21\" \"xlnx,num-sq-hw-21\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_22\" \"xlnx,num-sq-hw-22\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_23\" \"xlnx,num-sq-hw-23\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_24\" \"xlnx,num-sq-hw-24\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_25\" \"xlnx,num-sq-hw-25\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_26\" \"xlnx,num-sq-hw-26\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_27\" \"xlnx,num-sq-hw-27\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_28\" \"xlnx,num-sq-hw-28\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_29\" \"xlnx,num-sq-hw-29\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_30\" \"xlnx,num-sq-hw-30\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_HW_31\" \"xlnx,num-sq-hw-31\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_0\" \"xlnx,num-sq-sw-0\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_1\" \"xlnx,num-sq-sw-1\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_2\" \"xlnx,num-sq-sw-2\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_3\" \"xlnx,num-sq-sw-3\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_4\" \"xlnx,num-sq-sw-4\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_5\" \"xlnx,num-sq-sw-5\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_6\" \"xlnx,num-sq-sw-6\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_7\" \"xlnx,num-sq-sw-7\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_8\" \"xlnx,num-sq-sw-8\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_9\" \"xlnx,num-sq-sw-9\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_10\" \"xlnx,num-sq-sw-10\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_11\" \"xlnx,num-sq-sw-11\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_12\" \"xlnx,num-sq-sw-12\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_13\" \"xlnx,num-sq-sw-13\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_14\" \"xlnx,num-sq-sw-14\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_15\" \"xlnx,num-sq-sw-15\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_16\" \"xlnx,num-sq-sw-16\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_17\" \"xlnx,num-sq-sw-17\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_18\" \"xlnx,num-sq-sw-18\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_19\" \"xlnx,num-sq-sw-19\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_20\" \"xlnx,num-sq-sw-20\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_21\" \"xlnx,num-sq-sw-21\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_22\" \"xlnx,num-sq-sw-22\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_23\" \"xlnx,num-sq-sw-23\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_24\" \"xlnx,num-sq-sw-24\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_25\" \"xlnx,num-sq-sw-25\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_26\" \"xlnx,num-sq-sw-26\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_27\" \"xlnx,num-sq-sw-27\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_28\" \"xlnx,num-sq-sw-28\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_29\" \"xlnx,num-sq-sw-29\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_30\" \"xlnx,num-sq-sw-30\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SQ_SW_31\" \"xlnx,num-sq-sw-31\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_NUM_SSD\" \"xlnx,num-ssd\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_SQ_DEPTH_HW\" \"xlnx,sq-depth-hw\" $nvme_ip $ha_node\n gen_property \"CONFIG.C_SQ_DEPTH_SW\" \"xlnx,sq-depth-sw\" $nvme_ip $ha_node\n}\n\nproc gen_tc_node {periph addr parent_node drv_handle proc_type nvme_ip intr_parent intr} {\n\tset tc_node [add_or_get_dt_node -n \"nvme_tc\" -l nvme_tc_0 -u $addr -p $parent_node]\n\tset lite_size [get_property CONFIG.TC_S_AXI_LITE_SIZE $nvme_ip]\n\tset full_off [get_property CONFIG.TC_SW_S_AXI_OFFSET $nvme_ip]\n\tset full_size [get_property CONFIG.TC_SW_S_AXI_SIZE $nvme_ip]\n\tif {[string match -nocase $proc_type \"ps7_cortexa9\"] ||\n [string match -nocase $proc_type \"microblaze\"]} {\n\t\tset tc_reg \"0x$addr $lite_size $full_off $full_size\"\n\t} else {\n\t\tset tc_reg \"0x0 0x$addr 0x0 $lite_size 0x0 $full_off 0x0 $full_size\"\n\t}\n\thsi::utils::add_new_dts_param \"${tc_node}\" \"reg\" $tc_reg int\n\thsi::utils::add_new_dts_param \"${tc_node}\" \"compatible\" \"xlnx,nvme-tc-1.0\" string\n\n set intr_len [llength $intr]\n\tfor {set i 0} {$i < $intr_len} {incr i} {\n\t\tlappend intr_num [get_intr_id $nvme_ip [lindex $intr $i]]\n\t}\n\tregsub -all \"\\{||\\t\" $intr_num {} intr_num\n\tregsub -all \"\\}||\\t\" $intr_num {} intr_num\n\thsi::utils::add_new_dts_param ${tc_node} \"interrupts\" $intr_num intlist\n\thsi::utils::add_new_dts_param \"${tc_node}\" \"interrupt-parent\" $intr_parent reference\n\thsi::utils::add_new_dts_param \"${tc_node}\" \"interrupt-names\" $intr stringlist\n \n set debug_en [get_property CONFIG.DEBUG_EN $nvme_ip]\n if {[string match -nocase $debug_en \"true\"]} {\n hsi::utils::add_new_dts_param \"${tc_node}\" \"xlnx,debug-en\" \"0x1\" int\n } else {\n hsi::utils::add_new_dts_param \"${tc_node}\" \"xlnx,debug-en\" \"0x0\" int\n }\n\n gen_property \"CONFIG.C_ARB_BURST\" \"xlnx,arb-burst\" $nvme_ip $tc_node\n gen_property \"CONFIG.C_CAP_MAX_HOST_Q_DEPTH\" \"xlnx,cap-max-host-q-depth\" $nvme_ip $tc_node\n gen_property \"CONFIG.C_CAP_MPSMAX\" \"xlnx,cap-mpsmax\" $nvme_ip $tc_node\n gen_property \"CONFIG.C_CAP_MPSMIN\" \"xlnx,cap-mpsmin\" $nvme_ip $tc_node\n gen_property \"CONFIG.C_CAP_TIMEOUT\" \"xlnx,cap-timeout\" $nvme_ip $tc_node\n gen_property \"CONFIG.C_LBA_DATA_SIZE\" \"xlnx,lba-data-size\" $nvme_ip $tc_node\n gen_property \"CONFIG.C_MAX_DMA_SIZE\" \"xlnx,max-dma-size\" $nvme_ip $tc_node\n gen_property \"CONFIG.C_MDTS\" \"xlnx,mdts\" $nvme_ip $tc_node\n gen_property \"CONFIG.C_NUM_CMD_INDX\" \"xlnx,num-cmd-indx\" $nvme_ip $tc_node\n gen_property \"CONFIG.C_NUM_FUNC\" \"xlnx,num-func\" $nvme_ip $tc_node\n gen_property \"CONFIG.C_NUM_HSQ\" \"xlnx,num-hsq\" $nvme_ip $tc_node\n gen_property \"CONFIG.C_NUM_SGLS_PER_INDX\" \"xlnx,num-sgls-per-indx\" $nvme_ip $tc_node\n gen_property \"CONFIG.C_PERF_MON_EN\" \"xlnx,perf-mon-en\" $nvme_ip $tc_node\n gen_property \"CONFIG.C_S_AXI_ID_WIDTH\" \"xlnx,s-axi-id-width\" $nvme_ip $tc_node\n gen_property \"CONFIG.C_SGL_SUPPORT\" \"xlnx,sgl-support\" $nvme_ip $tc_node\n\n} \n\nproc gen_mapper_node {periph addr parent_node drv_handle proc_type nvme_ip intr_parent intr} {\n\tset mapper_node [add_or_get_dt_node -n \"nvme_mapper\" -l nvme_mapper_0 -u $addr -p $parent_node]\n\tset lite_size [get_property CONFIG.MAPPER_S_AXI_LITE_SIZE $nvme_ip]\n\tset full_off [get_property CONFIG.MAPPER_SW_S_AXI_OFFSET $nvme_ip]\n\tset full_size [get_property CONFIG.MAPPER_SW_S_AXI_SIZE $nvme_ip]\n\tif {[string match -nocase $proc_type \"ps7_cortexa9\"] ||\n [string match -nocase $proc_type \"microblaze\"]} {\n\t\tset mapper_reg \"0x$addr $lite_size $full_off $full_size\"\n\t} else {\n\t\tset mapper_reg \"0x0 0x$addr 0x0 $lite_size 0x0 $full_off 0x0 $full_size\"\n\t}\n\thsi::utils::add_new_dts_param \"${mapper_node}\" \"reg\" $mapper_reg int\n\thsi::utils::add_new_dts_param \"${mapper_node}\" \"compatible\" \"xlnx,nvme-mapper-1.0\" string\n\n\tset en_p2p [get_property CONFIG.EN_P2P_BUFFERS $nvme_ip]\n\tif {[string match -nocase $en_p2p \"true\"]} {\n\t hsi::utils::add_new_dts_param \"${mapper_node}\" \"xlnx,en-p2p-buffer\" \"\" boolean\n }\n gen_property \"CONFIG.MAX_PRP_PER_CMD\" \"xlnx,max-prp-per-cmd\" $periph $mapper_node\n gen_property \"CONFIG.NUM_UID_SUPPORT\" \"xlnx,num-uid-support\" $periph $mapper_node\n gen_property \"CONFIG.P2P_PF_NUM\" \"xlnx,p2p-pf-num\" $periph $mapper_node\n}\n\nproc gen_property {property pro_dt_name nvme_ip node} {\n set num_sgls [get_property $property $nvme_ip]\n set num_sgls 0x[format %0x $num_sgls]\n hsi::utils::add_new_dts_param \"$node\" $pro_dt_name $num_sgls int\n}\n" }, { "path": "ocmcps/data/ocmcps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver ocmcps\n\n OPTION supported_peripherals = (ps7_ocmc psu_ocm psv_ocm psx_ocm);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = ocmcps;\n\nEND driver\n" }, { "path": "ocmcps/data/ocmcps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n" }, { "path": "ospips/data/ospips.mdd", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver ospips\n\n OPTION supported_peripherals = (psu_ospi psv_pmc_ospi psx_pmc_ospi);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = ospips;\n DTGPARAM name = dtg.alias , default = spi;\n\nEND driver\n" }, { "path": "ospips/data/ospips.tcl", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\tif {[file exists $common_tcl_file]} {\n\t\tsource $common_tcl_file\n\t\tbreak\n\t\t}\n\t}\n\n\tset ospi_handle [get_cells -hier $drv_handle]\n\tset ospi_mode [hsi::utils::get_ip_param_value $ospi_handle \"C_OSPI_MODE\"]\n\tset is_stacked 0\n\tset is_dual 0\n\tif {$ospi_mode == 1} {\n\t\tset is_stacked 1\n\t}\n\n\tset_property CONFIG.is-dual $is_dual $drv_handle\n\tset_property CONFIG.is-stacked $is_stacked $drv_handle\n\n}\n" }, { "path": "pl310ps/data/pl310ps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver pl310ps\n\n OPTION supported_peripherals = (ps7_pl310);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = pl310ps;\n\nEND driver\n" }, { "path": "pl310ps/data/pl310ps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n" }, { "path": "pmups/data/pmups.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver pmups\n\n OPTION supported_peripherals = (ps7_pmu);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = pmups;\n\nEND driver\n" }, { "path": "pmups/data/pmups.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n" }, { "path": "pr_decoupler/data/pr_decoupler.mdd", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver pr_decoupler\n OPTION supported_peripherals = (pr_decoupler dfx_decoupler);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = pr_decoupler;\nEND driver\n" }, { "path": "pr_decoupler/data/pr_decoupler.tcl", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n set compatible [get_comp_str $drv_handle]\n set compatible [append compatible \" \" \"xlnx,pr-decoupler\"]\n set_drv_prop $drv_handle compatible \"$compatible\" stringlist\n}\n" }, { "path": "ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.mdd", "content": "#\n# (C) Copyright 2021-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver ptp_1588_timer_syncer\n\n OPTION supported_peripherals = (ptp_1588_timer_syncer);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = ptp_1588_timer_syncer;\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.tcl", "content": "#\n# (C) Copyright 2021-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset ip_ver [get_comp_ver $drv_handle]\n\tif {[string match -nocase $ip_ver \"2.0\"] || [string match -nocase $ip_ver \"3.0\"]} {\n\t\tset compatible [append compatible \" \" \"xlnx,timer-syncer-1588-3.0\"]\n\t} elseif {[string match -nocase $ip_ver \"1.0\"]} {\n\t\tset compatible [append compatible \" \" \"xlnx,timer-syncer-1588-1.0\"]\n\t}\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n}\n" }, { "path": "qspips/data/qspips.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver qspips\n\n OPTION supported_peripherals = (ps7_qspi psu_qspi psv_pmc_qspi psx_pmc_qspi);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = qspips;\n DTGPARAM name = is-dual, type = int;\n DTGPARAM name = dtg.alias , default = spi;\n\nEND driver\n" }, { "path": "qspips/data/qspips.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\tif {[file exists $common_tcl_file]} {\n\t\tsource $common_tcl_file\n\t\tbreak\n\t\t}\n\t}\n\n\tset slave [get_cells -hier $drv_handle]\n\tset qspi_mode [hsi::utils::get_ip_param_value $slave \"C_QSPI_MODE\"]\n\t#for versal setting spi-max-frequency to 40MHZ if fbclk disabled in design\n\tset pspmc [get_cells -hier -filter {IP_NAME == \"pspmc\"}]\n\tif {[llength $pspmc]} {\n\t\tset fbclk [get_property CONFIG.PMC_QSPI_FBCLK [get_cells -hier $pspmc]]\n\t\tif {[llength $fbclk]} {\n\t\t\tif {[regexp \"ENABLE 0\" $fbclk matched]} {\n\t\t\t\tset_spi_max_frequency $drv_handle\n\t\t\t}\n\t\t}\n\t}\n\t#for versal-net setting spi-max-frequency to 40MHZ if fbclk disabled in design\n\tset psxwizard [get_cells -hier -filter {IP_NAME == \"psx_wizard\"}]\n\tif {[llength $psxwizard]} {\n\t\tset psx_pmcx_config [get_property CONFIG.PSX_PMCX_CONFIG [get_cells -hier $psxwizard]]\n\t\tif {[llength $psx_pmcx_config]} {\n\t\t\tset qspi_fbclk \"\"\n\t\t\tif {[dict exists $psx_pmcx_config \"PMCX_QSPI_FBCLK\"]} {\n\t\t\t\tset qspi_fbclk [dict get $psx_pmcx_config \"PMCX_QSPI_FBCLK\"]\n\t\t\t\tset qspi_fbclk_enabled \"\"\n\t\t\t\tif {[dict exists $qspi_fbclk \"ENABLE\"]} {\n\t\t\t\t\tset qspi_fbclk_enabled [dict get $qspi_fbclk \"ENABLE\"]\n\t\t\t\t\tif {$qspi_fbclk_enabled == 0} {\n\t\t\t\t\t\tset_spi_max_frequency $drv_handle\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tset is_stacked 0\n\tif { $qspi_mode == 2} {\n\t\tset is_dual 1\n\t} elseif { $qspi_mode == 1} {\n\t\tset is_dual 0\n\t\tset is_stacked 1\n\t} elseif { $qspi_mode == 0} {\n\t\tset is_dual 0\n\t}\n\tset_property CONFIG.is-dual $is_dual $drv_handle\n\n\t# Set num-cs value to 2 if qspi is dual/stacked else 1\n\tset numcs 1\n\tif { $is_dual == 1 || $is_stacked == 1 } {\n\t\tset numcs 2\n\t}\n\thsi::utils::add_new_property $drv_handle \"num-cs\" int $numcs\n\n\tif {$is_stacked} {\n\t\tset_property CONFIG.is-stacked $is_stacked $drv_handle\n\t}\n\tset bus_width [get_property CONFIG.C_QSPI_BUS_WIDTH [get_cells -hier $drv_handle]]\n\n\tswitch $bus_width {\n\t\t\"3\" {\n\t\t\thsi::utils::add_new_property $drv_handle \"spi-tx-bus-width\" int 8\n\t\t\thsi::utils::add_new_property $drv_handle \"spi-rx-bus-width\" int 8\n\t\t}\n\t\t\"2\" {\n\t\t\thsi::utils::add_new_property $drv_handle \"spi-tx-bus-width\" int 4\n\t\t\thsi::utils::add_new_property $drv_handle \"spi-rx-bus-width\" int 4\n\t\t}\n\t\t\"1\" {\n\t\t\thsi::utils::add_new_property $drv_handle \"spi-tx-bus-width\" int 2\n\t\t\thsi::utils::add_new_property $drv_handle \"spi-rx-bus-width\" int 2\n\t\t}\n\t\t\"0\" {\n\t\t\thsi::utils::add_new_property $drv_handle \"spi-tx-bus-width\" int 1\n\t\t\thsi::utils::add_new_property $drv_handle \"spi-rx-bus-width\" int 1\n\t\t}\n\t\tdefault {\n\t\t\tdtg_warning \"Unsupported bus_width:$bus_width\"\n\t\t}\n\t}\n # these are board level information\n # set primary_flash [hsi::utils::add_new_child_node $drv_handle \"primary_flash\"]\n # hsi::utils::add_new_property $primary_flash \"dts.device_type\" string \"ps7-qspi\"\n # hsi::utils::add_new_property $primary_flash reg hexint 0\n # hsi::utils::add_new_property $primary_flash spi-max-frequency int 50000000\n}\n\n#when fbclk disabled in the design\n#this function will set the spi-max-freq to 40MHZ\nproc set_spi_max_frequency {drv_handle} {\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\thsi::utils::add_new_dts_param \"${node}\" \"/* hw design is missing feedback clock that's why spi-max-frequency is 40MHz */\" \"\" comment\n\thsi::utils::add_new_property $drv_handle spi-max-frequency int 40000000\n}\n" }, { "path": "ramps/data/ramps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver ramps\n\n OPTION supported_peripherals = (ps7_ram);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = ramps;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,ps7-ocm\" ;\n DTGPARAM name = reg, type = hexintlist , default = \"0xfffc0000 0x40000\";\nEND driver\n" }, { "path": "ramps/data/ramps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n set ip [get_cells -hier $drv_handle]\n if { [string match -nocase $ip \"ps7_ram_1\"] } {\n set_property NAME none $drv_handle\n }\n}\n" }, { "path": "rfdc/data/rfdc.mdd", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver rfdc\n\n OPTION supported_peripherals = (usp_rf_data_converter);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = rfdc;\n\nEND driver\n" }, { "path": "rfdc/data/rfdc.tcl", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\t# try to source the common tcl procs\n\t# assuming the order of return is based on repo priority\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset instances [llength [::hsi::utils::get_common_driver_ips $drv_handle]]\n\thsi::utils::add_new_property $drv_handle \"num-insts\" hexlist $instances\n\tadd_param_list_property $drv_handle \"DEVICE_ID\" \"C_BASEADDR\" \"C_High_Speed_ADC\" \"C_Sysref_Master\" \"C_Sysref_Master\" \"C_Sysref_Source\" \"C_Sysref_Source\" \"C_IP_Type\" \"C_Silicon_Revision\" \\\n\t\"C_DAC0_Enable\" \"C_DAC0_PLL_Enable\" \"C_DAC0_Sampling_Rate\" \"C_DAC0_Refclk_Freq\" \"C_DAC0_Fabric_Freq\" \"C_DAC0_FBDIV\" \"C_DAC0_OutDiv\" \"C_DAC0_Refclk_Div\" \"C_DAC0_Band\" \"C_DAC0_Fs_Max\" \"C_DAC0_Slices\" \"DAC0_Link_Coupling\" \\\n\t\"C_DAC_Slice00_Enable\" \"C_DAC_Invsinc_Ctrl00\" \"C_DAC_Mixer_Mode00\" \"C_DAC_Decoder_Mode00\" \\\n\t\"C_DAC_Slice01_Enable\" \"C_DAC_Invsinc_Ctrl01\" \"C_DAC_Mixer_Mode01\" \"C_DAC_Decoder_Mode01\" \\\n\t\"C_DAC_Slice02_Enable\" \"C_DAC_Invsinc_Ctrl02\" \"C_DAC_Mixer_Mode02\" \"C_DAC_Decoder_Mode02\" \\\n\t\"C_DAC_Slice03_Enable\" \"C_DAC_Invsinc_Ctrl03\" \"C_DAC_Mixer_Mode03\" \"C_DAC_Decoder_Mode03\" \\\n\t\"C_DAC_Data_Type00\" \"C_DAC_Data_Width00\" \"C_DAC_Interpolation_Mode00\" \"C_DAC_Fifo00_Enable\" \"C_DAC_Adder00_Enable\" \"C_DAC_Mixer_Type00\" \"C_DAC_NCO_Freq00\" \\\n\t\"C_DAC_Data_Type01\" \"C_DAC_Data_Width01\" \"C_DAC_Interpolation_Mode01\" \"C_DAC_Fifo01_Enable\" \"C_DAC_Adder01_Enable\" \"C_DAC_Mixer_Type01\" \"C_DAC_NCO_Freq01\" \\\n\t\"C_DAC_Data_Type02\" \"C_DAC_Data_Width02\" \"C_DAC_Interpolation_Mode02\" \"C_DAC_Fifo02_Enable\" \"C_DAC_Adder02_Enable\" \"C_DAC_Mixer_Type02\" \"C_DAC_NCO_Freq02\" \\\n\t\"C_DAC_Data_Type03\" \"C_DAC_Data_Width03\" \"C_DAC_Interpolation_Mode03\" \"C_DAC_Fifo03_Enable\" \"C_DAC_Adder03_Enable\" \"C_DAC_Mixer_Type03\" \"C_DAC_NCO_Freq03\" \\\n\t\"C_DAC1_Enable\" \"C_DAC1_PLL_Enable\" \"C_DAC1_Sampling_Rate\" \"C_DAC1_Refclk_Freq\" \"C_DAC1_Fabric_Freq\" \"C_DAC1_FBDIV\" \"C_DAC1_OutDiv\" \"C_DAC1_Refclk_Div\" \"C_DAC1_Band\" \"C_DAC1_Fs_Max\" \"C_DAC1_Slices\" \"DAC1_Link_Coupling\" \\\n\t\"C_DAC_Slice10_Enable\" \"C_DAC_Invsinc_Ctrl10\" \"C_DAC_Mixer_Mode10\" \"C_DAC_Decoder_Mode10\" \\\n\t\"C_DAC_Slice11_Enable\" \"C_DAC_Invsinc_Ctrl11\" \"C_DAC_Mixer_Mode11\" \"C_DAC_Decoder_Mode11\" \\\n\t\"C_DAC_Slice12_Enable\" \"C_DAC_Invsinc_Ctrl12\" \"C_DAC_Mixer_Mode12\" \"C_DAC_Decoder_Mode12\" \\\n\t\"C_DAC_Slice13_Enable\" \"C_DAC_Invsinc_Ctrl13\" \"C_DAC_Mixer_Mode13\" \"C_DAC_Decoder_Mode13\" \\\n\t\"C_DAC_Data_Type10\" \"C_DAC_Data_Width10\" \"C_DAC_Interpolation_Mode10\" \"C_DAC_Fifo10_Enable\" \"C_DAC_Adder10_Enable\" \"C_DAC_Mixer_Type10\" \"C_DAC_NCO_Freq10\" \\\n\t\"C_DAC_Data_Type11\" \"C_DAC_Data_Width11\" \"C_DAC_Interpolation_Mode11\" \"C_DAC_Fifo11_Enable\" \"C_DAC_Adder11_Enable\" \"C_DAC_Mixer_Type11\" \"C_DAC_NCO_Freq11\" \\\n\t\"C_DAC_Data_Type12\" \"C_DAC_Data_Width12\" \"C_DAC_Interpolation_Mode12\" \"C_DAC_Fifo12_Enable\" \"C_DAC_Adder12_Enable\" \"C_DAC_Mixer_Type12\" \"C_DAC_NCO_Freq12\" \\\n\t\"C_DAC_Data_Type13\" \"C_DAC_Data_Width13\" \"C_DAC_Interpolation_Mode13\" \"C_DAC_Fifo13_Enable\" \"C_DAC_Adder13_Enable\" \"C_DAC_Mixer_Type13\" \"C_DAC_NCO_Freq13\" \\\n\t\"C_DAC2_Enable\" \"C_DAC2_PLL_Enable\" \"C_DAC2_Sampling_Rate\" \"C_DAC2_Refclk_Freq\" \"C_DAC2_Fabric_Freq\" \"C_DAC2_FBDIV\" \"C_DAC2_OutDiv\" \"C_DAC2_Refclk_Div\" \"C_DAC2_Band\" \"C_DAC2_Fs_Max\" \"C_DAC2_Slices\" \"DAC2_Link_Coupling\" \\\n\t\"C_DAC_Slice20_Enable\" \"C_DAC_Invsinc_Ctrl20\" \"C_DAC_Mixer_Mode20\" \"C_DAC_Decoder_Mode20\" \\\n\t\"C_DAC_Slice21_Enable\" \"C_DAC_Invsinc_Ctrl21\" \"C_DAC_Mixer_Mode21\" \"C_DAC_Decoder_Mode21\" \\\n\t\"C_DAC_Slice22_Enable\" \"C_DAC_Invsinc_Ctrl22\" \"C_DAC_Mixer_Mode22\" \"C_DAC_Decoder_Mode22\" \\\n\t\"C_DAC_Slice23_Enable\" \"C_DAC_Invsinc_Ctrl23\" \"C_DAC_Mixer_Mode23\" \"C_DAC_Decoder_Mode23\" \\\n\t\"C_DAC_Data_Type20\" \"C_DAC_Data_Width20\" \"C_DAC_Interpolation_Mode20\" \"C_DAC_Fifo20_Enable\" \"C_DAC_Adder20_Enable\" \"C_DAC_Mixer_Type20\" \"C_DAC_NCO_Freq20\" \\\n\t\"C_DAC_Data_Type21\" \"C_DAC_Data_Width21\" \"C_DAC_Interpolation_Mode21\" \"C_DAC_Fifo21_Enable\" \"C_DAC_Adder21_Enable\" \"C_DAC_Mixer_Type21\" \"C_DAC_NCO_Freq21\" \\\n\t\"C_DAC_Data_Type22\" \"C_DAC_Data_Width22\" \"C_DAC_Interpolation_Mode22\" \"C_DAC_Fifo22_Enable\" \"C_DAC_Adder22_Enable\" \"C_DAC_Mixer_Type22\" \"C_DAC_NCO_Freq22\" \\\n\t\"C_DAC_Data_Type23\" \"C_DAC_Data_Width23\" \"C_DAC_Interpolation_Mode23\" \"C_DAC_Fifo23_Enable\" \"C_DAC_Adder23_Enable\" \"C_DAC_Mixer_Type23\" \"C_DAC_NCO_Freq23\" \\\n\t\"C_DAC3_Enable\" \"C_DAC3_PLL_Enable\" \"C_DAC3_Sampling_Rate\" \"C_DAC3_Refclk_Freq\" \"C_DAC3_Fabric_Freq\" \"C_DAC3_FBDIV\" \"C_DAC3_OutDiv\" \"C_DAC3_Refclk_Div\" \"C_DAC3_Band\" \"C_DAC3_Fs_Max\" \"C_DAC3_Slices\" \"DAC3_Link_Coupling\" \\\n\t\"C_DAC_Slice30_Enable\" \"C_DAC_Invsinc_Ctrl30\" \"C_DAC_Mixer_Mode30\" \"C_DAC_Decoder_Mode30\" \\\n\t\"C_DAC_Slice31_Enable\" \"C_DAC_Invsinc_Ctrl31\" \"C_DAC_Mixer_Mode31\" \"C_DAC_Decoder_Mode31\" \\\n\t\"C_DAC_Slice32_Enable\" \"C_DAC_Invsinc_Ctrl32\" \"C_DAC_Mixer_Mode32\" \"C_DAC_Decoder_Mode32\" \\\n\t\"C_DAC_Slice33_Enable\" \"C_DAC_Invsinc_Ctrl33\" \"C_DAC_Mixer_Mode33\" \"C_DAC_Decoder_Mode33\" \\\n\t\"C_DAC_Data_Type30\" \"C_DAC_Data_Width30\" \"C_DAC_Interpolation_Mode30\" \"C_DAC_Fifo30_Enable\" \"C_DAC_Adder30_Enable\" \"C_DAC_Mixer_Type30\" \"C_DAC_NCO_Freq30\" \\\n\t\"C_DAC_Data_Type31\" \"C_DAC_Data_Width31\" \"C_DAC_Interpolation_Mode31\" \"C_DAC_Fifo31_Enable\" \"C_DAC_Adder31_Enable\" \"C_DAC_Mixer_Type31\" \"C_DAC_NCO_Freq31\" \\\n\t\"C_DAC_Data_Type32\" \"C_DAC_Data_Width32\" \"C_DAC_Interpolation_Mode32\" \"C_DAC_Fifo32_Enable\" \"C_DAC_Adder32_Enable\" \"C_DAC_Mixer_Type32\" \"C_DAC_NCO_Freq32\" \\\n\t\"C_DAC_Data_Type33\" \"C_DAC_Data_Width33\" \"C_DAC_Interpolation_Mode33\" \"C_DAC_Fifo33_Enable\" \"C_DAC_Adder33_Enable\" \"C_DAC_Mixer_Type33\" \"C_DAC_NCO_Freq33\" \\\n\t\"C_ADC0_Enable\" \"C_ADC0_PLL_Enable\" \"C_ADC0_Sampling_Rate\" \"C_ADC0_Refclk_Freq\" \"C_ADC0_Fabric_Freq\" \"C_ADC0_FBDIV\" \"C_ADC0_OutDiv\" \"C_ADC0_Refclk_Div\" \"C_ADC0_Band\" \"C_ADC0_Fs_Max\" \"C_ADC0_Slices\" \\\n\t\"C_ADC_Slice00_Enable\" \"C_ADC_Mixer_Mode00\" \\\n\t\"C_ADC_Slice01_Enable\" \"C_ADC_Mixer_Mode01\" \\\n\t\"C_ADC_Slice02_Enable\" \"C_ADC_Mixer_Mode02\" \\\n\t\"C_ADC_Slice03_Enable\" \"C_ADC_Mixer_Mode03\" \\\n\t\"C_ADC_Data_Type00\" \"C_ADC_Data_Width00\" \"C_ADC_Decimation_Mode00\" \"C_ADC_Fifo00_Enable\" \"C_ADC_Mixer_Type00\" \"C_ADC_NCO_Freq00\" \\\n\t\"C_ADC_Data_Type01\" \"C_ADC_Data_Width01\" \"C_ADC_Decimation_Mode01\" \"C_ADC_Fifo01_Enable\" \"C_ADC_Mixer_Type01\" \"C_ADC_NCO_Freq01\" \\\n\t\"C_ADC_Data_Type02\" \"C_ADC_Data_Width02\" \"C_ADC_Decimation_Mode02\" \"C_ADC_Fifo02_Enable\" \"C_ADC_Mixer_Type02\" \"C_ADC_NCO_Freq02\" \\\n\t\"C_ADC_Data_Type03\" \"C_ADC_Data_Width03\" \"C_ADC_Decimation_Mode03\" \"C_ADC_Fifo03_Enable\" \"C_ADC_Mixer_Type03\" \"C_ADC_NCO_Freq03\" \\\n\t\"C_ADC1_Enable\" \"C_ADC1_PLL_Enable\" \"C_ADC1_Sampling_Rate\" \"C_ADC1_Refclk_Freq\" \"C_ADC1_Fabric_Freq\" \"C_ADC1_FBDIV\" \"C_ADC1_OutDiv\" \"C_ADC1_Refclk_Div\" \"C_ADC1_Band\" \"C_ADC1_Fs_Max\" \"C_ADC1_Slices\" \\\n\t\"C_ADC_Slice10_Enable\" \"C_ADC_Mixer_Mode10\" \\\n\t\"C_ADC_Slice11_Enable\" \"C_ADC_Mixer_Mode11\" \\\n\t\"C_ADC_Slice12_Enable\" \"C_ADC_Mixer_Mode12\" \\\n\t\"C_ADC_Slice13_Enable\" \"C_ADC_Mixer_Mode13\" \\\n\t\"C_ADC_Data_Type10\" \"C_ADC_Data_Width10\" \"C_ADC_Decimation_Mode10\" \"C_ADC_Fifo10_Enable\" \"C_ADC_Mixer_Type10\" \"C_ADC_NCO_Freq10\" \\\n\t\"C_ADC_Data_Type11\" \"C_ADC_Data_Width11\" \"C_ADC_Decimation_Mode11\" \"C_ADC_Fifo11_Enable\" \"C_ADC_Mixer_Type11\" \"C_ADC_NCO_Freq11\" \\\n\t\"C_ADC_Data_Type12\" \"C_ADC_Data_Width12\" \"C_ADC_Decimation_Mode12\" \"C_ADC_Fifo12_Enable\" \"C_ADC_Mixer_Type12\" \"C_ADC_NCO_Freq12\" \\\n\t\"C_ADC_Data_Type13\" \"C_ADC_Data_Width13\" \"C_ADC_Decimation_Mode13\" \"C_ADC_Fifo13_Enable\" \"C_ADC_Mixer_Type13\" \"C_ADC_NCO_Freq13\" \\\n\t\"C_ADC2_Enable\" \"C_ADC2_PLL_Enable\" \"C_ADC2_Sampling_Rate\" \"C_ADC2_Refclk_Freq\" \"C_ADC2_Fabric_Freq\" \"C_ADC2_FBDIV\" \"C_ADC2_OutDiv\" \"C_ADC2_Refclk_Div\" \"C_ADC2_Band\" \"C_ADC2_Fs_Max\" \"C_ADC2_Slices\" \\\n\t\"C_ADC_Slice20_Enable\" \"C_ADC_Mixer_Mode20\" \\\n\t\"C_ADC_Slice21_Enable\" \"C_ADC_Mixer_Mode21\" \\\n\t\"C_ADC_Slice22_Enable\" \"C_ADC_Mixer_Mode22\" \\\n\t\"C_ADC_Slice23_Enable\" \"C_ADC_Mixer_Mode23\" \\\n\t\"C_ADC_Data_Type20\" \"C_ADC_Data_Width20\" \"C_ADC_Decimation_Mode20\" \"C_ADC_Fifo20_Enable\" \"C_ADC_Mixer_Type20\" \"C_ADC_NCO_Freq20\" \\\n\t\"C_ADC_Data_Type21\" \"C_ADC_Data_Width21\" \"C_ADC_Decimation_Mode21\" \"C_ADC_Fifo21_Enable\" \"C_ADC_Mixer_Type21\" \"C_ADC_NCO_Freq21\" \\\n\t\"C_ADC_Data_Type22\" \"C_ADC_Data_Width22\" \"C_ADC_Decimation_Mode22\" \"C_ADC_Fifo22_Enable\" \"C_ADC_Mixer_Type22\" \"C_ADC_NCO_Freq22\" \\\n\t\"C_ADC_Data_Type23\" \"C_ADC_Data_Width23\" \"C_ADC_Decimation_Mode23\" \"C_ADC_Fifo23_Enable\" \"C_ADC_Mixer_Type23\" \"C_ADC_NCO_Freq23\" \\\n\t\"C_ADC3_Enable\" \"C_ADC3_PLL_Enable\" \"C_ADC3_Sampling_Rate\" \"C_ADC3_Refclk_Freq\" \"C_ADC3_Fabric_Freq\" \"C_ADC3_FBDIV\" \"C_ADC3_OutDiv\" \"C_ADC3_Refclk_Div\" \"C_ADC3_Band\" \"C_ADC3_Fs_Max\" \"C_ADC3_Slices\" \\\n\t\"C_ADC_Slice30_Enable\" \"C_ADC_Mixer_Mode30\" \\\n\t\"C_ADC_Slice31_Enable\" \"C_ADC_Mixer_Mode31\" \\\n\t\"C_ADC_Slice32_Enable\" \"C_ADC_Mixer_Mode32\" \\\n\t\"C_ADC_Slice33_Enable\" \"C_ADC_Mixer_Mode33\" \\\n\t\"C_ADC_Data_Type30\" \"C_ADC_Data_Width30\" \"C_ADC_Decimation_Mode30\" \"C_ADC_Fifo30_Enable\" \"C_ADC_Mixer_Type30\" \"C_ADC_NCO_Freq30\" \\\n\t\"C_ADC_Data_Type31\" \"C_ADC_Data_Width31\" \"C_ADC_Decimation_Mode31\" \"C_ADC_Fifo31_Enable\" \"C_ADC_Mixer_Type31\" \"C_ADC_NCO_Freq31\" \\\n\t\"C_ADC_Data_Type32\" \"C_ADC_Data_Width32\" \"C_ADC_Decimation_Mode32\" \"C_ADC_Fifo32_Enable\" \"C_ADC_Mixer_Type32\" \"C_ADC_NCO_Freq32\" \\\n\t\"C_ADC_Data_Type33\" \"C_ADC_Data_Width33\" \"C_ADC_Decimation_Mode33\" \"C_ADC_Fifo33_Enable\" \"C_ADC_Mixer_Type33\" \"C_ADC_NCO_Freq33\"\n}\n\nproc convert_hex_string_to_byte_code {var} {\n\treturn [string trimright [regsub -all {..} $var {& }]]\n}\n\nproc convert_double_to_le_byte_code_format {var} {\n\tset result \"\"\n\tset double [binary format q $var]\n\tbinary scan $double H* result\n\treturn [convert_hex_string_to_byte_code $result]\n}\n\nproc convert_int_to_le_byte_code_format {var} {\n\tset result \"\"\n\tset integer [binary format i $var]\n\tbinary scan $integer H* result\n\treturn [convert_hex_string_to_byte_code $result]\n}\n\n#\n# Given a list of arguments, add them in param-list property,\n# in byte code format\n#\nproc add_param_list_property {drv_handle args} {\n\tset args [::hsi::utils::get_exact_arg_list $args]\n\n\t# Get all peripherals connected to this driver\n\tset periphs [::hsi::utils::get_common_driver_ips $drv_handle]\n\tset device_id 0\n\tforeach periph $periphs {\n\t\tif {[string compare -nocase $periph $drv_handle] == 0} {\n\t\t\tbreak\n\t\t}\n\t\tincr device_id\n\t}\n\n\tforeach arg $args {\n\t\tif {[string compare -nocase \"DEVICE_ID\" $arg] == 0} {\n\t\t\tset value $device_id\n\t\t} else {\n\t\t\tset value [common::get_property CONFIG.$arg $periph]\n\t\t}\n\t\tif {[llength $value] == 0} {\n\t\t\tset value 0\n\t\t}\n\t\tif { [string first \"_Sampling_Rate\" $arg] > -1 || [string first \"_Refclk_Freq\" $arg] > -1 || [string first \"_Fabric_Freq\" $arg] > -1 || [string first \"_Fs_Max\" $arg] > -1 || [string match \"*_NCO_Freq*\" $arg]} {\n\t\t\tappend data \" \" [convert_double_to_le_byte_code_format $value]\n\t\t} elseif { [string first \"C_BASEADDR\" $arg] > -1 } {\n\t\t\tset high_addr 0x00000000\n\t\t\t#Check if address is greater than 4GB (i.e more than 32 bit)\n\t\t\tif {[regexp -nocase {([0-9a-f]{9})} \"$value\" match]} {\n\t\t\t\tset high_addr \"0x[string range $value 10 17]\"\n\t\t\t}\n\t\t\tset low_addr [string range $value 0 9]\n\t\t\tappend data \" \" [convert_int_to_le_byte_code_format $low_addr]\n\t\t\tappend data \" \" [convert_int_to_le_byte_code_format $high_addr]\n\t\t} else {\n\t\t\tif {[string compare -nocase \"false\" $value] == 0} {\n\t\t\t\tset value 0\n\t\t\t} elseif {[string compare -nocase \"true\" $value] == 0} {\n\t\t\t\tset value 1\n\t\t\t}\n\t\t\tappend data \" \" [convert_int_to_le_byte_code_format $value]\n\t\t}\n\t}\n\thsi::utils::add_new_property $drv_handle \"param-list\" bytelist $data\n}\n" }, { "path": "scene_change_detector/data/scene_change_detector.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver scene_change_detector\n\n OPTION supported_peripherals = (v_scenechange);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = scene_change_detector;\n\nEND driver\n" }, { "path": "scene_change_detector/data/scene_change_detector.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible \"xlnx,v-scd\"\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset ip [get_cells -hier $drv_handle]\n\tset max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,max-data-width\" $max_data_width int\n\tset memory_scd [get_property CONFIG.MEMORY_BASED [get_cells -hier $drv_handle]]\n\tif {$memory_scd == 1} {\n\t\tset max_nr_streams [get_property CONFIG.MAX_NR_STREAMS [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,numstreams\" $max_nr_streams int\n\t\thsi::utils::add_new_dts_param $node \"#address-cells\" 1 int\n\t\thsi::utils::add_new_dts_param $node \"#size-cells\" 0 int\n\t\thsi::utils::add_new_dts_param $node \"xlnx,memorybased\" \"\" boolean\n\t\thsi::utils::add_new_dts_param \"$node\" \"#dma-cells\" 1 int\n\t\tset aximm_addr_width [get_property CONFIG.AXIMM_ADDR_WIDTH [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,addrwidth\" $aximm_addr_width hexint\n\t\tfor {set stream 0} {$stream < $max_nr_streams} {incr stream} {\n\t\t\tset scd_node [add_or_get_dt_node -n \"subdev@$stream\" -p $node]\n\t\t\tset port_node [add_or_get_dt_node -n \"port@0\" -l port_$stream -p $scd_node]\n\t\t\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 0 int\n\t\t\tset endpoint [add_or_get_dt_node -n \"endpoint\" -l scd_in$stream -p $port_node]\n\t\t\thsi::utils::add_new_dts_param \"$endpoint\" \"remote-endpoint\" vcap0_out$stream reference\n\t\t}\n\t\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\t\tif {$dt_overlay} {\n\t\t\tset bus_node \"amba\"\n\t\t} else {\n\t\t\tset bus_node \"amba_pl\"\n\t\t}\n\t\tset dts_file [current_dt_tree]\n\t\tset dma_names \"\"\n\t\tset dmas \"\"\n\t\tset vcap_scd [add_or_get_dt_node -n \"video_cap\" -l videocap -d $dts_file -p $bus_node]\n\t\tfor {set stream 0} {$stream < $max_nr_streams} {incr stream} {\n\t\t\tappend dma_names \" \" \"port$stream\"\n\t\t\tset peri \"$drv_handle $stream\"\n\t\t\tset dmas [lappend dmas $peri]\n\t\t}\n\t\thsi::utils::add_new_dts_param \"$vcap_scd\" \"dma-names\" $dma_names stringlist\n\t\tgenerate_dmas $vcap_scd $dmas\n\t\tset ports_vcap [add_or_get_dt_node -n \"ports\" -l ports_vcap -p $vcap_scd]\n\t\thsi::utils::add_new_dts_param $ports_vcap \"#address-cells\" 1 int\n\t\thsi::utils::add_new_dts_param $ports_vcap \"#size-cells\" 0 int\n\t\thsi::utils::add_new_dts_param $vcap_scd \"compatible\" \"xlnx,video\" string\n\t\tfor {set stream 0} {$stream < $max_nr_streams} {incr stream} {\n\t\t\tset port_vcap_node [add_or_get_dt_node -n \"port@$stream\" -l port$stream -p $ports_vcap]\n\t\t\thsi::utils::add_new_dts_param \"$port_vcap_node\" \"reg\" $stream int\n\t\t\thsi::utils::add_new_dts_param \"$port_vcap_node\" \"direction\" output string\n\t\t\tset vcap_endpoint [add_or_get_dt_node -n \"endpoint\" -l vcap0_out$stream -p $port_vcap_node]\n\t\t\thsi::utils::add_new_dts_param \"$vcap_endpoint\" \"remote-endpoint\" scd_in$stream reference\n\t\t}\n\t} else {\n\t\tset max_nr_streams [get_property CONFIG.MAX_NR_STREAMS [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,numstreams\" $max_nr_streams int\n\t\thsi::utils::add_new_dts_param $node \"#address-cells\" 1 int\n\t\thsi::utils::add_new_dts_param $node \"#size-cells\" 0 int\n\t\tset scd_ports_node [add_or_get_dt_node -n \"scd\" -l scd_ports$drv_handle -p $node]\n\t\thsi::utils::add_new_dts_param \"$scd_ports_node\" \"#address-cells\" 1 int\n\t\thsi::utils::add_new_dts_param \"$scd_ports_node\" \"#size-cells\" 0 int\n\t\tset connect_out_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] \"M_AXIS_VIDEO\"]\n\t\tif {![llength $connect_out_ip]} {\n\t\t\tdtg_warning \"$drv_handle pin M_AXIS_VIDEO is not connected... check your design\"\n\t\t}\n\t\tforeach connected_out_ip $connect_out_ip {\n\t\t\tif {[llength $connected_out_ip]} {\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $connected_out_ip] \"system_ila\"]} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_out_ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_out_ip]\n\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\tset scd_port1_node [add_or_get_dt_node -n \"port\" -l scd_port1$drv_handle -u 1 -p $scd_ports_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"$scd_port1_node\" \"reg\" 1 int\n\t\t\t\t\tset scd_node [add_or_get_dt_node -n \"endpoint\" -l scd_out$drv_handle -p $scd_port1_node]\n\t\t\t\t\thsi::utils::add_new_dts_param \"$scd_node\" \"remote-endpoint\" $connected_out_ip$drv_handle reference\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $connected_out_ip] \"v_frmbuf_wr\"]} {\n\t\t\t\t\t\tgen_frmbuf_node $connected_out_ip $drv_handle\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tset connectip [get_connect_ip $connected_out_ip $master_intf]\n\t\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\t\tset scd_port1_node [add_or_get_dt_node -n \"port\" -l scd_port1$drv_handle -u 1 -p $scd_ports_node]\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$scd_port1_node\" \"reg\" 1 int\n\t\t\t\t\t\tset scd_node [add_or_get_dt_node -n \"endpoint\" -l scd_out$drv_handle -p $scd_port1_node]\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$scd_node\" \"remote-endpoint\" $connectip$drv_handle reference\n\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"v_frmbuf_wr\"]} {\n\t\t\t\t\t\t\t\tgen_frmbuf_node $connectip $drv_handle\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tdtg_warning \"$drv_handle pin M_AXIS_VIDEO is not connected... check your design\"\n\t\t\t}\n\t\t}\n\t}\n\tgen_gpio_reset $drv_handle $node\n}\n\nproc gen_frmbuf_node {ip drv_handle} {\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n\tset vcap [add_or_get_dt_node -n \"vcap_$drv_handle\" -p $bus_node]\n\thsi::utils::add_new_dts_param $vcap \"compatible\" \"xlnx,video\" string\n\thsi::utils::add_new_dts_param $vcap \"dmas\" \"$ip 0\" reference\n\thsi::utils::add_new_dts_param $vcap \"dma-names\" \"port0\" string\n\tset vcap_ports_node [add_or_get_dt_node -n \"ports\" -l vcap_ports$drv_handle -p $vcap]\n\thsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#size-cells\" 0 int\n\tset vcap_port_node [add_or_get_dt_node -n \"port\" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node]\n\thsi::utils::add_new_dts_param \"$vcap_port_node\" \"reg\" 0 int\n\thsi::utils::add_new_dts_param \"$vcap_port_node\" \"direction\" input string\n\tset vcap_in_node [add_or_get_dt_node -n \"endpoint\" -l $ip$drv_handle -p $vcap_port_node]\n\thsi::utils::add_new_dts_param \"$vcap_in_node\" \"remote-endpoint\" scd_out$drv_handle reference\n}\n\nproc generate_dmas {vcap_scd dmas} {\n\tset len [llength $dmas]\n\tswitch $len {\n\t\t\"1\" {\n\t\t\tset refs [lindex $dmas 0]\n\t\t\thsi::utils::add_new_dts_param \"$vcap_scd\" \"dmas\" $refs reference\n\t\t}\n\t\t\"2\" {\n\t\t\tset refs [lindex $dmas 0]\n\t\t\tappend refs \">, <&[lindex $dmas 1]\"\n\t\t\thsi::utils::add_new_dts_param \"$vcap_scd\" \"dmas\" $refs reference\n\t\t}\n\t\t\"3\" {\n\t\t\tset refs [lindex $dmas 0]\n\t\t\tappend refs \">, <&[lindex $dmas 1]>, <&[lindex $dmas 2]\"\n\t\t\thsi::utils::add_new_dts_param \"$vcap_scd\" \"dmas\" $refs reference\n\t\t}\n\t\t\"4\" {\n\t\t\tset refs [lindex $dmas 0]\n\t\t\tappend refs \">, <&[lindex $dmas 1]>, <&[lindex $dmas 2]>, <&[lindex $dmas 3]\"\n\t\t\thsi::utils::add_new_dts_param \"$vcap_scd\" \"dmas\" $refs reference\n\t\t}\n\t\t\"5\" {\n\t\t\tset refs [lindex $dmas 0]\n\t\t\tappend refs \">, <&[lindex $dmas 1]>, <&[lindex $dmas 2]>, <&[lindex $dmas 3]>, <&[lindex $dmas 4]\"\n\t\t\thsi::utils::add_new_dts_param \"$vcap_scd\" \"dmas\" $refs reference\n\t\t}\n\t\t\"6\" {\n\t\t\tset refs [lindex $dmas 0]\n\t\t\tappend refs \">, <&[lindex $dmas 1]>, <&[lindex $dmas 2]>, <&[lindex $dmas 3]>, <&[lindex $dmas 4]>, <&[lindex $dmas 5]\"\n\t\t\thsi::utils::add_new_dts_param \"$vcap_scd\" \"dmas\" $refs reference\n\t\t}\n\t\t\"7\" {\n\t\t\tset refs [lindex $dmas 0]\n\t\t\tappend refs \">, <&[lindex $dmas 1]>, <&[lindex $dmas 2]>, <&[lindex $dmas 3]>, <&[lindex $dmas 4]>, <&[lindex $dmas 5]>, <&[lindex $dmas 6]\"\n\t\t\thsi::utils::add_new_dts_param \"$vcap_scd\" \"dmas\" $refs reference\n\t\t}\n\t\t\"8\" {\n\t\t\tset refs [lindex $dmas 0]\n\t\t\tappend refs \">, <&[lindex $dmas 1]>, <&[lindex $dmas 2]>, <&[lindex $dmas 3]>, <&[lindex $dmas 4]>, <&[lindex $dmas 5]>, <&[lindex $dmas 6]>, <&[lindex $dmas 7]\"\n\t\t\thsi::utils::add_new_dts_param \"$vcap_scd\" \"dmas\" $refs reference\n\t\t}\n\t}\n}\n\nproc gen_gpio_reset {drv_handle node} {\n\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] \"ap_rst_n\"]]\n\tforeach pin $pins {\n\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tif {[llength $sink_periph]} {\n\t\t\tset sink_ip [get_property IP_NAME $sink_periph]\n\t\t\tif {[string match -nocase $sink_ip \"xlslice\"]} {\n\t\t\t\tset gpio [get_property CONFIG.DIN_FROM $sink_periph]\n\t\t\t\tset pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph \"Din\"]]]\n\t\t\t\tforeach pin $pins {\n\t\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t\tif {[llength $periph]} {\n\t\t\t\t\t\tset ip [get_property IP_NAME $periph]\n\t\t\t\t\t\tset proc_type [get_sw_proc_prop IP_NAME]\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psv_cortexa72\"] } {\n\t\t\t\t\t\t\tif { $ip in { \"versal_cips\" \"ps_wizard\" }} {\n\t\t\t\t\t\t\t\t# As versal has only bank0 for MIOs\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 26]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio0 $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psu_cortexa53\"]} {\n\t\t\t\t\t\t\tif {[string match -nocase $ip \"zynq_ultra_ps_e\"]} {\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 78]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $ip \"axi_gpio\"]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"$periph $gpio 1\" reference\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"$drv_handle: peripheral is NULL for the $pin $periph\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle:peripheral is NULL for the $pin $sink_periph\"\n\t\t}\n\t}\n}\n" }, { "path": "scugic/data/scugic.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver scugic\n\n OPTION supported_peripherals = (ps7_scugic psu_acpu_gic psv_acpu_gic psx_acpu_gic);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = scugic;\n DTGPARAM name = num_cpus, type = int, default = 2;\n DTGPARAM name = num_interrupts, type = int, default = 96;\n\nEND driver\n" }, { "path": "scugic/data/scugic.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset default_dts [set_drv_def_dts $drv_handle]\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tset cpm_ip [get_cells -hier -filter IP_NAME==psv_cpm]\n\tif {[string match -nocase $proctype \"psv_cortexa72\"] && \\\n\t\t[string match -nocase [get_property CONFIG.APU_GIC_ITS_CTL [get_cells -hier $drv_handle]] \"0xF9020000\"] && \\\n\t\t[llength $cpm_ip]} {\n\t\tset gic_node [add_or_get_dt_node -n \"&gic_its\" -d $default_dts]\n\t\thsi::utils::add_new_dts_param \"${gic_node}\" \"status\" \"okay\" string\n\t}\n}\n" }, { "path": "scutimer/data/scutimer.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver scutimer\n\n OPTION supported_peripherals = (ps7_scutimer);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = scutimer;\n\nEND driver\n" }, { "path": "scutimer/data/scutimer.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n" }, { "path": "scuwdt/data/scuwdt.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver scuwdt\n\n OPTION supported_peripherals = (ps7_scuwdt psu_wdt psv_wdt);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = scuwdt;\n\nEND driver\n" }, { "path": "scuwdt/data/scuwdt.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n" }, { "path": "sdfec/data/sdfec.mdd", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver sdfec\n\n OPTION supported_peripherals = (sd_fec);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = sdfec;\n PARAMETER name = dev_type, default = \"sd-fec\", type = string;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,fec-engine\";\n\nEND driver\n" }, { "path": "sdfec/data/sdfec.tcl", "content": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset ldpc_decode [get_property CONFIG.LDPC_Decode [get_cells -hier $drv_handle]]\n\tset ldpc_encode [get_property CONFIG.LDPC_Encode [get_cells -hier $drv_handle]]\n\tset turbo_decode [get_property CONFIG.Turbo_Decode [get_cells -hier $drv_handle]]\n\tif {[string match -nocase $turbo_decode \"true\"]} {\n\t\tset sdfec_code \"turbo\"\n\t} else {\n\t\tset sdfec_code \"ldpc\"\n\t}\n\tset_drv_property $drv_handle xlnx,sdfec-code $sdfec_code string\n\tset sdfec_dout_words [get_property CONFIG.C_S_DOUT_WORDS_MODE [get_cells -hier $drv_handle]]\n\tset sdfec_dout_width [get_property CONFIG.DOUT_Lanes [get_cells -hier $drv_handle]]\n\tset sdfec_din_words [get_property CONFIG.C_S_DIN_WORDS_MODE [get_cells -hier $drv_handle]]\n\tset sdfec_din_width [get_property CONFIG.DIN_Lanes [get_cells -hier $drv_handle]]\n\tset_drv_property $drv_handle xlnx,sdfec-dout-words $sdfec_dout_words int\n\tset_drv_property $drv_handle xlnx,sdfec-dout-width $sdfec_dout_width int\n\tset_drv_property $drv_handle xlnx,sdfec-din-words $sdfec_din_words int\n\tset_drv_property $drv_handle xlnx,sdfec-din-width $sdfec_din_width int\n}\n" }, { "path": "sdi_rx/data/sdi_rx.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver sdi_rx\n\n OPTION supported_peripherals = (v_smpte_uhdsdi_rx_ss);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = sdi_rx;\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "sdi_rx/data/sdi_rx.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,v-smpte-uhdsdi-rx-ss\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\n\tset ports_node [add_or_get_dt_node -n \"ports\" -l sdirx_ports$drv_handle -p $node]\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\tset port_node [add_or_get_dt_node -n \"port\" -l sdirx_port$drv_handle -u 0 -p $ports_node]\n\thsi::utils::add_new_dts_param \"${port_node}\" \"/* Fill the fields xlnx,video-format and xlnx,video-width based on user requirement */\" \"\" comment\n\thsi::utils::add_new_dts_param \"$port_node\" \"xlnx,video-format\" 0 int\n\thsi::utils::add_new_dts_param \"$port_node\" \"xlnx,video-width\" 10 int\n\thsi::utils::add_new_dts_param \"$port_node\" \"reg\" 0 int\n\n\tset sdirxip [get_connected_stream_ip [get_cells -hier $drv_handle] \"VIDEO_OUT\"]\n\tforeach ip $sdirxip {\n\t\tif {[llength $ip]} {\n\t\t\tif {[string match -nocase [get_property IP_NAME $ip] \"system_ila\"]} {\n\t\t\t\tcontinue\n\t\t\t}\n\t\t\tset intfpins [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip]\n\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\t\tset sdi_rx_node [add_or_get_dt_node -n \"endpoint\" -l sdirx_out$drv_handle -p $port_node]\n\t\t\t\tgen_endpoint $drv_handle \"sdirx_out$drv_handle\"\n\t\t\t\thsi::utils::add_new_dts_param \"$sdi_rx_node\" \"remote-endpoint\" $ip$drv_handle reference\n\t\t\t\tgen_remoteendpoint $drv_handle $ip$drv_handle\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $ip] \"v_frmbuf_wr\"]} {\n\t\t\t\t\tgen_frmbuf_wr_node $ip $drv_handle\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tset connectip [get_connect_ip $ip $intfpins]\n\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\tset sdi_rx_node [add_or_get_dt_node -n \"endpoint\" -l sdirx_out$drv_handle -p $port_node]\n\t\t\t\t\tgen_endpoint $drv_handle \"sdirx_out$drv_handle\"\n\t\t\t\t\thsi::utils::add_new_dts_param \"$sdi_rx_node\" \"remote-endpoint\" $connectip$drv_handle reference\n\t\t\t\t\tgen_remoteendpoint $drv_handle $connectip$drv_handle\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"axi_vdma\"] || [string match -nocase [get_property IP_NAME $connectip] \"v_frmbuf_wr\"]} {\n\t\t\t\t\t\tgen_frmbuf_wr_node $connectip $drv_handle\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc gen_frmbuf_wr_node {outip drv_handle} {\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n set vcap [add_or_get_dt_node -n \"vcap_sdirx$drv_handle\" -p $bus_node]\n hsi::utils::add_new_dts_param $vcap \"compatible\" \"xlnx,video\" string\n hsi::utils::add_new_dts_param $vcap \"dmas\" \"$outip 0\" reference\n hsi::utils::add_new_dts_param $vcap \"dma-names\" \"port0\" string\n set vcap_ports_node [add_or_get_dt_node -n \"ports\" -l vcap_ports$drv_handle -p $vcap]\n hsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#address-cells\" 1 int\n hsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#size-cells\" 0 int\n set vcap_port_node [add_or_get_dt_node -n \"port\" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node]\n hsi::utils::add_new_dts_param \"$vcap_port_node\" \"reg\" 0 int\n hsi::utils::add_new_dts_param \"$vcap_port_node\" \"direction\" input string\n set vcap_in_node [add_or_get_dt_node -n \"endpoint\" -l $outip$drv_handle -p $vcap_port_node]\n hsi::utils::add_new_dts_param \"$vcap_in_node\" \"remote-endpoint\" sdirx_out$drv_handle reference\n}\n" }, { "path": "sdi_tx/data/sdi_tx.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver sdi_tx\n\n OPTION supported_peripherals = (v_smpte_uhdsdi_tx_ss);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = sdi_tx;\n DTGPARAM name = dtg.ip_params, type = boolean;\n\nEND driver\n" }, { "path": "sdi_tx/data/sdi_tx.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,sdi-tx\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset exdes_board [get_property CONFIG.C_EXDES_BOARD [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,exdes-board\" $exdes_board string\n\tset exdes_config [get_property CONFIG.C_EXDES_CONFIG [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,exdes-config\" $exdes_config string\n\tset adv_features [get_property CONFIG.C_INCLUDE_ADV_FEATURES [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,include-adv-features\" $adv_features string\n\tset axilite [get_property CONFIG.C_INCLUDE_AXILITE [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,include-axilite\" $axilite string\n\tset edh [get_property CONFIG.C_INCLUDE_EDH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,include-edh\" $edh string\n\tset linerate [get_property CONFIG.C_LINE_RATE [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,line-rate\" $linerate string\n\tset pixelclock [get_property CONFIG.C_PIXELS_PER_CLOCK [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,pixels-per-clock\" $pixelclock string\n\tset video_intf [get_property CONFIG.C_VIDEO_INTF [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,video-intf\" $video_intf string\n\tset ports_node [add_or_get_dt_node -n \"ports\" -l sditx_ports$drv_handle -p $node]\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\tset audio_connected_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] \"SDI_TX_ANC_DS_OUT\"]\n\tif {[llength $audio_connected_ip] != 0} {\n\t\tset audio_connected_ip_type [get_property IP_NAME $audio_connected_ip]\n\t\tif {[string match -nocase $audio_connected_ip_type \"v_uhdsdi_audio\"]} {\n\t\t\tset sdi_audio_port [add_or_get_dt_node -n \"port\" -l sdi_audio_port -u 1 -p $ports_node]\n\t\t\thsi::utils::add_new_dts_param \"$sdi_audio_port\" \"reg\" 1 int\n\t\t\tset sdi_audio_node [add_or_get_dt_node -n \"endpoint\" -l sdi_audio_sink_port -p $sdi_audio_port]\n\t\t\thsi::utils::add_new_dts_param \"$sdi_audio_node\" \"remote-endpoint\" sditx_audio_embed_src reference\n\t\t}\n\t} else {\n\t\tdtg_warning \"$drv_handle:connected ip for audio port pin SDI_TX_ANC_DS_OUT is NULL\"\n\t}\n}\n" }, { "path": "sdps/data/sdps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver sdps\n\n OPTION supported_peripherals = (ps7_sdioi psu_sd psv_pmc_sd psx_pmc_sd);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = sdps;\n DTGPARAM name = clock-frequency , type = int ;\n\nEND driver\n" }, { "path": "sdps/data/sdps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n set ip [get_cells -hier $drv_handle]\n set clk_freq [hsi::utils::get_ip_param_value $ip C_SDIO_CLK_FREQ_HZ]\n set_property CONFIG.clock-frequency \"$clk_freq\" $drv_handle\n set_drv_conf_prop $drv_handle C_MIO_BANK xlnx,mio-bank hexint\n}\n\n\n" }, { "path": "slcrps/data/slcrps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver slcrps\n\n OPTION supported_peripherals = (ps7_slcr);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = slcrps;\n\nEND driver\n" }, { "path": "slcrps/data/slcrps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n\n set node [gen_peripheral_nodes $drv_handle]\n gen_clocks_node $node\n}\n\nproc gen_clocks_node {parent_node} {\n set clocks_child_name \"clkc\"\n set dts_file [get_property CONFIG.pcw_dts [get_os]]\n set clkc_node [add_or_get_dt_node -l $clocks_child_name -n $clocks_child_name -u 100 -d $dts_file -p $parent_node]\n\n if {[catch {set ps_clk_freq [get_property CONFIG.C_INPUT_CRYSTAL_FREQ_HZ [get_cells -hier ps7_clockc_0]]} msg]} {\n set ps_clk_freq \"\"\n }\n if {[string_is_empty ${ps_clk_freq}]} {\n puts \"WARNING: DTG failed to detect the ps-clk-frequency, Using default value - 33333333\"\n set ps_clk_freq 33333333\n }\n hsi::utils::add_new_dts_param \"${clkc_node}\" \"ps-clk-frequency\" ${ps_clk_freq} int\n\n set fclk_val \"0\"\n set clk_pin_list [get_pins [get_cells -hier ps7_clockc_0] -regexp FCLK_CLK[0-3]]\n foreach clk_pin ${clk_pin_list} {\n dtg_debug \"clk_pin: $clk_pin\"\n set clk_net [get_nets -of_objects $clk_pin]\n set connected_pin_names [get_pins -of_objects $clk_net]\n foreach target_pin ${connected_pin_names} {\n dtg_debug \" target_pin: $target_pin\"\n set connected_ip [get_cells -of_objects $target_pin]\n if {[is_pl_ip $connected_ip]} {\n regsub -all {FCLK_CLK} $clk_pin {} fclk_pin\n set fclk_val [expr [expr 1 << $fclk_pin] | $fclk_val]\n dtg_debug \" PL IP: $connected_ip, CLK_PIN: $clk_pin, FCLK_PIN: $fclk_pin, FCLK_VAL: [format %x $fclk_val]\"\n # Here could be break\n } elseif {![string match \"ps7_clockc_0\" $connected_ip]} {\n dtg_debug \" PS IP: $connected_ip\"\n }\n }\n }\n hsi::utils::add_new_dts_param \"${clkc_node}\" \"fclk-enable\" \"0x[format %x $fclk_val]\" int\n return $clkc_node\n}\n" }, { "path": "smccps/data/smccps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver smccps\n\n OPTION supported_peripherals = (ps7_smcc);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = smccps;\n\nEND driver\n" }, { "path": "smccps/data/smccps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n" }, { "path": "spips/data/spips.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver spips\n\n OPTION supported_peripherals = (ps7_spi psu_spi psv_spi psx_spi);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = spips;\n DTGPARAM name = num-cs , type = int, default = 1;\n DTGPARAM name = is-decoded-cs , type = int, default = 0;\n DTGPARAM name = dtg.alias , default = spi;\nEND driver\n" }, { "path": "spips/data/spips.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tset ip [get_cells -hier $drv_handle]\n\tset cs-num 0\n\t# SPI PS only have chip select range 0 - 2\n\tforeach n {0 1 2} {\n\t\tset cs_en [get_property CONFIG.C_HAS_SS${n} $ip]\n\t\tif {[string equal \"1\" $cs_en]} {\n\t\t\tinc cs-num\n\t\t}\n\t}\n\tif {${cs-num} != 0} {\n\t\tset_property CONFIG.num-cs ${cs-num} $drv_handle\n\t}\n\n\t# the is-decoded-cs property is hard coded as we do not know if the\n\t# board has external decoder connected or not\n\t# Once we had the board level information, is-decoded-cs need to be\n\t# generated based on it.\n}\n" }, { "path": "sync_ip/data/sync_ip.mdd", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver sync_ip\n\n OPTION supported_peripherals = (sync_ip);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = sync_ip;\n\nEND driver\n" }, { "path": "sync_ip/data/sync_ip.tcl", "content": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset enable_enc_dec [get_property CONFIG.ENABLE_ENC_DEC [get_cells -hier $drv_handle]]\n\tif {$enable_enc_dec == 0} {\n\t#encode case\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,encode\" \"\" boolean\n\t\tset no_of_enc_chan [get_property CONFIG.NO_OF_ENC_CHAN [get_cells -hier $drv_handle]]\n\t\tset no_of_enc_chan [expr $no_of_enc_chan + 1]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,num-chan\" $no_of_enc_chan int\n\t} else {\n\t#decode case\n\t\tset no_of_dec_chan [get_property CONFIG.NO_OF_DEC_CHAN [get_cells -hier $drv_handle]]\n\t\tset no_of_dec_chan [expr $no_of_dec_chan + 1]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,num-chan\" $no_of_dec_chan int\n\t}\n}\n" }, { "path": "sysmonpsv/data/sysmonpsv.mdd", "content": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver sysmon\n\n OPTION supported_peripherals = (psv_pmc_sysmon slv1_psv_pmc_sysmon slv2_psv_pmc_sysmon slv3_psv_pmc_sysmon);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = sysmonpsv;\n\nEND driver\n" }, { "path": "sysmonpsv/data/sysmonpsv.tcl", "content": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n set num_supply_channels 0\n set periph_list [get_cells -hier]\n set node [gen_peripheral_nodes $drv_handle]\n if {$node == 0} {\n\treturn\n }\n hsi::utils::add_new_dts_param $node \"#address-cells\" 2 int\n hsi::utils::add_new_dts_param $node \"#size-cells\" 2 int\n set ssitvalue [get_property IS_SSIT [get_current_part $drv_handle]]\n if {[llength $ssitvalue]} {\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,ssit-device\" \"$ssitvalue\" bool\n\t}\n set slrsvalue [get_property NUM_OF_SLRS [get_current_part $drv_handle]]\n if {[llength $slrsvalue] && $slrsvalue != \"-1\"} {\n\thsi::utils::add_new_dts_param \"$node\" \"xlnx,num-of-slr\" \"$slrsvalue\" int\n\t}\n\n for {set supply_num 0} {$supply_num < 160} {incr supply_num} {\n\t set meas \"C_MEAS_${supply_num}\"\n\t set id \"${meas}_ROOT_ID\"\n\t set value [get_property CONFIG.$meas [get_cells -hier $drv_handle]]\n\t if {[llength $value] != 0} {\n\t\t set local_value [string tolower [get_property CONFIG.$meas [get_cells -hier $drv_handle]]]\n\t\t set id_value [get_property CONFIG.$id [get_cells -hier $drv_handle]]\n set default_dts [get_property CONFIG.pcw_dts [get_os]]\n\t\t set supply_node [add_or_get_dt_node -n \"supply@$id_value\" -p $node -d ${default_dts}]\n\t\t hsi::utils::add_new_dts_param \"$supply_node\" \"reg\" \"$id_value\" int\n\t\t hsi::utils::add_new_dts_param \"$supply_node\" \"xlnx,name\" \"$local_value\" string\n\t\t incr num_supply_channels\n\t }\n }\n append numsupplies \"/bits/8 <$num_supply_channels>\"\n hsi::utils::add_new_dts_param $node \"xlnx,numchannels\" $numsupplies noformating\n}\n" }, { "path": "tmrctr/data/tmrctr.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver tmrctr\n\n OPTION supported_peripherals = (axi_timer);\n OPTION driver_state = ACTIVE;\n OPTION NAME = tmrctr;\n OPTION supported_os_types = (DTS);\n DTGPARAM name = dtg.ip_params, type = boolean;\n DTGPARAM name = dev_type, default = timer , type = string;\n DTGPARAM name = clock-frequency, type = int, default = 100000000;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,xps-timer-1.00.a\"\n\nEND driver\n" }, { "path": "tmrctr/data/tmrctr.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n # try to source the common tcl procs\n # assuming the order of return is based on repo priority\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n set compatible [get_comp_str $drv_handle]\n set compatible [append compatible \" \" \"xlnx,xps-timer-1.00.a\"]\n set_drv_prop $drv_handle compatible \"$compatible\" stringlist\n #adding clock frequency\n set ip [get_cells -hier $drv_handle]\n set clk [get_pins -of_objects $ip \"S_AXI_ACLK\"]\n if {[llength $clk] } {\n set freq [get_property CLK_FREQ $clk]\n set_property clock-frequency \"$freq\" $drv_handle\n }\n set proc_type [get_sw_proc_prop IP_NAME]\n switch $proc_type {\n \"microblaze\" {\n gen_dev_ccf_binding $drv_handle \"s_axi_aclk\"\n }\n }\n}\n" }, { "path": "tpg/data/tpg.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver tpg\n\n OPTION supported_peripherals = (v_tpg);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = tpg;\n\nEND driver\n" }, { "path": "tpg/data/tpg.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset tpg_count [hsi::utils::get_os_parameter_value \"tpg_count\"]\n\tif { [llength $tpg_count] == 0 } {\n\t\tset tpg_count 0\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,v-tpg-8.0\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset ip [get_cells -hier $drv_handle]\n\tset s_axi_ctrl_addr_width [get_property CONFIG.C_S_AXI_CTRL_ADDR_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,s-axi-ctrl-addr-width\" $s_axi_ctrl_addr_width int\n\tset s_axi_ctrl_data_width [get_property CONFIG.C_S_AXI_CTRL_DATA_WIDTH [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,s-axi-ctrl-data-width\" $s_axi_ctrl_data_width int\n\tset max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]]\n\tset pixels_per_clock [get_property CONFIG.SAMPLES_PER_CLOCK [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,ppc\" $pixels_per_clock int\n\tset max_cols [get_property CONFIG.MAX_COLS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,max-width\" $max_cols int\n\tset max_rows [get_property CONFIG.MAX_ROWS [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,max-height\" $max_rows int\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tif {[string match -nocase $proctype \"ps7_cortexa9\"]} {\n\t\t# Workaround for issue (TBF)\n\t\treturn\n\t}\n\tset ports_node [add_or_get_dt_node -n \"ports\" -l tpg_ports$drv_handle -p $node]\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\tset port1_node [add_or_get_dt_node -n \"port\" -l tpg_port1$drv_handle -u 1 -p $ports_node]\n\thsi::utils::add_new_dts_param \"$port1_node\" \"reg\" 1 int\n\thsi::utils::add_new_dts_param \"${port1_node}\" \"/* Fill the field xlnx,video-format based on user requirement */\" \"\" comment\n\thsi::utils::add_new_dts_param \"$port1_node\" \"xlnx,video-format\" 2 int\n\thsi::utils::add_new_dts_param \"$port1_node\" \"xlnx,video-width\" $max_data_width int\n\n\tset connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"S_AXIS_VIDEO\"]\n\tif {![llength $connect_ip]} {\n\t\tdtg_warning \"$drv_handle pin S_AXIS_VIDEO is not connected..check your design\"\n\t}\n\tforeach connected_ip $connect_ip {\n\t\tif {[llength $connected_ip] != 0} {\n\t\t\tset connected_ip_type [get_property IP_NAME $connected_ip]\n\t\t\tset ports_node \"\"\n\t\t\tset sink_periph \"\"\n\t\t\tif {[llength $connected_ip_type] != 0} {\n\t\t\t\tif {[string match -nocase $connected_ip_type \"system_ila\"]} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase $connected_ip_type \"v_vid_in_axi4s\"]} {\n\t\t\t\t\tset pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $connected_ip \"vid_active_video\"]]]\n\t\t\t\t\tforeach pin $pins {\n\t\t\t\t\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t\t\tset sink_ip [get_property IP_NAME $sink_periph]\n\t\t\t\t\t\tif {[string match -nocase $sink_ip \"v_tc\"]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"xlnx,vtc\" \"$sink_periph\" reference\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tset connect_out_ip [get_connected_stream_ip [get_cells -hier $drv_handle] \"M_AXIS_VIDEO\"]\n\tif {![llength $connect_out_ip]} {\n\t\tdtg_warning \"$drv_handle pin M_AXIS_VIDEO is not connected ...check your design\"\n\t}\n\tforeach out_ip $connect_out_ip {\n\t\tif {[llength $out_ip] != 0} {\n\t\t\tset connected_out_ip_type [get_property IP_NAME $out_ip]\n\t\t\tif {[llength $connected_out_ip_type] != 0} {\n\t\t\t\tif {[string match -nocase $connected_out_ip_type \"system_ila\"]} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $out_ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $out_ip]\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $out_ip] \"axis_switch\"]} {\n\t\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\t\tset tpg_node [add_or_get_dt_node -n \"endpoint\" -l tpg_out$drv_handle -p $port1_node]\n\t\t\t\t\t\tgen_axis_switch_in_endpoint $drv_handle \"tpg_out$drv_handle\"\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$tpg_node\" \"remote-endpoint\" $out_ip$drv_handle reference\n\t\t\t\t\t\tgen_axis_switch_in_remo_endpoint $drv_handle \"$out_ip$drv_handle\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\tset tpg_node [add_or_get_dt_node -n \"endpoint\" -l tpg_out$drv_handle -p $port1_node]\n\t\t\t\t\tgen_endpoint $drv_handle \"tpg_out$drv_handle\"\n\t\t\t\t\thsi::utils::add_new_dts_param \"$tpg_node\" \"remote-endpoint\" $out_ip$drv_handle reference\n\t\t\t\t\tgen_remoteendpoint $drv_handle \"$out_ip$drv_handle\"\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $out_ip] \"v_frmbuf_wr\"] || [string match -nocase [get_property IP_NAME $out_ip] \"axi_vdma\"]} {\n\t\t\t\t\t\tgen_frmbuf_node $out_ip $drv_handle\n\t\t\t\t\t}\n\t\t\t\t } else {\n\t\t\t\t\tset connectip [get_connect_ip $out_ip $master_intf]\n\t\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip]\n\t\t\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\t\t\tset tpg_node [add_or_get_dt_node -n \"endpoint\" -l tpg_out$drv_handle -p $port1_node]\n\t\t\t\t\t\t\tgen_endpoint $drv_handle \"tpg_out$drv_handle\"\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$tpg_node\" \"remote-endpoint\" $connectip$drv_handle reference\n\t\t\t\t\t\t\tgen_remoteendpoint $drv_handle \"$connectip$drv_handle\"\n\t\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"v_frmbuf_wr\"] || [string match -nocase [get_property IP_NAME $connectip] \"axi_vdma\"]} {\n\t\t\t\t\t\t\t\tgen_frmbuf_node $connectip $drv_handle\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle pin M_AXIS_VIDEO is not connected ...check your design\"\n\t\t}\n\t}\n\tgen_gpio_reset $drv_handle $node\n}\n\nproc gen_frmbuf_node {ip drv_handle} {\n\tset proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n\tset vcap [add_or_get_dt_node -n \"vcap_$drv_handle\" -p $bus_node]\n\thsi::utils::add_new_dts_param $vcap \"compatible\" \"xlnx,video\" string\n\thsi::utils::add_new_dts_param $vcap \"dmas\" \"$ip 0\" reference\n\thsi::utils::add_new_dts_param $vcap \"dma-names\" \"port0\" string\n\tset vcap_ports_node [add_or_get_dt_node -n \"ports\" -l vcap_ports$drv_handle -p $vcap]\n\thsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#size-cells\" 0 int\n\tif {[string match -nocase $proctype \"ps7_cortexa9\"]} {\n\t\t#Workaround for issue (TBF)\n\t\tset vcap_port_node [add_or_get_dt_node -n \"port\" -l vcap_port$drv_handle -p $vcap_ports_node]\n\t} else {\n\t\tset vcap_port_node [add_or_get_dt_node -n \"port\" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node]\n\t}\n\thsi::utils::add_new_dts_param \"$vcap_port_node\" \"reg\" 0 int\n\thsi::utils::add_new_dts_param \"$vcap_port_node\" \"direction\" input string\n\tset vcap_in_node [add_or_get_dt_node -n \"endpoint\" -l $ip$drv_handle -p $vcap_port_node]\n\thsi::utils::add_new_dts_param \"$vcap_in_node\" \"remote-endpoint\" tpg_out$drv_handle reference\n}\n\nproc gen_gpio_reset {drv_handle node} {\n\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] \"ap_rst_n\"]]\n\tforeach pin $pins {\n\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\tif {[llength $sink_periph]} {\n\t\t\tset sink_ip [get_property IP_NAME $sink_periph]\n\t\t\tif {[string match -nocase $sink_ip \"xlslice\"]} {\n\t\t\t\tset gpio [get_property CONFIG.DIN_FROM $sink_periph]\n\t\t\t\tset pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph \"Din\"]]]\n\t\t\t\tforeach pin $pins {\n\t\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t\tif {[llength $periph]} {\n\t\t\t\t\t\tset ip [get_property IP_NAME $periph]\n\t\t\t\t\t\tset proc_type [get_sw_proc_prop IP_NAME]\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psv_cortexa72\"] } {\n\t\t\t\t\t\t\tif { $ip in { \"versal_cips\" \"ps_wizard\" }} {\n\t\t\t\t\t\t\t\t# As versal has only bank0 for MIOs\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 26]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio0 $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n\t\t\t\t\t\t\tif {[string match -nocase $ip \"zynq_ultra_ps_e\"]} {\n\t\t\t\t\t\t\t\tset gpio [expr $gpio + 78]\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio $gpio 1\" reference\n\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif {[string match -nocase $ip \"axi_gpio\"]} {\n\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"$periph $gpio 1\" reference\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\tdtg_warning \"$drv_handle peripheral is NULL for the $pin $periph\"\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tdtg_warning \"$drv_handle peripheral is NULL for the $pin $sink_periph\"\n\t\t}\n\t}\n}\n" }, { "path": "tsn/data/tsn.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver tsn\n\n OPTION supported_peripherals = (tsn_endpoint_ethernet_mac);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = tsn;\n\nEND driver\n" }, { "path": "tsn/data/tsn.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset proc_type [get_sw_proc_prop IP_NAME]\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset eth_ip [get_cells -hier $drv_handle]\n\tset ip_name [get_property IP_NAME $eth_ip]\n\n\tglobal tsn_ep_node\n\tglobal tsn_emac0_node\n\tglobal tsn_emac1_node\n\tglobal tsn_ex_ep_node\n\tset tsn_ep_node \"tsn_ep\"\n\tset tsn_emac0_node \"tsn_emac_0\"\n\tset tsn_emac1_node \"tsn_emac_1\"\n\tset tsn_ex_ep_node \"tsn_ex_ep\"\n\tset end_point_ip \"\"\n\tset end1 \"\"\n\tset connectrx_ip \"\"\n\tset connecttx_ip \"\"\n\tset connected_ip [hsi::utils::get_connected_stream_ip $eth_ip \"tx_axis_be\"]\n\tif {[llength $connected_ip] != 0} {\n\t\tset end1_ip [hsi::utils::get_connected_stream_ip $connected_ip \"S00_AXIS\"]\n\t\tif {[llength $end1_ip] != 0} {\n\t\t\tset end1 [lappend end1 $end1_ip]\n\t\t} else {\n\t\t\tset connecttx_ip [lappend connecttx_ip $connected_ip]\n\t\t}\n\t}\n\tset connect_ip [hsi::utils::get_connected_stream_ip $eth_ip \"rx_axis_be\"]\n\tif {[llength $connect_ip] != 0} {\n\t\tset end_ip [hsi::utils::get_connected_stream_ip $connect_ip \"M00_AXIS\"]\n\t\tif {[llength $end_ip]!= 0} {\n\t\t\tset end_point_ip [lappend end_point_ip $end_ip]\n\t\t} else {\n\t\t\tset connectrx_ip [lappend connectrx_ip $connect_ip]\n\t\t}\n\t}\n\tforeach ip [get_drivers] {\n\t\tif {[string compare -nocase $ip $end_ip] == 0} {\n\t\t\tset target_handle $ip\n\t\t}\n\t}\n\tset connectedrx_ipname [get_property IP_NAME $end_ip]\n\tset id 1\n\tset queue \"\"\n\tif {$connectedrx_ipname == \"axi_mcdma\"} {\n\t\tset num_queues [get_property CONFIG.c_num_s2mm_channels $end_ip]\n\t\tset rx_queues [get_property CONFIG.c_num_mm2s_channels $end_ip]\n\t\tif {$num_queues > $rx_queues} {\n\t\t\tset queue $num_queues\n\t\t} else {\n\t\t\tset queue $rx_queues\n\t\t}\n\t\tfor {set i 2} {$i <= $num_queues} {incr i} {\n\t\t\tset i [format \"%x\" $i]\n\t\t\tappend id \"\\\"\"\n\t\t\tappend id \",\\\"\" $i\n\t\t\tset i [expr 0x$i]\n\t\t}\n\t\tset int1 [get_property CONFIG.interrupts $target_handle]\n\t\tset int2 [get_property CONFIG.interrupt-parent $target_handle]\n\t\tset int3 [get_property CONFIG.interrupt-names $target_handle]\n\t}\n\tset inhex [format %x $queue]\n\tappend queues \"/bits/ 16 <0x$inhex>\"\n\n\tset connected_ip [hsi::utils::get_connected_stream_ip $eth_ip \"tx_axis_res\"]\n\tif {[llength $connected_ip] != 0} {\n\t\tset end1_ip [hsi::utils::get_connected_stream_ip $connected_ip \"S00_AXIS\"]\n\t\tif {[llength $end1_ip] != 0} {\n\t\t\tset end1 [lappend end1 $end1_ip]\n\t\t} else {\n\t\t\tset connecttx_ip [lappend connecttx_ip $connected_ip]\n\t\t}\n\t}\n\tset connect_ip [hsi::utils::get_connected_stream_ip $eth_ip \"rx_axis_res\"]\n\tif {[llength $connect_ip] != 0} {\n\t\tset end_ip [hsi::utils::get_connected_stream_ip $connect_ip \"M00_AXIS\"]\n\t\tif {[llength $end_ip] != 0} {\n\t\t\tset end_point_ip [lappend end_point_ip $end_ip]\n\t\t} else {\n\t\t\tset connectrx_ip [lappend connectrx_ip $connect_ip]\n\t\t}\n\t}\n\n\tset connected_ip [hsi::utils::get_connected_stream_ip $eth_ip \"tx_axis_st\"]\n\tif {[llength $connected_ip] != 0} {\n\t\tset end1_ip [hsi::utils::get_connected_stream_ip $connected_ip \"S00_AXIS\"]\n\t\tif {[llength $end1_ip] != 0} {\n\t\t\tset end1 [lappend end1 $end1_ip]\n\t\t} else {\n\t\t\tset connecttx_ip [lappend connecttx_ip $connected_ip]\n\t\t}\n\t}\n\tset connect_ip [hsi::utils::get_connected_stream_ip $eth_ip \"rx_axis_st\"]\n\tif {[llength $connect_ip] != 0} {\n\t\tset end_ip [hsi::utils::get_connected_stream_ip $connect_ip \"M00_AXIS\"]\n\t\tif {[llength $end_ip] != 0} {\n\t\t\tset end_point_ip [lappend end_point_ip $end_ip]\n\t\t} else {\n\t\t\tset connectrx_ip [lappend connectrx_ip $connect_ip]\n\t\t}\n\t}\n\n\tset baseaddr [get_baseaddr $eth_ip no_prefix]\n\tset num_queues [get_property CONFIG.NUM_PRIORITIES $eth_ip]\n\tif {[string match -nocase $proc_type \"psu_cortexa53\"]} {\n\t\thsi::utils::add_new_dts_param $node \"#address-cells\" 2 int\n\t\thsi::utils::add_new_dts_param $node \"#size-cells\" 2 int\n\t\thsi::utils::add_new_dts_param \"${node}\" \"ranges\" \"\" boolean\n\t} elseif {[string match -nocase $proc_type \"ps7_cortexa9\"]} {\n\t\thsi::utils::add_new_dts_param $node \"#address-cells\" 1 int\n\t\thsi::utils::add_new_dts_param $node \"#size-cells\" 1 int\n\t\thsi::utils::add_new_dts_param \"${node}\" \"ranges\" \"\" boolean\n\t}\n\tset freq \"\"\n\tset clk [get_pins -of_objects $eth_ip \"S_AXI_ACLK\"]\n\tif {[llength $clk] } {\n\t\tset freq [get_property CLK_FREQ $clk]\n\t}\n\tset inhex [format %x $num_queues]\n\tappend numqueues \"/bits/ 16 <0x$inhex>\"\n\n\tset intr_val [get_property CONFIG.interrupts $drv_handle]\n\tset intr_parent [get_property CONFIG.interrupt-parent $drv_handle]\n\tset intr_names [get_property CONFIG.interrupt-names $drv_handle]\n\n\tset mac0intr \"\"\n\tset mac1intr \"\"\n\tset ep_sched_irq \"\"\n\tforeach intr1 $intr_names {\n\t\tset num [regexp -all -inline -- {[0-9]+} $intr1]\n\t\tif {$num == 1} {\n\t\t\tlappend mac0intr $intr1\n\t\t}\n\t\tif {$num == 2} {\n\t\t\tlappend mac1intr $intr1\n\t\t}\n\t\tif {[string match -nocase $intr1 \"interrupt_ptp_timer\"]} {\n\t\t\tlappend mac0intr $intr1\n\t\t}\n\t\tif {[string match -nocase $intr1 \"tsn_ep_scheduler_irq\"]} {\n\t\t\tlappend ep_sched_irq $intr1\n\t\t}\n\t}\n\tset switch_present \"\"\n\tset periph_list [get_cells -hier]\n set tsn_inst_name [get_cells -filter {IP_NAME =~ \"*tsn*\"}]\n\tforeach periph $periph_list {\n\t\tif {[string match -nocase \"${tsn_inst_name}_switch_core_top_0\" $periph] } {\n\t\t\tset switch_offset [get_property CONFIG.SWITCH_OFFSET $eth_ip]\n\t\t\tset high_addr [get_property CONFIG.C_HIGHADDR $eth_ip]\n\t\t\tset one 0x1\n\t\t\tset switch_present 0x1\n\t\t\tset switch_addr [format %08x [expr 0x$baseaddr + $switch_offset]]\n\t\t\tset switch_size [format %08x [expr $high_addr - 0x$switch_addr]]\n\t\t\tset switch_size [format %08x [expr 0x${switch_size} + 1]]\n\t\t\tgen_switch_node $periph $switch_addr $switch_size $numqueues $node $drv_handle $proc_type $eth_ip\n\t\t}\n\t\tif {[string match -nocase \"${tsn_inst_name}\" $periph] } {\n\t\t\tset baseaddr [get_baseaddr $eth_ip no_prefix]\n\t\t\tset tmac0_size [get_property CONFIG.TEMAC_1_SIZE $eth_ip]\n\t\t\tif { $switch_present != 1 } {\n\t\t\t\tgen_mac0_node $periph $baseaddr $tmac0_size $node $proc_type $drv_handle $numqueues $freq $intr_parent $mac0intr $eth_ip $queues $id $end1 $end_point_ip $connectrx_ip $connecttx_ip $tsn_inst_name\n\t\t\t} else {\n\t\t\t\tset end_point_ip \"\"\n\t\t\t\tset connectrx_ip \"\"\n\t\t\t\tset connecttx_ip \"\"\n\t\t\t\tgen_mac0_node $periph $baseaddr $tmac0_size $node $proc_type $drv_handle $numqueues $freq $intr_parent $mac0intr $eth_ip $queues $id $end1 $end_point_ip $connectrx_ip $connecttx_ip $tsn_inst_name\n\t\t\t}\n\t\t}\n\t\tif {[string match -nocase \"${tsn_inst_name}_tsn_temac_2\" $periph] } {\n\t\t\tset baseaddr [get_baseaddr $eth_ip no_prefix]\n\t\t\tset tmac1_offset [get_property CONFIG.TEMAC_2_OFFSET $eth_ip]\n\t\t\tset tmac1_size [get_property CONFIG.TEMAC_2_SIZE $eth_ip]\n\t\t\tset addr_off [format %08x [expr 0x$baseaddr + $tmac1_offset]]\n\t\t\tgen_mac1_node $periph $addr_off $tmac1_size $numqueues $intr_parent $node $drv_handle $proc_type $freq $eth_ip $mac1intr $baseaddr $queues $tsn_inst_name\n\t\t}\n\t\tif {[string match -nocase \"${tsn_inst_name}_tsn_endpoint_block_0\" $periph]} {\n\t\t\tset ep_offset [get_property CONFIG.EP_SCHEDULER_OFFSET $eth_ip]\n\t\t\tif {[llength $ep_offset] != 0} {\n\t\t\t\tset ep_addr [format %08x [expr 0x$baseaddr + $ep_offset]]\n\t\t\t\tset ep_size [get_property CONFIG.EP_SCHEDULER_SIZE $eth_ip]\n\t\t\t\tif { $switch_present == 1 } {\n\t\t\t\t\tgen_ep_node $periph $ep_addr $ep_size $numqueues $node $drv_handle $proc_type $ep_sched_irq $eth_ip $intr_parent $int3 $int1 $id $end1 $end_point_ip $connectrx_ip $connecttx_ip\n\t\t\t\t} else {\n\t\t\t\t\tset end_point_ip \"\"\n\t\t\t\t\tset connectrx_ip \"\"\n\t\t\t\t\tset connecttx_ip \"\"\n\t\t\t\t\tgen_ep_node $periph $ep_addr $ep_size $numqueues $node $drv_handle $proc_type $ep_sched_irq $eth_ip $intr_parent $int3 $int1 $id $end1 $end_point_ip $connectrx_ip $connecttx_ip\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc get_checksum {value} {\n\tif {[string compare -nocase $value \"None\"] == 0} {\n\t\tset value 0\n\t} elseif {[string compare -nocase $value \"Partial\"] == 0} {\n\t\tset value 1\n\t} else {\n\t\tset value 2\n\t}\n\treturn $value\n}\n\nproc get_phytype {value} {\n\tif {[string compare -nocase $value \"MII\"] == 0} {\n\t\tset value 0\n\t} elseif {[string compare -nocase $value \"GMII\"] == 0} {\n\t\tset value 1\n\t} elseif {[string compare -nocase $value \"RGMII\"] == 0} {\n\t\tset value 3\n\t} elseif {[string compare -nocase $value \"SGMII\"] == 0} {\n\t\tset value 4\n\t} else {\n\t\tset value 5\n\t}\n\treturn $value\n}\n\nproc pcspma_phy_node {slave tsn_inst_name} {\n\tset phyaddr [get_property CONFIG.PHYADDR $slave]\n\tset phyaddr [::hsi::utils::convert_binary_to_decimal $phyaddr]\n\tif {[string match -nocase $slave \"${tsn_inst_name}_tsn_temac_2\"]} {\n\t\tset phyaddr \"2\"\n\t} else {\n\t\tset phyaddr \"1\"\n\t}\n\tset phymode \"phy$phyaddr\"\n\treturn \"$phyaddr $phymode\"\n}\n\nproc gen_phy_node args {\n\tset mdio_node [lindex $args 0]\n\tset phy_name [lindex $args 1]\n\tset phya [lindex $args 2]\n\n\tset phy_node [add_or_get_dt_node -l ${phy_name} -n phy -u $phya -p $mdio_node]\n\thsi::utils::add_new_dts_param \"${phy_node}\" \"reg\" 0 int\n\thsi::utils::add_new_dts_param \"${phy_node}\" \"device_type\" \"ethernet-phy\" string\n\thsi::utils::add_new_dts_param \"${phy_node}\" \"compatible\" \"marvell,88e1111\" string\n\treturn $phy_node\n}\n\nproc gen_ep_node {periph ep_addr ep_size numqueues parent_node drv_handle proc_type ep_sched_irq eth_ip intr_parent int3 int1 id end1 end_point_ip connectrx_ip connecttx_ip} {\n\tglobal tsn_ep_node\n\tset ep_node [add_or_get_dt_node -n \"tsn_ep\" -l $tsn_ep_node -u $ep_addr -p $parent_node]\n\tif {[string match -nocase $proc_type \"ps7_cortexa9\"]} {\n\t\tset ep_reg \"0x$ep_addr $ep_size\"\n\t} else {\n\t\tset ep_reg \"0x0 0x$ep_addr 0x0 $ep_size\"\n\t}\n\tforeach intr $int3 {\n\t\tlappend ep_sched_irq $intr\n\t}\n\tif {[llength $ep_sched_irq] != 0} {\n\t\tset intr_num [get_intr_id $eth_ip [lindex $ep_sched_irq 0]]\n\t}\n\tforeach int $int1 {\n\t\tlappend intr_num $int\n\t}\n\thsi::utils::add_new_dts_param \"${ep_node}\" \"interrupt-names\" $ep_sched_irq stringlist\n\thsi::utils::add_new_dts_param ${ep_node} \"interrupts\" $intr_num intlist\n\thsi::utils::add_new_dts_param \"${ep_node}\" \"interrupt-parent\" $intr_parent reference\n\n\thsi::utils::add_new_dts_param \"${ep_node}\" \"reg\" $ep_reg int\n\thsi::utils::add_new_dts_param \"${ep_node}\" \"compatible\" \"xlnx,tsn-ep\" string\n\thsi::utils::add_new_dts_param \"${ep_node}\" \"xlnx,num-tc\" $numqueues noformating\n\thsi::utils::add_new_dts_param \"${ep_node}\" \"xlnx,channel-ids\" $id string\n\tset mac_addr \"00 0A 35 00 01 05\"\n\thsi::utils::add_new_dts_param $ep_node \"local-mac-address\" ${mac_addr} bytelist\n\thsi::utils::add_new_dts_param \"$ep_node\" \"xlnx,eth-hasnobuf\" \"\" boolean\n\tglobal tsn_ex_ep_node\n\tset tsn_ex_ep [get_property CONFIG.EN_EP_PORT_EXTN $eth_ip]\n\tif {[string match -nocase $tsn_ex_ep \"true\"]} {\n\t\tset tsn_ex_ep_node [add_or_get_dt_node -n \"tsn_ex_ep\" -l $tsn_ex_ep_node -p $parent_node]\n\t\thsi::utils::add_new_dts_param \"${tsn_ex_ep_node}\" \"compatible\" \"xlnx,tsn-ex-ep\" string\n\t\tset mac_addr \"00 0A 35 00 01 06\"\n\t\tset en_pkt_switch [get_property CONFIG.EN_EP_PKT_SWITCH $eth_ip]\n\t\tif {[string match -nocase $en_pkt_switch \"true\"]} {\n\t\t\t\thsi::utils::add_new_dts_param \"$tsn_ex_ep_node\" \"packet-switch\" 1 int\n\t\t}\n\t\thsi::utils::add_new_dts_param $tsn_ex_ep_node \"local-mac-address\" ${mac_addr} bytelist\n\t\thsi::utils::add_new_dts_param \"$tsn_ex_ep_node\" \"tsn,endpoint\" $tsn_ep_node reference\n\t}\n\n\tset len [llength $end1]\n\tswitch $len {\n\t\t\"1\" {\n\t\t\tset ref_id [lindex $end1 0]\n\t\t\thsi::utils::add_new_dts_param \"${ep_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t\t\"2\" {\n\t\t\tset ref_id [lindex $end1 0]\n\t\t\tappend ref_id \">, <&[lindex $end1 1]\"\n\t\t\thsi::utils::add_new_dts_param \"${ep_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t\t\"3\" {\n\t\t\tset ref_id [lindex $end1 0]\n\t\t\tappend ref_id \">, <&[lindex $end1 1]>, <&[lindex $end1 2]\"\n\t\t\thsi::utils::add_new_dts_param \"${ep_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t}\n\tset len3 [llength $connecttx_ip]\n\tswitch $len3 {\n\t\t\"1\" {\n\t\t\tset ref_id [lindex $connecttx_ip 0]\n\t\t\thsi::utils::add_new_dts_param \"${ep_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t\t\"2\" {\n\t\t\tset ref_id [lindex $connecttx_ip 0]\n\t\t\tappend ref_id \">, <&[lindex $connecttx_ip 1]\"\n\t\t\thsi::utils::add_new_dts_param \"${ep_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t\t\"3\" {\n\t\t\tset ref_id [lindex $connecttx_ip 0]\n\t\t\tappend ref_id \">, <&[lindex $connecttx_ip 1]>, <&[lindex $connecttx_ip 2]\"\n\t\t\thsi::utils::add_new_dts_param \"${ep_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t}\n\tif {$len && $len3} {\n\t\tif {$len == 1} {\n\t\t\tset ref_id [lindex $end1 0]\n\t\t\tappend ref_id \">, <&[lindex $connecttx_ip 1]>, <&[lindex $connecttx_ip 2]\"\n\t\t\thsi::utils::add_new_dts_param \"${ep_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t\tif {$len == 2} {\n\t\t\tset ref_id [lindex $end1 0]\n\t\t\tappend ref_id \">, <&[lindex $end1 1]>, <&[lindex $connecttx_ip 0]\"\n\t\t\thsi::utils::add_new_dts_param \"${ep_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t}\n\n\tset len1 [llength $end_point_ip]\n\tswitch $len1 {\n\t\t\"1\" {\n\t\t\tset ref_id [lindex $end_point_ip 0]\n\t\t\thsi::utils::add_new_dts_param \"${ep_node}\" \"axistream-connected-rx\" \"$ref_id\" reference\n\t\t}\n\t\t\"2\" {\n\t\t\tset ref_id [lindex $end_point_ip 0]\n\t\t\tappend ref_id \">, <&[lindex $end_point_ip 1]\"\n\t\t\thsi::utils::add_new_dts_param \"${ep_node}\" \"axistream-connected-rx\" \"$ref_id\" reference\n\t\t}\n\t\t\"3\" {\n\t\t\tset ref_id [lindex $end_point_ip 0]\n\t\t\tappend ref_id \">, <&[lindex $end_point_ip 1]>, <&[lindex $end_point_ip 2]\"\n\t\t\thsi::utils::add_new_dts_param \"${ep_node}\" \"axistream-connected-rx\" \"$ref_id\" reference\n\t\t}\n\t}\n\tset len2 [llength $connectrx_ip]\n\tswitch $len2 {\n\t\t\"1\" {\n\t\t\tset ref_id [lindex $connectrx_ip 0]\n\t\t\thsi::utils::add_new_dts_param \"${ep_node}\" \"axistream-connected-rx\" \"$ref_id\" reference\n\t\t}\n\t\t\"2\" {\n\t\t\tset ref_id [lindex $connectrx_ip 0]\n\t\t\tappend ref_id \">, <&[lindex $connectrx_ip 1]\"\n\t\t\thsi::utils::add_new_dts_param \"${ep_node}\" \"axistream-connected-rx\" \"$ref_id\" reference\n\t\t}\n\t\t\"3\" {\n\t\t\tset ref_id [lindex $connectrx_ip 0]\n\t\t\tappend ref_id \">, <&[lindex $connectrx_ip 1]>, <&[lindex $connectrx_ip 2]\"\n\t\t\thsi::utils::add_new_dts_param \"${ep_node}\" \"axistream-connected-rx\" \"$ref_id\" reference\n\t\t}\n\t}\n}\n\nproc gen_switch_node {periph addr size numqueues parent_node drv_handle proc_type eth_ip} {\n\tset switch_node [add_or_get_dt_node -n \"tsn_switch\" -l epswitch -u $addr -p $parent_node]\n\tset hwaddr_learn [get_property CONFIG.EN_HW_ADDR_LEARNING $eth_ip]\n\tset mgmt_tag [get_property CONFIG.EN_INBAND_MGMT_TAG $eth_ip]\n\tif {[string match -nocase $proc_type \"ps7_cortexa9\"]} {\n\t\tset switch_reg \"0x$addr 0x$size\"\n\t} else {\n\t\tset switch_reg \"0x0 0x$addr 0x0 0x$size\"\n\t}\n\thsi::utils::add_new_dts_param \"${switch_node}\" \"reg\" $switch_reg int\n\thsi::utils::add_new_dts_param \"${switch_node}\" \"compatible\" \"xlnx,tsn-switch\" string\n\thsi::utils::add_new_dts_param \"${switch_node}\" \"xlnx,num-tc\" $numqueues noformating\n\tif {[string match -nocase $hwaddr_learn \"true\"]} {\n\t\thsi::utils::add_new_dts_param \"${switch_node}\" \"xlnx,has-hwaddr-learning\" \"\" boolean\n\t}\n\tif {[string match -nocase $mgmt_tag \"true\"]} {\n\t\thsi::utils::add_new_dts_param \"${switch_node}\" \"xlnx,has-inband-mgmt-tag\" \"\" boolean\n\t}\n\tset inhex [format %x 3]\n\tappend numports \"/bits/ 16 <0x$inhex>\"\n\thsi::utils::add_new_dts_param \"${switch_node}\" \"xlnx,num-ports\" $numports noformating\n\tglobal tsn_ep_node\n\tglobal tsn_emac0_node\n\tglobal tsn_emac1_node\n\tset end1 \"\"\n\tset end1 [lappend end1 $tsn_ep_node]\n\tset end1 [lappend end1 $tsn_emac0_node]\n\tset end1 [lappend end1 $tsn_emac1_node]\n\tset len [llength $end1]\n switch $len {\n \"1\" {\n set ref_id [lindex $end1 0]\n hsi::utils::add_new_dts_param \"${switch_node}\" \"ports\" \"$ref_id\" reference\n }\n \"2\" {\n set ref_id [lindex $end1 0]\n append ref_id \">, <&[lindex $end1 1]\"\n hsi::utils::add_new_dts_param \"${switch_node}\" \"ports\" \"$ref_id\" reference\n }\n \"3\" {\n set ref_id [lindex $end1 0]\n append ref_id \">, <&[lindex $end1 1]>, <&[lindex $end1 2]\"\n hsi::utils::add_new_dts_param \"${switch_node}\" \"ports\" \"$ref_id\" reference\n }\n }\n\n}\n\nproc gen_mac0_node {periph addr size parent_node proc_type drv_handle numqueues freq intr_parent mac0intr eth_ip queues id end1 end_point_ip connectrx_ip connecttx_ip tsn_inst_name} {\n\tglobal tsn_emac0_node\n\tset tsn_mac_node [add_or_get_dt_node -n \"tsn_emac_0\" -l $tsn_emac0_node -u $addr -p $parent_node]\n\tif {[string match -nocase $proc_type \"ps7_cortexa9\"]} {\n\t\tset tsnreg \"0x$addr $size\"\n\t} else {\n\t\tset tsnreg \"0x0 0x$addr 0x0 $size\"\n\t}\n\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"reg\" $tsnreg int\n\tset tsn_comp \"xlnx,tsn-ethernet-1.00.a\"\n\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"compatible\" $tsn_comp stringlist\n\tset mdionode [add_or_get_dt_node -l ${drv_handle}_mdio0 -n mdio -p $tsn_mac_node]\n\thsi::utils::add_new_dts_param \"${mdionode}\" \"#address-cells\" 1 int \"\"\n\thsi::utils::add_new_dts_param \"${mdionode}\" \"#size-cells\" 0 int \"\"\n\tset phytype [string tolower [get_property CONFIG.PHYSICAL_INTERFACE $periph]]\n\tset txcsum \"0\"\n\tset rxcsum \"0\"\n\tset mac_addr \"00 0A 35 00 01 0e\"\n\tset phy_type [get_phytype $phytype]\n\tset qbv_offset [get_property CONFIG.TEMAC_1_SCHEDULER_OFFSET $periph]\n\tset qbv_size [get_property CONFIG.TEMAC_1_SCHEDULER_SIZE $periph]\n\thsi::utils::add_new_dts_param $tsn_mac_node \"local-mac-address\" ${mac_addr} bytelist\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,txsum\" $txcsum int\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,rxsum\" $rxcsum int\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,tsn\" \"\" boolean\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,eth-hasnobuf\" \"\" boolean\n\tset phymode $phytype\n\tif {$phytype == \"rgmii\"} {\n\t\tset phymode \"rgmii-id\"\n\t}\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"phy-mode\" $phymode string\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,num-tc\" $numqueues noformating\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,channel-ids\" $id string\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,num-queues\" $queues noformating\n\tglobal tsn_ep_node\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"tsn,endpoint\" $tsn_ep_node reference\n\tif {[llength $qbv_offset] != 0} {\n\t\tset qbv_addr 0x[format %08x [expr 0x$addr + $qbv_offset]]\n\t\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,qbv-addr\" $qbv_addr int\n\t\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,qbv-size\" $qbv_size int\n\t}\n\tset intr_len [llength $mac0intr]\n\tfor {set i 0} {$i < $intr_len} {incr i} {\n\t\tlappend intr [lindex $mac0intr $i]\n\t\tlappend intr_num [get_intr_id $eth_ip [lindex $mac0intr $i]]\n\t}\n\tregsub -all \"\\{||\\t\" $intr_num {} intr_num\n\tregsub -all \"\\}||\\t\" $intr_num {} intr_num\n\thsi::utils::add_new_dts_param $tsn_mac_node \"interrupts\" $intr_num intlist\n\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"interrupt-parent\" $intr_parent reference\n\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"interrupt-names\" $mac0intr stringlist\n\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"clock-frequency\" $freq int\n\tif {$phytype == \"rgmii\" || $phytype == \"gmii\"} {\n\t\tset phynode [pcspma_phy_node $periph $tsn_inst_name]\n\t\tset phya [lindex $phynode 0]\n\t\tif { $phya != \"-1\"} {\n\t\t\tset phy_name \"[lindex $phynode 1]\"\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"phy-handle\" $phy_name reference\n\t\t\tgen_phy_node $mdionode $phy_name $phya\n\t\t}\n\t}\n\tset len [llength $end1]\n\tswitch $len {\n\t\t\"1\" {\n\t\t\tset ref_id [lindex $end1 0]\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t\t\"2\" {\n\t\t\tset ref_id [lindex $end1 0]\n\t\t\tappend ref_id \">, <&[lindex $end1 1]\"\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t\t\"3\" {\n\t\t\tset ref_id [lindex $end1 0]\n\t\t\tappend ref_id \">, <&[lindex $end1 1]>, <&[lindex $end1 2]\"\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t}\n\tset len3 [llength $connecttx_ip]\n\tswitch $len3 {\n\t\t\"1\" {\n\t\t\tset ref_id [lindex $connecttx_ip 0]\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t\t\"2\" {\n\t\t\tset ref_id [lindex $connecttx_ip 0]\n\t\t\tappend ref_id \">, <&[lindex $connecttx_ip 1]\"\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t\t\"3\" {\n\t\t\tset ref_id [lindex $connecttx_ip 0]\n\t\t\tappend ref_id \">, <&[lindex $connecttx_ip 1]>, <&[lindex $connecttx_ip 2]\"\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t}\n\tif {$len && $len3} {\n\t\tif {$len == 1} {\n\t\t\tset ref_id [lindex $end1 0]\n\t\t\tappend ref_id \">, <&[lindex $connecttx_ip 1]>, <&[lindex $connecttx_ip 2]\"\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t\tif {$len == 2} {\n\t\t\tset ref_id [lindex $end1 0]\n\t\t\tappend ref_id \">, <&[lindex $end1 1]>, <&[lindex $connecttx_ip 0]\"\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"axistream-connected-tx\" \"$ref_id\" reference\n\t\t}\n\t}\n\n\tset len1 [llength $end_point_ip]\n\tswitch $len1 {\n\t\t\"1\" {\n\t\t\tset ref_id [lindex $end_point_ip 0]\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"axistream-connected-rx\" \"$ref_id\" reference\n\t\t}\n\t\t\"2\" {\n\t\t\tset ref_id [lindex $end_point_ip 0]\n\t\t\tappend ref_id \">, <&[lindex $end_point_ip 1]\"\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"axistream-connected-rx\" \"$ref_id\" reference\n\t\t}\n\t\t\"3\" {\n\t\t\tset ref_id [lindex $end_point_ip 0]\n\t\t\tappend ref_id \">, <&[lindex $end_point_ip 1]>, <&[lindex $end_point_ip 2]\"\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"axistream-connected-rx\" \"$ref_id\" reference\n\t\t}\n\t}\n\tset len2 [llength $connectrx_ip]\n\tswitch $len2 {\n\t\t\"1\" {\n\t\t\tset ref_id [lindex $connectrx_ip 0]\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"axistream-connected-rx\" \"$ref_id\" reference\n\t\t}\n\t\t\"2\" {\n\t\t\tset ref_id [lindex $connectrx_ip 0]\n\t\t\tappend ref_id \">, <&[lindex $connectrx_ip 1]\"\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"axistream-connected-rx\" \"$ref_id\" reference\n\t\t}\n\t\t\"3\" {\n\t\t\tset ref_id [lindex $connectrx_ip 0]\n\t\t\tappend ref_id \">, <&[lindex $connectrx_ip 1]>, <&[lindex $connectrx_ip 2]\"\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"axistream-connected-rx\" \"$ref_id\" reference\n\t\t}\n\t}\n}\n\nproc gen_mac1_node {periph addr size numqueues intr_parent parent_node drv_handle proc_type freq eth_ip mac1intr baseaddr queues tsn_inst_name} {\n\tglobal tsn_emac1_node\n\tset tsn_mac_node [add_or_get_dt_node -n \"tsn_emac_1\" -l $tsn_emac1_node -u $addr -p $parent_node]\n\tif {[string match -nocase $proc_type \"ps7_cortexa9\"]} {\n\t\tset tsn_reg \"0x$addr $size\"\n\t} else {\n\t\tset tsn_reg \"0x0 0x$addr 0x0 $size\"\n\t}\n\tset tsn_comp \"xlnx,tsn-ethernet-1.00.a\"\n\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"reg\" $tsn_reg int\n\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"compatible\" $tsn_comp stringlist\n\tset mdionode [add_or_get_dt_node -l ${drv_handle}_mdio1 -n mdio -p $tsn_mac_node]\n\thsi::utils::add_new_dts_param \"${mdionode}\" \"#address-cells\" 1 int \"\"\n\thsi::utils::add_new_dts_param \"${mdionode}\" \"#size-cells\" 0 int \"\"\n\tset tsn_emac2_ip [get_property IP_NAME $periph]\n\tset tsn_ip [get_cells -hier -filter {IP_NAME == $tsn_emac2_ip}]\n\tset phytype [string tolower [get_property CONFIG.Physical_Interface $periph]]\n\tset txcsum \"0\"\n\tset rxcsum \"0\"\n\tset mac_addr \"00 0A 35 00 01 0f\"\n\tset phy_type [get_phytype $phytype]\n\tset qbv_offset [get_property CONFIG.TEMAC_2_SCHEDULER_OFFSET $eth_ip]\n\tset qbv_size [get_property CONFIG.TEMAC_2_SCHEDULER_SIZE $eth_ip]\n\thsi::utils::add_new_dts_param $tsn_mac_node \"local-mac-address\" ${mac_addr} bytelist\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,txsum\" $txcsum int\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,rxsum\" $rxcsum int\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,tsn\" \"\" boolean\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,tsn-slave\" \"\" boolean\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,eth-hasnobuf\" \"\" boolean\n\tset phymode $phytype\n\tif {$phytype == \"rgmii\"} {\n\t\tset phymode \"rgmii-id\"\n\t}\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"phy-mode\" $phymode string\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,num-tc\" $numqueues noformating\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,num-queues\" $queues noformating\n\tglobal tsn_ep_node\n\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"tsn,endpoint\" $tsn_ep_node reference\n\tif {[llength $qbv_offset] != 0} {\n\t\tset qbv_addr 0x[format %08x [expr 0x$baseaddr + $qbv_offset]]\n\t\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,qbv-addr\" $qbv_addr int\n\t\thsi::utils::add_new_dts_param \"$tsn_mac_node\" \"xlnx,qbv-size\" $qbv_size int\n\t}\n\tset intr_len [llength $mac1intr]\n\tfor {set i 0} {$i < $intr_len} {incr i} {\n\t\tlappend intr [lindex $mac1intr $i]\n\t\tlappend intr_num [get_intr_id $eth_ip [lindex $mac1intr $i]]\n\t}\n\tregsub -all \"\\{||\\t\" $intr_num {} intr_num\n\tregsub -all \"\\}||\\t\" $intr_num {} intr_num\n\thsi::utils::add_new_dts_param $tsn_mac_node \"interrupts\" $intr_num intlist\n\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"interrupt-parent\" $intr_parent reference\n\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"interrupt-names\" $mac1intr stringlist\n\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"clock-frequency\" $freq int\n\tif {$phytype == \"rgmii\" || $phytype == \"gmii\"} {\n\t\tset phynode [pcspma_phy_node $periph $tsn_inst_name]\n\t\tset phya [lindex $phynode 0]\n\t\tif { $phya != \"-1\"} {\n\t\t\tset phy_name \"[lindex $phynode 1]\"\n\t\t\thsi::utils::add_new_dts_param \"${tsn_mac_node}\" \"phy-handle\" $phy_name reference\n\t\t\tgen_phy_node $mdionode $phy_name $phya\n\t\t}\n\t}\n}\n" }, { "path": "ttcps/data/ttcps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver ttcps\n\n OPTION supported_peripherals = (ps7_ttc psu_ttc psv_ttc psx_ttc);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = ttcps;\n\nEND driver\n" }, { "path": "ttcps/data/ttcps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n" }, { "path": "uartlite/data/uartlite.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver uartlite\n\n OPTION supported_peripherals = (mdm axi_uartlite);\n OPTION driver_state = ACTIVE;\n OPTION supported_os_types = (DTS);\n OPTION NAME = uartlite;\n PARAMETER name = dev_type, default = \"serial\", type = string;\n DTGPARAM name = dtg.ip_params, type = boolean;\n DTGPARAM name = dtg.alias, type = string, default = serial;\n DTGPARAM name = port-number, type = int, default = 0;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,xps-uartlite-1.00.a\";\n DTGPARAM name = device_type, type = string, default = serial;\n\nEND driver\n" }, { "path": "uartlite/data/uartlite.tcl", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n # try to source the common tcl procs\n # assuming the order of return is based on repo priority\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n set compatible [get_comp_str $drv_handle]\n set compatible [append compatible \" \" \"xlnx,xps-uartlite-1.00.a\"]\n set_drv_prop $drv_handle compatible \"$compatible\" stringlist\n set config_baud [get_property CONFIG.dt_setbaud [get_os]]\n set ip [get_cells -hier $drv_handle]\n set consoleip [get_property CONFIG.console_device [get_os]]\n if { [string match -nocase $consoleip $ip] } {\n set ip_type [get_property IP_NAME $ip]\n\tif {!$config_baud} {\n\t\tif { [string match -nocase $ip_type] } {\n\t\t\thsi::utils::set_os_parameter_value \"console\" \"ttyUL0,115200\"\n\t\t} else {\n\t\t\thsi::utils::set_os_parameter_value \"console\" \"ttyUL0,[hsi::utils::get_ip_param_value $ip C_BAUDRATE]\"\n\t\t}\n\t} else {\n\t\thsi::utils::set_os_parameter_value \"console\" \"ttyUL0,$config_baud\"\n\t}\n }\n\n set_drv_conf_prop $drv_handle C_BAUDRATE current-speed int\n set proc_type [get_sw_proc_prop IP_NAME]\n switch $proc_type {\n \"microblaze\" {\n gen_dev_ccf_binding $drv_handle \"s_axi_aclk\"\n\t }\n }\n}\n" }, { "path": "uartns/data/uartns.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver uartns\n\n OPTION supported_peripherals = (axi_uart16550);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = uartns;\n PARAMETER name = dev_type, default = \"serial\", type = string;\n DTGPARAM name = dtg.ip_params, type = boolean;\n DTGPARAM name = compatible, type = stringlist, default = \"xlnx,xps-uart16550-2.00.a ns16550a\";\n DTGPARAM name = current-speed, type = int, default = 115200;\n DTGPARAM name = device_type, type = string, default = serial;\n DTGPARAM name = dtg.alias, type = string, default = serial;\n DTGPARAM name = reg-offset, type = hexint, default = 0x1000;\n DTGPARAM name = reg-shift, type = int, default = 2;\n DTGPARAM name = clock-frequency, type = int, default = 100000000;\n DTGPARAM name = port-number, type = int, default = 0;\n\nEND driver\n" }, { "path": "uartns/data/uartns.tcl", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n # try to source the common tcl procs\n # assuming the order of return is based on repo priority\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n\n set ip [get_cells -hier $drv_handle]\n set has_xin [hsi::utils::get_ip_param_value $ip C_HAS_EXTERNAL_XIN]\n set clock_port \"S_AXI_ACLK\"\n if { [string match -nocase \"$has_xin\" \"1\"] } {\n set_drv_conf_prop $drv_handle C_EXTERNAL_XIN_CLK_HZ clock-frequency\n # TODO: update the clock-names and clocks properties and create a\n # fixed clock node. Currently this is causing any issue as the\n # driver only uses clock-frequency property\n\n } else {\n set freq [hsi::utils::get_clk_pin_freq $ip \"$clock_port\"]\n set_property clock-frequency $freq $drv_handle\n }\n\n set consoleip [get_property CONFIG.console_device [get_os]]\n if { [string match -nocase $consoleip $ip] } {\n hsi::utils::set_os_parameter_value \"console\" \"ttyS0,115200\"\n }\n\n set proc_type [get_sw_proc_prop IP_NAME]\n switch $proc_type {\n \"microblaze\" {\n gen_dev_ccf_binding $drv_handle \"s_axi_aclk\"\n }\n }\n}\n" }, { "path": "uartps/data/uartps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver uartps\n\n OPTION supported_peripherals = (ps7_uart psu_uart psu_sbsauart psv_uart psv_sbsauart psx_sbsauart);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = uartps;\n DTGPARAM name = device_type , type = string, default = serial;\n DTGPARAM name = dtg.alias, type = string, default = serial;\n DTGPARAM name = port-number, type = int, default = 0;\n\nEND driver\n" }, { "path": "uartps/data/uartps.tcl", "content": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# Michal SIMEK \n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n set ip [get_cells -hier $drv_handle]\n set consoleip [get_property CONFIG.console_device [get_os]]\n set config_baud [get_property CONFIG.dt_setbaud [get_os]]\n\n set port_number 0\n if {[string match -nocase \"$ip\" \"$consoleip\"] == 0} {\n set serial_count [hsi::utils::get_os_parameter_value \"serial_count\"]\n if { [llength $serial_count] == 0 } {\n set serial_count 0\n }\n incr serial_count\n hsi::utils::set_os_parameter_value \"serial_count\" $serial_count\n set port_number $serial_count\n } else {\n #adding os console property if this is console ip\n set avail_param [list_property [get_cells -hier $drv_handle]]\n # This check is needed because BAUDRATE parameter for psuart is available from\n # 2017.1 onwards\n if {[lsearch -nocase $avail_param \"CONFIG.C_BAUDRATE\"] >= 0} {\n set baud [get_property CONFIG.C_BAUDRATE [get_cells -hier $drv_handle]]\n } else {\n set baud \"115200\"\n }\n\tif {$config_baud} {\n\t\thsi::utils::set_os_parameter_value \"console\" \"ttyPS0,$config_baud\"\n\t\tif {[string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\tset_drv_prop $drv_handle \"current-speed\" $config_baud int\n\t\t}\n\t} else {\n\t\thsi::utils::set_os_parameter_value \"console\" \"ttyPS0,$baud\"\n\t\tif {[string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t\tset_drv_prop $drv_handle \"current-speed\" $baud int\n\t\t}\n\t}\n }\n set_property CONFIG.port-number $port_number $drv_handle\n set uboot_prop [get_property IP_NAME [get_cells -hier $drv_handle]]\n if {[string match -nocase $uboot_prop \"psu_uart\"] || [string match -nocase $uboot_prop \"psu_sbsauart\"]} {\n set_drv_prop $drv_handle \"u-boot,dm-pre-reloc\" \"\" boolean\n }\n set has_modem [get_property CONFIG.C_HAS_MODEM [get_cells -hier $drv_handle]]\n if {$has_modem == 0} {\n hsi::utils::add_new_property $drv_handle \"cts-override\" boolean \"\"\n }\n}\n" }, { "path": "usbps/data/usbps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver usbps\n\n OPTION supported_peripherals = (ps7_usb psu_usb_xhci psv_usb_xhci psx_usb_xhci);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = usbps;\n\nEND driver\n" }, { "path": "usbps/data/usbps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n foreach i [get_sw_cores device_tree] {\n set common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n if {[file exists $common_tcl_file]} {\n source $common_tcl_file\n break\n }\n }\n ps7_reset_handle $drv_handle CONFIG.C_USB_RESET CONFIG.usb-reset\n set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]\n set default_dts [set_drv_def_dts $drv_handle]\n if {[string match -nocase $proctype \"ps7_cortexa9\"] } {\n set_drv_prop $drv_handle phy_type ulpi string\n } else {\n\tset mainline_ker [get_property CONFIG.mainline_kernel [get_os]]\n\tif {[string match -nocase $proctype \"psv_cortexa72\"] || [string match -nocase $proctype \"psx_cortexa78\"]} {\n\t\t#TODO:Remove this once the versal dts is fully updated.\n\t\treturn\n\t}\n\tif {[string match -nocase $mainline_ker \"none\"]} {\n set index [string index $drv_handle end]\n set rt_node [add_or_get_dt_node -n usb -l usb$index -d $default_dts -auto_ref_parent]\n hsi::utils::add_new_dts_param \"${rt_node}\" \"status\" \"okay\" string\n }\n }\n}\n" }, { "path": "vid_phy_ctrl/data/vid_phy_ctrl.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver vid_phy_ctrl\n\n OPTION supported_peripherals = (vid_phy_controller);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = vid_phy_ctrl;\n\nEND driver\n" }, { "path": "vid_phy_ctrl/data/vid_phy_ctrl.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,vid-phy-controller-2.1\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset input_pixels_per_clock [get_property CONFIG.C_INPUT_PIXELS_PER_CLOCK [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,input-pixels-per-clock\" $input_pixels_per_clock int\n\tset nidru [get_property CONFIG.C_NIDRU [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,nidru\" $nidru int\n\tset nidru_refclk_sel [get_property CONFIG.C_NIDRU_REFCLK_SEL [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,nidru-refclk-sel\" $nidru_refclk_sel int\n\tset Rx_No_Of_Channels [get_property CONFIG.C_Rx_No_Of_Channels [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,rx-no-of-channels\" $Rx_No_Of_Channels int\n\tset rx_pll_selection [get_property CONFIG.C_RX_PLL_SELECTION [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,rx-pll-selection\" $rx_pll_selection int\n\tset rx_protocol [get_property CONFIG.C_Rx_Protocol [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,rx-protocol\" $rx_protocol int\n\tset rx_refclk_sel [get_property CONFIG.C_RX_REFCLK_SEL [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,rx-refclk-sel\" $rx_refclk_sel int\n\tset tx_no_of_channels [get_property CONFIG.C_Tx_No_Of_Channels [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,tx-no-of-channels\" $tx_no_of_channels int\n\tset tx_pll_selection [get_property CONFIG.C_TX_PLL_SELECTION [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,tx-pll-selection\" $tx_pll_selection int\n\tset tx_protocol [get_property CONFIG.C_Tx_Protocol [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,tx-protocol\" $tx_protocol int\n\tset tx_refclk_sel [get_property CONFIG.C_TX_REFCLK_SEL [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,tx-refclk-sel\" $tx_refclk_sel int\n\tset hdmi_fast_switch [get_property CONFIG.C_Hdmi_Fast_Switch [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,hdmi-fast-switch\" $hdmi_fast_switch int\n\tset tx_buffer_bypass [get_property CONFIG.Tx_Buffer_Bypass [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,tx-buffer-bypass\" $tx_buffer_bypass int\n\tset transceiver_width [get_property CONFIG.Transceiver_Width [get_cells -hier $drv_handle]]\n\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,transceiver-width\" $transceiver_width int\n\tset use_gt_ch4_hdmi [get_property CONFIG.C_Use_GT_CH4_HDMI [get_cells -hier $drv_handle]]\n\tif {[llength $use_gt_ch4_hdmi]} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,use-gt-ch4-hdmi\" $use_gt_ch4_hdmi int\n\t}\n\tfor {set ch 0} {$ch < $Rx_No_Of_Channels} {incr ch} {\n\t\tset rxpinname \"vid_phy_rx_axi4s_ch$ch\"\n\t\tset channelip [get_connected_stream_ip [get_cells -hier $drv_handle] $rxpinname]\n\t\tif {[llength $channelip] && [llength [hsi::utils::get_ip_mem_ranges $channelip]]} {\n\t\t\tset phy_node [add_or_get_dt_node -n \"${rxpinname}${channelip}\" -l ${drv_handle}rxphy_lane${ch} -p $node]\n\t\t\thsi::utils::add_new_dts_param \"$phy_node\" \"#phy-cells\" 4 int\n\t\t}\n\t}\n\tfor {set ch 0} {$ch < $tx_no_of_channels} {incr ch} {\n\t\tset txpinname \"vid_phy_tx_axi4s_ch$ch\"\n\t\tset channelip [get_connected_stream_ip [get_cells -hier $drv_handle] $txpinname]\n\t\tif {[llength $channelip] && [llength [hsi::utils::get_ip_mem_ranges $channelip]]} {\n\t\t\tset phy_node [add_or_get_dt_node -n \"${txpinname}${channelip}\" -l ${drv_handle}txphy_lane${ch} -p $node]\n\t\t\thsi::utils::add_new_dts_param \"$phy_node\" \"#phy-cells\" 4 int\n\t\t}\n\t}\n\tset transceiver [get_property CONFIG.Transceiver [get_cells -hier $drv_handle]]\n\tswitch $transceiver {\n\t\t\t\"GTXE2\" {\n\t\t\t hsi::utils::add_new_dts_param \"${node}\" \"xlnx,transceiver-type\" 1 int\n\t\t\t}\n\t\t\t\"GTHE2\" {\n\t\t\t hsi::utils::add_new_dts_param \"${node}\" \"xlnx,transceiver-type\" 2 int\n\t\t\t}\n\t\t\t\"GTPE2\" {\n\t\t\t hsi::utils::add_new_dts_param \"${node}\" \"xlnx,transceiver-type\" 3 int\n\t\t\t}\n\t\t\t\"GTHE3\" {\n\t\t\t hsi::utils::add_new_dts_param \"${node}\" \"xlnx,transceiver-type\" 4 int\n\t\t\t}\n\t\t\t\"GTHE4\" {\n\t\t\t hsi::utils::add_new_dts_param \"${node}\" \"xlnx,transceiver-type\" 5 int\n\t\t\t}\n\t\t\t\"GTHE5\" {\n\t\t\t hsi::utils::add_new_dts_param \"${node}\" \"xlnx,transceiver-type\" 6 int\n\t\t\t}\n\t}\n}\n" }, { "path": "vproc_ss/data/vproc_ss.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver vproc_ss\n\n OPTION supported_peripherals = (v_proc_ss);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = vproc_ss;\n\nEND driver\n" }, { "path": "vproc_ss/data/vproc_ss.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset ip [get_property IP_NAME [get_cells -hier $drv_handle]]\n\tset topology [get_property CONFIG.C_TOPOLOGY [get_cells -hier $drv_handle]]\n\tif {$topology == 0} {\n\t#scaler\n\t\tset name [get_property NAME [get_cells -hier $drv_handle]]\n\t\tset compatible [get_comp_str $drv_handle]\n\t\tset compatible [append compatible \" \" \"xlnx,vpss-scaler-2.2 xlnx,v-vpss-scaler-2.2 xlnx,vpss-scaler\"]\n\t\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\t\tset ip [get_cells -hier $drv_handle]\n\t\tset csc_enable_window [get_property CONFIG.C_CSC_ENABLE_WINDOW [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,csc-enable-window\" $csc_enable_window string\n\t\tset topology [get_property CONFIG.C_TOPOLOGY [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,topology\" $topology int\n\t\tset v_scaler_phases [get_property CONFIG.C_V_SCALER_PHASES [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,v-scaler-phases\" $v_scaler_phases int\n\t\tset v_scaler_taps [get_property CONFIG.C_V_SCALER_TAPS [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,v-scaler-taps\" $v_scaler_taps int\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,num-vert-taps\" $v_scaler_taps int\n\t\tset h_scaler_phases [get_property CONFIG.C_H_SCALER_PHASES [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,h-scaler-phases\" $h_scaler_phases int\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,max-num-phases\" $h_scaler_phases int\n\t\tset h_scaler_taps [get_property CONFIG.C_H_SCALER_TAPS [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,h-scaler-taps\" $h_scaler_taps int\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,num-hori-taps\" $h_scaler_taps int\n\t\tset max_cols [get_property CONFIG.C_MAX_COLS [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,max-width\" $max_cols int\n\t\tset max_rows [get_property CONFIG.C_MAX_ROWS [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,max-height\" $max_rows int\n\t\tset samples_per_clk [get_property CONFIG.C_SAMPLES_PER_CLK [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,samples-per-clk\" $samples_per_clk int\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,pix-per-clk\" $samples_per_clk int\n\t\tset scaler_algo [get_property CONFIG.C_SCALER_ALGORITHM [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,scaler-algorithm\" $scaler_algo int\n\t\tset enable_csc [get_property CONFIG.C_ENABLE_CSC [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,enable-csc\" $enable_csc string\n\t\tset color_support [get_property CONFIG.C_COLORSPACE_SUPPORT [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,colorspace-support\" $color_support int\n\t\tset use_uram [get_property CONFIG.C_USE_URAM [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,use-uram\" $use_uram int\n\t\tset max_data_width [get_property CONFIG.C_MAX_DATA_WIDTH [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,video-width\" $max_data_width int\n\n\t\tset ports_node [add_or_get_dt_node -n \"ports\" -l scaler_ports$drv_handle -p $node]\n\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\t\tset port1_node [add_or_get_dt_node -n \"port\" -l scaler_port1$drv_handle -u 1 -p $ports_node]\n\t\thsi::utils::add_new_dts_param \"${port1_node}\" \"/* For xlnx,video-format user needs to fill as per their requirement */\" \"\" comment\n\t\thsi::utils::add_new_dts_param \"$port1_node\" \"reg\" 1 int\n\t\thsi::utils::add_new_dts_param \"$port1_node\" \"xlnx,video-format\" 3 int\n\t\thsi::utils::add_new_dts_param \"$port1_node\" \"xlnx,video-width\" $max_data_width int\n\t\tset scaoutip [get_connected_stream_ip [get_cells -hier $drv_handle] \"m_axis\"]\n\t\tif {[llength $scaoutip]} {\n\t\t\tif {[string match -nocase [get_property IP_NAME $scaoutip] \"axis_broadcaster\"]} {\n\t\t\t\tset sca_node [add_or_get_dt_node -n \"endpoint\" -l sca_out$drv_handle -p $port1_node]\n\t\t\t\tgen_endpoint $drv_handle \"sca_out$drv_handle\"\n\t\t\t\thsi::utils::add_new_dts_param \"$sca_node\" \"remote-endpoint\" $scaoutip$drv_handle reference\n\t\t\t\tgen_remoteendpoint $drv_handle \"$scaoutip$drv_handle\"\n\t\t\t}\n\t\t}\n\t\tforeach outip $scaoutip {\n\t\t\tif {[llength $outip]} {\n\t\t\t\tif {[string match -nocase [get_property IP_NAME $outip] \"system_ila\"]} {\n\t\t\t\t\tcontinue\n\t\t\t\t}\n\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $outip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $outip]\n\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\t\t\tset sca_node [add_or_get_dt_node -n \"endpoint\" -l sca_out$drv_handle -p $port1_node]\n\t\t\t\t\tgen_endpoint $drv_handle \"sca_out$drv_handle\"\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $outip] \"v_mix\"]} {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$sca_node\" \"remote-endpoint\" \"mixer_crtc$outip\" reference\n\t\t\t\t\t} else {\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$sca_node\" \"remote-endpoint\" $outip$drv_handle reference\n\t\t\t\t\t}\n\t\t\t\t\tgen_remoteendpoint $drv_handle \"$outip$drv_handle\"\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $outip] \"v_frmbuf_wr\"] \\\n\t\t\t\t\t\t|| [string match -nocase [get_property IP_NAME $outip] \"axi_vdma\"]} {\n\t\t\t\t\t\tgen_sca_frm_buf_node $outip $drv_handle\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tset connectip [get_connect_ip $outip $master_intf]\n\t\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\t\tset sca_node [add_or_get_dt_node -n \"endpoint\" -l sca_out$drv_handle -p $port1_node]\n\t\t\t\t\t\tgen_endpoint $drv_handle \"sca_out$drv_handle\"\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$sca_node\" \"remote-endpoint\" $connectip$drv_handle reference\n\t\t\t\t\t\tgen_remoteendpoint $drv_handle \"$connectip$drv_handle\"\n\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"v_frmbuf_wr\"] \\\n\t\t\t\t\t\t\t|| [string match -nocase [get_property IP_NAME $connectip] \"axi_vdma\"]} {\n\t\t\t\t\t\t\tgen_sca_frm_buf_node $connectip $drv_handle\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tdtg_warning \"$drv_handle pin m_axis is not connected..check your design\"\n\t\t\t}\n\t\t}\n\t\tgen_gpio_reset $drv_handle $node $topology\n\n\t}\n\tif {$topology == 3} {\n\t#CSC\n\t\tset name [get_property NAME [get_cells -hier $drv_handle]]\n\t\tset compatible [get_comp_str $drv_handle]\n\t\tset compatible [append compatible \" \" \"xlnx,vpss-csc xlnx,v-vpss-csc\"]\n\t\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\t\tset ip [get_cells -hier $drv_handle]\n\t\tset topology [get_property CONFIG.C_TOPOLOGY [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,topology\" $topology int\n\t\tset color_support [get_property CONFIG.C_COLORSPACE_SUPPORT [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,colorspace-support\" $color_support int\n\t\tset csc_enable_window [get_property CONFIG.C_CSC_ENABLE_WINDOW [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,csc-enable-window\" $csc_enable_window string\n\t\tset max_cols [get_property CONFIG.C_MAX_COLS [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,max-width\" $max_cols int\n\t\tset max_data_width [get_property CONFIG.C_MAX_DATA_WIDTH [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,video-width\" $max_data_width int\n\t\tset max_rows [get_property CONFIG.C_MAX_ROWS [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,max-height\" $max_rows int\n\t\tset num_video_comp [get_property CONFIG.C_NUM_VIDEO_COMPONENTS [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,num-video-components\" $num_video_comp int\n\t\tset samples_per_clk [get_property CONFIG.C_SAMPLES_PER_CLK [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,samples-per-clk\" $samples_per_clk int\n\t\tset topology [get_property CONFIG.C_TOPOLOGY [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,topology\" $topology int\n\t\tset use_uram [get_property CONFIG.C_USE_URAM [get_cells -hier $drv_handle]]\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,use-uram\" $use_uram int\n\n\t\tset ports_node [add_or_get_dt_node -n \"ports\" -l csc_ports$drv_handle -p $node]\n\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#address-cells\" 1 int\n\t\thsi::utils::add_new_dts_param \"$ports_node\" \"#size-cells\" 0 int\n\t\tset port1_node [add_or_get_dt_node -n \"port\" -l csc_port1$drv_handle -u 1 -p $ports_node]\n\t\thsi::utils::add_new_dts_param \"${port1_node}\" \"/* For xlnx,video-format user needs to fill as per their requirement */\" \"\" comment\n\t\thsi::utils::add_new_dts_param \"$port1_node\" \"reg\" 1 int\n\t\thsi::utils::add_new_dts_param \"$port1_node\" \"xlnx,video-format\" 3 int\n\t\thsi::utils::add_new_dts_param \"$port1_node\" \"xlnx,video-width\" $max_data_width int\n\t\tset outip [get_connected_stream_ip [get_cells -hier $drv_handle] \"m_axis\"]\n\t\tif {[llength $outip]} {\n\t\t\tif {[string match -nocase [get_property IP_NAME $outip] \"axis_broadcaster\"]} {\n\t\t\t\tset csc_node [add_or_get_dt_node -n \"endpoint\" -l csc_out$drv_handle -p $port1_node]\n\t\t\t\tgen_endpoint $drv_handle \"csc_out$drv_handle\"\n\t\t\t\thsi::utils::add_new_dts_param \"$csc_node\" \"remote-endpoint\" $outip$drv_handle reference\n\t\t\t\tgen_remoteendpoint $drv_handle \"$outip$drv_handle\"\n\t\t\t}\n\t\t}\n\t\tforeach ip $outip {\n\t\t\tif {[llength $ip]} {\n\t\t\t\tset master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $outip] -filter {TYPE==MASTER || TYPE ==INITIATOR}]\n\t\t\t\tset ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip]\n\t\t\t\tif {[llength $ip_mem_handles]} {\n\t\t\t\t\tset base [string tolower [get_property BASE_VALUE $ip_mem_handles]]\n\t\t\t\t\tset cscoutnode [add_or_get_dt_node -n \"endpoint\" -l csc_out$drv_handle -p $port1_node]\n\t\t\t\t\tgen_endpoint $drv_handle \"csc_out$drv_handle\"\n\t\t\t\t\thsi::utils::add_new_dts_param \"$cscoutnode\" \"remote-endpoint\" $ip$drv_handle reference\n\t\t\t\t\tgen_remoteendpoint $drv_handle \"$ip$drv_handle\"\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $ip] \"v_frmbuf_wr\"] \\\n\t\t\t\t\t\t|| [string match -nocase [get_property IP_NAME $ip] \"axi_vdma\"]} {\n\t\t\t\t\t\tgen_csc_frm_buf_node $ip $drv_handle\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $ip] \"system_ila\"]} {\n\t\t\t\t\t\tcontinue\n\t\t\t\t\t}\n\t\t\t\t\tset connectip [get_connect_ip $ip $master_intf]\n\t\t\t\t\tif {[llength $connectip]} {\n\t\t\t\t\t\tset cscoutnode [add_or_get_dt_node -n \"endpoint\" -l csc_out$drv_handle -p $port1_node]\n\t\t\t\t\t\tgen_endpoint $drv_handle \"csc_out$drv_handle\"\n\t\t\t\t\t\thsi::utils::add_new_dts_param \"$cscoutnode\" \"remote-endpoint\" $connectip$drv_handle reference\n\t\t\t\t\t\tgen_remoteendpoint $drv_handle \"$connectip$drv_handle\"\n\t\t\t\t\t\tif {[string match -nocase [get_property IP_NAME $connectip] \"v_frmbuf_wr\"] \\\n\t\t\t\t\t\t\t|| [string match -nocase [get_property IP_NAME $ip] \"axi_vdma\"]} {\n\t\t\t\t\t\t\tgen_csc_frm_buf_node $connectip $drv_handle\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tdtg_warning \"$drv_handle pin m_axis is not connected..check your design\"\n\t\t\t}\n\t\t}\n\t\tgen_gpio_reset $drv_handle $node $topology\n\t}\n}\n\nproc gen_sca_frm_buf_node {outip drv_handle} {\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n\tset vcap [add_or_get_dt_node -n \"vcap_$drv_handle\" -p $bus_node]\n\thsi::utils::add_new_dts_param $vcap \"compatible\" \"xlnx,video\" string\n\thsi::utils::add_new_dts_param $vcap \"dmas\" \"$outip 0\" reference\n\thsi::utils::add_new_dts_param $vcap \"dma-names\" \"port0\" string\n\tset vcap_ports_node [add_or_get_dt_node -n \"ports\" -l vcap_ports$drv_handle -p $vcap]\n\thsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#size-cells\" 0 int\n\tset vcap_port_node [add_or_get_dt_node -n \"port\" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node]\n\thsi::utils::add_new_dts_param \"$vcap_port_node\" \"reg\" 0 int\n\thsi::utils::add_new_dts_param \"$vcap_port_node\" \"direction\" input string\n\tset vcap_in_node [add_or_get_dt_node -n \"endpoint\" -l $outip$drv_handle -p $vcap_port_node]\n\tgen_endpoint $drv_handle \"sca_out$drv_handle\"\n\thsi::utils::add_new_dts_param \"$vcap_in_node\" \"remote-endpoint\" sca_out$drv_handle reference\n\tgen_remoteendpoint $drv_handle \"$outip$drv_handle\"\n}\n\nproc gen_csc_frm_buf_node {outip drv_handle} {\n\tset dt_overlay [get_property CONFIG.dt_overlay [get_os]]\n\tif {$dt_overlay} {\n\t\tset bus_node \"amba\"\n\t} else {\n\t\tset bus_node \"amba_pl\"\n\t}\n\tset vcap [add_or_get_dt_node -n \"vcap_$drv_handle\" -p $bus_node]\n\thsi::utils::add_new_dts_param $vcap \"compatible\" \"xlnx,video\" string\n\thsi::utils::add_new_dts_param $vcap \"dmas\" \"$outip 0\" reference\n\thsi::utils::add_new_dts_param $vcap \"dma-names\" \"port0\" string\n\tset vcap_ports_node [add_or_get_dt_node -n \"ports\" -l vcap_ports$drv_handle -p $vcap]\n\thsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#address-cells\" 1 int\n\thsi::utils::add_new_dts_param \"$vcap_ports_node\" \"#size-cells\" 0 int\n\tset vcap_port_node [add_or_get_dt_node -n \"port\" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node]\n\thsi::utils::add_new_dts_param \"$vcap_port_node\" \"reg\" 0 int\n\thsi::utils::add_new_dts_param \"$vcap_port_node\" \"direction\" input string\n\tset vcap_in_node [add_or_get_dt_node -n \"endpoint\" -l $outip$drv_handle -p $vcap_port_node]\n\tgen_endpoint $drv_handle \"csc_out$drv_handle\"\n\thsi::utils::add_new_dts_param \"$vcap_in_node\" \"remote-endpoint\" csc_out$drv_handle reference\n\tgen_remoteendpoint $drv_handle \"$outip$drv_handle\"\n}\n\nproc gen_gpio_reset {drv_handle node topology} {\n\tset proc_type [get_sw_proc_prop IP_NAME]\n\tif {$topology == 3} {\n\t\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] \"aresetn\"]]\n\t}\n\tif {$topology == 0} {\n\t\tset pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] \"aresetn_ctrl\"]]\n\t}\n\tforeach pin $pins {\n\t\t\tset sink_periph [::hsi::get_cells -of_objects $pin]\n\t\t\tif {[llength $sink_periph]} {\n\t\t\t\tset sink_ip [get_property IP_NAME $sink_periph]\n\t\t\t\tif {[string match -nocase $sink_ip \"axi_gpio\"]} {\n\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"$sink_periph 0 1\" reference\n\t\t\t\t}\n\t\t\t\tif {[string match -nocase $sink_ip \"xlslice\"]} {\n\t\t\t\t\tset gpio [get_property CONFIG.DIN_FROM $sink_periph]\n\t\t\t\t\tset pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph \"Din\"]]]\n\t\t\t\t\tforeach pin $pins {\n\t\t\t\t\t\tset periph [::hsi::get_cells -of_objects $pin]\n\t\t\t\t\t\tif {[llength $periph]} {\n\t\t\t\t\t\t\tset ip [get_property IP_NAME $periph]\n\t\t\t\t\t\t\tif {[string match -nocase $proc_type \"psv_cortexa72\"] } {\n\t\t\t\t\t\t\t\tif { $ip in { \"versal_cips\" \"ps_wizard\" }} {\n\t\t\t\t\t\t\t\t\t# As versal has only bank0 for MIOs\n\t\t\t\t\t\t\t\t\tset gpio [expr $gpio + 26]\n\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio0 $gpio 1\" reference\n\t\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tif {[string match -nocase $proc_type \"psu_cortexa53\"] } {\n\t\t\t\t\t\t\t\tif {[string match -nocase $ip \"zynq_ultra_ps_e\"]} {\n\t\t\t\t\t\t\t\t\tset gpio [expr $gpio + 78]\n\t\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"gpio $gpio 1\" reference\n\t\t\t\t\t\t\t\t\tbreak\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tif {[string match -nocase $ip \"axi_gpio\"]} {\n\t\t\t\t\t\t\t\thsi::utils::add_new_dts_param \"$node\" \"reset-gpios\" \"$periph $gpio 1\" reference\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tdtg_warning \"peripheral is NULL for the $pin $periph\"\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tdtg_warning \"$drv_handle:peripheral is NULL for the $pin $sink_periph\"\n\t\t\t}\n\t\t}\n}\n" }, { "path": "vtc/data/vtc.mdd", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver vtc\n\n OPTION supported_peripherals = (v_tc);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = vtc;\n\nEND driver\n" }, { "path": "vtc/data/vtc.tcl", "content": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n\tforeach i [get_sw_cores device_tree] {\n\t\tset common_tcl_file \"[get_property \"REPOSITORY\" $i]/data/common_proc.tcl\"\n\t\tif {[file exists $common_tcl_file]} {\n\t\t\tsource $common_tcl_file\n\t\t\tbreak\n\t\t}\n\t}\n\tset node [gen_peripheral_nodes $drv_handle]\n\tif {$node == 0} {\n\t\treturn\n\t}\n\tset compatible [get_comp_str $drv_handle]\n\tset compatible [append compatible \" \" \"xlnx,v-tc-6.1\"]\n\tset compatible [append compatible \" \" \"xlnx,bridge-v-tc-6.1\"]\n\tset_drv_prop $drv_handle compatible \"$compatible\" stringlist\n\tset generate_en [get_property CONFIG.C_GENERATE_EN [get_cells -hier $drv_handle]]\n\tif {$generate_en == 1} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,generator\" \"\" boolean\n\t}\n\tset detect_en [get_property CONFIG.C_DETECT_EN [get_cells -hier $drv_handle]]\n\tif {$detect_en == 1} {\n\t\thsi::utils::add_new_dts_param \"${node}\" \"xlnx,detector\" \"\" boolean\n\t}\n}\n" }, { "path": "wdtps/data/wdtps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver wdtps\n\n OPTION supported_peripherals = (ps7_wdt psu_wdt psv_wdt psx_wwdt);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = wdtps;\n\nEND driver\n" }, { "path": "wdtps/data/wdtps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n" }, { "path": "xadcps/data/xadcps.mdd", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nOPTION psf_version = 3.0;\n\nBEGIN driver xadcps\n\n OPTION supported_peripherals = (ps7_xadc);\n OPTION supported_os_types = (DTS);\n OPTION driver_state = ACTIVE;\n OPTION NAME = xadcps;\n\nEND driver\n" }, { "path": "xadcps/data/xadcps.tcl", "content": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License as\n# published by the Free Software Foundation; either version 2 of\n# the License, or (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n# GNU General Public License for more details.\n#\n\nproc generate {drv_handle} {\n}\n" } ]